JP5929705B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device.

2. Description of the Related Art A semiconductor light emitting device in which a group III nitride semiconductor layer including a light emitting layer that emits light when energized is laminated on a substrate is known.
In such a semiconductor light emitting device, the side surface of the group III nitride semiconductor layer is inclined outward with respect to the normal line of the upper surface of the substrate so that the cross-sectional shape of the group III nitride semiconductor layer becomes narrower toward the substrate side. Thus, there is a technique for improving the light extraction efficiency in the semiconductor light emitting device (see Patent Document 1).

JP 2007-116114 A

By the way, when the side surface of the semiconductor layer is inclined outward with respect to the normal line of the upper surface of the substrate in the semiconductor light emitting device, there is a concern that cracks are likely to occur at the end of the semiconductor layer.
An object of this invention is to provide the semiconductor light-emitting device which suppressed the crack of the semiconductor layer.

The semiconductor light-emitting device of the present invention is a semiconductor light-emitting device including a semiconductor layer including a light-emitting layer that emits light when energized, and the semiconductor layer includes a semiconductor bottom surface and a first periphery of the semiconductor bottom surface above the semiconductor layer. And a semiconductor side surface rising outward, and a semiconductor upper surface extending upward from the second peripheral edge above the semiconductor side surface toward the inner side of the semiconductor layer, the second peripheral edge being a straight line A plurality of linear portions extending in a shape and a plurality of connecting portions that connect adjacent linear portions, and when viewed from a direction perpendicular to the upper surface of the semiconductor, each connecting portion is connected to the connecting portion. The semiconductor side surface is located on the inner side of the intersection of the extended lines of the two linear portions to be connected, and the semiconductor side surface extends from the first peripheral edge toward the linear portion at the second peripheral edge, 1 fringe A connecting side surface extending toward the connecting portion at the second peripheral edge, and the connecting side surface includes an inclined portion that rises upward and outward from the first peripheral edge from the first peripheral edge, and from the inclined portion. And a vertical portion that rises upward toward the connection portion at the second peripheral edge .

Further, the semiconductor light emitting device of the present invention may be characterized in that the straight side surface rises upward and outward from the first peripheral edge toward the straight line portion at the second peripheral edge .
Furthermore, in the semiconductor light emitting device of the present invention, the plurality of linear portions include a first linear portion extending in a first direction when the semiconductor layer is viewed from a direction perpendicular to the semiconductor upper surface, and the first direction. A second linear portion extending in a vertical second direction and connected to the first linear portion via the connecting portion, and when the semiconductor layer is viewed from a direction perpendicular to the upper surface of the semiconductor, the first linear portion The shortest distance from one straight line part to the first peripheral edge is X, the shortest distance from the second straight line part to the first peripheral edge is Y, and an extension line of the first straight line part and the second straight line part X, Y, and L, where L is the shortest distance from the intersection of the straight line connecting the intersection with the extension line to the first peripheral edge and the connecting portion to the first peripheral edge. ^is to characterized in that it has a relationship of ^{L 2 = a × (X 2} + Y 2) 0 <a ≦ 0.95 .
Furthermore, the connection part has an arc shape when the semiconductor layer is viewed from a direction perpendicular to the semiconductor upper surface.

Further, when the present invention is regarded as a method for manufacturing a semiconductor light emitting device, the semiconductor light emitting device manufacturing method of the present invention includes a semiconductor layer including a light emitting layer that emits light when energized on a substrate and made of a group III nitride semiconductor. A first groove portion extending along the surface of the semiconductor layer by locally removing a part of the semiconductor layer from a side opposite to the substrate with respect to the stacked semiconductor multilayer substrate, and the semiconductor layer A second groove that extends along the surface and intersects the first groove, a recess that is provided in a region where the first groove and the second groove intersect, and is recessed from the first groove and the second groove, A part of the semiconductor layer locally from the side opposite to the substrate with respect to the semiconductor laminated substrate in which the first groove portion, the second groove portion, and the concave portion are formed. Remove until you reach It is a dividing groove forming step of forming the plurality of dividing grooves that divide the intersecting and the semiconductor layer into a plurality of regions in the first groove and the second along the groove and the recess, said first groove, A wet etching step of performing wet etching on the semiconductor laminated substrate in which the second groove portion, the concave portion, and the plurality of divided grooves are formed.
Furthermore, in the method for manufacturing a semiconductor light emitting device of the present invention, in the semiconductor removal step, a removal suppression layer that prevents removal of the semiconductor layer is partially stacked on the semiconductor layer, and the removal suppression layer of the semiconductor layer The recess may be formed by removing a region where no is formed from the opposite side of the substrate.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device which suppressed the crack of the semiconductor layer can be provided.

It is an example of the perspective view of the semiconductor light-emitting device to which this Embodiment is applied. It is an example of the top view of the semiconductor light-emitting device shown in FIG. It is an example of the longitudinal cross-sectional view of the board | substrate with which this Embodiment is applied, a laminated semiconductor layer, and a transparent conductive layer. It is an example of the longitudinal cross-sectional view of the semiconductor light-emitting device to which this Embodiment is applied. It is an example of the longitudinal cross-sectional view of the semiconductor light-emitting device to which this Embodiment is applied. It is a figure for demonstrating the structure of the periphery of the connection part and connection side surface of a lower side semiconductor layer to which this Embodiment is applied. It is a flowchart which shows an example of the manufacturing method of the semiconductor light-emitting device to which this Embodiment is applied. It is the figure which showed the semiconductor laminated substrate after mask formation obtained by performing a mask formation process. It is the figure which showed the semiconductor laminated substrate after forming a transparent conductive layer and a resist obtained by performing to a resist formation process. It is the figure which showed the semiconductor laminated substrate after 1st groove part, 2nd groove part, a recessed part, and semiconductor exposure surface formation obtained by performing a 1st etching process. It is the figure which showed the semiconductor laminated substrate after 1st irradiation line and 2nd irradiation line formation obtained by performing an electrode formation process and a surface laser process. It is the figure which showed the structure of the level | step difference vicinity in the lower side semiconductor layer after completion | finish of a surface laser process. It is the figure which showed the semiconductor laminated substrate obtained by performing a 2nd etching process. It is a figure for demonstrating progress of the wet etching in the level | step difference vicinity of a lower side semiconductor layer. FIG. 10 is a diagram for explaining the method of manufacturing the semiconductor light emitting element in the second embodiment. FIG. 10 is a diagram for illustrating a second etching process in the second embodiment. It is a figure for demonstrating progress of the wet etching of the lower side semiconductor layer in the convex part vicinity. FIG. 11 is a diagram for illustrating the method of manufacturing the semiconductor light emitting element in the third embodiment.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, the size, thickness, and the like of each part in the drawings referred to in the following description may be different from the dimensions of an actual semiconductor light emitting element or the like.

[Embodiment 1]
(Structure of semiconductor light emitting device)
FIG. 1 is an example of a perspective view of a semiconductor light emitting device 1 to which the present embodiment is applied, and FIG. 2 is an example of a top view of the semiconductor light emitting device 1 shown in FIG.
As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 according to the present embodiment includes a substrate 100, a laminated semiconductor layer 200 as an example of a semiconductor layer laminated on the substrate 100, and the laminated semiconductor layer 200. It has a laminated transparent conductive layer 300, a p-electrode 350 formed on the transparent conductive layer 300, and an n-electrode 400 formed on the laminated semiconductor layer 200.

  In addition, the stacked semiconductor layer 200 of this embodiment includes a lower semiconductor layer 210 stacked on the substrate 100 and an upper semiconductor layer 250 stacked on the lower semiconductor layer 210. In this example, the n-electrode 400 is formed on the lower semiconductor layer 210 (a semiconductor exposed surface 213a described later).

As shown in FIG. 1, the semiconductor light emitting device 1 of the present embodiment has a substantially rectangular parallelepiped shape. As shown in FIG. 2, the semiconductor light emitting device 1 has a substantially rectangular shape having a long side and a short side when viewed from the side where the p electrode 350 and the n electrode 400 are formed. Have.
In the present embodiment, when the semiconductor light emitting device 1 is viewed from the side where the p-electrode 350 and the n-electrode 400 are formed, the direction along the long side is defined as the first direction x, and the direction along the short side is defined as the first direction x. Let it be two directions y. A direction perpendicular to the first direction x and the second direction y and from the substrate 100 side to the laminated semiconductor layer 200 side in the semiconductor light emitting element 1 is defined as a third direction z.

Furthermore, as shown in FIG. 1, the substrate 100 of the present embodiment has a substantially rectangular parallelepiped shape. As shown in FIG. 2, the substrate 100 has a long side along the first direction x and a short side along the second direction y when viewed from the side on which the laminated semiconductor layer 200 is laminated. It has a substantially rectangular shape. Therefore, the substrate 100 includes four substrate side surfaces, a substrate upper surface 113 on which the laminated semiconductor layer 200 is stacked, and a substrate bottom surface 114 (see FIG. 3 described later) facing the substrate upper surface 113 through the four substrate side surfaces. Have. The substrate top surface 113 and the substrate bottom surface 114 each have a rectangular shape having two long sides along the first direction x and two short sides along the second direction y.
In the present embodiment, of the four substrate side surfaces, the two long side substrate side surfaces along the first direction x are referred to as first substrate side surfaces 111, respectively, and two short sides along the second direction y. The side substrate side surfaces are referred to as second substrate side surfaces 112, respectively.

  In this example, a sapphire single crystal having a C-plane as the substrate upper surface 113 is used as the substrate 100. Note that as the plane orientation of the substrate upper surface 113, it is desirable to use a C plane of sapphire single crystal from which a high-quality laminated semiconductor layer 200 can be easily obtained. As the substrate upper surface 113, it is more desirable to use a surface to which a minute off angle is given with respect to the C surface of the sapphire single crystal. When providing an off angle, 1 ° or less is applied as the off angle. In the present embodiment, the substrate upper surface 113 is simply referred to as the C plane, including the case where such an off angle is provided. Further, the sapphire single crystal used as the substrate 100 may contain a small amount of impurities.

The lower semiconductor layer 210 of the present embodiment has a substantially rectangular parallelepiped shape as shown in FIGS. Accordingly, the lower semiconductor layer 210 is an example of a lower semiconductor upper surface 213 as an example of a semiconductor upper surface on which the upper semiconductor layer 250 is stacked, and an example of a semiconductor lower surface facing the lower semiconductor upper surface 213 and in contact with the substrate upper surface 113. The lower semiconductor bottom surface 214 (see FIG. 4 described later), the periphery of the lower semiconductor top surface 213 (upper surface periphery 230 described later), and the periphery of the lower semiconductor bottom surface 214 (bottom surface periphery 240 described later) are provided. It has a lower semiconductor side surface as an example of the semiconductor side surface.
In the present embodiment, the area of the lower semiconductor bottom surface 214 in the lower semiconductor layer 210 is smaller than the area of the substrate upper surface 113 in the substrate 100. In addition, the area of the lower semiconductor upper surface 213 in the lower semiconductor layer 210 is smaller than the area of the substrate upper surface 113. Therefore, the peripheral edge of the substrate upper surface 113 of the substrate 100 is exposed to the outside, and when the semiconductor light emitting device 1 is viewed from the side where the p electrode 350 and the n electrode 400 are formed as shown in FIG. The peripheral edge of the exposed substrate upper surface 113 can be visually recognized.
Furthermore, in this example, the area of the lower semiconductor bottom surface 214 is formed smaller than the area of the lower semiconductor upper surface 213.

  As shown in FIGS. 1 and 2, a semiconductor exposed surface 213a exposed by cutting out a part of the upper semiconductor layer 250 is formed on the lower semiconductor upper surface 213 of the present embodiment. The n-electrode 400 is provided on the semiconductor exposed surface 213a as described above.

As shown in FIG. 2, the lower semiconductor upper surface 213 of the present embodiment has a shape (so-called rounded rectangle) that approximates a rectangle in which four corners have arc shapes. That is, the upper surface peripheral edge 230 of the lower semiconductor upper surface 213 includes a linear first linear portion 231 along the first direction x, a linear second linear portion 232 along the second direction y, and a first linear portion 231. And an arc-shaped connecting portion 233 that connects the second straight portion 232 to each other. In the present embodiment, two first straight portions 231 and two second straight portions 232 are provided, and four connection portions 233 are provided.
Here, the upper surface peripheral edge 230 is an example of a second peripheral edge, and in the present embodiment, the first linear part 231 and the second linear part 232 form a linear part.

  Further, the lower semiconductor side surface of the lower semiconductor layer 210 includes two first lower semiconductor side surfaces 211 extending from the first linear portion 231 of the lower semiconductor upper surface 213 toward the substrate upper surface 113, as shown in FIG. , Two second lower semiconductor side surfaces 212 extending from the second linear portion 232 of the lower semiconductor upper surface 213 toward the substrate upper surface 113. Further, the lower semiconductor side surface of the lower semiconductor layer 210 includes four connection side surfaces 235 extending from the connection portion 233 of the lower semiconductor upper surface 213 toward the substrate upper surface 113.

Furthermore, the bottom surface periphery 240 as an example of the 1st periphery in the lower semiconductor bottom surface 214 of this Embodiment has a rectangular shape, as shown in FIG. Specifically, the bottom peripheral edge 240 of the lower semiconductor bottom surface 214 includes a first straight portion 241 corresponding to a boundary between the first lower semiconductor side surface 211 and the lower semiconductor bottom surface 214, and a second lower semiconductor side surface 212. A second linear portion 242 corresponding to the boundary with the lower semiconductor bottom surface 214. The first straight part 241 and the second straight part 242 extend substantially perpendicular to each other and intersect each other.
The detailed structure of the lower semiconductor layer 210 will be described later.

Furthermore, as shown in FIGS. 1 and 2, the upper semiconductor layer 250 of the present embodiment has a substantially rectangular parallelepiped shape. Accordingly, the upper semiconductor layer 250 faces the upper semiconductor upper surface 253 via the four upper semiconductor side surfaces, the upper semiconductor upper surface 253 on which the transparent conductive layer 300 is laminated, and the four upper semiconductor side surfaces, and the lower semiconductor layer 210. And an upper semiconductor bottom surface (not shown) in contact with the lower semiconductor upper surface 213. In the present embodiment, of the four upper semiconductor side surfaces in the upper semiconductor layer 250, the two upper semiconductor side surfaces along the first direction x are referred to as first upper semiconductor side surfaces 251 and 2 along the second direction y. The two upper semiconductor side surfaces are respectively referred to as second upper semiconductor side surfaces 252. Of the two second upper semiconductor side surfaces 252, one second upper semiconductor side surface 252 has a curved portion along the semiconductor exposed surface 213a of the lower semiconductor upper surface 213.
In the present embodiment, the two first upper semiconductor side surfaces 251 and the two second upper semiconductor side surfaces 252 are provided substantially perpendicular to the lower semiconductor upper surface 213 in the lower semiconductor layer 210, respectively.

  Here, in the present embodiment, the area of the upper semiconductor bottom surface in the upper semiconductor layer 250 is smaller than the area of the lower semiconductor upper surface 213 in the lower semiconductor layer 210. Accordingly, a part of the lower semiconductor upper surface 213 of the lower semiconductor layer 210 is exposed to the outside.

Furthermore, as shown in FIGS. 1 and 2, the transparent conductive layer 300 of this embodiment is formed so as to cover substantially the entire upper semiconductor upper surface 253 in the upper semiconductor layer 250.
The transparent conductive layer 300 is not limited to such a shape. For example, the transparent conductive layer 300 may be formed in a lattice shape or a tree shape with gaps.

Next, a stacked structure of the substrate 100, the stacked semiconductor layer 200, and the transparent conductive layer 300 in the semiconductor light emitting device 1 of the present embodiment will be described.
FIG. 3 is an example of a longitudinal sectional view of the substrate 100, the laminated semiconductor layer 200, and the transparent conductive layer 300 to which this embodiment is applied. In this embodiment, a cross section along a direction perpendicular to the substrate upper surface 113 of the substrate 100 may be referred to as a vertical cross section.

As shown in FIG. 3, the substrate 100 of the present embodiment has a plurality of protrusions 113 a that protrude toward the laminated semiconductor layer 200 on a flat substrate upper surface 113. The width of each protrusion 113a is preferably 0.05 μm to 5 μm, and the height of each protrusion 113a is preferably in the range of 0.05 μm to 5 μm.
Note that the protrusion 113 a is not necessarily provided on the substrate upper surface 113 of the substrate 100, but from the viewpoint of improving the crystallinity of the stacked semiconductor layer 200 stacked on the substrate 100 and the light emission efficiency in the semiconductor light emitting device 1. Is preferably provided with a plurality of convex portions 113a on the upper surface 113 of the substrate.

As shown in FIG. 3, the stacked semiconductor layer 200 according to the present embodiment is stacked on the substrate upper surface 113 of the substrate 100 and the convex portion 113 a formed on the substrate upper surface 113.
The stacked semiconductor layer 200 according to the present embodiment includes an intermediate layer 201 stacked on the substrate 100, a base layer 202 stacked on the intermediate layer 201, and an n-type semiconductor layer stacked on the base layer 202. 203, a light emitting layer 204 stacked on the n-type semiconductor layer 203, and a p-type semiconductor layer 205 stacked on the light emitting layer 204.

The n-type semiconductor layer 203 includes an n-contact layer 203a stacked on the base layer 202 and an n-cladding layer 203b stacked on the n-contact layer 203a. The n contact layer 203a can also serve as the n clad layer 203b.
The p-type semiconductor layer 205 includes a p-cladding layer 205a stacked on the light emitting layer 204 and a p-contact layer 205b stacked on the p-cladding layer 205a. The p contact layer 205b can also serve as the p clad layer 205a.

  In the present embodiment, the lower semiconductor layer 210 is constituted by a part of the intermediate layer 201, the base layer 202, and the n contact layer 203a on the base layer 202 side. Further, the upper semiconductor layer 250 includes a part of the n contact layer 203a on the n clad layer 203b side, the n clad layer 203b, the light emitting layer 204, the p clad layer 205a, and the p contact layer 205b.

Subsequently, each layer constituting the laminated semiconductor layer 200 will be described.
In the following description, AlGaN and GaInN may be described in a form in which the composition ratio of each element is omitted.
<Intermediate layer>
The intermediate layer 201 is provided to alleviate the difference in lattice constant between the substrate 100 and the base layer 202. The intermediate layer 201 is easy to form a c-axis oriented single crystal layer on the C plane ((0001) plane) of the substrate 100, particularly when the substrate 100 is composed of a sapphire single crystal having a C plane as a main surface. There is work to make. Therefore, by forming the intermediate layer 201, the crystallinity of the base layer 202 stacked thereon can be improved.

The intermediate layer 201 of the present embodiment is made of AlN. The intermediate layer 201 is made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1) or single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1) other than AlN. May be used.
The thickness of the intermediate layer 201 is preferably in the range of 0.01 μm to 0.5 μm. If the thickness of the intermediate layer 201 is less than 0.01 μm, the intermediate layer 201 may not sufficiently obtain an effect of relaxing the difference in lattice constant between the substrate 100 and the base layer 202. Further, if the thickness of the intermediate layer 201 exceeds 0.5 μm, the film forming process time of the intermediate layer 201 becomes longer and the productivity may be lowered, although the function as the intermediate layer 201 is not changed. There is.

<Underlayer>
As the underlayer 202, Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used.
The thickness of the underlayer 202 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. By setting the thickness of the underlayer 202 to 1 μm or more, it becomes easy to obtain the underlayer 202 with good crystallinity.
In order to improve the crystallinity of the base layer 202, it is preferable that the base layer 202 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added.

  Here, as a suitable example of the intermediate layer 201 and the base layer 202, a material containing AlGaN can be used for the intermediate layer 201, and a material containing GaN and InGaN can be used for the base layer 202. Further, a dopant may be added to the intermediate layer 201 or the base layer 202. In this case, it is desirable to change the kind of dopant to be added and the doping amount between the intermediate layer 201 and the base layer 202.

<N contact layer>
The n contact layer 203 a is a layer for providing the n electrode 400.
The n contact layer 203a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1).
The n contact layer 203a is preferably doped with an n-type impurity. When an n-type impurity is contained at a concentration of 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ , the n-type impurity can be easily obtained. It is preferable at the point which can maintain ohmic contact. Examples of the n-type impurity include Si, Ge, and Sn, and preferably Si and Ge.

  The thickness of the n contact layer 203a is preferably 0.5 μm to 5 μm, and more preferably set to a range of 1 μm to 3 μm. When the thickness of the n contact layer 203a is in the above range, the crystallinity of the light emitting layer 204 and the like is maintained well. Further, when the thickness of the n contact layer 203a is within this range, the electric resistance is lowered, which is effective in reducing the operating voltage (VF). Note that if the thickness of the n-contact layer 203a is too thick, the productivity is reduced.

<N clad layer>
The n-clad layer 203b is a layer that performs carrier injection and carrier confinement into the light-emitting layer 204.
The n-clad layer 203b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. When the n-cladding layer 203b is formed of GaInN, it is desirable to make it larger than the GaInN band gap of the light emitting layer 204.

The n-type impurity concentration of the n-clad layer 203b is preferably 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ . When the impurity concentration is within this range, it is preferable from the viewpoint of improving the light emission efficiency by maintaining good crystallinity and reducing the operating voltage of the device.
The thickness of the n-clad layer 203b is preferably 5 nm to 500 nm, more preferably 50 nm to 200 nm.

When the n clad layer 203b is a layer including a superlattice structure, the composition differs between the n-side first layer made of a group III nitride semiconductor having a thickness of 10 nm or less and the n-side first layer. In addition, a structure in which an n-side second layer made of a group III nitride semiconductor having a thickness of 10 nm or less is stacked may be included.
The n-clad layer 203b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. In this case, an alternate structure of GaInN and GaN. Alternatively, an alternate structure of GaInN having different compositions is preferable.

<Light emitting layer>
As the light emitting layer 204 laminated on the n-clad layer 203b, a single quantum well structure or a multiple quantum well structure can be adopted.
As a well layer having a quantum well structure, a group III nitride semiconductor layer made of Ga _1-y In _y N (0 <y <0.4) adjusted so as to obtain a desired emission wavelength is usually used. When the light emitting layer 204 having a multiple quantum well structure is used, the Ga _1-y In _y N is used as a well layer, and Al _z Ga _1-z N (0 ≦ z <0. 3) is a barrier layer. The well layer and the barrier layer may be doped with impurities by design or may not be doped with impurities.

<P-clad layer>
The p-cladding layer 205a is a layer that performs confinement of carriers and injection of carriers in the light-emitting layer 204.
The p clad layer 205a is not particularly limited as long as it has a composition larger than the band gap energy of the light emitting layer 204 and can confine carriers in the light emitting layer 204. For example, Al _x Ga _1-x N (0 It is desirable to use <x ≦ 0.4). When the p-clad layer 205a is made of such AlGaN, it is preferable in terms of confining carriers in the light-emitting layer 204.

The p-type impurity concentration of the p-clad layer 205a is preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ . When the p-type impurity concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
Further, the p-cladding layer 205a may have a superlattice structure similarly to the n-cladding layer 203b described above. In this case, a structure in which AlGaN having different composition ratios and other AlGaN are alternately stacked or a structure in which AlGaN and GaN having different compositions are alternately stacked is preferable.
The thickness of the p-cladding layer 205a is not particularly limited, but is preferably 1 nm to 400 nm, more preferably 5 nm to 100 nm.

<P contact layer>
The p contact layer 205 b is a layer for providing the p electrode 350 through the transparent conductive layer 300. The p contact layer 205b is preferably made of Al _x Ga _1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity and good ohmic contact with the p-electrode 350 can be maintained.
The p-type impurity concentration of the p-contact layer 205b is preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ , more preferably 5 × 10 ¹⁹ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ . A p-type impurity concentration in the above range is preferable in that good ohmic contact and good crystallinity can be maintained. Although it does not specifically limit as a p-type impurity, For example, Mg etc. are mentioned.
The thickness of the p contact layer 205b is not particularly limited, but is preferably 10 nm to 500 nm, and more preferably 50 nm to 200 nm. When the thickness of the p contact layer 205b is in the above range, it is preferable in terms of light emission output and operating voltage.

<Transparent conductive layer>
Furthermore, as described above, the transparent conductive layer 300 is provided on the stacked semiconductor layer 200 (upper semiconductor upper surface 253) of the present embodiment.
The transparent conductive layer 300 preferably has a small contact resistance with the p-type semiconductor layer 205 (p contact layer 205b). Further, in the semiconductor light emitting device 1 of the present embodiment, since the light output from the light emitting layer 204 is taken out to the side where the p electrode 350 is formed, the transparent conductive layer 300 corresponds to the light output from the light emitting layer 204. It is preferable that it is excellent in permeability. Furthermore, it is preferable that the transparent conductive layer 300 has excellent conductivity in order to diffuse current uniformly over the entire surface of the p-type semiconductor layer 205.

From the above, as a material constituting the transparent conductive layer 300, for example, it is preferable to use a translucent conductive material made of a conductive oxide containing at least In. As the conductive oxide containing In, for example, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (indium gallium oxide (In ₂ O ₃ —Ga ₂ O ₃ )), ICO (indium cerium oxide (In ₂ O ₃ —CeO ₂ )) and the like. In these, impurities such as fluorine may be added.
Although the thickness in particular of the transparent conductive layer 300 is not restrict | limited, For example, the range of 10 nm-500 nm is preferable.

(Description of detailed structure of lower semiconductor layer)
Next, the detailed structure of the lower semiconductor layer 210 in the semiconductor light emitting device 1 of the present embodiment will be described.
4 and 5 are examples of longitudinal sectional views of the semiconductor light emitting element 1 to which the present exemplary embodiment is applied. 4A is a cross-sectional view taken along the line IVA-IVA in FIG. 2, and FIG. 4B is a cross-sectional view taken along the line IVB-IVB in FIG. 5 is a cross-sectional view taken along line VV in FIG.

As shown in FIG. 4A, in the lower semiconductor layer 210, an angle formed by the first lower semiconductor side surface 211 and the lower semiconductor upper surface 213 is θ1a. In the present embodiment, θ1a is an acute angle (θ1a <90 °).
In the lower semiconductor layer 210, an angle formed by the first lower semiconductor side surface 211 and the lower semiconductor bottom surface 214 is θ1b. In the present embodiment, θ1b is an obtuse angle (θ1b> 90 °).

In the present embodiment, the two first lower semiconductor side surfaces 211 have a shape inclined toward the outer side of the lower semiconductor layer 210 with respect to a plane along the first direction x and perpendicular to the substrate upper surface 113. doing.
As shown in FIG. 4A, the lower semiconductor layer 210 has a boundary portion (that is, a first straight portion) between the first lower semiconductor side surface 211 and the lower semiconductor upper surface 213 along the second direction y. 231), the thickness decreases.

Similarly, as shown in FIG. 4B, in the lower semiconductor layer 210, the angle formed by the second lower semiconductor side surface 212 and the lower semiconductor upper surface 213 is θ2a. In the present embodiment, θ2a is an acute angle (θ2a <90 °).
In the lower semiconductor layer 210, an angle formed by the second lower semiconductor side surface 212 and the lower semiconductor bottom surface 214 is θ2b. In the present embodiment, θ2b is an obtuse angle (θ2b> 90 °).

In the present embodiment, the two second lower semiconductor side surfaces 212 have a shape inclined toward the outer side of the lower semiconductor layer 210 with respect to a plane along the second direction y and perpendicular to the substrate upper surface 113. doing.
As shown in FIG. 4B, the lower semiconductor layer 210 has a boundary portion (that is, a second straight line portion) between the second lower semiconductor side surface 212 and the lower semiconductor upper surface 213 along the first direction x. The thickness becomes thinner toward 232).

Next, the configuration of the connection part 233 and the connection side surface 235 in the lower semiconductor layer 210 will be described. 5 is a cross-sectional view taken along the line VV in FIG. 2, and is a vertical cross-sectional view of the semiconductor light emitting element 1 cut so as to pass through the connection portion 233 and the connection side surface 235. FIG. 6 is a diagram for explaining the structure around the connection portion 233 and the connection side surface 235 of the lower semiconductor layer 210 to which the present embodiment is applied. FIG. 6A is a diagram illustrating the VIA in FIG. FIG. 6B is a view of the lower semiconductor layer 210 in FIG. 6A viewed from the VIB direction.
Here, in FIG. 6B, the lower semiconductor bottom surface 214 is projected onto the lower semiconductor upper surface 213, and the lower semiconductor bottom surface 214 projected onto the lower semiconductor upper surface 213 is indicated by a one-dot chain line. ing. In FIG. 6B, illustration of the substrate 100 and the upper semiconductor layer 250 is omitted.

  As shown in FIGS. 5 and 6A, the connection side surface 235 of the lower semiconductor layer 210 includes a vertical portion 235a extending from the connection portion 233 of the lower semiconductor upper surface 213 toward the substrate 100, and a vertical portion 235a. And an inclined portion 235b extending toward the substrate upper surface 113 from below the vertical portion 235a. The vertical portion 235a is provided along the third direction z, and the angle formed by the vertical portion 235a and the inclined portion 235b is an obtuse angle.

As shown in FIG. 6A, if the angle formed by the vertical portion 235a of the connection side surface 235 and the lower semiconductor upper surface 213 is θ3a, in this embodiment, θ3a is approximately 90 °.
Furthermore, if the angle formed by the inclined portion 235b of the connection side surface 235 and the lower semiconductor bottom surface 214 is θ3b, θ3b is an obtuse angle (θ3b> 90 °). In this embodiment, θ3b is larger than θ1b and θ2b (θ3b> θ1b, θ3b> θ2b).
As shown in FIG. 5, the inclined portion 235 b has a shape inclined with respect to a plane perpendicular to the substrate upper surface 113. In addition, the shape of the inclined portion 235b gradually changes along the vertical portion 235a from the lower semiconductor bottom surface 214 side toward the vertical portion 235a side.

  Here, the lower semiconductor layer 210 of the present embodiment has a thickness along the third direction z in the vicinity of the connection side surface 235 because the connection side surface 235 includes the vertical portion 235a and the inclined portion 235b. Yes. Specifically, as shown in FIG. 6A, in the connection side surface 235 of the present embodiment, the height of the vertical portion 235a is H (> 0), thereby the lower semiconductor layer 210. The thickness of the connecting portion 233 is H.

Further, as described above, the connection portion 233 of the lower semiconductor upper surface 213 has an arc shape when the lower semiconductor upper surface 213 is viewed from the side where the n-electrode 400 is formed.
As shown in FIG. 6B, when the lower semiconductor upper surface 213 is viewed along the third direction z from the side where the n-electrode 400 is formed, the connecting portion 233 is connected to the first linear portion 231. The extension line and the extension line of the second straight portion 232 are located on the inner side of the intersection. Thereby, when the connection part 233 is seen along the 3rd direction z, the extension line of the 1st straight line part 231 and the 1st straight line part 231, and the extension line of the 2nd straight line part 232 and the 2nd straight line part 232 are seen. (See also FIG. 2).

Here, conventionally, in the semiconductor light emitting device 1 having the structure in which the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 of the lower semiconductor layer 210 are inclined with respect to the direction perpendicular to the substrate upper surface 113, There was a tendency for the lower semiconductor layer 210 and the like to break easily. In FIGS. 6A and 6B, an example of the outer edge of the lower semiconductor layer 210 in the conventional semiconductor light emitting device 1 having such an inclined structure is indicated by a broken line.
In the conventional semiconductor light emitting device 1 having the structure in which the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 are inclined with respect to the direction perpendicular to the substrate upper surface 113, the lower semiconductor upper surface 213 in the lower semiconductor layer 210. Has a substantially rectangular shape. That is, the lower semiconductor upper surface 213 in the conventional semiconductor light emitting device 1 does not have the connection portion 233 as shown by a broken line in FIG. 6B, and the first straight portion 231 and the second straight portion 232. Is crossing. That is, in the conventional semiconductor light emitting device 1, the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212 directly intersect, and the lower semiconductor upper surface 213 and the first lower semiconductor side surface are crossed. A corner pointed to the outside of the lower semiconductor layer 210 (hereinafter, referred to as a pointed portion) is formed at a boundary portion between 211 and the second lower semiconductor side surface 212.

  The side surfaces of the lower semiconductor layer 210 (the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212) are inclined with respect to the lower semiconductor upper surface 213 and the lower semiconductor bottom surface 214. At the pointed portion located at the boundary between the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212, as shown by a broken line in FIG. The thickness decreases from the center to the outside. Thereby, in the conventional semiconductor light emitting device 1, the strength of the pointed portion of the lower semiconductor layer 210 is lower than that of other regions.

Further, in the conventional semiconductor light emitting device 1, the pointed portion of the lower semiconductor layer 210 protrudes as compared with other portions. For example, when the semiconductor light emitting device 1 is manufactured or the semiconductor light emitting device 1 is applied to a lamp. During the operation, the tip of the lower semiconductor layer 210 is likely to collide with other members.
Here, generally, in a member having a pointed shape, when an external force is applied to the pointed portion, the force is difficult to disperse and the force tends to concentrate on the pointed portion. For example, in the conventional semiconductor light emitting device 1, when the lower semiconductor layer 210 hits another member or the like and a force is applied to the lower semiconductor layer 210 from the outside, the force is applied to the lower semiconductor layer 210. It is easy to concentrate on the tip.
In the conventional semiconductor light emitting device 1, since the tip of the lower semiconductor layer 210 is thin as described above, the lower semiconductor layer 210 is placed on the tip when the force applied from the outside is concentrated. There is a concern that it is easy to lack.

On the other hand, in the semiconductor light emitting device 1 of the present embodiment, the connection side surface 235 is formed between the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 in the lower semiconductor layer 210. . Further, in the semiconductor light emitting device 1 according to the present embodiment, when the lower semiconductor layer 210 is viewed from the third direction z, the first straight line portion 231 and the second straight line portion 232 at the upper surface periphery 230 of the lower semiconductor upper surface 213. A connection portion 233 that is a boundary between the connection side surface 235 and the lower semiconductor upper surface 213 is formed between the connection surface 235 and the connection surface 233. The connection portion 233 is surrounded by the extension lines of the first straight portion 231 and the first straight portion 231 and the extension lines of the second straight portion 232 and the second straight portion 232 when viewed from the third direction z. It is located inside the rectangle.
That is, in the semiconductor light emitting device 1 of the present embodiment, in the lower semiconductor layer 210, the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212 do not cross each other directly. The tip as in the example is not formed.

  Thereby, in this Embodiment, the protrusion amount of the lower side semiconductor layer 210 is small compared with the conventional semiconductor light emitting element 1 which has a pointed part. As a result, in the semiconductor light emitting device 1 of the present embodiment, the lower semiconductor layer 210 can be prevented from colliding with other semiconductor light emitting devices 1 and other members. In the semiconductor light emitting device 1 of the present embodiment, the lower semiconductor layer 210 is prevented from colliding with other members and the like, so that the stacked semiconductor layer 200 (lower side) is compared with the case where this configuration is not adopted. It is possible to suppress the occurrence of cracks and chips in the semiconductor layer 210).

  Further, in the semiconductor light emitting device 1 of the present embodiment, the connection portion 233 of the lower semiconductor upper surface 213 has an arc shape when viewed from the third direction z. That is, the connection part 233 has a shape in which the force is easily dispersed as compared with the case where the connection part 233 has a sharp shape. Thereby, in the present embodiment, for example, when force is applied from the outside via the lower semiconductor upper surface 213, concentration of force in the lower semiconductor layer 210 is suppressed as compared with the case where this configuration is not adopted. it can. As a result, in the semiconductor light emitting device 1 of the present embodiment, this configuration is not adopted even when the connection part 233 of the lower semiconductor layer 210 collides with another semiconductor light emitting device 1 or another member. Compared to the case, it is possible to suppress the occurrence of cracking and chipping of the laminated semiconductor layer 200 (lower semiconductor layer 210).

Furthermore, as described above, in the semiconductor light emitting device 1 of the present embodiment, the lower semiconductor layer 210 has a thickness H (> 0) at the connection portion 233. That is, the lower semiconductor layer 210 of the present embodiment does not have a thickness at the first straight portion 231 and the second straight portion 232 as described above, but has a thickness at the connection portion 233. .
Thereby, for example, the strength of the lower semiconductor layer 210 can be increased as compared with the case where the lower semiconductor layer 210 does not have a thickness at the tip as in the conventional example. Thereby, compared with the case where this structure is not employ | adopted, it becomes possible to suppress generation | occurrence | production of the crack and notch | chip of the lower semiconductor layer 210 in the semiconductor light-emitting device 1. FIG.

In addition, the thickness (height of the vertical portion 235a on the connection side surface 235) H at the boundary between the connection side surface 235 and the lower semiconductor upper surface 213 in the lower semiconductor layer 210 is the thickness of the lower semiconductor layer 210 (that is, lower The distance between the side semiconductor upper surface 213 and the lower semiconductor bottom surface 214 in the third direction z) is preferably ½ or less.
By setting the height of the vertical portion 235a within such a range, for example, the area of the inclined portion 235b is larger than when the height H is larger than ½ of the thickness of the lower semiconductor layer 210. Become. Thereby, compared with the case where this structure is not employ | adopted, the light output from the light emitting layer 204 (refer FIG. 3 etc.) of the semiconductor light emitting element 1 (refer FIG. 1) is the semiconductor light emitting element 1 via the inclination part 235b. Thus, the output of the semiconductor light emitting element 1 can be prevented from being lowered.

Here, in the semiconductor light emitting device 1 of the present embodiment, as shown in FIG. 6B, the second straight line at the bottom peripheral edge 240 (see FIG. 2) of the lower semiconductor bottom surface 214 projected onto the lower semiconductor top surface 213. Let X be the shortest distance between the portion 242 and the second straight portion 232 at the upper surface periphery 230 (see FIG. 2). Similarly, Y is the shortest distance between the first straight line portion 241 at the bottom surface periphery 240 projected onto the lower semiconductor upper surface 213 and the first straight line portion 231 at the upper surface periphery 230.
Further, as shown in FIG. 6B, the distance from the intersection of the first straight portion 241 and the second straight portion 242 at the bottom surface periphery 240 to the center of the connection portion 233 at the top surface periphery 230 is L. In this example, the central portion of the connecting portion 233 is defined as the extension line of the first straight portion 231 of the upper surface periphery 230 and the second line from the intersection of the first straight portion 241 and the second straight portion 242 of the bottom surface periphery 240. A straight line extending to the intersection with the extension line of the straight line portion 232 (that is, a straight line connecting the shortest distance between the intersection line of the extension line of the first straight line portion 231 and the extension line of the second straight line portion 232 and the bottom surface periphery 240). The point which crosses the connection part 233.
In the present embodiment, the distance L is preferably in a range represented by the following formula.
L ² = A × (X ² + Y ² ) 0 <A ≦ 0.95 (1)

By setting the distance L within the range represented by the expression (1), the amount of protrusion of the lower semiconductor layer 210 at the connection portion 233 and the connection side surface 235 can be reduced as compared with the case where this configuration is not adopted. . Here, when the protruding amount of the lower semiconductor layer 210 is large, as described above, when the lower semiconductor layer 210 receives a force, the force tends to concentrate on the protruding portion, and the lower semiconductor layer 210 is damaged. It tends to be easy to do.
Therefore, by reducing the protruding amount of the lower semiconductor layer 210 as in this embodiment, it is possible to suppress the occurrence of chipping, cracking, and the like of the lower semiconductor layer 210 as compared with the case where this configuration is not adopted. Is possible.

  In the semiconductor light emitting device 1 of the present embodiment, as described above, the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 of the lower semiconductor layer 210 are the lower semiconductor upper surface 213 and the lower semiconductor, respectively. Inclined with respect to the bottom surface 214. Accordingly, the lower semiconductor layer 210 includes a boundary portion (first linear portion 231) between the first lower semiconductor side surface 211 and the lower semiconductor upper surface 213, and the second lower semiconductor side surface 212 and the lower semiconductor upper surface 213. The boundary portion (second straight portion 232) is thin, and has a sharp shape in the longitudinal section (see FIGS. 4A and 4B).

However, the first linear portion 231 and the second linear portion 232 have a substantially linear shape when viewed from a direction perpendicular to the lower semiconductor upper surface 213. Therefore, for example, even when an external force is applied to the vicinity of the first straight line portion 231 or the second straight line portion 232 of the lower semiconductor layer 210 via the lower semiconductor upper surface 213, the first straight line portion 231 or the second straight line portion 231 It is difficult for the force to concentrate on the two straight portions 232.
Therefore, even when the lower semiconductor layer 210 has a sharp shape in the longitudinal section in the first straight portion 231 and the second straight portion 232, chipping, cracking, etc. in the lower semiconductor layer 210 are not caused. Hard to occur.

In the present embodiment, the shape of the connection portion 233 when viewed from the third direction z is an arc shape, but the shape of the connection portion 233 is not limited to this. As described above, if the connection part 233 is located inside the intersection of the extension line of the first straight line part 231 and the extension line of the second straight line part 232, the connection part 233 viewed from the third direction z will be described. The shape may be a linear shape, a curved shape, a broken line shape, or a combination thereof.
In addition, the first straight portion 231 and the second straight portion 232 described above do not have to be strictly perfectly linear, and even if a part that is bent or uneven is formed as a whole, Any form that can approximate a straight line is acceptable.

In this embodiment, the semiconductor light emitting element 1 has a substantially rectangular parallelepiped shape, and the semiconductor light emitting element 1 viewed from the side where the p electrode 350 and the n electrode 400 are formed is substantially rectangular. Although demonstrated, the shape of the semiconductor light-emitting device 1 is not restricted to this.
For example, if the lower semiconductor layer 210 has the connection part 233 and the connection side surface 235 as described above, the shape of the semiconductor light emitting element 1 viewed from the side where the p electrode 350 and the n electrode 400 are formed is a square or It may be a shape approximated to a parallelogram, or may be a shape approximated to a polygon other than a quadrangle (such as a triangle or a hexagon).

(Manufacturing method of semiconductor light emitting device)
Then, the manufacturing method of the semiconductor light-emitting device 1 of this Embodiment is demonstrated. In the present embodiment, the laminated semiconductor layer 200 is laminated on the wafer-like substrate 100, and a plurality of transparent conductive layers 300, p-electrodes 350, n-electrodes 400, and the like are formed on the laminated semiconductor layer 200. By dividing this, a plurality of semiconductor light emitting elements 1 are obtained. FIG. 7 is a flowchart showing an example of a method for manufacturing the semiconductor light emitting device 1 to which the present exemplary embodiment is applied.

In this example, first, a semiconductor lamination process is performed in which a laminated semiconductor layer 200 is laminated on a wafer-like substrate 100 to form a wafer-like semiconductor laminated substrate 20 (see FIG. 8 described later) (step 101).
Next, a mask forming process is performed for forming a mask 51 (see FIG. 8 described later) made of SiO ₂ or the like on the laminated semiconductor layer 200 of the semiconductor laminated substrate 20 formed in Step 101 (Step 102). .
Next, a transparent conductive layer forming step for forming the transparent conductive layer 300 on the laminated semiconductor layer 200 of the semiconductor laminated substrate 20 on which the mask 51 is formed in step 102 is executed (step 103).
Subsequently, a resist forming step is performed in which a resist 61 (see FIG. 9 described later) is formed on the laminated semiconductor layer 200 and the transparent conductive layer 300 of the semiconductor laminated substrate 20 on which the transparent conductive layer 300 is formed in Step 103. (Step 104).
Next, a part of the laminated semiconductor layer 200 is removed by etching from the semiconductor laminated substrate 20 on which the resist 61 has been formed in Step 104, whereby a plurality of first groove parts 71 and a plurality of second groove parts 72 ( In both cases, a first etching process is performed to form (see FIG. 10 described later) and the like (step 105).
In the present embodiment, the mask formation process in step 102, the resist formation process in step 104, and the first etching process in step 105 correspond to the semiconductor removal process.

Next, an n-electrode 400 and a p-electrode 350 are formed on the laminated semiconductor layer 200 and the transparent conductive layer 300 of the semiconductor laminated substrate 20 from which part of the laminated semiconductor layer 200 has been removed in step 105, respectively, and the laminated semiconductor An electrode forming process for forming the protective film 500 on the layer 200 and the transparent conductive layer 300 is performed (step 106).
Subsequently, with respect to the semiconductor laminated substrate 20 on which the n electrode 400, the p electrode 350, and the protective film 500 are formed in Step 106, the first step is performed from the surface side of the semiconductor laminated substrate 20 on which the n electrode 400 and the p electrode 350 are formed. A laser beam is irradiated along the one direction x and the second direction y to perform a surface laser process for forming a first irradiation line 81 and a second irradiation line 82 (both refer to FIG. 11 described later) (step 107). ).
Next, a second etching process as an example of a wet etching process is performed on the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in Step 107 (Step 108).
Next, the semiconductor multilayer substrate 20 that has been wet-etched in step 108 is divided along the first irradiation line 81 and the second irradiation line 82, thereby dividing the plurality of semiconductor light emitting devices 1 (FIG. 1). A dividing step for obtaining a reference) is executed (step 109).
In the present embodiment, the surface laser process in step 107 corresponds to the dividing groove forming process, and the second etching process in step 108 corresponds to the wet etching process.

Then, the process of each step mentioned above is demonstrated in order.
(Semiconductor lamination process)
In the semiconductor lamination process of step 101, first, a wafer-like substrate 100 (see FIG. 1) made of a sapphire single crystal having a C-plane as a main surface is prepared, and surface processing is performed. As the surface processing, for example, wet etching, dry etching, sputtering, or the like is used to form a plurality of convex portions 113a (see FIG. 3) on the substrate upper surface 113 (see FIG. 1) of the wafer-like substrate 100. .

  Next, an intermediate layer 201 (see FIG. 3) made of AlN is formed on the wafer-like substrate 100 subjected to surface processing by sputtering or the like. Note that the intermediate layer 201 can be formed not only by sputtering but also by MOCVD.

Subsequently, with respect to the wafer-like substrate 100 on which the intermediate layer 201 is formed, a base layer 202 made of a group III nitride, an n-type semiconductor layer 203 (n-contact layer 203a, n-cladding layer 203b), light-emitting layer 204, and p A stacked semiconductor layer 205 (a p-clad layer 205a and a p-contact layer 205b) is sequentially stacked to form a semiconductor stacked substrate 20 (see FIG. 8 described later) in which a stacked semiconductor layer 200 is stacked on a wafer-like substrate 100 (see FIG. 8 described later). (See FIG. 3).
As a method for laminating these layers, methods such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), and sputtering can be used. it can. A particularly preferable lamination method is MOCVD from the viewpoint of film thickness controllability and mass productivity.

Here, in the present embodiment, a plurality of convex portions 113 a are formed on the substrate upper surface 113 of the substrate 100. When the intermediate layer 201 made of AlN, the base layer 202 made of a group III nitride semiconductor layer such as GaN, the n-contact layer 203a, and the like are laminated on the substrate upper surface 113 of the substrate 100, first, the substrate is perpendicular to the substrate upper surface 113. A plurality of island-like crystals extending in a certain direction are formed. When the lamination is further continued, the group III nitride grows in a direction perpendicular to the substrate upper surface 113, and a plurality of island-like crystals are connected to each other, so that a flat crystal growth surface is obtained.
Therefore, the intermediate layer 201, the base layer 202, the n contact layer 203a, and the like in the lower semiconductor layer 210 of this embodiment are gradually increased from the lower semiconductor bottom surface 214 side to the lower semiconductor upper surface 213 side. It is formed so that the crystallinity of the group nitride is improved.
As a result, the lower semiconductor layer 210 as a whole is formed so that the crystallinity of the group III nitride gradually improves from the lower semiconductor bottom surface 214 side toward the lower semiconductor upper surface 213 side.

  Further, in the present embodiment, when the laminated semiconductor layer 200 is laminated on the substrate 100 made of sapphire by the MOCVD method, the group III nitride constituting the laminated semiconductor layer 200 is an N-polar plane (000− 1) The crystal faces so that the surface faces the substrate upper surface 113 side of the substrate 100 and the (0001) surface, which is a group III element polar surface (for example, Ga polar surface), faces the upper semiconductor upper surface 253 side of the upper semiconductor layer 250. grow up.

(Mask formation process)
Next, the mask formation process in step 102 will be described.
FIG. 8 is a view showing the semiconductor laminated substrate 20 after the formation of the mask 51 obtained by executing the mask forming step. 8A is a top view of the semiconductor multilayer substrate 20 after the mask 51 is formed as viewed from the side on which the mask 51 is formed. FIG. 8B is an enlarged view of a part of FIG. 8 (c) is a cross-sectional view taken along the line VIIIC-VIIIC of FIG. 8 (b).

In the mask formation process of step 102, a mask 51 as an example of a removal suppression layer is formed on the stacked semiconductor layer 200 of the semiconductor stacked substrate 20 obtained in the semiconductor stacking process of step 101.
A portion of the mask 51 on the laminated semiconductor layer 200 corresponds to a planned formation position (hereinafter referred to as an element formation planned position) of a plurality of semiconductor light emitting elements 1 (see FIG. 1) formed from the semiconductor laminated substrate 20. It is laminated on the area.

In the present embodiment, formation planned positions (hereinafter referred to as element formation planned positions) of a plurality of semiconductor light emitting elements 1 (see FIG. 1) formed from the semiconductor multilayer substrate 20 with respect to the semiconductor multilayer substrate 20 are in a matrix form. Is set.
The mask 51 is provided along the first direction x and the second direction y so as to surround the periphery of the element formation scheduled position. In the mask 51, a plurality of first holes 52 provided corresponding to the respective element formation scheduled positions are formed. The mask 51 has second holes 53 formed at the four corners of the respective element formation scheduled positions and at the centers of the four adjacent element formation planned positions.
As shown in FIG. 8A, the laminated semiconductor layer 200 is exposed from the first hole 52 and the second hole 53. Note that a mask 51 is formed in a region corresponding to the semiconductor exposed surface 213a (see FIG. 1) in the element formation scheduled position, and the stacked semiconductor layer 200 is not exposed.

As shown in FIGS. 8A and 8B, each first hole 52 has a shape approximate to a rectangle when viewed from the third direction z.
As shown in FIGS. 8 (a) and 8 (b), each of the second holes 53 has four outer peripheral sides facing each other in a circular arc having a central angle of 90 degrees so that the four corners at the element formation scheduled positions are arcuate. It has a different shape. As a result, second holes 53 having a shape extending in a cross shape in the first direction x and the second direction y (hereinafter sometimes referred to as a cross shape) are formed at the four corners of each element formation scheduled position. Yes.

The mask 51 is used to adjust the thickness or the like of the stacked semiconductor layer 200 to be removed when part of the stacked semiconductor layer 200 is removed by an etching process in a first etching process of Step 105 described later. Although details will be described later, in the first etching step of Step 105, the stacked semiconductor layer 200 is removed by an etching method such as wet etching or dry etching.
As the mask 51 of the present embodiment, it is preferable to use a material that can be removed together with the stacked semiconductor layer 200 by an etching solution such as an acid or an etching gas used for etching in the first etching process of Step 105. Examples of the material used for such a mask 51 include, but are not limited to, SiO _{2 and the} like.

Further, the thickness of the mask 51 is the thickness of the laminated semiconductor layer 200 to be removed in the first etching process of Step 105, the thickness of the laminated semiconductor layer 200 to be left without being removed, the kind of etching solution or etching gas used for the etching, etc. Is set according to When SiO ₂ is used as the mask 51, the thickness of the mask 51 is preferably in the range of 0.01 μm to 5 μm, and more preferably in the range of 0.05 μm to 1 μm.

The mask 51 can be formed by a conventionally known CVD method, vapor deposition method, sputtering method, or the like.
In addition, in order to form the first hole 52 and the second hole 53 in the mask 51 so that the mask 51 has the above-described shape, a resist pattern is formed by a conventionally known photolithography method, and a conventionally known etching is performed. A method of removing a portion of the mask 51 not covered with a resist by a method or the like can be used.
The formation method of the mask 51 is not limited to this, and a conventionally known method can be used as appropriate.

(Transparent conductive layer forming process)
Next, the transparent conductive layer forming process in step 103 will be described.
The transparent conductive layer 300 (see FIG. 9 and the like described later) is exposed to the plurality of first holes 52 in the mask 51 formed in step 102 so as to correspond to each of a plurality of element formation scheduled positions. Provided on top.

For the transparent conductive layer 300, for example, a translucent conductive material made of an oxide containing In can be used.
The transparent conductive layer 300 can be formed by providing these materials on the laminated semiconductor layer 200 by conventional means well known in this technical field. In addition, after forming the transparent conductive layer 300 on the laminated semiconductor layer 200, a thermal annealing treatment may be performed for the purpose of making the transparent conductive layer 300 transparent or reducing resistance.

(Resist formation process)
Next, the resist forming process in step 104 will be described.
FIG. 9 is a diagram showing the semiconductor laminated substrate 20 after the formation of the transparent conductive layer 300 and the resist 61 obtained by executing the steps up to the resist formation step of Step 104. FIG. 9A is a top view of a part of the semiconductor laminated substrate 20 after the transparent conductive layer 300 and the resist 61 are formed as viewed from the side on which the transparent conductive layer 300 and the resist 61 are formed. 9B is a cross-sectional view taken along the line IXB-IXB in FIG. 9A, FIG. 9C is a cross-sectional view taken along the line IXC-IXC in FIG. 9A, and FIG. FIG. 10 is a cross-sectional view taken along IXD-IXD in FIG.

As shown in FIGS. 9A to 9D, a resist 61 as another example of the removal suppressing layer is a stacked semiconductor layer exposed from the first hole 52 in the mask 51 formed in the mask forming process of Step 102. 200 and on the transparent conductive layer 300 formed in step 103. Note that the resist 61 is not provided on the mask 51 and the stacked semiconductor layer 200 exposed from the second hole 53.
As the resist 61, a conventionally known material can be used. As a method for forming the resist 61, a conventionally known photolithography method or the like can be employed.

(First etching process)
Subsequently, the first etching process of Step 105 will be described.
FIG. 10 is a diagram illustrating the semiconductor multilayer substrate 20 after the first groove 71, the second groove 72, the recess 73, and the semiconductor exposed surface 213a are formed, which is obtained by performing the first etching process of Step 105. . FIG. 10A is a top view of a part of the semiconductor laminated substrate 20 after the first groove 71 and the second groove 72 are formed, as viewed from the side where the first groove 71, the second groove 72, and the like are formed. . 10B is a cross-sectional view taken along the line XB-XB in FIG. 10A, FIG. 10C is a cross-sectional view taken along the line XC-XC in FIG. 10A, and FIG. It is XD-XD sectional drawing of Fig.10 (a).

  In the first etching process of Step 105, the n-contact layer 203a (FIG. 3) is removed by removing a part of the stacked semiconductor layer 200 from the semiconductor stacked substrate 20 on which the resist 61 is formed by the resist formation process of Step 104. Expose a part of Thereby, the 1st groove part 71, the 2nd groove part 72, the recessed part 73, and the semiconductor exposed surface 213a are formed.

As shown in FIG. 10A, a plurality of first groove portions 71 are formed, and each is provided along the first direction x. The plurality of first groove portions 71 are arranged substantially parallel to each other so that the intervals between the adjacent first groove portions 71 are equal. Similarly, a plurality of second groove portions 72 are formed, and each is provided along the second direction y. The plurality of second groove portions 72 are arranged substantially parallel to each other so that the intervals between the adjacent second groove portions 72 are equal.
In the present embodiment, the interval between adjacent first groove portions 71 is narrower than the interval between adjacent second groove portions 72.
A plurality of exposed semiconductor surfaces 213a are formed. In this example, the plurality of exposed semiconductor surfaces 213 a are arranged side by side along the second direction y, and each of them is connected to the second groove portion 72.

As shown in FIGS. 10A to 10D, the first groove 71 and the second groove 72 are formed, so that the laminated semiconductor layer 200 is provided over the entire area of the wafer-like substrate 100. A side semiconductor layer 210 and an upper semiconductor layer 250 provided on the lower semiconductor layer 210 and separated into a plurality of regions by the first groove portion 71 and the second groove portion 72 are formed.
As shown in FIG. 10A, the shape of the upper semiconductor layer 250 viewed from the third direction z is a rectangle with the long side in the direction along the first direction x and the short side in the direction along the second direction y. Approximate.

As shown in FIG. 10A, the recess 73 as an example of the uneven portion is formed in a region where the first groove 71 and the second groove 72 intersect. As shown in FIG. 10B, the recess 73 is provided so as to be further recessed toward the substrate 100 with respect to the first groove 71 and the second groove 72, and an n contact layer 203a (see FIG. 3) is provided. Exposed.
When viewed from the third direction z, the wall surface of the recess 73 has a cross shape in which four arcs face each other as shown in FIG. Each of the arc-shaped wall surfaces constituting the recess 73 corresponds to the shape of the connection portion 233 in the semiconductor light emitting element 1 formed from the semiconductor laminated substrate 20.

An etching method can be used as a method of removing a part of the laminated semiconductor layer 200 in order to form the first groove portion 71, the second groove portion 72, the concave portion 73, and the semiconductor exposed surface 213a. By using the etching method, for example, compared with the case where the laminated semiconductor layer 200 is removed by a method such as a dicing method or a scribe method, it is possible to suppress damage of a portion of the laminated semiconductor layer 200 that is not removed. Become.
As an etching method, for example, dry etching, a reactive ion etching, ion milling, focused beam etching, ECR etching, or the like can be used. For wet etching, for example, sulfuric acid and phosphoric acid are used. Mixed acids can be used.

Etching in the first etching step of Step 105 proceeds from the upper surface side (the side opposite to the substrate 100) of the laminated semiconductor layer 200, and the laminated semiconductor layer 200 is removed from the upper surface side.
Here, in the present embodiment, the mask 51 for adjusting the thickness of the stacked semiconductor layer 200 to be removed by etching in a partial region on the stacked semiconductor layer 200 in the mask formation step of Step 102 described above. (See FIGS. 8 and 9). Further, in the resist forming step of Step 104 described above, a resist 61 (FIG. 9) prevents removal of the stacked semiconductor layer 200 and the transparent conductive layer 300 by etching on a partial region on the stacked semiconductor layer 200 and the transparent conductive layer 300. See).

Thereby, in the region where the mask 51 is formed in the laminated semiconductor layer 200 in the semiconductor laminated substrate 20, the etching of the laminated semiconductor layer 200 is started after the mask 51 is first removed by etching. Therefore, in the region where the mask 51 is formed, a part of the stacked semiconductor layer 200 is removed, but the region where both the mask 51 and the resist 61 are not formed (second hole 53 (see FIG. 9)). The amount of the stacked semiconductor layer 200 to be removed is small compared to the region exposed from (1).
Further, in the region where the resist 61 is formed in the laminated semiconductor layer 200 and the transparent conductive layer 300, the etching does not proceed, and the laminated semiconductor layer 200 and the transparent conductive layer 300 are not removed.
On the other hand, in the region where both the mask 51 and the resist 61 are not formed in the stacked semiconductor layer 200 (region exposed from the second hole 53), the etching proceeds without being interrupted by the mask 51 and the resist 61.

The etching is preferably terminated when a part of the laminated semiconductor layer 200 is removed and the n contact layer 203a is exposed in the region of the semiconductor laminated substrate 20 where the mask 51 is formed.
As a result, in the region where the mask 51 is formed in the semiconductor multilayer substrate 20, a part of the multilayer semiconductor layer 200 is removed by etching, whereby the first groove portion 71, the second groove portion 72 and the n-contact layer 203a are exposed. A semiconductor exposed surface 213a is formed.
In addition, in a region where both the mask 51 and the resist 61 are not formed (a region exposed from the second hole 53), the stacked semiconductor layer 200 (n contact layer 203a) has a shape of the second hole 53 by etching. As a result, the recess 73 exposing the n contact layer 203a is formed. Since neither the mask 51 nor the resist 61 is formed on the laminated semiconductor layer 200 exposed from the second hole 53, the laminated semiconductor layer is located more than the first groove 71, the second groove 72, and the semiconductor exposed surface 213a. Since 200 is sharpened, the recess 73 is formed to be recessed with respect to the first groove 71 and the second groove 72.
Furthermore, on the laminated semiconductor layer 200 and the transparent conductive layer 300 on which the resist 61 is formed, the laminated semiconductor layer 200 and the transparent conductive layer 300 remain without being removed.

  In the first etching step of Step 105, a part of the laminated semiconductor layer 200 is removed from the semiconductor laminated substrate 20 by the above steps, whereby the first groove portion 71, the second groove portion 72, the concave portion 73, and the semiconductor exposed surface 213a. Are formed, and the lower semiconductor layer 210 and the upper semiconductor layer 250 divided into a plurality of regions are formed.

(Electrode formation process)
Next, the electrode forming process in step 106 will be described.
In the electrode forming process of step 106, a p-electrode 350 (see FIG. 1, FIG. 11 described later) is formed at a predetermined position on each transparent conductive layer 300, and an n-electrode 400 (see FIG. 11) is formed on each semiconductor exposed surface 213a. 1, see FIG.
As the p-electrode 350 and the n-electrode 400, various compositions and structures are known, and these known compositions and structures can be used without any limitation.
In addition, as a means for forming the p electrode 350 and the n electrode 400, a known method such as a vacuum deposition method or a sputtering method can be used without any limitation.
Further, in the electrode formation process of step 106, the upper semiconductor layer 250 is excluded except for a part of the regions (openings) on the surfaces of the p electrode 350 and the n electrode 400 and on the first groove 71 and the second groove 72. A protective film 500 (see FIG. 11 described later) made of SiO ₂ or the like is formed so as to cover the upper surfaces and side surfaces of the transparent conductive layer 300, the p electrode 350, and the n electrode 400.

(Surface laser process)
Next, the surface laser process in step 107 will be described.
FIG. 11 is a diagram showing the semiconductor laminated substrate 20 after the first irradiation line 81 and the second irradiation line 82 are formed, which is obtained by executing the electrode forming process in step 106 and the surface laser process in step 107. . FIG. 11A shows an upper surface of a part of the semiconductor laminated substrate 20 after the first irradiation line 81 and the second irradiation line 82 are formed as viewed from the side where the first irradiation line 81 and the second irradiation line 82 are formed. FIG. 11 (b) is a cross-sectional view taken along the line XIB-XIB in FIG. 11 (a), FIG. 11 (c) is a cross-sectional view taken along the line XIC-XIC in FIG. 11 (a), and FIG. FIG. 11 is a cross-sectional view taken along the line XID-XID in FIG. In FIG. 11A, the protective film 500 is not shown.

  In the surface laser process of step 107, the semiconductor multilayer substrate 20 is irradiated with laser from the side of the laminated semiconductor layer 200 along the first groove 71 and the second groove 72 formed in the first etching process of step 105. Then, by removing a part of the laminated semiconductor layer 200, the first irradiation line 81 and the second irradiation line 82 as an example of the dividing groove are formed.

As shown in FIG. 11A, the first irradiation line 81 is formed along the first groove 71 and along the first direction x. Further, as shown in FIG. 11D, the first irradiation line 81 is formed so as to separate the stacked semiconductor layer 200 (lower semiconductor layer 210) and reaches the inside of the substrate 100.
Similarly, as shown in FIG. 11A, the second irradiation line 82 is formed along the second groove 72 and along the second direction y. The second irradiation line 82 is formed so as to separate the stacked semiconductor layer 200 as shown in FIG. 11C and reaches the inside of the substrate 100.
Thereby, the lower semiconductor layer 210 is separated into a plurality of portions by the first irradiation line 81 and the second irradiation line 82.

Further, as described above, the concave portion 73 (see FIG. 10) is provided at the portion where the first groove portion 71 and the second groove portion 72 intersect, and the first irradiation line 81 and the second irradiation line 82 are: It is provided so as to intersect at the recess 73. And as shown to Fig.11 (a), the recessed part 73 is isolate | separated by the 1st irradiation line 81 and the 2nd irradiation line 82, and when it sees from the 3rd direction z, the curved surface 74a of the curved shape is obtained. Four steps 74 are formed.
FIG. 12 is a view showing the structure in the vicinity of the step 74 in the lower semiconductor layer 210 after completion of the surface laser process in step 104. In FIG. 12, one step 74 is shown among a plurality of (four) steps 74 formed by separating the recess 73 by the first irradiation line 81 and the second irradiation line 82.

As shown in FIGS. 12 and 11A, in the lower semiconductor layer 210 in which the first irradiation line 81 and the second irradiation line 82 are formed in the surface laser process of Step 107, the lower semiconductor layer 210 is in contact with the upper semiconductor layer 250. On the side semiconductor upper surface 213 side, the curved surface 74a is formed to have a so-called rounded rectangular shape in which the corner portion has an arc shape when viewed from the third direction z. On the other hand, the lower semiconductor bottom surface 214 in contact with the substrate 100 in the lower semiconductor layer 210 has a rectangular shape when viewed from the third direction z.
Accordingly, the lower semiconductor layer 210 has a substantially rectangular parallelepiped shape as a whole, and the curved surface 74a forms steps 74 having arc-shaped curved surfaces 74a at the four corners when viewed from the third direction z. Will be.

(Second etching process)
Subsequently, the second etching process of Step 108 will be described.
FIG. 13 is a view showing the semiconductor laminated substrate 20 obtained by executing the second etching process of Step 108. FIG. 13A is a top view of a part of the semiconductor multilayer substrate 20 after the wet etching is viewed from the side where the p-electrode 350 and the n-electrode 400 are formed. 13B is a cross-sectional view taken along line XIIIB-XIIIB in FIG. 13A, FIG. 13C is a cross-sectional view taken along line XIIIC-XIIIC in FIG. 13A, and FIG. It is XIIID-XIIID sectional drawing of Fig.13 (a). In FIG. 13A, the protective film 500 is not shown.

In the second etching step of step 108, the first lower semiconductor side surface 211 (by the wet etching of the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in the surface laser step of step 107. 1), a second lower semiconductor side surface 212 (see FIG. 2) and a connection side surface 235 (see FIG. 1) are formed.
In the wet etching, an etching solution such as orthophosphoric acid in which the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed is heated to a predetermined temperature while the protective film 500 is formed. It is performed by dipping in

  When the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in the surface laser process of step 107 is immersed in an etching solution, the etching solution is in the first irradiation line 81 and the second irradiation line 82. Infiltrate inside. In the first irradiation line 81 and the second irradiation line 82, the lower semiconductor layer 210 is exposed. Therefore, the exposed lower semiconductor layer 210 is eroded by the etchant that has entered the first irradiation line 81 and the second irradiation line 82. On the other hand, the protective film 500, the transparent conductive layer 300 covered by the protective film 500, and the upper semiconductor layer 250 are not eroded by the etching solution.

  Here, in the present embodiment, the lower semiconductor layer 210 includes a side facing the upper semiconductor layer 250 (lower semiconductor upper surface 213 side) and a side facing the substrate 100 (lower semiconductor bottom surface 214 side). The ease of erosion by the etching solution is different. Specifically, compared to the lower semiconductor upper surface 213 side of the lower semiconductor layer 210, the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 is more easily eroded by the etching solution.

This is due to the following reason.
In general, the AlN constituting the intermediate layer 201 (see FIG. 3) of the present embodiment is the AlGaN or GaN constituting the base layer 202 (see FIG. 3) and the n contact layer 203a (see FIG. 3) of the present embodiment. Compared with InGaN or the like, it has a property of being easily eroded by an etching solution such as orthophosphoric acid.
Further, as described above, in this embodiment, the intermediate layer 201, the base layer 202, and the n contact layer 203 a constituting the lower semiconductor layer 210 are each in contact with the upper semiconductor layer 250 from the side close to the substrate 100. The crystallinity is gradually improved toward.
Furthermore, as described above, the group III nitride semiconductor constituting the lower semiconductor layer 210 in the present embodiment grows so that the N-polar surface faces the substrate upper surface 113 of the substrate 100. In general, when a group III nitride semiconductor is wet-etched, it is known that etching proceeds from the N-polar surface side.

For the above reason, the lower semiconductor layer 210 of this embodiment is more easily eroded by the etching solution on the lower semiconductor bottom surface 214 side than on the lower semiconductor upper surface 213 side.
Therefore, in the portion of the lower semiconductor layer 210 excluding the step 74, the etching proceeds, and as shown in FIGS. 13C and 13D, the lower semiconductor bottom surface 214 side is closer to the lower semiconductor upper surface. Sharper than the 213 side. 13C and 13D, the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 that are inclined with respect to the direction perpendicular to the substrate upper surface 113 of the substrate 100 are formed. become.

On the other hand, in the region of the lower semiconductor layer 210 where the step 74 is formed, the etching progresses differently from the region where the step 74 is not formed. Subsequently, etching at the step 74 of the lower semiconductor layer 210 will be described.
FIG. 14 is a diagram for explaining the progress of wet etching in the vicinity of the step 74 of the lower semiconductor layer 210. FIG. 14A is a top view of the vicinity of the step 74 of the lower semiconductor layer 210 in the semiconductor laminated substrate 20 as viewed from the lower semiconductor upper surface 213 side, and FIG. 14B is the same as FIG. It is XIVB-XIVB sectional drawing. In FIG. 14, the upper semiconductor layer 250 and the protective film 500 are not shown.

  Here, in the lower semiconductor layer 210 located in the region surrounded by the first irradiation line 81 and the second irradiation line 82, the direction perpendicular to the substrate upper surface 113 (third direction) like the curved surface 74 a in the step 74. When there is a surface extending in z), the laminated semiconductor layer 200 (depending on the shape of the curved surface 74a by wet etching, on the inner side of the curved surface 74a (the side away from the first irradiation line 81 and the second irradiation line 82) ( The lower semiconductor layer 210) is removed.

Therefore, in the wet etching performed in the second etching process of the present embodiment, the lower semiconductor layer 210 maintains the shape of the curved surface 74a in the step 74 as shown in FIG. Then, it is eroded toward the inside of the lower semiconductor layer 210.
That is, as shown in FIG. 14A, the lower semiconductor layer 210 is removed from the curved surface 74a toward the inside of the lower semiconductor layer 210 so as to exhibit an arc shape when viewed from the third direction z. Will be.
As a result, as shown in FIGS. 14A and 14B and FIG. 1, a vertical portion 235a extending along the third direction z and having an arc shape when viewed from the third direction z is formed. A connecting portion 233 having an arc shape is formed at the boundary between the semiconductor upper surface 213 and the vertical portion 235a.

On the other hand, in the step 74 of the lower semiconductor layer 210, in the region closer to the lower semiconductor bottom surface 214 than the curved surface 74a (the lower step in the step 74), Similarly, the closer to the substrate 100, the easier the etching proceeds.
Therefore, as shown in FIG. 14B, in the step 74, in the region on the lower semiconductor bottom surface 214 side than the curved surface 74a, the lower semiconductor bottom surface 214 side is sharpened more than the lower semiconductor top surface 213 side. . Thereby, an inclined portion 235b inclined with respect to the direction perpendicular to the substrate upper surface 113 of the substrate 100 and the vertical portion 235a is formed.

  As described above, the connection side surface 235 having the vertical portion 235a and the inclined portion 235b is formed between the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 by the second etching step of step 108. Will be. Then, on the lower semiconductor upper surface 213 of the lower semiconductor layer 210, the first straight portion 231, the second straight portion 232, and the connection portion 233 are formed.

(Division process)
In the dividing process of step 109, the semiconductor multilayer substrate 20 in which the lower semiconductor layer 210 is separated into a plurality of regions by the second etching process of step 108 is cut and divided into a plurality of semiconductor light emitting elements 1.
Before the semiconductor multilayer substrate 20 is divided into a plurality of semiconductor light emitting elements 1, a step of grinding and polishing the substrate bottom surface 114 of the substrate 100 is provided so that the substrate 100 in the semiconductor multilayer substrate 20 has a predetermined thickness. Also good.
The thickness of the substrate 100 after grinding and polishing is 60 μm to 300 μm, preferably 80 μm to 250 μm, more preferably 100 μm to 200 μm. By setting the thickness of the substrate 100 within the above range, it is possible to efficiently divide the semiconductor laminated substrate 20 in the dividing step of Step 109.

In the dividing step of step 109, first, from the substrate bottom surface 114 (see FIG. 3) side of the wafer-like substrate 100 in the semiconductor laminated substrate 20, along the first irradiation line 81 and the second irradiation line 82, the inside of the substrate 100. Irradiate laser. Thereby, a plurality of modified regions in which the sapphire single crystal is modified along the first irradiation line 81 and the second irradiation line 82 are formed in the substrate 100.
Subsequently, the modified region is formed by pressing the blade from the substrate bottom surface 114 side of the wafer-like substrate 100 along the modified region formed along the first irradiation line 81 and the second irradiation line 82. A crack is generated as a starting point, and the wafer-like substrate 100 is divided into a plurality of substrates 100. At this time, the lower semiconductor layer 210, the upper semiconductor layer 250, the transparent conductive layer 300, the p-electrode 350, and the n-electrode 400 exist on each separated substrate 100.
By this division, the first substrate side surface 111 and the second substrate side surface 112 in the substrate 100 are formed.
And the semiconductor light-emitting device 1 shown in FIG. 1 can be obtained through the above process.

Here, conventionally, when the semiconductor multilayer substrate 20 is divided into the plurality of semiconductor light emitting elements 1 in the dividing step, vibrations or the like may occur in the semiconductor multilayer substrate 20, and the lower semiconductor layer in the semiconductor multilayer substrate 20 may be generated. 210 may collide with each other and the lower semiconductor layer 210 may be chipped.
In the semiconductor multilayer substrate 20 of the present embodiment, as described above, the lower semiconductor layer 210 separated into a plurality of regions by the surface laser process in Step 107 and the second etching process in Step 108 is the first lower semiconductor. A connection side surface 235 is formed at a portion connecting the side surface 211 and the second lower semiconductor side surface 212, and the corner portion of the lower semiconductor layer 210 is rounded so that the protruding amount is small.
Therefore, compared to the case without this configuration, the lower semiconductor layers 210 are less likely to collide with each other in the dividing step, and even when the lower semiconductor layers 210 collide with each other, Compared with the case where the lower semiconductor layer 210 has a sharp corner, the occurrence of cracks and chips can be suppressed.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. In the second embodiment, the semiconductor light emitting element 1 (see FIG. 1) is manufactured by a method different from that of the first embodiment.
Hereinafter, a method for manufacturing the semiconductor light emitting device 1 in the second embodiment will be described. Note that the same reference numerals are used for the same configurations and the same processes as those in the first embodiment, and detailed description thereof is omitted here.

In the second embodiment, as in the first embodiment, the semiconductor laminating process in step 101, the mask forming process in step 102, the transparent conductive layer forming process in step 103, the resist forming process in step 104, and the first etching in step 105 are performed. The semiconductor light emitting device 1 is obtained through the process, the electrode forming process of step 106, the surface laser process of step 107, the second etching process of step 108, and the dividing process of step 109 (see FIG. 7 respectively).
In the second embodiment, the shape of the mask 55 (see FIG. 15 to be described later) formed in the mask forming process in step 102, the shape of the stacked semiconductor layer 200 removed in the first etching process in step 105, and the second in step 108. The semiconductor light emitting device 1 is formed by a method almost the same as that of the first embodiment, except that the way of wet etching of the laminated semiconductor layer 200 in the etching process is different from that of the first embodiment.
In the second embodiment, as in the first embodiment, the mask forming process in step 102, the resist forming process in step 104, and the first etching process in step 105 correspond to the semiconductor removal process, and the surface laser process in step 107 is performed. Corresponding to the dividing groove forming process, the second etching process of step 108 corresponds to the wet etching process.

FIG. 15 is a diagram for explaining a method of manufacturing the semiconductor light emitting element 1 in the present embodiment. FIGS. 15A and 15B show the semiconductor laminated substrate 20 after the mask 55, the transparent conductive layer 300, and the resist 61 are formed after the steps up to the resist forming step of Step 104 are performed. FIG. 15A is a top view of a part of the semiconductor laminated substrate 20 after the mask 55, the transparent conductive layer 300, and the resist 61 are formed, as viewed from the side on which the mask 55 and the like are formed. These are XVB-XVB sectional drawings of Drawing 15 (a).
FIGS. 15C and 15D show the semiconductor laminated substrate 20 after the first etching step of Step 105 is performed, and details will be described later.

  In the present embodiment, in the mask formation process of step 102, another example of the removal suppression layer on the laminated semiconductor layer 200 with respect to the wafer-like semiconductor laminated substrate 20 on which the laminated semiconductor layer 200 is formed in step 101. As a mask 55 is formed. Here, the shape of the mask 55 formed in the present embodiment is different from the shape of the mask 51 (see FIG. 8) in the first embodiment.

  A plurality of masks 55 of the present embodiment are provided on the laminated semiconductor layer 200 of the semiconductor laminated substrate 20, and each has an arc shape when viewed from the third direction z as shown in FIG. Have. Each mask 55 corresponds to the position of the connection portion 233 (see FIG. 1) of the semiconductor light emitting element 1 (see FIG. 1) formed from the semiconductor multilayer substrate 20 when viewed from the third direction z. These are provided so as to surround the four corners of the element formation scheduled position.

The mask 55 can be made of SiO ₂ or the like as in the first embodiment. The thickness of the mask 55 is set according to the thickness of the stacked semiconductor layer 200 to be removed in the first etching process of Step 105, the etching gas used for etching, and the like.
The mask 55 can be formed by a conventionally known CVD method, vapor deposition method, sputtering method, or the like, as in the first embodiment.

Subsequently, the first etching process of step 105 in the present embodiment will be described.
FIGS. 15C and 15D show the semiconductor laminated substrate 20 in which a part of the laminated semiconductor layer 200 is removed by performing the first etching step of Step 105 in the second embodiment, as described above. It is a figure. FIG. 15C is a top view of a part of the semiconductor laminated substrate 20 from which a part of the laminated semiconductor layer 200 has been removed as viewed from the side where the transparent conductive layer 300 is formed, and FIG. FIG. 15 is a cross-sectional view taken along the line XVD-XVD in FIG.

As shown in FIGS. 15C and 15D, in the first etching process of Step 105 in the present embodiment, the laminated semiconductor layer 200 is matched with the shape of the mask 55 formed in the mask formation process of Step 102. Is removed.
Then, in the first etching step of Step 105 in the present embodiment, by removing a part of the laminated semiconductor layer 200, the first groove 71, the second groove 72, the semiconductor exposed surface 213a, the first groove 71, and the first The convex part 75 as an example of the uneven | corrugated | grooved part which protrudes from the 2 groove part 72 is formed.

As shown in FIG. 15C, a plurality of first groove portions 71 and second groove portions 72 are formed along the first direction x and the second direction y, respectively.
Further, as shown in FIG. 15C, a plurality of convex portions 75 are formed in a region where the first groove portion 71 and the second groove portion 72 intersect. Specifically, the convex portion 75 is formed in the region where the above-described mask 55 is formed, and when viewed from the third direction z, the convex portion 75 of the connection portion 233 of the semiconductor light emitting element 1 formed from the semiconductor multilayer substrate 20. Corresponding to the position, it is provided so as to surround the four corners of the element formation scheduled position.

As a method of removing a part of the laminated semiconductor layer 200 in order to form the first groove portion 71, the second groove portion 72, the convex portion 75, and the semiconductor exposed surface 213a, as in the first embodiment, dry etching or wet etching is performed. Etching methods such as these are used.
As in the first embodiment, the etching in the first etching process of Step 105 proceeds from the upper surface side (the side opposite to the substrate 100) of the laminated semiconductor layer 200, and the laminated semiconductor layer 200 is removed from the upper surface side.
Here, in the present embodiment, the mask 55 is formed in a part of the region on the stacked semiconductor layer 200 in the mask formation step of Step 102 described above. Further, in the resist formation step of Step 104 described above, a resist 61 is formed on a partial region on the laminated semiconductor layer 200 and the transparent conductive layer 300.

Thereby, in the area | region in which the mask 55 is formed among the laminated semiconductor layers 200 in the semiconductor laminated substrate 20, the mask 55 is first removed by etching.
Further, in the region where the resist 61 is formed in the laminated semiconductor layer 200 and the transparent conductive layer 300, the etching does not proceed, and the laminated semiconductor layer 200 and the transparent conductive layer 300 are not removed.
On the other hand, in the region where neither the mask 55 nor the resist 61 is formed in the laminated semiconductor layer 200, the etching proceeds without being interrupted by the mask 55 and the resist 61.

Here, in this embodiment, the etching is performed by removing a part of the laminated semiconductor layer 200 in the region where both the mask 55 and the resist 61 are not formed in the laminated semiconductor layer 200 to form the n contact layer 203a. Finish when exposed.
Thereby, in the semiconductor laminated substrate 20, in the region where the mask 55 and the resist 61 are not formed, the first groove portion 71, the second groove portion 72, and the semiconductor exposed surface 213a where the n contact layer 203a is exposed are formed.
In the present embodiment, in the region where the mask 55 is formed in the semiconductor multilayer substrate 20, for example, the etching is terminated when the mask 55 is removed, and the stacked semiconductor layer 200 remains without being removed. A convex portion 75 protruding from the first groove portion 71 and the second groove portion 72 is formed.
Furthermore, on the laminated semiconductor layer 200 and the transparent conductive layer 300 on which the resist 61 is formed on the semiconductor laminated substrate 20, the laminated semiconductor layer 200 and the transparent conductive layer 300 remain without being removed.

In the present embodiment, in the region where the mask 55 is formed in the semiconductor multilayer substrate 20, the etching is finished when the mask 55 is removed. For example, after the mask 55 is removed, the mask is removed. A part of the laminated semiconductor layer 200 located below 55 may be removed by etching.
In this case, the amount of the stacked semiconductor layer 200 to be removed is smaller in the region where the mask 55 is formed than in the region where neither the mask 55 nor the resist 61 is formed. Therefore, the convex part 75 which protrudes from the 1st groove part 71 and the 2nd groove part 72 is formed in the area | region in which the mask 55 was formed.

  As described above, in the first etching step of Step 105, the first groove 71, the second groove 72, the semiconductor exposed surface 213a, and the protrusion 75 are formed in the semiconductor multilayer substrate 20, and the lower semiconductor layer 210 and An upper semiconductor layer 250 divided into a plurality of regions is formed.

  Subsequently, the second etching process of Step 108 will be described. FIG. 16 is a diagram for explaining the second etching step of step 108 in the present embodiment. FIG. 16A shows a part of the semiconductor laminated substrate 20 (before performing the second etching process of step 108) obtained by performing the electrode forming process of step 106 and the surface laser process of step 107. It is the top view seen from the side in which the 1st irradiation line 81 and the 2nd irradiation line 82 were formed. Moreover, FIG.16 (b) is XVIB-XVIB sectional drawing in Fig.16 (a). Further, FIG. 16C shows a convex portion 75 in the semiconductor laminated substrate 20 after the electrode forming process in step 106 and the surface laser process in step 107 and before the second etching process in step 108 is performed. It is a perspective view of the vicinity.

  FIG. 17 is a diagram for explaining the progress of wet etching of the lower semiconductor layer 210 in the vicinity of the convex portion 75. 17A is a top view of the vicinity of the convex portion 75 of the lower semiconductor layer 210 in the semiconductor laminated substrate 20 as viewed from the lower semiconductor upper surface 213 side, and FIG. 17B is the same as FIG. It is XVIIB-XVIIB sectional drawing in. In FIG. 17, the upper semiconductor layer 250 and the protective film 500 are not shown.

  In the surface laser process of step 107, as shown in FIG. 16A, at the center of the four protrusions 75 formed at the intersection of the first groove 71 and the second groove 72 in the first etching process of step 105. A first irradiation line 81 and a second irradiation line 82 are provided so as to intersect. Thus, the lower semiconductor layer 210 is separated into a plurality of portions by the first irradiation line 81 and the second irradiation line 82, and one convex portion is provided at each of the four corners of each separated lower semiconductor layer 210. 75 will be arranged.

In the second etching step of step 108, as in the first embodiment, the first lower semiconductor side surface 211, the second lower semiconductor side surface 212, and the connection side surface 235 (see FIG. 1) are formed by wet etching.
Here, as shown in FIGS. 16A to 16C, in the laminated semiconductor layer 200 in the semiconductor laminated substrate 20 before the second etching process of Step 108 is performed, the upper surface of the substrate is formed at the four corners of the element formation scheduled positions. A convex portion 75 extending along a direction perpendicular to 113 (third direction z) is formed. As described in the first embodiment, when there is a surface extending in the third direction z in the stacked semiconductor layer 200, on the inner side (the side away from the first irradiation line 81 and the second irradiation line 82) from this surface, The laminated semiconductor layer 200 is removed by wet etching depending on the shape of this surface.

Therefore, in the present embodiment, wet etching is performed on the semiconductor multilayer substrate 20, so that the lower semiconductor layer 210 is below the convex portion 75 and inside the convex portion 75 (the first irradiation line 81 and In the portion located on the side away from the second irradiation line 82, as shown in FIG. 17A, depending on the shape of the convex portion 75, the bottom is formed so as to exhibit an arc shape when viewed from the third direction z. The side semiconductor layer 210 is removed.
Thus, as in the first embodiment, the vertical portion 235a extending along the third direction z and having an arc shape when viewed from the third direction z is formed, and the lower semiconductor upper surface 213 and the vertical portion 235a are formed. A connecting portion 233 having an arc shape is formed at the boundary portion (see FIG. 1 and the like).

The lower semiconductor bottom surface 214 is formed in a region on the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 located under the convex portion 75 and in a region of the lower semiconductor layer 210 where the convex portion 75 is not formed. The side is shaved larger than the lower semiconductor upper surface 213 side.
As a result, as shown in FIG. 17B, in the region on the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 located below the convex portion 75, the substrate upper surface 113 is inclined with respect to the vertical portion 235a. An inclined portion 235b that is inclined with respect to a direction perpendicular to the vertical direction is formed.
Further, in the region where the convex portion 75 is not formed in the lower semiconductor layer 210, the lower semiconductor layer is etched by the etchant entering through the first irradiation line 81 and the second irradiation line 82, as in the first embodiment. By cutting away part of the layer 210, the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 that are inclined with respect to the direction perpendicular to the substrate upper surface 113 are formed (see FIG. 1 and the like).

  Thereafter, as in the first embodiment, the semiconductor light emitting element 1 shown in FIG. 1 can be obtained by executing the dividing step of step 109.

[Embodiment 3]
Subsequently, Embodiment 3 of the present invention will be described. In the third embodiment, the semiconductor light emitting element 1 (see FIG. 1) is manufactured by a method different from that in the first and second embodiments. In addition, the same code | symbol is used about the structure similar to Embodiment 1 and Embodiment 2, a similar process, etc., and detailed description is abbreviate | omitted here.

In the method for manufacturing the semiconductor light emitting element 1 according to the third embodiment, unlike the first and second embodiments, the mask forming process of step 102 is not executed. That is, in the third embodiment, the transparent conductive layer forming step for forming the transparent conductive layer 300 without executing the mask forming step is performed on the semiconductor laminated substrate 20 on which the laminated semiconductor layer 200 is formed in Step 101. (Step 103). Thereafter, similarly to the first and second embodiments, the resist forming process (step 104), the first etching process (step 105), the electrode forming process (step 106), the surface laser process (step 107), the second The semiconductor light emitting device 1 shown in FIG. 1 is obtained by executing the etching process (step 108) and the dividing process (step 109).
In the third embodiment, the resist formation process in step 104 and the first etching process in step 105 correspond to the semiconductor removal process, the surface laser process in step 107 corresponds to the split groove formation process, and the second etching in step 108. The process corresponds to the wet etching process.
In the present embodiment, the shape of the resist 65 formed in the resist formation step in step 104 is different from the shape of the resist 61 formed in the first and second embodiments.

FIG. 18 is a diagram for explaining a method of manufacturing the semiconductor light emitting device 1 in the present embodiment. FIGS. 18A and 18B show the semiconductor laminated substrate 20 after the formation of the transparent conductive layer 300 and the resist 65 after performing the process up to the resist formation in step 104. FIG. 18A is a top view of a part of the semiconductor multilayer substrate 20 after the formation of the transparent conductive layer 300 and the resist 65 as viewed from the side on which the resist 65 and the like are formed, and FIG. It is XVIIIB-XVIIIB sectional drawing of 18 (a).
FIGS. 18C and 18D are views showing the semiconductor laminated substrate 20 after the first etching process of Step 105 is performed, and details will be described later.

The resist 65 as another example of the removal suppressing layer according to the present embodiment includes a first resist 65a provided on the transparent conductive layer 300 and on the laminated semiconductor layer 200 positioned around the transparent conductive layer 300, and a semiconductor laminated substrate. 20 and a second resist 65b provided at a position corresponding to the connection portion 233 (see FIG. 1) in the semiconductor light emitting element 1 formed from 20.
First resist 65a has the same shape as resist 61 in the first and second embodiments.
The second resist 65b has the same shape as the mask 55 in the second embodiment. Specifically, as shown in FIG. 18A, the second resist 65b is connected in the semiconductor light emitting device 1 (see FIG. 1) formed from the semiconductor multilayer substrate 20 when viewed from the third direction z. Corresponding to the position of the part 233 (see FIG. 1), the semiconductor light emitting element 1 is provided so as to surround the four corners at the planned formation position.

Subsequently, the first etching process of step 105 in the present embodiment will be described.
18C and 18D are diagrams showing the semiconductor laminated substrate 20 from which a part of the laminated semiconductor layer 200 has been removed by executing the first etching step of Step 105 in the third embodiment. FIG. 18C is a top view of a part of the semiconductor multilayer substrate 20 from which part of the multilayer semiconductor layer 200 has been removed as viewed from the side on which the transparent conductive layer 300 is formed, and FIG. It is XVIIID-XVIIID sectional drawing in Fig.18 (a).

As shown in FIGS. 18C and 18D, in the first etching process of Step 105 in the present embodiment, the laminated semiconductor layer 200 is matched with the shape of the resist 65 formed in the resist formation process of Step 104. Is removed.
In the present embodiment, in the first etching step of Step 105, by removing a part of the laminated semiconductor layer 200, the first groove 71, the second groove 72, and the semiconductor exposed surface 213a are removed as in the second embodiment. A convex portion 75 protruding from the first groove portion 71 and the second groove portion 72 is formed.

As a method of removing a part of the laminated semiconductor layer 200 in order to form the first groove 71, the second groove 72, the convex 75, and the semiconductor exposed surface 213a, as in the first and second embodiments, An etching method such as dry etching or wet etching is used.
As described in the first and second embodiments, the etching in the first etching step of Step 105 proceeds from the upper surface side (the side opposite to the substrate 100) of the laminated semiconductor layer 200, and the laminated semiconductor from the upper surface side. Layer 200 is removed.
Here, in the present embodiment, the resist 65 (the first resist 65a and the second resist 65b) is formed in a part of the region on the stacked semiconductor layer 200 in the resist forming process in Step 104 described above.

Therefore, in the first etching step of step 105 in the present embodiment, the laminated semiconductor layer 200 in the region where the resist 65 is not formed is removed from the semiconductor laminated substrate 20 and the laminated semiconductor layer in which the resist 65 is formed. 200 and the transparent conductive layer 300 remain without being removed.
Here, in the present embodiment, the etching ends when a part of the laminated semiconductor layer 200 is removed and the n contact layer 203a is exposed in a region of the laminated semiconductor layer 200 where the resist 65 is not formed. .

As a result, as shown in FIGS. 18C and 18D, the n contact layer 203 a is exposed in the region where the resist 65 (the first resist 65 a and the second resist 65 b) is not formed in the semiconductor laminated substrate 20. A first groove 71, a second groove 72, and a semiconductor exposed surface 213a are formed.
Further, in the semiconductor multilayer substrate 20, as an example of the concavo-convex portion protruding from the first groove portion 71 and the second groove portion 72 because the laminated semiconductor layer 200 remains without being removed in the region where the second resist 65 b is formed. The convex portion 75 is formed.
In addition, on the laminated semiconductor layer 200 and the transparent conductive layer 300 on which the first resist 65a is formed in the semiconductor laminated substrate 20, the laminated semiconductor layer 200 and the transparent conductive layer 300 remain without being removed.

Here, as shown in FIGS. 18C and 18D, the shape of the semiconductor laminated substrate 20 after the removal of the laminated semiconductor layer 200 formed by the first etching step of Step 105 in the present embodiment is as shown in FIG. (C) It is equal to the shape of the semiconductor laminated substrate 20 formed by the first etching process of step 105 in the second embodiment shown in (d).
Therefore, similarly to the second embodiment, the semiconductor light emitting device shown in FIG. 1 is obtained by performing the electrode forming process in step 106, the surface laser process in step 107, the second etching process in step 108, and the dividing process in step 109. 1 can be obtained.

  In the third embodiment, unlike the first and second embodiments, the mask forming process in step 102 is not executed. Therefore, in the present embodiment, the manufacturing process of the semiconductor light emitting element 1 can be simplified as compared with the first and second embodiments.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 20 ... Semiconductor laminated substrate, 100 ... Substrate, 200 ... Multilayer semiconductor layer, 210 ... Lower semiconductor layer, 211 ... First lower semiconductor side surface, 212 ... Second lower semiconductor side surface, 213 ... Lower Side semiconductor upper surface, 214 ... lower semiconductor bottom surface, 230 ... upper surface periphery, 231 ... first straight line portion, 232 ... second straight line portion, 233 ... connection portion, 235 ... connection side surface, 235a ... vertical portion, 235b ... inclined portion, 240 ... bottom edge, 250 ... upper semiconductor layer, 300 ... transparent conductive layer, 350 ... p electrode, 400 ... n electrode

Claims (6)

A semiconductor light emitting device including a semiconductor layer including a light emitting layer that emits light when energized,
The semiconductor layer includes a semiconductor bottom surface, a semiconductor side surface that rises upward and outward from the first peripheral edge of the semiconductor bottom surface, and a second peripheral edge above the semiconductor side surface and inward of the semiconductor layer. A semiconductor upper surface extending upward and extending upward,
The second peripheral edge has a plurality of linear portions extending linearly and a plurality of connection portions connecting the adjacent linear portions, and when viewed from a direction perpendicular to the upper surface of the semiconductor, The connecting part is located on the inner side of the intersection of the extension lines of the two straight parts connected to the connecting part ,
The semiconductor side surface includes a linear side surface extending from the first peripheral edge toward the straight line portion at the second peripheral edge, and a connection side surface extending from the first peripheral edge toward the connection portion at the second peripheral edge. Have
The connection side surface includes an inclined portion that rises upward and outward from the semiconductor layer from the first peripheral edge, and a vertical portion that rises upward from the inclined portion toward the connection portion at the second peripheral edge. A semiconductor light emitting device characterized by the above. 2. The semiconductor light emitting element according to claim 1, wherein the straight side surface rises upward and outward from the first peripheral edge toward the straight line portion at the second peripheral edge. When the semiconductor layer is viewed from a direction perpendicular to the upper surface of the semiconductor, the plurality of straight portions extend in a first direction extending in a first direction, and extends in a second direction perpendicular to the first direction. And a second straight part connected to the first straight part via
When the semiconductor layer is viewed from a direction perpendicular to the upper surface of the semiconductor, the shortest distance from the first straight portion to the first peripheral edge is X, and the shortest distance from the second straight portion to the first peripheral edge is X. The distance is Y, and from the intersection of the connecting line and the straight line connecting the shortest distance from the intersection of the extension line of the first straight line part and the extension line of the second straight line part to the first peripheral edge, When the shortest distance to the periphery of 1 is L, X, Y and L are
L ² = A × (X ² + Y ² ) 0 <A ≦ 0.95
The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device has the following relationship.   4. The semiconductor light emitting element according to claim 1, wherein the connection portion has an arc shape when the semiconductor layer is viewed from a direction perpendicular to the upper surface of the semiconductor. 5. With respect to a semiconductor laminated substrate in which a semiconductor layer composed of a group III nitride semiconductor including a light emitting layer that emits light when energized is laminated on the substrate, a part of the semiconductor layer is locally applied from the side opposite to the substrate. The first groove portion extending along the surface of the semiconductor layer, the second groove portion extending along the surface of the semiconductor layer and intersecting the first groove portion, the first groove portion, and the second groove portion. A semiconductor removal step of forming a recess provided in a region intersecting with the first groove and the second groove .
By removing a part of the semiconductor layer from the opposite side of the semiconductor laminated substrate in which the first groove portion, the second groove portion and the concave portion are formed until the substrate reaches the substrate locally. A split groove forming step of forming a plurality of split grooves that divide the semiconductor layer into a plurality of regions along the first groove portion and the second groove portion and intersect at the concave portion ;
A method of manufacturing a semiconductor light emitting device, comprising: a wet etching step of performing wet etching on the semiconductor laminated substrate in which the first groove portion, the second groove portion, the concave portion, and the plurality of divided grooves are formed. In the semiconductor removal step, a removal suppression layer that prevents the removal of the semiconductor layer is partially stacked on the semiconductor layer, and a region of the semiconductor layer where the removal suppression layer is not formed is formed from the opposite side of the substrate. 6. The method of manufacturing a semiconductor light emitting element according to claim 5, wherein the recess is formed by removing the recess .

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