JP5077224B2 - Group III nitride semiconductor light emitting device and method for manufacturing the same - Google Patents

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor light emitting device having a step of removing a growth substrate by a substrate lift-off method, and the light emitting device.

  A sapphire substrate is generally used as a growth substrate for a group III nitride semiconductor. However, sapphire has problems with conductivity and thermal conductivity, and it is not easy to process without a clear cleavage plane. Therefore, as a technique for solving these problems, a technique (substrate lift-off) has been developed in which a growth substrate is removed after a group III nitride semiconductor is grown on the growth substrate.

  One such technique is the laser lift-off method. This is because after the group III nitride semiconductor layer and the support substrate are joined, the interface between the growth substrate and the group III nitride semiconductor is irradiated with a laser to decompose the group III nitride semiconductor layer and remove the growth substrate. It is a method to do. As another technique, a layer that can be dissolved in a chemical solution is introduced into a layer close to the growth substrate of the group III nitride semiconductor layer, the group III nitride semiconductor layer and the support substrate are joined, and then the above-described method is performed using a desired chemical solution. A method of removing a growth substrate by dissolving a layer that can be dissolved in a chemical solution (chemical lift-off method) is also known.

  The surface of the group III nitride semiconductor layer exposed by removing the growth substrate has conventionally been subjected to fine unevenness processing by wet etching in order to increase the light extraction efficiency. However, uneven processing by wet etching varies, and flat regions and uneven regions having depths that are not effective for light extraction remain in places. Therefore, the light extraction efficiency has not been sufficiently improved.

Therefore, Patent Document 1 discloses a method for improving light extraction efficiency by performing two-step uneven processing. Specifically, periodic pattern irregularities are formed by etching using a mask on the exposed group III nitride semiconductor layer surface, and then finely etched by wet etching on the group III nitride semiconductor layer surface and the bottom surface of the recess. Irregularities are formed.
JP 2008-47861 A

  However, in the method of Patent Document 1, since the surface of the group III nitride semiconductor layer is provided with unevenness that is deeper than fine unevenness by wet etching, current diffusion in the in-plane direction is hindered, and the uniformity of light emission is impaired. It was. Patent Document 1 also discloses a method of improving current diffusivity by providing a transparent electrode such as ITO on the entire surface of a group III nitride semiconductor layer subjected to two-step unevenness processing. Is not low, and the current diffusivity cannot be sufficiently improved.

  Accordingly, an object of the present invention is to provide a group III nitride semiconductor light-emitting device that achieves both improved light extraction efficiency and light emission uniformity, and a method for manufacturing the same.

  According to a first aspect of the present invention, there is provided a first step of sequentially stacking an n-type layer made of a group III nitride semiconductor, an active layer, and a p-type layer on a growth substrate, and forming a p-electrode on the p-type layer; And a second step of forming a conductive support, a third step of separating and removing the growth substrate by substrate lift-off, and a pattern having a plurality of closed curves on the surface of the n-type layer exposed by removal of the growth substrate. A fourth step of forming fine irregularities on the surface of the n-type layer and the bottom surface of the depression by wet etching, and a wiring shape that passes through all of the closed curve by the concave portions on the n-type layer on which the irregularities are formed And a fifth step of forming an n-electrode having the above pattern. A method for manufacturing a Group III nitride semiconductor light-emitting device.

  According to a second aspect of the present invention, there is provided a first step of sequentially stacking an n-type layer made of a group III nitride semiconductor, an active layer, and a p-type layer on a growth substrate, and forming a p-electrode on the p-type layer; In addition, a second step of forming a conductive support, a third step of separating and removing the growth substrate by substrate lift-off, and forming a recess having a predetermined pattern on the surface of the n-type layer exposed by removing the growth substrate A fourth step of forming fine irregularities on the n-type layer surface and the bottom surface of the recess by wet etching, and a wiring pattern having a plurality of closed curves on the n-type layer on which the irregularities are formed, And a fifth step of forming an n-electrode so as to include a recess in the n-type layer region within the closed curve, and a method for manufacturing a group III nitride semiconductor light-emitting device.

In the first and second inventions, the group III nitride semiconductor is a semiconductor represented by the general formula Al _x Ga _y In _z N (x + y + z = 1, 0 ≦ x, y, z ≦ 1), Al, Including those in which part of Ga and In is substituted with other group 13 elements B and Tl, and part of N is substituted with other group 15 elements P, As, Sb and Bi Shall be. More generally, GaN, InGaN, AlGaN, or AlGaInN containing at least Ga is shown. Usually, Si is used as an n-type impurity and Mg is used as a p-type impurity.

  Further, the fine unevenness means that the depth and width of the unevenness are smaller than the depth and width of the recess formed on the surface of the n-type layer. The depth of the recess is desirably 1/4 to 3/4 of the thickness of the n-type layer. If it is shallower than 1/4 of the thickness of the n-type layer, it cannot be expected to improve the light extraction efficiency. If it is deeper than 3/4 of the thickness of the n-type layer, the current diffusivity in the surface direction will be hindered. The uniformity of light emission is impaired, resulting in a decrease in output and an increase in drive voltage. Moreover, it is preferable that the width | variety of a recessed part shall be the minimum width which can be formed reliably, for example, is 10-20 micrometers. This is because the wider the width, the more difficult the current diffusion in the surface direction, and the uniformity of light emission is impaired. Of course, the width may be narrower than 10 μm by a highly accurate processing step.

  The growth substrate is generally sapphire, but other materials such as SiC, ZnO, and spinel can be used. Further, Si, Ge, GaAs, Cu, Cu—W, or the like can be used as the support, and the support is formed on the p electrode by bonding the p electrode and the support substrate through the metal layer. be able to. Further, a metal layer such as Cu may be formed directly on the p-electrode by plating, sputtering, or the like to form a support.

  The substrate lift-off is a method such as laser lift-off or chemical lift-off, for example.

  In the first invention, the pattern of the recesses and the n electrode may be any pattern in which the pattern of the recesses has a continuous pattern of at least a plurality of minimum closed curves, and the pattern of the n electrodes does not have a closed curve. May be. In the second invention, the n electrode pattern may be a pattern having at least a plurality of continuous minimum closed curves, and the concave pattern may be a pattern having no closed curve. A pattern having a continuous series of a plurality of minimum closed curves is, for example, a stripe shape or a lattice shape, and is a pattern having a plurality of rectangular closed curves. The minimum closed curve means a closed curve in which no closed curve exists in the closed curve, and the closed curve in the claims means the minimum closed curve. And in 1st invention, it has at least 1 wiring-shaped n electrode inside the minimum closed curve by all the recessed parts. In the second invention, at least one concave portion is provided inside the minimum closed curve formed by all the wiring-shaped n-electrodes.

  As the solution used for wet etching, for example, an alkaline aqueous solution such as KOH, NaOH, TMAH (tetramethylammonium hydroxide) can be used.

  A third invention is a group III nitride semiconductor light emitting device according to the first invention, wherein the n electrode pattern or the recess pattern is a pattern in which the closed curve by the recess is equally divided by the wiring n electrode It is a manufacturing method of an element.

  A fourth invention is the group III nitride semiconductor according to the second invention, wherein the pattern of the n electrode or the pattern of the recess is a pattern in which the closed curve by the wiring n electrode is equally divided by the recess It is a manufacturing method of a light emitting element.

  A fifth invention is a method of manufacturing a group III nitride semiconductor light emitting device according to the first to fourth inventions, wherein the pattern of the n electrode or the pattern of the recesses is a lattice pattern.

  According to a sixth invention, in the first to fifth inventions, the fourth step comprises a step of forming a recess by dry etching and a step of forming fine irregularities by wet etching after the formation of the recess. This is a method for producing a Group III nitride semiconductor light-emitting device.

  According to a seventh aspect of the present invention, in the first to fifth aspects of the present invention, the fourth step includes a step of forming a molten layer melted by wet etching on the surface of the n-type layer exposed by removing the growth substrate; A method of manufacturing a group III nitride semiconductor light-emitting device comprising: forming a concave portion and a fine concave and convex simultaneously by melting an n-type layer and a molten layer by etching.

  According to an eighth aspect of the present invention, there is provided a conductive support, a p-electrode formed on the support, a p-type layer made of a group III nitride semiconductor, an active layer, and an n-type layer, which are sequentially stacked on the p-electrode. And a n-electrode formed on the n-type layer, the surface of the n-type layer on the n-electrode formation side is formed with a plurality of concave portions having a closed curve, A Group III nitride semiconductor light emitting device characterized in that fine irregularities are formed on the surface and the bottom surface of the recess, and the n-electrode is formed in a wiring pattern that passes through all of the closed curve by the recess. .

  According to a ninth aspect of the present invention, there is provided a conductive support, a p-electrode formed on the support, and a p-type layer made of a group III nitride semiconductor, an active layer, and an n-type layer, which are sequentially stacked on the p-electrode. And a n-electrode formed on the n-type layer, a recess having a predetermined pattern is formed on the surface of the n-type layer on the n-electrode formation side. A fine unevenness is formed on the bottom surface of the recess, and the n electrode has a pattern of wiring having a plurality of closed curves, and is formed so as to include a recess in the n-type layer region in each closed curve. This is a group III nitride semiconductor light emitting device.

  A tenth invention is the group III nitride semiconductor light-emitting device according to the eighth invention, wherein the electrode pattern or the recess pattern is a pattern in which a closed curve by the recess is equally divided by a wiring-shaped n-electrode It is.

  An eleventh aspect of the invention is the group III nitride semiconductor according to the ninth aspect, wherein the n-electrode pattern or the recess pattern is a pattern in which the closed curve by the wiring-like n-electrode is equally divided by the recess. It is a light emitting element.

  A twelfth invention is the group III nitride semiconductor light emitting device according to the eighth invention to the eleventh invention, wherein the pattern of the n electrode or the pattern of the recesses is a lattice pattern.

  In the first and second inventions, the light extraction efficiency is improved by two-step unevenness processing using the recesses and fine unevenness. Moreover, if the concave pattern and the n electrode pattern are formed as in the first and second inventions, it is possible to suppress the deterioration of the current diffusivity in the in-plane direction due to the concave section formed on the n-type layer surface. And uniformity of light emission can be maintained. Therefore, according to the first and second inventions, the light extraction efficiency can be improved without deteriorating the uniformity of light emission.

  Further, if a concave pattern and an n-electrode pattern are formed as in the third and fourth inventions, it is possible to further suppress the deterioration of the current diffusibility in the in-plane direction. Further, as in the fifth invention, a grid pattern can be adopted as the concave pattern and the n-electrode pattern, and according to such a grid pattern, the patterns of the third and fourth inventions can be easily implemented. Can be realized.

  Further, the two-step uneven processing by the concave portion and the fine unevenness can be easily realized by the processes of the sixth and seventh inventions.

  Further, according to the eighth to twelfth inventions, a group III nitride semiconductor light emitting device having high light extraction efficiency and high light emission uniformity can be realized.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to the examples.

  FIG. 1 is a cross-sectional view showing the structure of the light emitting device 100 of Example 1. The light-emitting element 100 includes a support 101, a p-electrode 103 bonded to the support 101 via a low-melting-point metal layer 102, and a p-type layer made of a group III nitride semiconductor sequentially stacked on the p-electrode 103. 104, an active layer 105, an n-type layer 106, and an n-electrode 107 formed on the n-type layer 106.

  As the support 101, a conductive substrate made of Si, GaAs, Cu, Cu—W, or the like can be used.

  As the low melting point metal layer 102, a metal eutectic layer such as an Au—Sn layer, an Au—Si layer, an Ag—Sn—Cu layer, or a Sn—Bi layer can be used. An Sn layer, a Cu layer, or the like can also be used.

  For the p-electrode 103, a metal having high light reflectivity and low contact resistance such as Ag, Rh, Pt, Ru, or an alloy containing these metals as a main component, Ni, Ni alloy, Au alloy, or the like can be used. Moreover, the composite layer which consists of transparent electrode films, such as ITO, and a highly reflective metal film may be sufficient. In order to improve the light extraction efficiency, it is desirable that the pattern of the p electrode 103 is a pattern obtained by inverting the pattern of the n electrode 107. That is, the p-electrode 103 is formed under the region where the n-electrode 107 is not formed, and the p-electrode 103 is not formed under the region where the n-electrode 107 is formed. In a region where the p-electrode is not formed, an insulating film or the like may be provided so that the low melting point metal layer 102 and the p-type layer 104 are not in direct contact.

  The p-type layer 104, the active layer 105, and the n-type layer 106 may have any configuration conventionally known as a configuration of a light emitting element. The p-type layer 104 has, for example, a structure in which a p-contact layer doped with Mg made of GaN and a p-cladding layer doped with Mg made of AlGaN are stacked in order from the support 101 side. The active layer 105 has, for example, an MQW structure in which a barrier layer made of GaN and a well layer made of InGaN are repeatedly stacked. The n-type layer 106 has, for example, a structure in which an n-cladding layer made of GaN and an n-type contact layer doped with Si at a high concentration are stacked in order from the active layer 105 side.

  FIG. 2 is a plan view of the light emitting device 100 as viewed from the n-electrode 107 side. The planar shape of the light emitting element 100 is a square. As shown in FIG. 2, a lattice-shaped pattern of recesses 108 is formed on the surface of the n-type layer 106 on the n-electrode 107 side, and the surface of the n-type layer 106 is partitioned into squares. Further, on the bottom surface 108a of the recess 108 and the surface 106a of the n-type layer 106 where the recess 108 is not formed, fine unevenness 109 having a height and width smaller than the depth and width of the recess 108 is formed. Yes. In other words, the surface of the n-type layer 106 on the n-electrode 107 side is subjected to two-step concavo-convex processing by the concave portion 108 and the fine concavo-convex 109.

  For the n-electrode 107, for example, Al / Ti / Ni / Au is used. As shown in FIG. 2, the n-electrode 107 includes a wiring portion 110 and two pad portions 111. The two pad portions 111 are respectively disposed at two corner portions on one side of the square light emitting element. The wiring part 110 is formed in a square lattice pattern in which wirings are arranged in parallel to the square side which is the planar shape of the light emitting element 100, and is connected to the two pad parts 111. The pattern of the recess 108 and the pattern of the wiring part 110 are formed in such a pattern that the center of each square grid of the wiring part 110 coincides with the grid point of the recess 108. Therefore, each square grid of the wiring part 110 is equally divided into four squares by the cross-shaped recess 108. In addition, in each square lattice of the recesses 108, the wiring portions 110 have a pattern formed in a cross shape, a T shape, or an L shape, and the wiring portions 110 are formed in the lattice formed by the recess portions 108. There is nothing that is not. In addition, the square by the grid | lattice pattern of the wiring-shaped part 110 and the recessed part 108 respond | corresponds to the closed curve of this invention.

  In this light emitting element 100, the surface of the n-type layer 106 on the n-electrode 107 side is subjected to two-step unevenness processing with different depth and width by the recesses 108 and the fine unevenness 109. The light extraction efficiency is improved as compared with the case where only 109 is applied. Further, the pattern of the recess 108 and the pattern of the wiring part 110 are such that the wiring part 110 of the n-electrode 107 is always formed in each square lattice of the recess 108. In the case where the recess 108 exists on the n-type layer 106, current is difficult to diffuse in the closed region (each lattice) surrounded by the recess 108, and the uniformity of light emission is impaired. Since the wiring portion 110 of the n-electrode 107 is formed in the closed region, current can be uniformly diffused in the closed region, and the uniformity of light emission can be maintained. In particular, since each square grid of the wiring part 110 is a pattern that is equally divided by the recesses 108, the distance between the recesses 108 and the wiring part 110 is substantially uniform, and further, the current is uniformly diffused in the plane to emit light. Can improve the uniformity. On the contrary, even in a pattern in which each square grid formed by the recesses 108 is equally divided by the wiring portion 110, the current can be uniformly diffused in the plane.

  It is desirable that the depth of the recess 108 is ¼ to ¾ of the thickness of the n-type layer 106. If it is shallower than 1/4, the effect of improving the light extraction efficiency cannot be sufficiently obtained. If it is deeper than 3/4, the sheet resistance of the n-type layer 106 is adversely affected and the current is diffused in the in-plane direction. As a result, the uniformity of light emission is impaired and the driving voltage is increased. Further, it is desirable that the width of the recess 108 be the minimum width that can be reliably formed. This is because the wider the width, the worse the uniformity of light emission. For example, the width is 10 to 20 μm. Of course, the width may be narrower than this by a highly accurate processing step.

  Next, a manufacturing process of the light emitting element 100 will be described with reference to FIG. For simplicity of explanation, the element separation step for separating the light emitting elements 100 in the following description is omitted.

First, an n-type layer 106 made of a group III nitride semiconductor, an active layer 105, and a p-type layer 104 are sequentially laminated on a sapphire substrate 112 (corresponding to the growth substrate of the present invention) (FIG. 3.A). . Raw material gas used in the MOCVD method, as the nitrogen source, ammonia (NH _3), as a Ga source, trimethyl gallium _{(Ga (CH 3) 3)} , as an In source, trimethylindium _{(In (CH 3) 3)} , Al source Trimethylaluminum (Al (CH ₃ ) ₃ ), silane (SiH ₄ ) as an n-type doping gas, cyclopentadienylmagnesium (Mg (C ₅ H ₅ ) ₂ ) as a p-type doping gas, and H as a carrier gas ₂ or N ₂ . In addition to the sapphire substrate 112, SiC, ZnO, spinel, or the like can be used.

  Next, a p-electrode 103 is formed in a predetermined region on the surface of the p-type layer 104 by a lift-off method using a resist, a low-melting point metal diffusion preventing layer (not shown) is formed on the p-electrode 103, and a low-melting point metal is further formed thereon. Layer 102 is formed (FIG. 3.B).

  Next, the support body 101 is prepared, and the support body 101 and the p electrode 103 are joined via the low melting-point metal layer 102 (FIG. 3.C). The low melting point metal diffusion prevention layer (not shown) is a layer for preventing the metal of the low melting point metal layer 102 from diffusing to the p-electrode 103 side beyond the low melting point metal diffusion prevention layer.

  Then, laser light is irradiated from the sapphire substrate 112 side, and the sapphire substrate 112 is separated and removed by laser lift-off (FIG. 3.D).

  Next, the n-type layer 106 is etched on the surface of the n-type layer 106 exposed by the removal of the sapphire substrate 112 by dry etching such as chlorine plasma treatment using a mask to form the concave portions 108 having a square lattice pattern. Form (FIG. 3.E).

  Next, by immersing the wafer in a 4.5 wt%, 60 ° C. aqueous KOH solution, fine irregularities 109 are formed on the surface of the n-type layer 106 where the recesses 108 are not formed or on the bottoms of the recesses 108 (FIG. 3). F). In addition to KOH, an aqueous solution such as NaOH or TMAH (tetramethylammonium hydroxide) can also be used.

  Next, an n-electrode 107 having a grid pattern wiring portion 110 and two pad portions 111 is formed on the n-type layer 106 in which the concave portion 108 and the fine unevenness 109 are formed by a lift-off method using a resist. Form. Through the above manufacturing process, the light-emitting element 100 illustrated in FIG. 1 can be manufactured.

  In Example 2, the method for forming the recesses 108 and the fine irregularities 109 in the manufacturing process of the light-emitting element of Example 1 is changed as follows.

FIG. From A to FIG. Up to D is the same manufacturing process. FIG. After the sapphire substrate 112 is separated and removed by the process D, the SiO ₂ film 120 (in accordance with the present invention) is formed on the surface of the n-type layer 106 exposed by the removal of the sapphire substrate 112 in a pattern opposite to the pattern of the recess 108 to be formed. (Corresponding to a molten layer) is formed by sputtering or the like (FIG. 4.A). That is, a window is opened where the recess 108 is formed, and the SiO ₂ film 120 is formed where the recess 108 is not formed.

Next, the wafer is immersed in a 4.5 wt%, 60 ° C. aqueous KOH solution. As a result, the surface of the n-type layer 106 where the SiO ₂ film 120 is not formed is etched to form a recess 108 with fine irregularities 109 formed on the bottom surface, and the SiO ₂ film 120 itself is gradually etched. (Fig. 4.B).

As the etching further progresses, the depth of the recess 108 becomes deeper, and the SiO ₂ film 120 is etched and removed, and fine irregularities 109 are also formed on the surface of the n-type layer 106 covered with the SiO ₂ film 120. Formed (FIG. 4.C). Note that the depth of the recess 108 can be controlled by the thickness of the SiO ₂ film 120. In addition to the SiO ₂ film 120, any material that can be gradually etched with respect to the group III nitride semiconductor wet etching solution may be used, and metal materials such as Ti and Ni can also be used.

  As described above, according to the manufacturing process of the second embodiment, two-step concavo-convex processing of the concave portion 108 and the fine concavo-convex 109 can be performed by wet etching.

  In each embodiment, both the concave pattern and the n-electrode pattern are in a lattice pattern, but the present invention is not limited to this, and any pattern may be used as long as it has a plurality of closed curves. When the concave pattern is a pattern having a plurality of closed curves, it is sufficient that at least one wiring-like n electrode is formed in each minimum closed curve, and the n electrode pattern may be a pattern having no closed curve. Good. Further, when the n-electrode pattern is a pattern having a plurality of closed curves, it is sufficient that at least one recess is formed in each minimum closed curve, and the pattern of the recess may be a pattern having no closed curve. In either case, deterioration of current diffusibility in the element plane can be suppressed.

  In each example, laser lift-off is used to remove the sapphire substrate, but a buffer layer that can be dissolved in a chemical solution is formed between the sapphire substrate and the n-type layer, and the chemical solution is bonded to the support. Alternatively, chemical lift-off in which the buffer layer is dissolved to separate and remove the sapphire substrate may be used.

  The group III nitride semiconductor light-emitting device of the present invention can be used for display devices, lighting devices, and the like.

FIG. 4 shows a structure of a light-emitting element 100 of Example 1. The figure which looked at the light emitting element 100 from the upper surface. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a manufacturing process of the light-emitting element 100 of Example 1. FIG. 6 shows a part of the manufacturing process of the light-emitting element 100 of Example 2. FIG. 6 shows a part of the manufacturing process of the light-emitting element 100 of Example 2. FIG. 6 shows a part of the manufacturing process of the light-emitting element 100 of Example 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100: Light emitting element 101: Support body 102: Low melting-point metal layer 103: P electrode 104: P-type layer 105: Active layer 106: N-type layer 107: P electrode 108: Concave 109: Fine unevenness 110: Wiring part 120: SiO ₂ film

Claims (12)

A first step of sequentially stacking a group III nitride semiconductor n-type layer, an active layer, and a p-type layer on a growth substrate, and forming a p-electrode on the p-type layer;
A second step of forming a conductive support on the p-electrode;
A third step of separating and removing the growth substrate by substrate lift-off;
A recess having a pattern having a plurality of closed curves is formed on the surface of the n-type layer exposed by removing the growth substrate, and fine irregularities are formed on the surface of the n-type layer and the bottom of the recess by wet etching. Process,
A fifth step of forming a wiring-like n-electrode in a pattern that passes through all of the closed curve by the concave portion on the n-type layer on which the concave and convex portions are formed;
A method for producing a Group III nitride semiconductor light-emitting device, comprising: A first step of sequentially stacking a group III nitride semiconductor n-type layer, an active layer, and a p-type layer on a growth substrate, and forming a p-electrode on the p-type layer;
A second step of forming a conductive support on the p-electrode;
A third step of separating and removing the growth substrate by substrate lift-off;
A fourth step of forming a concave portion of a predetermined pattern on the surface of the n-type layer exposed by removing the growth substrate, and forming fine irregularities on the surface of the n-type layer and the bottom surface of the concave portion by wet etching;
A fifth step of forming an n-electrode on the n-type layer on which the projections and depressions are formed, in a pattern of wiring having a plurality of closed curves, so as to include the recesses in the n-type layer region in each closed curve; ,
A method for producing a Group III nitride semiconductor light-emitting device, comprising:   2. The group III nitride semiconductor light emitting device according to claim 1, wherein the pattern of the n electrode or the pattern of the recess is a pattern in which a closed curve by the recess is equally divided by the wiring-like n electrode. 3. Production method.   3. The group III nitride semiconductor light-emitting device according to claim 2, wherein the n-electrode pattern or the recess pattern is a pattern in which a closed curve by the wiring-like n-electrode is equally divided by the recess. Manufacturing method.   5. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 1, wherein the pattern of the n electrode or the pattern of the recesses is in a lattice shape. 6.   6. The method according to claim 1, wherein the fourth step includes a step of forming the concave portion by dry etching and a step of forming fine irregularities by wet etching after the formation of the concave portion. A method for producing a group III nitride semiconductor light-emitting device according to claim 1.   The fourth step includes forming a molten layer that melts by wet etching on the surface of the n-type layer exposed by removing the growth substrate, and melting the n-type layer and the molten layer by wet etching. The method of manufacturing a group III nitride semiconductor light-emitting device according to claim 1, further comprising: simultaneously forming the recess and the fine unevenness. A conductive support, a p-electrode formed on the support, a p-type layer made of a group III nitride semiconductor, an active layer, an n-type layer, and the n-layer, which are sequentially stacked on the p-electrode; A group III nitride semiconductor light-emitting device having an n-electrode formed on the mold layer,
A recess having a pattern having a plurality of closed curves is formed on the surface of the n-type layer on the n-electrode formation side, and fine unevenness is formed on the surface and the bottom surface of the recess,
The n electrode is formed in a wiring pattern having a pattern that passes through all of the closed curve by the concave portion.
A group III nitride semiconductor light emitting device characterized by the above. A conductive support, a p-electrode formed on the support, a p-type layer made of a group III nitride semiconductor, an active layer, an n-type layer, and the n-layer, which are sequentially stacked on the p-electrode; A group III nitride semiconductor light-emitting device having an n-electrode formed on the mold layer,
A concave portion having a predetermined pattern is formed on the surface of the n-type layer on the n electrode forming side, and fine irregularities are formed on the surface and the bottom surface of the concave portion,
The n electrode is a wiring pattern having a plurality of closed curves, and is formed so as to include the concave portion in the n-type layer region in each closed curve.
A group III nitride semiconductor light emitting device characterized by the above.   9. The group III nitride semiconductor light emitting device according to claim 8, wherein the pattern of the n electrode or the pattern of the recess is a pattern in which a closed curve by the recess is equally divided by the wiring-like n electrode.   10. The group III nitride semiconductor light-emitting device according to claim 9, wherein the pattern of the n electrode or the pattern of the recess is a pattern in which a closed curve by the wiring-like n electrode is equally divided by the recess. .   12. The group III nitride semiconductor light-emitting device according to claim 8, wherein the pattern of the n-electrode or the pattern of the recesses is in a lattice shape.

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