JP5152466B2 - Memory controller - Google Patents

Description

  The present invention relates to a technique for performing read / write access to a memory at high speed.

  Recently, switching operations of semiconductor transistors and the like can be performed at high speed. For this reason, an operation clock suitable for the characteristics of a memory composed of a semiconductor transistor or the like has become faster as the operation clock of a host system that performs read / write access to the memory.

  In this case, in synchronization with the high-speed operation clock of the host system, the host system outputs a read control signal to the memory and inputs read data from the memory, thereby performing read access to the memory at high speed. Is becoming possible.

  In addition, in synchronization with a high-speed operation clock of the host system, the host system can perform write access to the memory at high speed by outputting a write control signal and write data to the memory.

  However, whether or not the host system can perform read / write access to the memory at high speed greatly affects not only the operation clock of the host system and the operation clock suitable for the characteristics of the memory but also the software control of the host system. Dependent.

  That is, depending on the software control of the host system, the memory cannot input a read control signal from the host system at a timing suitable for the characteristics of the memory, and cannot output read data to the host system.

  Further, depending on the software control of the host system, the memory cannot input a write control signal and write data from the host system at a timing suitable for the characteristics of the memory.

  For this reason, the host system may not be able to perform read / write access to the memory at a high speed even though the operation clock suitable for the characteristics of the host system and the memory is high speed.

  Therefore, in view of the above problems, the present invention does not depend on the software control of the host system, and does not depend on the difference between the operation clock of the host system and the operation clock suitable for the characteristics of the memory. An object of the present invention is to provide a means for performing a high speed on a memory.

In order to solve the above problem, the invention according to claim 1 is a memory controller that performs read access to a memory storing data read by a host system, and after inputting a read command from the host system, Control signal output means for outputting a control signal to the memory in synchronization with a second clock signal which is a clock signal having a frequency determined according to the characteristics of the memory and satisfying the operation guarantee of the memory; After the read data related to the read command is input from the memory in synchronization with the second clock signal, the read to the host system is performed in synchronization with the first clock signal that is a clock signal input from the host system. Data input / output means for outputting read data related to the command. The control signal output means outputs the control signal to the memory when the read data related to the read command is input from the memory, and outputs the read data related to the read command to the host system. Sometimes, a time series pattern of a memory control signal for controlling the memory as a time series pattern of the control signal determined according to a characteristic of the memory and means for stopping the output of the control signal to the memory And a time series pattern of an internal control signal for performing internal control of the memory controller, which is determined according to the characteristics of the memory, and in synchronization with the second clock signal, And outputting the memory control signal as the control signal to the memory When controlling the serial memory control signals, based on the time series pattern of the internal control signal being stored, characterized in that it comprises a means for executing the memory controller internal control.

According to a second aspect of the present invention, in the memory controller according to the first aspect, the data input / output means stores a read unit related to the read command and a buffer unit that stores the read data related to the read command, and the read data related to the read command from the memory. Means for setting the second clock signal as a clock signal for operating the buffer unit when inputting, and operating the buffer unit when outputting read data related to the read command to the host system Means for setting a clock signal to the first clock signal.

According to a third aspect of the present invention, in the memory controller according to the first or second aspect , the data input / output unit includes a buffer unit that stores read data related to the read command, and the memory The means for setting the operation clock of the buffer unit to the second clock when inputting read data related to the read command, and the operation clock of the buffer unit when outputting read data related to the read command to the host system Means for setting to the first clock.

According to a fourth aspect of the present invention, in the memory controller according to any one of the first to third aspects, after the data input / output unit is permitted to read the read data related to the read command from the memory, Access path setting means for setting an access path for inputting read data related to the read command from the memory, wherein the access path setting means sets a time series pattern of an access path setting signal for setting the access path. Means for storing and setting the access path in synchronization with the second clock signal.

The invention according to claim 5 is a memory controller for performing write access to a memory storing data to be written by the host system, and is determined according to the characteristics of the memory after a write command is input from the host system. A control signal output means for outputting a control signal to the memory in synchronization with a second clock signal which is a clock frequency having a frequency that satisfies the operation guarantee of the memory, and a clock input from the host system The write data related to the write command is input from the host system in synchronization with the first clock signal, and then the write data related to the write command is output to the memory in synchronization with the second clock. Data input / output means, the control signal output means, Means for stopping the output of the control signal to the memory when inputting write data related to the write command from the host system; and the control for the memory when outputting write data related to the write command to the memory. Means for outputting a signal; storing a time series pattern of a memory control signal for controlling the memory as a time series pattern of the control signal determined according to characteristics of the memory; and A time series pattern of an internal control signal for performing internal control of the memory controller, which is determined according to the characteristics of the memory controller, is stored, and the memory as the control signal is stored in the memory in synchronization with the second clock signal Control signal is output and the memory is controlled by the memory control signal That case, based on the time series pattern of the internal control signal being stored, characterized in that it comprises a means for executing the memory controller internal control.

According to a sixth aspect of the present invention, in the memory controller according to the fifth aspect , the data input / output means includes a buffer unit for storing write data related to the write command, and write data related to the write command from the host system. Is input to the first clock signal, and when the write data related to the write command is output to the memory, the buffer unit is operated. Means for setting a clock signal to the second clock signal.

According to a ninth aspect of the present invention, in the memory controller according to any one of the sixth to eighth aspects, the data input / output means receives the write data related to the write command from the host system. Means for permitting the system to write data related to the write command; and means for prohibiting writing of the write data related to the write command to the host system when outputting the write data related to the write command to the memory; , Including.

According to an eighth aspect of the present invention, in the memory controller according to any one of the first to seventh aspects, the second clock signal has a higher frequency than the first clock signal.

According to a ninth aspect of the present invention, in the memory controller according to any one of the first to eighth aspects, the second clock signal has a frequency that is variable according to the operation guarantee of the memory. To do.

A tenth aspect of the present invention is the memory controller according to any one of the first to ninth aspects, further comprising a clock conversion unit that converts the first clock signal into the second clock signal. And

The invention according to claim 11 is the memory controller according to any one of claims 1 to 9 , further comprising means for inputting the second clock signal from a clock generator for generating the second clock signal, It is characterized by providing.

According to a twelfth aspect of the present invention, in the memory controller according to any one of the second to fourth aspects, or the sixth to eleventh aspects, the buffer unit is an
It is characterized by being FO.

According to a thirteenth aspect of the present invention, in the memory controller according to the first to fourth aspects or the fifth to twelfth aspects, the time series pattern of the memory control signal and the time series pattern of the internal control signal are: It is variable according to the characteristics of the memory.

  A memory controller disposed between the host system and the memory outputs a read / write control signal suitable for the characteristics of the memory to the memory by hardware control of the memory controller. Specifically, the memory controller stores in advance a time series pattern of read / write control signals suitable for the characteristics of the memory as a vector pattern. The memory controller outputs a read / write control signal suitable for the memory characteristics to the memory in synchronization with an operation clock suitable for the memory characteristics.

  The memory controller temporarily stores read / write data in the buffer unit. When the memory controller exchanges read / write data with the memory, the operation clock of the buffer unit is set to an operation clock suitable for the characteristics of the memory. When the memory controller exchanges read / write data with the host system, the operation clock of the buffer unit is set to the operation clock of the host system.

  Then, the memory can operate at a timing suitable for the characteristics of the memory. The host system can operate at a timing suitable for the characteristics of the host system. Therefore, the host system does not depend on the host system software control, and does not depend on the difference between the operation clock of the host system and the operation clock suitable for the characteristics of the memory. Can be done.

  Furthermore, the present invention can also be implemented when the host system performs read / write access to various memories. Specifically, the memory controller sets the time-series pattern and operation clock of the read / write control signal suitable for various memory characteristics.

{Components of information processing apparatus according to this embodiment}
Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, components of the information processing apparatus according to the present embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing the flow of read access processing. FIG. 6 is a block diagram showing a flow of write access processing. The information processing apparatus shown in FIG. 1 and FIG. 6 is the same information processing apparatus, and includes a host system 1, a memory system 2, and the like. Further, the memory system 2 includes a memory 3 and a memory controller 4.

  The host system 1 outputs a read command to the memory controller 4 in order to read data from the memory 3. Further, the host system 1 outputs a write command and write data to the memory controller 4 in order to write data to the memory 3. The processing flow of the host system 1 is performed in synchronization with the operation clock of the host system 1. In order to distinguish the operation clock of the host system 1 from other operation clocks to be described later, it is defined as a first clock (CLK1).

  The memory 3 inputs a read command from the memory controller 4 and outputs read data to the memory controller 4. The memory 3 also receives a write command and write data from the memory controller 4. The processing flow of the memory 3 is performed in synchronization with an operation clock suitable for the characteristics of the memory 3. An operation clock suitable for the characteristics of the memory 3 is defined as a second clock (CLK2).

  In the present embodiment, a NAND flash memory is used as the memory 3. However, other memories such as NOR flash memory can also be used. An embodiment using another memory will be described later as a modified example.

  The memory controller 4 relays read / write commands and read / write data between the host system 1 and the memory 3. That is, the memory controller 4 exchanges commands and data with the host system 1 in synchronization with the first clock. The memory controller 4 exchanges commands and data with the memory 3 in synchronization with the second clock.

  The first clock and the second clock usually have different frequencies. However, the memory controller 4 can separate the exchange with the host system 1 and the exchange with the memory 3. Therefore, the host system 1 and the memory 3 can perform each processing flow at a timing suitable for each characteristic.

  The memory controller 4 includes a host interface unit 41, a clock changing unit 42, a command decoder unit 43, an access controller unit 44, an SRAM unit 45, a buffer unit 46, an edge sensitive circuit unit 47, a memory interface unit 48, a gate circuit unit 49G, and a selector. 49S.

  The host interface unit 41 is an interface for exchanging read / write commands, read / write data, a first clock, and the like between the host system 1 and the memory controller 4.

  The clock conversion unit 42 converts the first clock into the second clock. In the present embodiment, a phase locked loop (PLL) is used as the clock converter 42. Then, the present invention can be implemented without depending on the level relationship between the frequencies of the first clock and the second clock. In addition, a clock generation unit that generates the second clock without converting the first clock may be externally attached to the host system 1 or the memory system 2. An embodiment in which the clock generation unit is externally attached will be described later as a modified example.

  The command decoder unit 43 extracts the read command ID and the read address from the read command. Further, the command decoder unit 43 extracts the write command ID and the write address from the write command. In this embodiment, a hexadecimal number such as “00H” is used as the read / write command ID.

  The access controller unit 44 performs read / write access to the memory 3. However, the access controller unit 44 does not output a memory control signal to the memory 3. Rather, the access controller unit 44 notifies the SRAM unit 45 to output a memory control signal to the memory 3. The processing flow of the access controller unit 44 is performed in synchronization with the second clock.

  The SRAM unit 45 outputs a memory control signal to the memory 3 in response to the notification from the access controller unit 44. The processing flow of the SRAM unit 45 is also performed in synchronization with the second clock, similar to the processing flow of the access controller unit 44. Here, the memory control signal output from the SRAM unit 45 to the memory 3 is preset by the vector pattern 451 so as to suit the characteristics of the memory 3.

  Then, the memory controller 4 can output a memory control signal suitable for the characteristics of the memory 3 to the memory 3 in synchronization with the second clock suitable for the characteristics of the memory 3. That is, the memory controller 4 can perform read / write access to the memory 3 by the hardware control of the memory controller 4 without being controlled by the software of the host system 1. Therefore, the memory 3 can input a memory control signal at a timing suitable for the characteristics of the memory 3.

  The buffer unit 46 temporarily stores read / write data in the FIFO 461. When the buffer unit 46 exchanges read / write data with the host system 1, the buffer control clock is set to the first clock. When the buffer unit 46 exchanges read / write data with the memory 3, the buffer control clock is set to the second clock. Therefore, the host system 1 can input read data and can output write data at a timing suitable for the characteristics of the host system 1. In addition, the memory 3 can output read data and input write data at a timing suitable for the characteristics of the memory 3.

  The edge sensitive circuit unit 47 notifies the access controller unit 44 to stop the read / write access when the buffer unit 46 exchanges read / write data with the host system 1. Then, the edge sensitive circuit unit 47 notifies the host system 1 that data reading / writing is permitted.

  The edge sensitive circuit unit 47 notifies the access controller unit 44 to perform read / write access when the buffer unit 46 exchanges read / write data with the memory 3. Then, the edge sensitive circuit unit 47 notifies the host system 1 that data reading / writing is prohibited.

  Then, the edge sensitive circuit unit 47 does not permit read / write access by the access controller unit 44 and data read / write by the host system 1 at the same time. That is, the memory controller 4 can separate the exchange with the host system 1 and the exchange with the memory 3. Therefore, the host system 1 and the memory 3 can perform each processing flow at a timing suitable for each characteristic.

  The memory interface unit 48 is an interface for exchanging read / write commands, read / write data, memory control signals, and the like between the memory 3 and the memory controller 4.

  The gate circuit unit 49G1 and the selector unit 49S1 are a gate and a selector for the memory 3 to input a read / write command and write data. The gate circuit unit 49G2 is a gate through which the buffer unit 46 inputs read data. The selector unit 49S2 is a selector for the buffer unit 46 to input read / write data. The gate circuit units 49G3 and 49G4 and the selector units 49S3 and 49S4 constitute a circuit that switches the buffer control clock between the first clock and the second clock.

{Flow of read access processing}
Next, the flow of read access processing will be described with reference to FIGS. FIG. 2 is a flowchart showing the flow of read access processing. Step SR in the read access shown in FIG. 2 corresponds to step SR in the read access shown in FIG. In the present embodiment, the host system 1 tries to read data for a plurality of pages in the memory 3. Further, the buffer unit 46 can store read data for one page of the memory 3.

  The command decoder unit 43 inputs a read command from the host system 1 via the host interface unit 41 (step SR1). Then, the command decoder unit 43 extracts the read command ID and the read address from the read command (step SR2). In the present embodiment, the read address is a read address for a plurality of pages in the memory 3. Then, the command decoder unit 43 outputs the read command ID and the read address to the access controller unit 44.

  The access controller 44 recognizes the read command ID and outputs a read / write select signal “1” to the selectors 49S2 and 49S3. The thick lines indicated by the selectors 49S2 and 49S3 indicate that the selectors 49S2 and 49S3 are inputting the read / write select signal “1”. Therefore, a read data path is generated between the buffer unit 46 and the memory 3 (step SR3).

  The access controller unit 44 receives an access stop signal “0” or “1” from the edge sensitive circuit unit 47. The access stop signal is a signal for permitting or prohibiting the access controller unit 44 from accessing the memory 3. Here, in the read / write access, the logic of the access stop signal is inverted. That is, in read access, the access stop signal “0” indicates access permission, and the access stop signal “1” indicates access prohibition. In write access, the access stop signal “0” indicates access prohibition, and the access stop signal “1” indicates access permission.

  The access controller unit 44 adopts the logic of the access stop signal in the read access by recognizing the read command ID. As will be described later, the access controller unit 44 inputs the access stop signal “0” from the edge sensitive circuit unit 47 in step SR3. Therefore, the access controller unit 44 starts read access (step SR4).

  The access controller unit 44 outputs the SRAM address to the SRAM unit 45. Then, the SRAM unit 45 performs a read operation on the SRAM address. The SRAM unit 45 then outputs the data stored at the SRAM address to the memory 3 and the memory controller 4. The processing flow of the access controller unit 44 and the SRAM unit 45 described above is performed in synchronization with the second clock generated by the clock conversion unit 42 converting the first clock.

  The SRAM unit 45 stores in advance a time series pattern of memory control signals suitable for the characteristics of the memory 3 as a vector pattern 451. Therefore, the SRAM unit 45 outputs a memory control signal suitable for the characteristics of the memory 3 to the memory 3 in synchronization with the second clock suitable for the characteristics of the memory 3. A method in which the SRAM unit 45 outputs the memory control signal will be specifically described below.

  First, the vector pattern 451 stored in the SRAM unit 45 will be described. FIG. 3 is a code image of the vector pattern 451 of the read access waveform. ADD is the SRAM address, CLE is the command latch enable signal, CE is the chip enable signal, WE is the write enable signal, ALE is the address latch enable signal, RE is the read enable signal, DIR indicates a direction signal, STR indicates a strobe signal, and SEL indicates a selector signal.

  Memory control signals (CLE, CE, WE, ALE, RE) are control signals output from the SRAM unit 45 to the memory 3. Internal control signals (DIR, STR, SEL) are control signals output from the SRAM unit 45 to the memory controller 4. Further, bars attached to CE, WE, and RE indicate that the memory control signals (CE, WE, and RE) are active low.

  The access controller unit 44 recognizes the read command ID and outputs the address R0 as the SRAM address to the SRAM unit 45 at the rising edge of the second clock. Then, the SRAM unit 45 performs a read operation on the address R0, and outputs a memory control signal and an internal control signal preset in the address R0 to the memory 3 and the memory controller 4.

  That is, the SRAM unit 45 sets “0” as the command latch enable signal, “1” as the chip enable signal, “1” as the write enable signal, and “0” as the address latch enable signal. Then, “1” is output to the memory 3 as a read enable signal.

  In addition, the SRAM unit 45 outputs “0” as the direction signal to the gate circuit unit 49G1. The SRAM unit 45 then outputs “0” as the strobe signal to the selector unit 49S4. Further, the SRAM unit 45 outputs “1” as a selector signal to the selector unit 49S1.

  The access controller unit 44 outputs the address R1 as the SRAM address to the SRAM unit 45 at the next rising edge of the second clock. Then, the SRAM unit 45 outputs a memory control signal and an internal control signal set in advance to the address R1 to the memory 3 and the memory controller 4. Each time the second clock rises, the access controller unit 44 and the SRAM unit 45 perform the above-described processing flow until the buffer unit 46 inputs read data for one page.

  In the present embodiment, the access controller unit 44 outputs the SRAM address to the SRAM unit 45 by address increment from the address R0. However, the access controller unit 44 may output the SRAM address to the SRAM unit 45 by address decrement or address jump.

  Next, time series patterns of the memory control signals (CLE, CE, WE, ALE, RE) and internal control signals (DIR, STR, SEL) will be described. 4 and 5 are diagrams showing read access waveforms.

  It shows that time passes as it moves from the left side to the right side. 4 and 5 are connected by an alternate long and short dash line A. That is, after moving from the left end of FIG. 4 to the right end, time passes as it moves from the left end of FIG. 5 to the right end. The interval between the broken lines in the vertical direction indicates the period of the second clock. In the period of the broken line in the left-right direction, the read access waveform is omitted.

  During the period when ADD is R0, the SRAM unit 45 outputs the memory control signals (CLE, CE, WE, ALE, RE) relating to the address R0 to the memory 3. The SRAM unit 45 outputs internal control signals (DIR, STR, SEL) related to the address R0 to the inside of the memory controller 4. Each memory control signal and each internal control signal are reflected in the read access waveform. Even in a period when ADD is other than R0, each memory control signal and each internal control signal are reflected in the read access waveform.

  In a period in which ADD is R2, R5, R7, and R10, the SRAM unit 45 outputs an internal control signal (SEL) “1” to the selector unit 49S1. The SRAM unit 45 outputs an internal control signal (DIR) “0” to the gate circuit unit 49G1. Therefore, the access controller unit 44 can output the read command ID and the read address to the memory 3 via the I / O terminal of the memory 3.

  In a period in which ADD is R2 and R10, the memory control signal (WE) is “0”. The memory control signal (CLE) is “1” when the memory control signal (WE) falls and rises. Therefore, the read command ID and the read start command ID are taken into the memory 3.

  In a period in which ADD is R5 and R7, the memory control signal (WE) is “0”. The memory control signal (ALE) is “1” when the memory control signal (WE) falls and rises. Therefore, the read column address and read page address are taken into the memory 3.

  In the present embodiment, the host system 1 tries to read data for a plurality of pages. The buffer unit 46 can store read data for one page. Therefore, the first page among a plurality of pages is set as the read page address. In addition, the first column 0 is set as the read column address. Then, as will be described later, the data stored in the first page is read to the buffer unit 46 in the order from the first column 0 to the last column.

  Here, a method for setting the period of the second clock will be specifically described below. For example, the minimum time when the memory control signal (WE) should be set to “0” when the read command ID is taken into the memory 3 during the period when ADD is R2 is described in the characteristic value table of the memory 3 or the like. Has been.

  Consider a case where the minimum time for setting the memory control signal (WE) to “0” is, for example, 20 nsec. In this case, the cycle of the second clock may be set to 20 nsec, similarly to the minimum time when the memory control signal (WE) should be set to “0”. The period of the second clock is set by the clock converter 42.

  In addition to the method described above, other methods can be adopted as a method for setting the period of the second clock. For example, during the period when ADD is R13, the minimum time during which the memory control signal (RE) should be set to “0” can be set as the period of the second clock.

  During the period when ADD is R10, the read operation is started inside the memory 3 after the read start command ID is taken into the memory 3. When the read operation is performed in the memory 3, the RDY / BSY signal “0” is output from the memory 3 to the access controller unit 44. The RDY / BSY signal “0” is a signal indicating that the operation state of the memory 3 is the BUSY state.

  When the access controller 44 recognizes the RDY / BSY signal “0”, the access controller 44 temporarily stops the address control for incrementing the SRAM address. That is, the access controller unit 44 holds the SRAM address output to the SRAM unit 45 as it is without incrementing the address R12 to the address R13.

  When the read operation ends in the memory 3, the RDY / BSY signal “1” is output from the memory 3 to the access controller unit 44. The RDY / BSY signal “1” is a signal indicating that the operation state of the memory 3 is the READY state.

  When the access controller unit 44 recognizes the RDY / BSY signal “1”, the access controller unit 44 resumes the address control for incrementing the SRAM address. In other words, the access controller unit 44 increments the SRAM address output to the SRAM unit 45 from the address R12 to the address R13.

  When a transition is made from a period in which ADD is R12 to a period in which ADD is R13, the internal control signal (DIR) is switched from “0” to “1”. In other words, when the read operation is completed in the memory 3, an access path for the memory controller 4 to read data stored in the first page from the memory 3 is quickly set.

  When performing read access under software control of the host system 1, even if the read operation ends in the memory 3, the access path cannot be set quickly. However, when a read access is performed by hardware control of the memory controller 4, that is, by the vector pattern 451 of the read control signal, the access path can be quickly set when the read operation is completed inside the memory 3.

  In a period in which ADD is R13, the memory control signal (RE) is “0”. Therefore, the data stored in the first column 0 of the first page is stored in the memory 3 via the I / O terminal of the memory 3 after a predetermined time according to the characteristics of the memory 3 from the falling edge of the memory control signal (RE). Is output to the memory controller 4.

  Even in a period in which ADD is R15, R17, R19, RN-2, etc., the memory control signal (RE) is “0”. Therefore, the data stored in the first page is output from the memory 3 to the memory controller 4 in the order from the column 1 to the last column. The address RN in the vector pattern 451 is determined by the number of columns in one page.

  In a period in which ADD is R14, R16, R18, RN-1, etc., the internal control signal (STR) is “1”. As will be described later, the buffer unit 46 receives an internal control signal (STR) from the SRAM unit 45 as a buffer control clock (step SR5). In step SR3, a read data path has already been generated. Then, the buffer unit 46 can input the data stored in the first page while acquiring the timing for inputting the read data (step SR6).

  In the present embodiment, the buffer unit 46 can store read data for one page. Therefore, the FIFO 461 outputs the full signal “1” to the edge sensitive circuit unit 47 when all the data stored in the first page has been input. Then, the edge sensitive circuit unit 47 outputs the access stop signal “1” to the access controller unit 44, the gate circuit units 49G3 and 49G4, and the host system 1 by detecting the rising edge of the Full signal.

  In step SR3, the access controller unit 44 employs the logic of an access stop signal in read access. Therefore, the access controller unit 44 temporarily stops read access. That is, the access controller unit 44 temporarily stops the output of the SRAM address (step SR7).

  The selector unit 49S3 receives the read / write select signal “1” from the access controller unit 44 in step SR3. Therefore, the selector unit 49S3 inputs the signal “1” that is not logically inverted from the access stop signal “1” from the gate circuit unit 49G3, and outputs it to the selector unit 49S4. Then, the buffer unit 46 inputs the first clock from the host system 1 as the buffer control clock (step SR8).

  The host system 1 inputs the access stop signal “1” as the read permission signal “1”. The read permission signal is a signal for permitting or prohibiting the host system 1 from reading data from the buffer unit 46. The read permission signal “0” indicates read prohibition, and the read permission signal “1” indicates read permission. Then, the buffer unit 46 outputs the data stored in the first page to the host system 1 in synchronization with the first clock as the buffer control clock (step SR9).

  The FIFO 461 outputs the Empty signal “1” to the edge-sensitive circuit unit 47 when all the data stored in the first page has been output. Then, the edge sensitive circuit unit 47 outputs the access stop signal “0” to the access controller unit 44, the gate circuit units 49G3 and 49G4, and the host system 1 by detecting the rising edge of the Empty signal.

  In step SR2, the access controller unit 44 inputs read addresses for a plurality of pages from the command decoder unit 43. However, the access controller unit 44 has already performed only the read access for the first page among the read accesses for a plurality of pages (step SR10). Therefore, the access controller unit 44 resumes read access. That is, the access controller unit 44 resumes outputting the SRAM address (step SR4).

  The selector unit 49S3 inputs a signal “0” that is not logically inverted from the access stop signal “0” from the gate circuit unit 49G3, and outputs the signal to the selector unit 49S4. Then, the buffer unit 46 inputs an internal control signal (STR) from the SRAM unit 45 as a buffer control clock (step SR5).

  The host system 1 inputs the access stop signal “0” as the read permission signal “0”. Then, the buffer unit 46 stores the read data until the next time the access stop signal is switched from “0” to “1”, that is, until the next time the read permission signal is switched from “0” to “1”. It is not output to 1.

  The flow of read access processing for the remaining pages is the same as the flow of read access processing for the first page. That is, the access controller unit 44 outputs the SRAM address to the SRAM unit 45 by address increment from the address R0 to the address RN in synchronization with the second clock. Then, the SRAM unit 45 outputs a memory control signal to the memory 3 based on the vector pattern 451 in synchronization with the second clock.

  The buffer unit 46 inputs read data from the memory 3 one page at a time in synchronization with the second clock. Then, the edge sensitive circuit unit 47 notifies the access controller unit 44 so as to temporarily stop the read access. Further, the edge sensitive circuit unit 47 switches the buffer control clock from the second clock to the first clock. Then, the host system 1 inputs read data for each page from the buffer unit 46 in synchronization with the first clock.

{Flow of write access processing}
Next, the flow of the write access process will be described with reference to FIGS. FIG. 7 is a flowchart showing the flow of the write access process. Step SW in the write access shown in FIG. 7 corresponds to step SW in the write access shown in FIG. In the present embodiment, the host system 1 is going to write data for a plurality of pages in the memory 3. The buffer unit 46 can store write data for one page in the memory 3.

  The command decoder unit 43 inputs a write command from the host system 1 via the host interface unit 41 (step SW1). Then, the command decoder unit 43 extracts the write command ID and the write address from the write command (step SW2). In the present embodiment, the write address is a write address for a plurality of pages in the memory 3. Then, the command decoder unit 43 outputs the write command ID and the write address to the access controller unit 44.

  The access controller 44 recognizes the write command ID and outputs a read / write select signal “0” to the selectors 49S2 and 49S3. The thick lines indicated by the selectors 49S2 and 49S3 indicate that the selectors 49S2 and 49S3 are inputting the read / write select signal “0”. Therefore, a write data path is generated between the buffer unit 46 and the host system 1 (step SW3).

  The access controller unit 44 receives an access stop signal “0” or “1” from the edge sensitive circuit unit 47. The access stop signal is a signal for permitting or prohibiting the access controller unit 44 from accessing the memory 3. Here, in the read / write access, the logic of the access stop signal is inverted. In write access, the access stop signal “0” indicates access prohibition, and the access stop signal “1” indicates access permission. The access controller unit 44 adopts the logic of the access stop signal in the write access by recognizing the write command ID.

  In the present embodiment, the buffer unit 46 can store write data for one page. Therefore, the FIFO 461 outputs an Empty signal “1” to the edge sensitive circuit unit 47 before starting to input write data. Then, the edge sensitive circuit unit 47 outputs an access stop signal “0” to the access controller unit 44, the gate circuit units 49G3 and 49G4, and the host system 1 by detecting the Empty signal “1”.

  In step SW3, the access controller unit 44 employs the logic of an access stop signal in the write access. Therefore, the access controller unit 44 does not perform write access. That is, the access controller unit 44 does not output the SRAM address.

  The selector unit 49S3 inputs the read / write select signal “0” from the access controller unit 44 in step SW3. Therefore, the selector unit 49S3 inputs the signal “1” obtained by logically inverting the access stop signal “0” from the gate circuit unit 49G4, and outputs it to the selector unit 49S4. Then, the buffer unit 46 inputs the first clock from the host system 1 as the buffer control clock (step SW4).

  The host system 1 inputs the access stop signal “0” as the write permission signal “0”. The write permission signal is a signal for permitting or prohibiting the host system 1 from writing data into the buffer unit 46. The write permission signal “0” indicates write permission, and the write permission signal “1” indicates write prohibition. Then, the buffer unit 46 inputs the write data from the host system 1 in synchronization with the first clock as the buffer control clock (step SW5).

  The FIFO 461 outputs a full signal “1” to the edge-sensitive circuit unit 47 when the write data for one page has been input. Then, the edge sensitive circuit unit 47 outputs the access stop signal “1” to the access controller unit 44, the gate circuit units 49G3 and 49G4, and the host system 1 by detecting the rising edge of the Full signal.

  In step SW3, the access controller unit 44 employs the logic of an access stop signal in the write access. Therefore, the access controller unit 44 starts write access. That is, the access controller unit 44 starts outputting the SRAM address (step SW6).

  The selector unit 49S3 inputs a signal “0” obtained by logically inverting the access stop signal “1” from the gate circuit unit 49G4 and outputs the signal to the selector unit 49S4. Then, the buffer unit 46 inputs an internal control signal (STR) from the SRAM unit 45 as a buffer control clock (step SW7).

  The host system 1 inputs the access stop signal “1” as the write permission signal “1”. Then, the buffer unit 46 stores the write data until the next time the access stop signal is switched from “1” to “0”, that is, until the next time the write permission signal is switched from “1” to “0”. There is no input from 1.

  The method in which the SRAM unit 45 outputs the memory control signal when the access controller unit 44 performs read / write access is the same. First, the vector pattern 451 stored in the SRAM unit 45 will be described. FIG. 8 is a code image of the vector pattern 451 of the write access waveform.

  The access controller unit 44 recognizes the write command ID. Therefore, the access controller unit 44 outputs the SRAM address in the vector pattern 451 to the SRAM unit 45 by incrementing the address from the address W0. Then, the SRAM unit 45 outputs a memory control signal and an internal control signal to the memory 3 and the memory controller 4 based on the vector pattern 451. The processing flow of the access controller unit 44 and the SRAM unit 45 is performed in synchronization with the second clock.

  Next, time series patterns of the memory control signals (CLE, CE, WE, ALE, RE) and internal control signals (DIR, STR, SEL) will be described. 9 and 10 are diagrams showing write access waveforms, which are connected by a one-dot chain line B. FIG.

  During the period when ADD is W2, W5, W7, and WN-2, the SRAM unit 45 outputs the internal control signal (SEL) “1” to the selector unit 49S1. The SRAM unit 45 outputs an internal control signal (DIR) “0” to the gate circuit unit 49G1. Therefore, the access controller unit 44 can output the write command ID and the write address to the memory 3 via the I / O terminal of the memory 3.

  In a period in which ADD is W2 and WN-2, the memory control signal (WE) is “0”. The memory control signal (CLE) is “1” when the memory control signal (WE) falls and rises. Therefore, the write command ID and the write start command ID are taken into the memory 3.

  In a period when ADD is W5 and W7, the memory control signal (WE) is “0”. The memory control signal (ALE) is “1” when the memory control signal (WE) falls and rises. Therefore, the write column address and the write page address are taken into the memory 3.

  In the present embodiment, the host system 1 tries to write data for a plurality of pages. The buffer unit 46 can store write data for one page. Therefore, the first page among a plurality of pages is set as the write page address. Also, the first column 0 is set as the write column address. Then, as will be described later, data to be written to the first page is written to the memory 3 in the order from the first column 0 to the last column.

  In a period in which ADD is W10, W12, W14, WN-5, etc., the SRAM unit 45 outputs an internal control signal (SEL) “0” to the selector unit 49S1. The SRAM unit 45 outputs an internal control signal (DIR) “0” to the gate circuit unit 49G1. Therefore, the memory controller 4 can output data to be written to the first page to the memory 3 via the I / O terminal of the memory 3.

  In a period when ADD is W10, the memory control signal (WE) is “0”. Therefore, data to be written to the first column 0 of the first page is output from the memory controller 4 to the memory 3 via the I / O terminal of the memory 3.

  Even in a period in which ADD is W12, W14, WN-5, etc., the memory control signal (WE) is “0”. Therefore, data to be written to the first page is output from the memory controller 4 to the memory 3 in the order from the column 1 to the last column. The address WN in the vector pattern 451 is determined by the number of columns in one page.

  In a period in which ADD is W10, W12, W14, WN-5, etc., the internal control signal (STR) is “1”. In step SW7, the buffer unit 46 receives an internal control signal (STR) from the SRAM unit 45 as a buffer control clock. The internal control signal (SEL) is “0”. Then, the buffer unit 46 can output the data to be written to the first page while acquiring the timing for outputting the write data (step SW8).

  When the ADD is WN-5, the FIFO 461 outputs the Empty signal “1” to the edge-sensitive circuit unit 47 when it finishes outputting the data to be written to the first page. Then, the edge sensitive circuit unit 47 outputs the access stop signal “0” to the access controller unit 44, the gate circuit units 49G3 and 49G4, and the host system 1 by detecting the rising edge of the Empty signal.

  During the period when ADD is WN-2, the write operation is started inside the memory 3 after the write start command ID is taken into the memory 3. When the write operation is performed in the memory 3, the RDY / BSY signal “0” is output from the memory 3 to the memory controller 44.

  As described above, the access controller unit 44 temporarily stops the write access. That is, the access controller unit 44 temporarily stops outputting the SRAM address (step SW9). Further, the buffer unit 46 receives the first clock from the host system 1 as a buffer control clock (step SW4).

  The access controller unit 44 inputs the write addresses for a plurality of pages from the command decoder unit 43 in step SW2. However, the access controller unit 44 has already performed only the write access for the first page among the write accesses for a plurality of pages (step SW10). Therefore, the buffer unit 46 inputs the write data from the host system 1 in synchronization with the first clock as the buffer control clock (step SW5).

  The flow of processing for write access for the remaining pages is the same as the flow of processing for write access for the first page. That is, the host system 1 outputs write data for one page to the buffer unit 46 in synchronization with the first clock. Then, the edge sensitive circuit unit 47 notifies the access controller unit 44 to start the write access. Further, the edge sensitive circuit unit 47 switches the buffer control clock from the first clock to the second clock.

  The access controller unit 44 outputs the SRAM address to the SRAM unit 45 by address increment from the address W0 to the address WN in synchronization with the second clock. Then, the SRAM unit 45 outputs a memory control signal to the memory 3 based on the vector pattern 451 in synchronization with the second clock. Then, the memory 3 inputs write data for each page from the buffer unit 46 in synchronization with the second clock.

{Configuration example of edge-sensitive circuit section}
The effects of the invention in read / write access will be summarized. The memory controller 4 stores in advance a time series pattern of memory control signals suitable for the characteristics of the memory 3 as a vector pattern 451. The memory controller 4 outputs a memory control signal suitable for the characteristics of the memory 3 to the memory 3 based on the vector pattern 451 in synchronization with the operation clock suitable for the characteristics of the memory 3.

  The memory controller 4 inputs read data from the memory 3 in synchronization with an operation clock suitable for the characteristics of the memory 3. Then, the memory controller 4 outputs read data to the host system 1 in synchronization with the operation clock of the host system 1. Further, the memory controller 4 can separately perform exchange of read data with the memory 3 and exchange of read data with the host system 1.

  The memory controller 4 inputs write data from the host system 1 in synchronization with the operation clock of the host system 1. Then, the memory controller 4 outputs write data to the memory 3 in synchronization with an operation clock suitable for the characteristics of the memory 3. Furthermore, the memory controller 4 can perform the exchange of write data with the host system 1 and the exchange of write data with the memory 3 separately.

  That is, the memory controller 4 can perform read / write access to the memory 3 by the hardware control of the memory controller 4 without being controlled by the software of the host system 1. Further, the memory controller 4 can cause the host system 1 and the memory 3 to perform processing at a timing suitable for each characteristic by eliminating the handshake of the host system 1 and the memory 3. Therefore, the memory controller 4 can perform read / write access at high speed.

  The edge sensitive circuit unit 47 can eliminate the handshake between the host system 1 and the memory 3 and can switch the buffer control clock between the first clock and the second clock. It is an essential component. A configuration example of the edge sensitive circuit unit 47 will be described with reference to FIG. FIG. 11 is a diagram illustrating a configuration example of the edge sensitive circuit unit 47.

  The FIFO 461 outputs the Empty signal “1” and the Full signal “0” to the edge sensitive circuit unit 47 when the data capacity is not used at all. Further, the FIFO 461 outputs the Empty signal “0” and the Full signal “1” to the edge sensitive circuit unit 47 when all the data capacity is used. Furthermore, the FIFO 461 outputs an Empty signal “0” and a Full signal “0” to the edge sensitive circuit unit 47 when none of the two cases described above applies.

  The Empty signal and the Full signal are input to the RS flip-flop circuit unit 471 as a reset signal and a set signal, respectively. Then, when the FIFO 461 finishes outputting one page of data, the output signal becomes “0”. The output signal continues to be “0” until the FIFO 461 finishes inputting one page of data. When the FIFO 461 finishes inputting one page of data, the output signal becomes “1”. The output signal continues to be “1” until the FIFO 461 finishes outputting one page of data. The process flow described above is similarly repeated thereafter.

  The output signal of the RS flip-flop circuit unit 471 is converted into an access stop signal delayed by two cycles of the second clock by the delay flip-flop circuit units 472-1 and 472-2. The reason why the edge sensitive circuit unit 47 includes not only the RS flip-flop circuit unit 471 but also the delay flip-flop circuit units 472-1 and 472-2 will be described below.

  In the period when ADD shown in FIG. 10 is WN-5, the data capacity of the FIFO 461 is not used at all. Then, the Empty signal “1” and the Full signal “0” are input to the RS flip-flop circuit unit 471. Then, an access stop signal “0” is input to the access controller unit 44. Then, the access controller unit 44 temporarily stops the write access.

  If the data capacity of the FIFO 461 is not used at all and the access controller unit 44 temporarily stops the write access, the write start command ID is taken into the memory 3 during the period when ADD is WN-2. Absent. Then, the writing operation is not started inside the memory 3.

  Therefore, the access controller unit 44 may suspend the write access after a delay of several cycles of the second clock from when the data capacity of the FIFO 461 is not used at all. Therefore, the edge sensitive circuit unit 47 also includes delay flip-flop circuit units 472-1 and 472-2.

  In the present embodiment, the edge sensitive circuit unit 47 includes two delay flip-flop circuit units. However, there may be a case where a time corresponding to a multi-cycle of the second clock is required from when the data to be written to the last column is taken into the memory 3 to when the write start command ID is taken into the memory 3. In this case, the edge sensitive circuit unit 47 may include more delay flip-flop circuit units.

{Variation with external clock generator}
In the present embodiment, a clock conversion unit 42 that converts the first clock into the second clock is arranged inside the memory controller 4. However, a clock generation unit that generates the second clock without converting the first clock may be externally attached to the host system 1 or the memory system 2. A modification in which the clock generation unit is externally attached will be described below.

  First, a high frequency oscillator can be used as the clock generation unit. This is convenient when the operation clock suitable for the characteristics of the memory 3 is high speed. Next, a programmable oscillator can be used as the clock generator. This is convenient when various memories are incorporated as the memory 3 when the memory system 2 is manufactured. When the programmable oscillator is used, the operation clock frequency suitable for the characteristics of various memories may be set by referring to the characteristic value tables of various memories.

{Variations for incorporating various memories}
In this embodiment, a NAND flash memory is used. However, other memories such as NOR flash memory can also be used. Modification examples for incorporating various memories will be described with specific examples for incorporating a NAND flash memory or a NOR flash memory.

  The NAND flash memory and the NOR flash memory store a vector pattern 451 in a partial area for memory control signals suitable for each characteristic. When switching from the state using the NAND flash memory to the state using the NOR flash memory, the host system 1 performs initialization settings.

  The host system 1 notifies the access controller unit 44 of switching from the NAND flash memory to the NOR flash memory. The access controller unit 44 performs read access to the NOR flash memory, and reads the vector pattern 451 stored in the NOR flash memory to the SRAM unit 45. Then, the memory controller 4 can output a memory control signal suitable for the characteristics of the NOR flash memory to the NOR flash memory.

  When switching from the NAND flash memory to the NOR flash memory, only the vector pattern 451 has to be changed without changing the components of the memory controller 4. When the NOR flash memory is used, it is convenient when reading / writing is performed in units of one page as in the case of using the NAND flash memory.

It is a block diagram which shows the flow of a read access process. It is a flowchart which shows the flow of a read access process. It is a code image of the vector pattern of a read access waveform. It is a figure which shows a read access waveform. It is a figure which shows a read access waveform. It is a block diagram which shows the flow of a process of write access. It is a flowchart which shows the flow of a process of write access. It is a code image of the vector pattern of a write access waveform. It is a figure which shows a write access waveform. It is a figure which shows a write access waveform. It is a figure which shows the structural example of an edge sensitive circuit part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host system 2 Memory system 3 Memory 4 Memory controller 41 Host interface part 42 Clock conversion part 43 Command decoder part 44 Access controller part 45 SRAM part 46 Buffer part 47 Edge sensitive circuit part 48 Memory interface part 49G1, 49G2, 49G3, 49G4 Gate Circuit unit 49S1, 49S2, 49S3, 49S4 Selector unit 451 Vector pattern 461 FIFO
471 RS flip-flop circuit unit 472-1, 472-2 Delay flip-flop circuit unit

Claims (13)

A memory controller that performs read access to a memory that stores data to be read by a host system,
After inputting a read command from the host system, the memory is synchronized with a second clock signal that is a clock signal having a frequency determined according to the characteristics of the memory and satisfying the operation guarantee of the memory. Control signal output means for outputting a control signal to,
After the read data related to the read command is input from the memory in synchronization with the second clock signal, the read to the host system is performed in synchronization with the first clock signal that is a clock signal input from the host system. Data input / output means for outputting read data relating to the command;
With
The control signal output means includes
Means for outputting the control signal to the memory when inputting read data related to the read command from the memory;
Means for stopping output of the control signal to the memory when outputting read data related to the read command to the host system;
A time series pattern of a memory control signal for controlling the memory is stored as a time series pattern of the control signal, which is determined according to the characteristics of the memory, and is further determined according to the characteristics of the memory. Storing a time series pattern of an internal control signal for performing internal control of the memory controller, outputting the memory control signal as the control signal to the memory in synchronization with the second clock signal, and Means for executing internal control of the memory controller based on a time-series pattern of the stored internal control signal when the memory is controlled by the memory control signal;
A memory controller comprising: The memory controller of claim 1, wherein
The data input / output means includes
A buffer unit for storing read data related to the read command;
Means for setting a clock signal for operating the buffer unit to the second clock signal when inputting read data related to the read command from the memory;
Means for setting a clock signal for operating the buffer unit to the first clock signal when outputting read data related to the read command to the host system;
A memory controller comprising: The memory controller according to claim 1 or 2 ,
The data input / output means includes
Means for prohibiting the host system from reading the read data related to the read command when inputting read data related to the read command from the memory;
Means for allowing the host system to read the read data related to the read command when outputting read data related to the read command to the host system;
A memory controller comprising: The memory controller according to any one of claims 1 to 3 ,
The data input / output means includes
An access path setting means for setting an access path for inputting the read data related to the read command from the memory after being permitted to read the read data related to the read command from the memory;
Including
The access path setting means includes
Means for storing a time-series pattern of an access path setting signal for setting the access path and setting the access path in synchronization with the second clock signal;
A memory controller comprising: A memory controller that performs write access to a memory that stores data to be written by a host system,
After inputting a write command from the host system, the memory is synchronized with a second clock signal, which is a clock signal having a frequency determined according to the characteristics of the memory and satisfying the operation guarantee of the memory. Control signal output means for outputting a control signal to,
The write data related to the write command is input from the host system in synchronization with a first clock signal that is a clock signal input from the host system, and then the write to the memory is synchronized with the second clock signal. Data input / output means for outputting write data according to the command;
With
The control signal output means includes
Means for stopping output of the control signal to the memory when inputting write data related to the write command from the host system;
Means for outputting the control signal to the memory when outputting write data relating to the write command to the memory;
A time series pattern of a memory control signal for controlling the memory is stored as a time series pattern of the control signal, which is determined according to the characteristics of the memory, and is further determined according to the characteristics of the memory. Storing a time series pattern of an internal control signal for performing internal control of the memory controller, outputting the memory control signal as the control signal to the memory in synchronization with the second clock signal, and Means for executing internal control of the memory controller based on a time-series pattern of the stored internal control signal when the memory is controlled by the memory control signal;
A memory controller comprising: The memory controller of claim 5 , wherein
The data input / output means includes
A buffer unit for storing write data according to the write command;
Means for setting a clock signal for operating the buffer unit to the first clock signal when inputting write data related to the write command from the host system;
Means for setting a clock signal for operating the buffer unit to the second clock signal when outputting write data relating to the write command to the memory;
A memory controller comprising: The memory controller according to claim 5 or 6 ,
The data input / output means includes
Means for allowing the host system to write the write data according to the write command when inputting the write data according to the write command from the host system;
Means for prohibiting the host system from writing the write data according to the write command when outputting the write data according to the write command to the memory;
A memory controller comprising: The memory controller according to any one of claims 1 to 7 ,
The second clock signal is
A memory controller having a frequency higher than that of the first clock signal. The memory controller according to any one of claims 1 to 8 ,
The second clock signal is
A memory controller having a frequency that is variable according to the operation guarantee of the memory. In the memory controller according to any one of claims 1 to 9, further
A clock converter for converting the first clock signal into the second clock signal;
A memory controller comprising: In the memory controller according to any one of claims 1 to 9, further
Means for inputting the second clock signal from a clock generator for generating the second clock signal;
A memory controller comprising: The memory controller according to any one of claims 2 to 4 , or any one of claims 6 to 11 .
The buffer unit is
A memory controller characterized by being a FIFO. The memory controller according to any one of claims 1 to 4 or claim 5 to 12 ,
The time series pattern of the memory control signal and the time series pattern of the internal control signal are:
A memory controller characterized by being variable according to the characteristics of the memory.

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