JP5147654B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device used in a semiconductor integrated circuit, and more particularly to a technique for improving characteristics of a transistor pair constituting, for example, a differential circuit.

  In a differential amplifier circuit and a current mirror circuit used in a semiconductor integrated circuit device, a large number of paired transistors are used, and the difference in the characteristics of these paired transistors affects the performance and yield of the circuit. .

  In particular, in a transistor using an element isolation technique such as STI (Shallow Trench Isolation), channel mobility and threshold voltage change due to mechanical stress applied to the active region of the transistor due to STI. It is known that the difference in characteristics increases when the shape of the active region of the transistor is different (see Non-Patent Document 1, for example).

  In addition, in the lithography process or the etching process of the gate electrode, there is a possibility that the size shifts due to the layout pattern of the surrounding gate electrode and a characteristic difference occurs. In recent years, a method of covering the upper part of the gate electrode and the active region with a high strain film to improve the driving capability of the transistor is known, but depending on the layout pattern of the gate electrode of the paired transistor and the surrounding gate electrode, the stress may be Since the influence is different, a characteristic difference may occur (see Non-Patent Document 2).

  In the conventional semiconductor device, in order to suppress the characteristic difference between the paired transistors, countermeasures such as arranging the layout completely symmetrically have been performed in order to suppress the characteristic change due to the difference in the layout pattern.

For example, as shown in FIG. 21, for the paired transistors 100a and 100b, dummy elements 102a and 102b having the same shape as the transistor 101 adjacent in the channel length direction are provided on opposite sides of the transistors 100a and 100b, respectively. Similarly, also in the channel width direction, dummy elements 104a and 104b having the same shape as the adjacent transistor 103 are provided at the same distance in the channel width direction of the transistors 100a and 100b, respectively. In this way, by making the layouts around the paired transistors coincide with each other, an unbalance of transistor characteristics is prevented (Patent Document 1).
Japanese Patent Laid-Open No. 11-234109 “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, G. Scott, et. Al., IEDM digest, pp.91, 1999 “High Performance CMOSFET Technology for 45nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique”, A. Oishi, et. Al., IEDM digest, pp.239, 2005

  However, in the above-described method, since it is necessary to dispose dummy elements having the same layout pattern around the target pair of transistors, the circuit area may increase. Further, in the above method, only the shape of the closest element is considered, but the shape of the element located further away from the target transistor via the element isolation region can also be a factor causing an imbalance in transistor characteristics. .

  An object of the present invention is to enable a semiconductor device having a transistor pair to suppress an increase in circuit area and to prevent the characteristics of transistors forming a pair from becoming unbalanced.

  In the first semiconductor device according to the present invention, the channel length and the channel width are equal to each other, and the first and second transistors used as the transistor pair are the same in channel length and channel width and the third is used as the transistor pair. And the fourth transistor, and the first and second transistors have an active region pattern including an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. The first and second active regions are identical to each other, and the third and fourth transistors are formed around the active region of the transistor and the active region via an element isolation region The active region pattern composed of the surrounding active regions has the same third and fourth active region identical regions. The active regions of the third and fourth transistors are longer in the channel length direction than the active regions of the first and second transistors, and the same regions of the third and fourth active regions are The width in the channel length direction is narrower than the same region of the first and second active regions.

  According to the first semiconductor device of the present invention, the first and second transistors have the first and second active region identical regions having the same active region pattern. The stresses are equal to each other, and an unbalance in transistor characteristics due to the layout pattern of the active region and the surrounding active region can be suppressed. Similarly, also in the third and fourth transistors, transistor characteristic imbalance due to the layout pattern of the active region and the surrounding active region can be suppressed. Further, the third and fourth transistors have a longer length in the channel length direction of the active region than the first and second transistors, and the third and fourth active region identical regions are the first and second active regions. The width in the channel length direction is narrower than that of the same region. This takes into account the element separation distance in the channel length direction where the stress applied to the channel region is saturated. Thereby, the area | region which restrict | limits a layout pattern becomes narrow and the area | region which can be laid out freely can be increased. Further, since there is no need to arrange dummy elements or the like in a region outside the same active region, an increase in circuit area can be suppressed. That is, it is possible to suppress an unbalance of transistor characteristics due to the layout pattern while suppressing an increase in circuit area.

  In the second semiconductor device according to the present invention, the channel length and the channel width are equal to each other, and the first and second transistors used as the transistor pair are equal to each other in the channel length and the channel width. A fourth transistor, and the first and second transistors have an active region pattern composed of an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. The first and second active regions are identical and have the same region, and the third and fourth transistors are formed around the active region of the transistor and the active region through an element isolation region. The active region pattern consisting of the active region has the same third region and the fourth active region, the same region, The active regions of the third and fourth transistors are longer in the channel width direction than the active regions of the first and second transistors, and the same region of the third and fourth active regions is the first region. The width in the channel width direction is narrower than that of the same region of the second active region.

  According to the second semiconductor device of the present invention, the first and second transistors have the first and second active region identical regions having the same active region pattern. The stresses are equal to each other, and an unbalance in transistor characteristics due to the layout pattern of the active region and the surrounding active region can be suppressed. Similarly, also in the third and fourth transistors, transistor characteristic imbalance due to the layout pattern of the active region and the surrounding active region can be suppressed. Further, the third and fourth transistors have a longer length in the channel width direction of the active region than the first and second transistors, and the third and fourth active region identical regions are the first and second active regions. The width in the channel width direction is narrower than the same region. This takes into account the element separation distance in the channel width direction where the stress applied to the channel region is saturated. Thereby, the area | region which restrict | limits a layout pattern becomes narrow and the area | region which can be laid out freely can be increased. Further, since there is no need to arrange dummy elements or the like in a region outside the same active region, an increase in circuit area can be suppressed. That is, it is possible to suppress an unbalance of transistor characteristics due to the layout pattern while suppressing an increase in circuit area.

  In the first or second semiconductor device, at least a part of the surrounding active region may constitute a dummy element. Alternatively, it may constitute an active element.

  As a result, either a dummy element or an active element can be selected as the surrounding active region, so that the degree of freedom in design is improved and an increase in circuit area is suppressed, and an unbalance in transistor characteristics due to a layout pattern is suppressed. it can.

  In the third semiconductor device according to the present invention, the channel length and the channel width are equal to each other, and the first and second transistors used as the transistor pair are the same in channel length and channel width, and the third semiconductor device is used as the transistor pair. And the fourth transistor, wherein the first and second transistors have the same gate electrode pattern composed of a gate electrode of the transistor and a peripheral gate electrode formed around the gate electrode. The third and fourth transistors have the same region of the first and second gate electrodes, and the third and fourth transistors have the same gate electrode pattern composed of the gate electrode of the transistor and the peripheral gate electrode formed around the gate electrode. The third and fourth gate electrodes have the same region, and the third and fourth gate electrodes have the same region. The channel length of the transistor is longer than the channel lengths of the first and second transistors, and the third and fourth gate electrode identical regions are larger than the first and second gate electrode identical regions. The width in the channel length direction is narrow.

  According to the third semiconductor device of the present invention, the first and second transistors have the same region of the first and second gate electrodes having the same gate electrode pattern. Since the dimensions of the gate electrodes of the transistors are formed to be equal and the mechanical stress applied to the channel region is also equal, it is possible to suppress unbalance in transistor characteristics due to the layout pattern of the gate electrodes. Similarly, for the third and fourth transistors, an unbalance in transistor characteristics due to the layout pattern of the gate electrode can be suppressed. Further, the third and fourth transistors have a channel length longer than that of the first and second transistors, and the third and fourth gate electrode identical regions are more in the channel length direction than the first and second gate electrode identical regions. The width of is narrow. This takes into account the distance between the gates where the stress related to the channel region is saturated. Thereby, the area | region which restrict | limits a layout pattern becomes narrow and the area | region which can be laid out freely can be increased. Further, since it is not necessary to dispose the dummy gate electrode in a region outside the same region of the gate electrode, an increase in circuit area can be suppressed. That is, it is possible to suppress an unbalance of transistor characteristics due to the layout pattern while suppressing an increase in circuit area.

  In the third semiconductor device, at least a part of the peripheral gate electrode may be a dummy gate electrode. Alternatively, at least a part of the peripheral gate electrode may be an active gate electrode.

  As a result, either the dummy gate electrode or the active gate electrode can be selected as the peripheral gate electrode, so that the degree of freedom in design is improved and the increase in circuit area is suppressed, and the transistor characteristics caused by the layout pattern are unenhanced. Balance can be suppressed.

Also, in the first to third semiconductor devices, the first and second transistors is the same direction of the current relative to the said semiconductor device, said third and fourth transistors, the The direction of current with respect to the semiconductor device may be the same.

  Thereby, an unbalance of transistor characteristics due to the asymmetry of the implanted impurity distribution in the channel region near the source / drain can be suppressed.

In the first or second semiconductor device, the first and second transistors have the same current direction based on an active region pattern in the same region of the first and second active regions, The third and fourth transistors may have the same current direction based on an active region pattern in the same region of the third and fourth active regions.

  As a result, it is possible to suppress the unbalance of transistor characteristics due to the asymmetry of the implanted impurity distribution caused by the mechanical stress in the channel region near the source / drain.

  Furthermore, the fifth and sixth transistors having the same channel length and channel width are provided, and the fifth and sixth transistors have the same active region pattern as the first and second active region identical regions. , The fifth and sixth active regions have the same region, and the current directions with respect to the active region pattern in the fifth and sixth active regions are the same, and the first and second The fifth transistor has a current direction opposite to that of the first transistor, and the fifth transistor has a current direction opposite to that of the first transistor. The sixth transistor has a current direction opposite to that of the second transistor and the second transistor. And registers, gates, drains and sources may be those which are connected respectively.

  Thereby, the fifth and sixth transistors can cancel the unbalance of the transistor characteristics due to the asymmetry of the impurity distribution caused by the implantation, and can suppress the unbalance of the transistor characteristics caused by the layout pattern. The degree of freedom can also be improved.

  According to the present invention, by providing the same active region and the same gate electrode region for transistor pairs constituting a differential circuit or the like, the influence of mechanical stress caused by the layout pattern is matched, and the transistor characteristics are unbalanced. Can be suppressed. Also, by setting the size of the same active region and the same gate electrode according to the active region length and channel length of the transistor, or by setting the same active region and the same gate electrode separately, Improvement of design freedom and suppression of circuit area increase can be realized. Therefore, a semiconductor device having circuit characteristics close to a desired design target can be obtained while suppressing an increase in area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1A is a plan view showing a structural example of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1A, the semiconductor device according to the present embodiment has the same channel length and channel width as the first and second transistors 1a and 1b having the same channel length and channel width. Transistors 2a and 2b as third and fourth transistors are provided. As shown in the circuit diagram of FIG. 1B, the transistors 1a and 1b and the transistors 2a and 2b are used, for example, as transistor pairs that constitute a differential circuit.

  The transistors 1a and 1b have active regions 11a and 11b of the same size, respectively, and the transistors 2a and 2b have active regions 13a and 13b of the same size, respectively. In each transistor, a region where the active region and the gate electrode overlap is a channel region. The length OL2 in the channel length direction of the active regions 13a and 13b of the transistors 2a and 2b is longer than the length OL1 in the channel length direction of the active regions 11a and 11b of the transistors 1a and 1b.

  The transistors 1a and 1b have the same active region pattern in which the active regions 11a and 11b and the peripheral active region 12 formed around the active region 11a through the element isolation region are the same. Regions A1a and A1b. The active region pattern is the layout pattern of the active region and the surrounding active region. The same active region pattern means that the shapes and arrangements of the active region and the surrounding active region match within the region. It means that The regions A1a and A1b occupy a range from the channel region of the transistors 1a and 1b to the distance AL1 in the channel length direction and the distance AW1 in the channel width direction. Except for the regions A1a and A1b, the shape and arrangement of the active regions do not necessarily match.

  Transistors 2a and 2b have the same active region pattern composed of active regions 13a and 13b and peripheral active region 12 formed therearound via an element isolation region, and are the same as the third and fourth active regions. Regions A2a and A2b. The regions A2a and A2b occupy a range from the channel region of the transistors 2a and 2b to the distance AL2 in the channel length direction and the distance AW2 in the channel width direction. Except for the areas A2a and A2b, the shape and arrangement of the active areas do not necessarily match.

As shown in FIG. 1A, the widths of the regions A2a and A2b in the channel length direction are narrower than the widths of the regions A1a and A1b in the channel length direction. That is,
OL1 <OL2, AL1> AL2
It is.

  FIG. 2 shows a process simulation result of mechanical stress in the channel length direction generated in the channel region of the transistor. For stress analysis, a two-dimensional process simulator was used, and stress calculation was performed in consideration of the effects of thermal stress, internal stress and thermal oxidation stress. The average stress value at the interface of the channel region was plotted when the channel length of the transistor was 0.4 μm and the length of the active region in the channel length direction was 0.4 μm, 1.2 μm, 2.4 μm, and 3 μm, respectively. The horizontal axis represents the element separation distance D [μm] in the channel length direction, and the vertical axis represents the stress ratio when the stress when D = 0.2 μm is 1. That is, FIG. 2 represents the arrangement dependence of the surrounding active region of the mechanical stress generated in the channel region.

  2 that the stress in the channel length direction applied to the channel region increases as the element isolation distance D in the channel length direction increases, and saturates when the distance D exceeds a certain level. From this, it is considered that the influence on the stress due to the shape and arrangement of the active region is almost negligible in a region longer than a predetermined distance in the channel length direction from the channel region.

  Therefore, the distance from the channel region where the transistor characteristics and stress values are saturated is obtained from the actual measurement results of the active region shape dependency of the transistor characteristics and the stress analysis result of the process simulation. Set. Then, the shape and arrangement of the active region in the region are matched between the two transistors forming a pair. Thereby, an unbalance of transistor characteristics due to the active region pattern can be suppressed. In addition, since the shape and arrangement of all the active regions in the same active region are made to coincide, not only the adjacent surrounding active region but also the surrounding active region located further away from the target transistor through the element isolation region. The influence can also be suppressed.

  Further, FIG. 2 shows that the longer the active region length in the channel length direction, the shorter the element separation distance in the channel length direction in which the stress in the channel region is saturated. Therefore, the transistor pair having a long active region length in the channel length direction may be narrower in the channel length direction in the same region of the active region than the transistor pair having a short active region length in the channel length direction. become. That is, a transistor pair having a long active region length in the channel length direction can suppress an unbalance of transistor characteristics by a narrower active region same region.

  As described above, in the semiconductor device according to this embodiment, as shown in FIG. 1A, the active region length OL2 in the channel length direction of the transistors 2a and 2b is larger than the active region length OL1 in the channel length direction of the transistors 1a and 1b. Therefore, the active region identical regions A2a and A2b of the transistors 2a and 2b are set narrower in the channel length direction than the active region identical regions A1a and A1b of the transistors 1a and 1b. As a result, the active region identical regions A2a and A2b are narrower than the active region identical regions A1a and A1b, and the range in which the layout pattern is limited is narrowed. Therefore, the active regions can be arranged freely and the degree of freedom in design Can be improved.

  FIG. 3 is a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 3, the same active regions A2a and A2b of the transistors 2a and 2b are arranged adjacent to each other. As a result, the range in which the layout pattern is limited is narrowed down, so that the circuit area can be further reduced.

  FIG. 4 is also a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 1, the transistors 1a and 1b are arranged adjacent to each other, and the transistors 2a and 2b are also arranged adjacent to each other. However, the transistors forming the transistor pair are not necessarily arranged adjacent to each other. That is, in the structure of FIG. 4, the transistors 1a and 1b are arranged apart from each other, and the transistors 2a and 2b are also arranged apart from each other.

  The surrounding active region 12 formed in each active region identical region A1a, A1b, A2a, A2b may constitute an electrically connected active active region, that is, an active element, Alternatively, a dummy active region that is not electrically connected, that is, a dummy element may be configured. Since either a dummy active region or an active active region can be selected, an unbalance of transistor characteristics can be suppressed while improving design flexibility.

(Second Embodiment)
In the first embodiment, the structure in which the lengths of the active regions in the channel length direction are different in the two transistor pairs has been described. In the second embodiment, a structure in which two transistor pairs have different lengths in the channel width direction of the active region will be described.

  FIG. 5A is a plan view showing a structural example of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 5A, the semiconductor device according to this embodiment has the same channel length and channel width as the first and second transistors 1a and 1b having the same channel length and channel width. Transistors 3a and 3b as third and fourth transistors are provided. As shown in the circuit diagram of FIG. 5B, the transistors 1a and 1b and the transistors 3a and 3b are used as, for example, transistor pairs that constitute a differential circuit.

  The transistors 1a and 1b have active regions 11a and 11b of the same size, respectively, and the transistors 3a and 3b have active regions 21a and 21b of the same size, respectively. In each transistor, a region where the active region and the gate electrode overlap is a channel region. The length OW2 in the channel width direction of the active regions 21a and 21b of the transistors 3a and 3b is longer than the length OW1 in the channel width direction of the active regions 11a and 11b of the transistors 1a and 1b.

  Transistors 1a and 1b have the same active region pattern consisting of active regions 11a and 11b and a peripheral active region 12 formed in the periphery thereof through an element isolation region. Regions A1a and A1b. The regions A1a and A1b occupy a range from the channel region of the transistors 1a and 1b to the distance AL1 in the channel length direction and the distance AW1 in the channel width direction. Except for the regions A1a and A1b, the shape and arrangement of the active regions do not necessarily match.

  Transistors 3a and 3b have the same active region pattern composed of active regions 21a and 21b and peripheral active region 12 formed therearound via an element isolation region, and are the same as the third and fourth active region identical regions. Regions A3a and A3b. The regions A3a and A3b occupy a range from the channel region of the transistors 3a and 3b to the distance AL3 in the channel length direction and the distance AW3 in the channel width direction. Except for the regions A3a and A3b, the shape and arrangement of the active regions do not necessarily match.

As shown in FIG. 5A, the widths of the regions A3a and A3b in the channel width direction are narrower than the widths of the regions A1a and A1b in the channel width direction. That is,
OW1 <OW2, AW1> AW3
It is.

  FIG. 6 shows a process simulation result of mechanical stress in the channel width direction generated in the channel region of the transistor. The analysis method was the same as in FIG. The average stress value at the interface of the channel region was plotted when the channel length of the transistor was 0.4 μm and the length of the active region in the channel width direction was 0.4 μm, 1.2 μm, 2.4 μm, and 3 μm, respectively. The horizontal axis represents the element separation distance D [μm] in the channel width direction, and the vertical axis represents the stress ratio when the stress when D = 0.2 μm is 1.

  6 that the stress in the channel width direction applied to the channel region increases as the element isolation distance D in the channel width direction increases, and saturates when the distance D exceeds a certain level. From this, similar to the stress in the channel length direction shown in FIG. 2, the stress in the channel width direction is also affected by the shape and arrangement of the active region in a region outside a predetermined distance from the channel region. The effects of can be considered almost negligible.

  Further, FIG. 6 shows that the transistor having a longer active region length in the channel width direction has a shorter element isolation distance in the channel width direction where the stress in the channel region is saturated. That is, the longer the active region length in the channel width direction, the narrower the width in the channel width direction of the same active region region.

  As described above, in the semiconductor device according to the present embodiment, as shown in FIG. 5A, the active region length OW2 in the channel width direction of the transistors 3a and 3b is larger than the active region length OW1 in the channel width direction of the transistors 1a and 1b. Therefore, the active region identical regions A3a and A3b of the transistors 3a and 3b are set narrower in the channel width direction than the active region identical regions A1a and A1b of the transistors 1a and 1b. As a result, the active region identical regions A3a and A3b are narrower than the active region identical regions A1a and A1b, and the region where the layout pattern is limited is also narrowed. Can be improved.

  FIG. 7 is a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 7, the active region identical regions A3a and A3b of the transistors 3a and 3b are arranged so that the upper sides thereof are on the same straight line as the active region identical regions A1a and A1b of the transistors 1a and 1b. As a result, the range in which the layout pattern is limited is narrowed down, so that the circuit area can be further reduced.

  FIG. 8 is also a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 5, the transistors 1a and 1b are arranged adjacent to each other, and the transistors 3a and 3b are also arranged adjacent to each other. However, the transistors forming the transistor pair are not necessarily arranged adjacent to each other. That is, in the structure of FIG. 8, the transistors 1a and 1b are spaced apart, and the transistors 3a and 3b are also spaced apart.

  As in the first embodiment, the surrounding active region 12 formed in each active region identical region A1a, A1b, A3a, A3b constitutes an electrically connected active active region, that is, an active element. Alternatively, it may be a dummy active region that is not electrically connected, that is, a dummy element. Since either a dummy active region or an active active region can be selected, an unbalance of transistor characteristics can be suppressed while improving design flexibility.

(Third embodiment)
In the first and second embodiments described above, the structure in which the two transistors forming the transistor pair have regions having the same active region pattern has been described. In the third embodiment, a structure in which two transistors forming a transistor pair have a region having the same gate electrode pattern will be described.

  FIG. 9A is a plan view showing a structural example of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 9A, the semiconductor device according to the present embodiment includes transistors 4a and 4b as first and second transistors having the same channel length (CL1) and channel width, and a channel length (CL2). And third and fourth transistors 5a and 5b having the same channel width. As shown in the circuit diagram of FIG. 9B, the transistors 4a and 4b and the transistors 5a and 5b are used, for example, as transistor pairs that constitute a differential circuit.

  In each transistor, a region where the active region and the gate electrode overlap is a channel region. The channel length CL2 of the transistors 5a and 5b is longer than the channel length CL1 of the transistors 4a and 4b.

  The transistors 4a and 4b have the same gate electrode pattern consisting of the gate electrodes 32a and 32b forming the transistor and the peripheral gate electrode 33 formed around the gate electrodes 32a and 32b. Regions B4a and B4b. Note that the gate electrode pattern is a layout pattern of the gate electrode and the surrounding gate electrode, and the same gate electrode pattern means that the shape and arrangement of the gate electrode and the surrounding gate electrode are identical in the region. It means that The regions B4a and B4b occupy a range from the channel region of the transistors 4a and 4b to the distance BL1 in the channel length direction and the distance BW1 in the channel width direction. Except for the regions B4a and B4b, the shape and arrangement of the gate electrodes do not necessarily match.

  The transistors 5a and 5b have the same gate electrode pattern consisting of the gate electrodes 34a and 34b forming the transistor and the peripheral gate electrode 33 formed around the gate electrodes 34a and 34b. Regions B5a and B5b. The regions B5a and B5b occupy a range from the channel region of the transistors 5a and 5b to the distance BL2 in the channel length direction and the distance BW2 in the channel width direction. Except for the regions B5a and B5b, the shape and arrangement of the gate electrodes do not necessarily match.

As shown in FIG. 9A, the widths of the regions B5a and B5b in the channel length direction are narrower than the widths of the regions B4a and B4b in the channel length direction. That is,
CL1 <CL2, BL1> BL2
It is.

  FIG. 10 shows a process simulation result of mechanical stress in the channel length direction generated in the channel region of the transistor. The average stress values at the interface of the channel region were plotted for the case where the channel lengths were 0.1 μm, 0.4 μm, and 1.0 μm, respectively. The horizontal axis represents the gate-gate distance S [μm] in the channel length direction, and the vertical axis represents the stress ratio when the stress when S = 0.2 μm is 1. That is, FIG. 10 shows the arrangement dependence of the surrounding gate electrode of the mechanical stress generated in the channel region.

  FIG. 10 shows that the stress in the channel length direction applied to the channel region increases as the gate-to-gate distance S in the channel length direction increases, and saturates when the distance S exceeds a certain level. From this, it can be considered that the influence of the stress due to the shape and arrangement of the gate electrode is almost negligible in a region longer than a predetermined distance in the channel length direction from the channel region.

  Therefore, the distance from the channel region where the transistor characteristics and the stress value are saturated is obtained from the actual measurement result of the shape dependence of the surrounding gate electrode of the transistor characteristics, the stress analysis result of the process simulation, and the like. Set the same area. Then, the shape and arrangement of the gate electrode in the region are matched between the two transistors forming a pair. Thereby, an unbalance of transistor characteristics due to the gate electrode pattern can be suppressed. In addition, since the shape and arrangement of all the gate electrodes in the same region of the gate electrode are matched, it is possible to suppress not only the neighboring peripheral gate electrode but also the influence of the peripheral gate electrode located farther from the target transistor. it can.

  FIG. 10 also shows that the longer the channel length, the shorter the gate-gate distance at which the stress in the channel region is saturated. Therefore, for a transistor pair having a long channel length, the width in the channel length direction of the same region of the gate electrode may be narrower than that of a transistor pair having a short channel length. That is, a transistor pair having a long channel length can suppress an unbalance of transistor characteristics by a narrower gate electrode same region.

  As described above, in the semiconductor device according to the present embodiment, as shown in FIG. 9A, the channel length CL2 of the transistors 5a and 5b is longer than the channel length CL1 of the transistors 4a and 4b, and thus the gates of the transistors 5a and 5b. The same electrode regions B5a and B5b are set to have a narrower width in the channel length direction than the gate electrode same regions B4a and B4b of the transistors 4a and 4b. As a result, the gate electrode identical regions B5a and B5b are narrower than the gate electrode identical regions B4a and B4b, and the range in which the layout pattern is limited is narrowed. Can be improved.

  FIG. 11 is a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 11, the gate electrode identical regions B5a and B5b of the transistors 5a and 5b are arranged adjacent to each other. As a result, the range in which the layout pattern is limited is narrowed down, so that the circuit area can be further reduced.

  FIG. 12 is also a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 9, the transistors 4a and 4b are disposed adjacent to each other, and the transistors 5a and 5b are also disposed adjacent to each other. However, the transistors forming the transistor pair are not necessarily arranged adjacent to each other. That is, in the structure of FIG. 12, the transistors 4a and 4b are arranged apart from each other, and the transistors 5a and 5b are also arranged apart from each other.

  The peripheral gate electrode 33 formed in the same region B4a, B4b, B5a, B5b of each gate electrode may be an electrically connected active gate electrode or may be electrically connected. A dummy gate electrode may be used. Since either a dummy gate electrode or an active gate electrode can be selected, an unbalance in transistor characteristics can be suppressed while improving design freedom.

(Fourth embodiment)
In the fourth embodiment, the transistor pair has both the same active region region described in the first and second embodiments and the same gate electrode region described in the third embodiment. The structure which is doing is demonstrated.

  FIG. 13 is a plan view showing a structural example of a semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 13, the semiconductor device according to this embodiment includes transistors 41a and 41b as first and second transistors having the same channel length and channel width, and third and third transistors having the same channel length and channel width. Transistors 42a and 42b as fourth transistors are provided. The transistors 42a and 42b have the same channel length as the transistors 41a and 41b, and the length of the active region in the channel length direction is longer than that of the transistors 41a and 41b.

  Transistors 41a and 41b have first and second active region identical regions A41a and A41b having the same active region pattern. Transistors 42a and 42b have regions A42a and A42b as third and fourth active region identical regions having the same active region pattern. Since the transistors 42a and 42b are longer in the channel length direction of the active region than the transistors 41a and 41b, the widths of the regions A42a and A42b in the channel length direction are larger than the widths of the regions A41a and A41b in the channel length direction. Even narrower. This is the same as in the first embodiment.

  The transistors 41a and 41b have regions B41a and B41b as the same region of the first and second gate electrodes having the same gate electrode pattern. The transistors 42a and 42b have regions B42a and B42b as third and fourth gate electrode identical regions having the same gate electrode pattern. Since the transistors 42a and 42b have the same channel length as the transistors 41a and 41b, the widths of the regions B42a and B42b in the channel length direction are equal to the widths of the regions B41a and B41b in the channel length direction.

  In the configuration of FIG. 13, the active region identical regions A41a and A41b and the gate electrode identical regions B41a and B41b are different in size, and the active region identical regions A42a and A42b and the gate electrode identical regions B42a and B42b are different in size. Is different.

  According to the present embodiment, it is possible to improve the degree of freedom of layout by setting the active region identical regions A41a, A41b, A42a, A42b and the gate electrode identical regions B41a, B41b, B42a, B42b separately and independently. . For example, in the case of a layout in which the influence of the active region shape is smaller than the influence of the gate electrode shape on the unbalance of the transistor characteristics, as shown in FIG. 13, the active region identical regions A42a and A42b are It can be set narrower in the channel length direction than the gate electrode identical regions B42a and B42b. For this reason, the area where the layout pattern of the active region is limited is reduced, and the layout of the gate electrode is also limited because the range limited to the active region shape is reduced, so that the layout can be determined more freely.

  FIG. 14 is a plan view showing another structural example of the semiconductor device according to the present embodiment. In the structure of FIG. 14, instead of the transistors 42a and 42b in FIG. 13, the transistors 43a and 43b have a channel length longer than that of the transistors 41a and 41b and the length of the active region in the channel length direction is equal to the transistors 41a and 41b. It has.

  The transistors 43a and 43 have regions A43a and A43b as third and fourth active region identical regions having the same active region pattern. Since the transistors 43a and 43b have the same active region in the channel length direction as the transistors 41a and 41b, the widths of the regions A43a and A43b in the channel length direction are equal to the widths of the regions A41a and A41b in the channel length direction. It has become.

  The transistors 43a and 43b have regions B43a and B43b as third and fourth gate electrode identical regions having the same gate electrode pattern. Since the transistors 43a and 43b have longer channel lengths than the transistors 41a and 41b, the widths of the regions B43a and B43b in the channel length direction are narrower than the widths of the regions B41a and B41b in the channel length direction. This is the same as in the third embodiment.

  In the configuration of FIG. 14, the active region identical regions A41a and A41b and the gate electrode identical regions B41a and B41b are different in size, and the active region identical regions A43a and A43b and the gate electrode identical regions B43a and B43b are different in size. Is different.

  In the case of a layout in which the influence of the gate electrode shape on the transistor characteristic imbalance is smaller than the influence of the active region shape, as shown in FIG. 14, the gate electrode identical regions B43a and B43b are made active regions. It can be set narrower in the channel length direction than the same regions A43a and A43b. For this reason, the area where the layout pattern of the gate electrode is restricted is reduced, and the area restricted by the gate electrode shape is reduced with respect to the layout of the active area, so that the layout can be determined more freely.

  Here, the configuration in which the present embodiment is implemented in combination with the first or third embodiment has been described. However, the present embodiment may be implemented in combination with the second embodiment. For example, in the configuration of FIG. 13, when the lengths of the active regions of the transistors 42a and 42b are longer than those of the transistors 41a and 41b, the widths of the regions A42a and A42b in the channel width direction are It may be narrower than the width in the direction. Of course, it is also possible to implement in combination with two or more of the first to third embodiments.

<About the same active region pattern and gate electrode pattern>
In the present specification, the active region pattern and the gate electrode pattern are “same” as long as the pattern size and shape itself are the same, and the pattern is rotated or turned over. You may do it. For example, the case where the patterns are line symmetric or point symmetric is also included as “same”. Thereby, the freedom degree of a layout improves.

  FIG. 15 is a plan view showing a structural example of a semiconductor device according to a modification. In the modification of FIG. 15, the active region patterns and the gate electrode patterns are line symmetric. As shown in FIG. 15, the semiconductor device according to this modification includes transistors 44a and 44b having the same channel length and channel width, and transistors 45a and 45b having the same channel length and channel width. In the transistors 45a and 45b, the channel length and the length of the active region in the channel length direction are longer than those of the transistors 44a and 44b.

  Transistors 44a and 44b have active region identical regions A44a and A44b and gate electrode identical regions B44a and B44b. Here, in the active region identical regions A44a and A44b, the active region pattern, that is, the shape and arrangement of the active region and the surrounding active region are in a line-symmetric relationship. Similarly, in the same gate electrode regions B44a and B44b, the shape and arrangement of the gate electrode pattern, that is, the gate electrode and the surrounding gate electrode are in a line-symmetric relationship.

  Transistors 45a and 45b have active region identical regions A45a and A45b and gate electrode identical regions B45a and B45b. Here, in the same active region A45a, A45b, the active region pattern is in a line-symmetric relationship, and similarly, in the same gate electrode region B45a, B45b, the gate electrode pattern is in a line-symmetric relationship. The active region identical regions A45a and A45b are narrower in the channel length direction than the active region identical regions A44a and A44b, and the gate electrode identical regions B45a and B45b are channeled more than the gate electrode identical regions B44a and B44b. The width in the long direction is narrow.

  FIG. 16 is a plan view showing a structural example of a semiconductor device according to another modification. In the modification of FIG. 16, the active region patterns and the gate electrode patterns are point-symmetric. As shown in FIG. 16, the semiconductor device according to this modification includes transistors 50a and 50b having the same channel length and channel width, and transistors 51a and 51b having the same channel length and channel width. In the transistors 51a and 51b, the channel length and the length of the active region in the channel length direction are longer than those of the transistors 50a and 50b.

  Transistors 50a and 50b have active region identical regions A50a and A50b and gate electrode identical regions B50a and B50b. Here, in the same active region A50a, A50b, the active region pattern has a point-symmetric relationship. Similarly, in the same gate electrode region B50a, B50b, the gate electrode pattern is point-symmetric.

  Transistors 51a and 51b have active region identical regions A51a and A51b and gate electrode identical regions B51a and B51b. Here, in the same active region A51a, A51b, the active region pattern is point-symmetric, and similarly, in the same gate electrode region B51a, B51b, the gate electrode pattern is point-symmetric. The active region identical regions A51a and A51b are narrower in the channel length direction than the active region identical regions A50a and A50b, and the gate electrode identical regions B51a and B51b are channeled more than the gate electrode identical regions B50a and B50b. The width in the long direction is narrow.

  FIG. 17 is an example of a layout in which a pair of transistors share an active region according to another modification. In the layout of FIG. A, Tr. With respect to B, the active region pattern and the gate electrode pattern are line-symmetric or point-symmetric, ie, the same. Therefore, the same effects as those of the above-described embodiments can be obtained, and the unbalance of transistor characteristics due to the layout pattern of the active region and the gate electrode can be suppressed.

(Fifth embodiment)
FIG. 18 is a plan view showing a structural example of a semiconductor device according to the fifth embodiment of the present invention. As shown in FIG. 18, the semiconductor device according to this embodiment includes transistors 56a and 56b having the same channel length and channel width, and transistors 57a and 57b having the same channel length and channel width. The transistors 57a and 57b have a channel length and a length in the channel length direction of the active region longer than those of the transistors 56a and 56b.

  Transistors 56a and 56b have active region identical regions A56a and A56b and gate electrode identical regions B56a and B56b. Transistors 57a and 57b have active region identical regions A57a and A57b and gate electrode identical regions B57a and B57b. The active region identical regions A57a and A57b are narrower in the channel length direction than the active region identical regions A56a and A56b, and the gate electrode identical regions B57a and B57b are channeled more than the gate electrode identical regions B56a and B56b. The width in the long direction is narrow.

  In the configuration of FIG. 18, the source / drain directions of the transistors 56a and 56b are the same, and similarly, the source / drain directions of the transistors 57a and 57b are the same. That is, the direction of the current with respect to the semiconductor device is the same between the transistors 56a and 56b and between the transistors 57a and 57b. In this way, by making the source / drain direction the same between the paired transistors, an unbalance in transistor characteristics due to the current direction can be suppressed.

  That is, in the transistor manufacturing process, when the impurity implantation is performed on the semiconductor substrate using the gate electrode as a mask to form the source / drain regions, a large implantation angle may occur depending on the wafer position of the target transistor. There is. At this time, the implantation is blocked by the gate electrode, and the source / drain impurity distribution is asymmetric. For this reason, when the source / drain orientations of the paired transistors are different, the asymmetry of the impurity distribution may cause a large difference in characteristics such as transistor current.

  With the configuration of FIG. 18, by suppressing the unbalance of the transistor characteristics due to the layout pattern of the active region and the gate electrode, by making the source / drain directions of the paired transistors the same, the transistor characteristics due to the asymmetry of the impurity distribution Unbalance can also be suppressed.

  FIG. 19 is a plan view showing another structural example of the semiconductor device according to the present embodiment. The semiconductor device in FIG. 19 includes transistors 62a and 62b having the same channel length and channel width, and transistors 63a and 63b having the same channel length and channel width. In the transistors 63a and 63b, the channel length and the length of the active region in the channel length direction are longer than those of the transistors 62a and 62b.

  Transistors 62a and 62b have active region identical regions A62a and A62b and gate electrode identical regions B62a and B62b. Transistors 63a and 63b have active region identical regions A63a and A63b and gate electrode identical regions B63a and B63b. The active region identical regions A63a and A63b are narrower in the channel length direction than the active region identical regions A62a and A62b, and the gate electrode identical regions B63a and B63b are closer to the channel length direction than the gate electrode identical regions B62a and B62b. The width of is narrow.

  Here, in the active region identical regions A62a and A62b, the active region patterns are in a line-symmetric relationship. In the active region identical regions A63a and A63b, the active region patterns have a line-symmetric relationship.

  In the configuration of FIG. 19, the direction of the source / drain of the paired transistors 62a and 62b coincides with the active region pattern in the same active region A62a and A62b. That is, since the active region patterns of the same active regions A62a and A62b have a line-symmetric relationship, the direction of the source / drain of the transistors 62a and 62b is also line-symmetric, that is, opposite to the active region pattern. . Similarly, the directions of the source / drain of the transistors 63a and 63b are opposite to each other because the active region patterns of the same active region A63a and A63b are line symmetric. That is, the paired transistors have the same current direction based on the active region pattern in the same active region. The same applies to the configuration of FIG.

  By making the direction of the source / drain between the paired transistors the same with respect to the active region pattern, an unbalance of transistor characteristics due to asymmetry of mechanical stress can be suppressed.

  The mechanical stress from the STI not only affects the electron mobility of the channel, but also affects the diffusion of impurities in the heat treatment process in the transistor manufacturing process. Therefore, when the active region pattern of the transistor is asymmetric near the source / drain, the mechanical stress is applied differently on the source side and the drain side, so that the impurity distribution in the channel region near the source / drain is / Asymmetric at the drain. For this reason, when the source / drain directions of the paired transistors are different, the asymmetry of the impurity distribution caused by the mechanical stress causes a large difference in characteristics such as transistor current.

  With the configuration of FIG. 19, the transistor characteristics due to the asymmetry of the impurity distribution are obtained by making the source / drain directions the same with respect to the active region pattern while suppressing the unbalance of the transistor characteristics due to the layout pattern of the active region and gate electrode It is also possible to suppress unbalance.

(Sixth embodiment)
FIG. 20 is a plan view showing a structural example of the semiconductor device according to the sixth embodiment of the present invention. In addition, a circuit diagram of a differential circuit using the illustrated transistor is also shown. 20 includes transistors 68a and 68b as first and second transistors having the same channel length and channel width, and transistors 74a and 68b as third and fourth transistors having the same channel length and channel width. 74b. Transistors 74a and 74b have longer channel lengths and lengths in the channel length direction and channel width direction of the active region than transistors 68a and 68b.

  Transistors 68a and 68b have active region identical regions A68a and A68b and gate electrode identical regions B68a and B68b. Transistors 74a and 74b have active region identical regions A74a and A74b and gate electrode identical regions B74a and B74b. The active region identical regions A74a and A74b are narrower in the channel length direction and the channel width direction than the active region identical regions A68a and A68b, and the gate electrode identical regions B63a and B63b are smaller than the gate electrode identical regions B62a and B62b. The width in the channel length direction is narrow.

  Here, in the same active region A68a and A68b, the active region pattern has a line-symmetric relationship, and in the same gate electrode region B68a and B68b, the gate electrode pattern has a line-symmetric relationship. Similarly, in the same active region A74a, A74b, the active region pattern has a line-symmetric relationship, and in the same gate electrode region B74a, B74b, the gate electrode pattern has a line-symmetric relationship. Further, the directions of the source / drain of the transistors 68a and 68b are opposite to each other, and the directions of currents based on the active region pattern of the same active region A68a and A68b are the same. The directions of the source / drain of the transistors 74a and 74b are also opposite to each other, and the directions of currents based on the active region pattern of the same active region A74a and A74b are the same.

  According to the configuration of FIG. 20, as described in the fifth embodiment, by making the current direction the same with respect to the active region pattern in the paired transistors, the asymmetry of the impurity distribution caused by the mechanical stress is caused. Unbalance of transistor characteristics can also be suppressed. However, since the direction of the source / drain differs between the transistors 68a and 68b with respect to the wafer, that is, the semiconductor device, there is a possibility that asymmetry of the impurity distribution due to implantation may occur.

  Therefore, in the present embodiment, transistors 69a and 69b as a pair of fifth and sixth transistors having the same active region pattern and gate electrode pattern and the same source / drain direction are provided for the transistors 68a and 68b. Thus, the connection is made so as to cancel out the mismatch of the current directions. Similarly, paired transistors 75a and 75b having the same active region pattern and the same gate electrode pattern and the same source / drain direction are provided for the transistors 74a and 74b so as to cancel the mismatch of the current directions. Connected. The transistors 69a and 69b have the same active region A69a and A69b and the same gate electrode region B69a and B69b. The transistors 75a and 75b have the same active region A75a and A75b and the same gate electrode region B75a and B75b. doing.

  The direction of the current of the transistor 69a with respect to the semiconductor device is opposite to that of the transistor 68a. As shown in the circuit diagram, the transistor 69a is connected to the transistor 68a at the source, the drain, and the gate. The transistor 69b has a current direction reverse to that of the transistor 68b with respect to the semiconductor device, and the transistor 68b is connected to the source, the drain, and the gate. Similarly, in the transistor 75a, the direction of current with respect to the semiconductor device is opposite to that of the transistor 74a, and the transistor 74a is connected to the source, the drain, and the gate. The transistor 75b has a current direction reverse to that of the transistor 74b with respect to the semiconductor device, and the transistor 74b is connected to the source, the drain, and the gate.

  The configuration shown in FIG. 20 suppresses the unbalance of the transistor characteristics due to the layout of the active region and the gate electrode and the unbalance due to the asymmetry of the impurity distribution due to the mechanical stress, and the asymmetry of the impurity distribution due to the implantation. Unbalance can also be suppressed. Therefore, it is possible to reduce the area that restricts the layout pattern while suppressing these imbalances, thereby improving the degree of design freedom and suppressing an increase in circuit area.

  In the present invention, an increase in circuit area can be suppressed and an unbalance in characteristics of transistor pairs due to a layout pattern can be suppressed. For example, in a semiconductor device having a transistor using an element isolation technique such as STI, a yield reduction can be achieved. This is useful for improving the performance of a semiconductor circuit including a differential circuit.

(A) is a top view which shows the structural example of the semiconductor device which concerns on 1st Embodiment, (b) is a circuit diagram of the differential circuit using the transistor shown to (a). It is a process simulation analysis result for verifying the effect of the semiconductor device concerning a 1st embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 1st Embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 1st Embodiment. (A) is a top view which shows the structural example of the semiconductor device which concerns on 2nd Embodiment, (b) is a circuit diagram of the differential circuit using the transistor shown to (a). It is a process simulation analysis result for verifying the effect of the semiconductor device concerning a 2nd embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 2nd Embodiment. (A) is a top view which shows the structural example of the semiconductor device which concerns on 3rd Embodiment, (b) is a circuit diagram of the differential circuit using the transistor shown to (a). It is a process simulation analysis result for verifying the effect of the semiconductor device concerning a 3rd embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows the structural example of the semiconductor device which concerns on 4th Embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 4th Embodiment. It is a top view which shows the structural example of the semiconductor device which concerns on a modification. It is a top view which shows the structural example of the semiconductor device which concerns on another modification. It is an example of a layout in case the transistor which makes a pair based on another modification shares an active region. It is a top view which shows the structural example of the semiconductor device which concerns on 5th Embodiment. It is a top view which shows the other structural example of the semiconductor device which concerns on 5th Embodiment. It is a top view which shows the structural example of the semiconductor device which concerns on 6th Embodiment. It is a top view for demonstrating the semiconductor device of a prior art.

1a, 4a 1st transistor 1b, 4b 2nd transistor 2a, 3a, 5a 3rd transistor 2b, 3b, 5b 4th transistor 11a, 11b, 13a, 13b, 21a, 21b Active region 12 Surrounding active region 32a , 32b, 34a, 34b Gate electrode A1a First active region identical region A1b Second active region identical region A2a, A3a Third active region identical region A2b, A3b Fourth active region identical region OL1, OL2 Channel length direction length OW1, OW2 Channel width direction length of active region B4a First gate electrode same region B4b Second gate electrode same region B5a Third gate electrode same region B5b Fourth gate electrode same region CL1, CL2 channel length 41a, 44a, 50a, 56a, 62a, 68a first transistor 41b, 44b, 50b, 56b, 62b, 68b Second transistor 42a, 43a, 45a, 51a, 57a, 63a, 74a Third transistor 42b, 43b, 45b, 51b, 57b, 63b, 74b Fourth transistor 69a Fifth transistor 69b Sixth transistors A41a, A44a, A50a, A56a, A62a, A68a First active region identical region A41b, A44b, A50b, A56b, A62b, A68b Second active region identical region A42a, A43a, A45a , A51a, A63a, A74a Third active region same region A42b, A43b, A45b, A51b, A63b, A74b Fourth active region same region B41a, B44a, B50a, B56a, B62a, B68a First gate electrode same region B 41b, B44b, B50b, B56b, B62b, B68b Second gate electrode same region B42a, B43a, B45a, B51a, B57a, B63a, B74a Third gate electrode same region B42b, B43b, B45b, B51b, B57b, B63b, B74b Fourth gate electrode same region

Claims (10)

First and second transistors having equal channel lengths and channel widths and used as transistor pairs;
A channel length and a channel width are equal to each other, and comprise third and fourth transistors used as transistor pairs,
The first and second transistors have the same active region pattern composed of an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. Two active regions having the same region,
The third and fourth transistors have the same active region pattern composed of an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. 4 active regions have the same region,
The active regions of the third and fourth transistors are longer in the channel length direction than the active regions of the first and second transistors,
The third and fourth active region identical regions have a narrower width in the channel length direction than the first and second active region identical regions. First and second transistors having equal channel lengths and channel widths and used as transistor pairs;
A channel length and a channel width are equal to each other, and comprise a third and a fourth transistor as a transistor pair,
The first and second transistors have the same active region pattern composed of an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. Two active regions having the same region,
The third and fourth transistors have the same active region pattern composed of an active region of the transistor and a peripheral active region formed around the active region via an element isolation region. 4 active regions have the same region,
The active regions of the third and fourth transistors are longer in the channel width direction than the active regions of the first and second transistors,
The third and fourth active region identical regions have a narrower width in the channel width direction than the first and second active region identical regions. In claim 1 or 2,
At least a part of the surrounding active region constitutes a dummy element. In claim 1 or 2,
At least a part of the surrounding active region constitutes an active element. First and second transistors having equal channel lengths and channel widths and used as transistor pairs;
A channel length and a channel width are equal to each other, and comprise third and fourth transistors used as transistor pairs,
The first and second transistors have the same first and second gate electrode regions in which the gate electrode patterns composed of the gate electrode of the transistor and the peripheral gate electrode formed around the gate electrode are the same. Have
The third and fourth transistors have the same third and fourth gate electrode regions in which the gate electrode patterns composed of the gate electrode of the transistor and the peripheral gate electrode formed around the gate electrode are the same. Have
The channel length of the third and fourth transistors is longer than the channel length of the first and second transistors,
The third and fourth gate electrode identical regions have a narrower width in the channel length direction than the first and second gate electrode identical regions. In claim 5,
At least a part of the peripheral gate electrode is a dummy gate electrode. In claim 5,
At least a part of the peripheral gate electrode is an active gate electrode. In claim 1, 2 or 5 ,
The first and second transistors have the same current direction with respect to the semiconductor device,
In the semiconductor device, the third and fourth transistors have the same current direction with respect to the semiconductor device. In claim 1 or 2 ,
The first and second transistors have the same current direction based on an active region pattern in the same region of the first and second active regions,
3. The semiconductor device according to claim 1, wherein the third and fourth transistors have the same current direction based on an active region pattern in the same region of the third and fourth active regions. In claim 9 ,
Comprising fifth and sixth transistors having channel lengths and channel widths equal to each other;
The fifth and sixth transistors have fifth and sixth active region identical regions, the active region pattern of which is the same as the first and second active region identical regions, and the fifth and sixth transistors The direction of the current based on the active region pattern in the same region of the sixth active region is the same,
The first and second transistors have opposite current directions with respect to the semiconductor device,
The fifth transistor has a current direction opposite to that of the first transistor, and the gate, drain and source of the first transistor are connected to each other,
The semiconductor device according to claim 6, wherein the current direction of the sixth transistor is opposite to that of the second transistor, and the gate, drain, and source of the second transistor are connected to each other.

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