JP5141037B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device made of a group III nitride semiconductor, and relates to a method of forming an n-type or p-type region at the bottom of a trench groove.

  Patent Documents 1 and 2 disclose a method of forming an n-type or p-type region at the bottom of a trench. Patent Document 1 uses such a structure for trench isolation, and Patent Document 2 uses it to increase the breakdown voltage of a trench type semiconductor device.

In the forming method according to Patent Document 1, after etching a semiconductor layer made of silicon to form a trench groove, a mask made of SiO ₂ is formed by an atmospheric pressure CVD method. The mask formed by the atmospheric pressure CVD method has a thick film in the vicinity of the opening of the trench groove, and the film thickness decreases as it goes to the bottom of the trench groove, and becomes the thinnest at the bottom of the trench groove. Next, when boron ion implantation is performed, doping of the opening and side surfaces of the trench is suppressed by the mask. On the other hand, since the mask on the bottom of the trench groove is thin, ions can be implanted beyond the mask. Therefore, the p-type region can be formed only at the bottom of the trench groove. As described above, the method of Patent Document 1 uses the poor step coverage of a mask made of SiO ₂ formed by atmospheric pressure CVD.

In the forming method according to Patent Document 2, the p-type region is formed only at the bottom of the trench groove by etching the side surface of the trench groove after ion implantation.
JP-A 5-283520 JP-A-11-26758

However, it is extremely difficult to control the step coverage of the mask as disclosed in Patent Document 1. Actually, the mask made of SiO ₂ formed by the atmospheric pressure CVD method has an overhang shape in the vicinity of the opening of the trench groove. Therefore, when ions are implanted using this mask, impurities are only present near the center of the bottom of the trench groove. Is not injected.

  In addition, since the group III nitride semiconductor is physically and chemically very stable, etching is difficult, and the method of Patent Document 2 is applied to a method for manufacturing a semiconductor device made of a group III nitride semiconductor. Have difficulty.

  Accordingly, an object of the present invention is to provide a method of forming an n-type or p-type region only at the bottom of a trench groove in a method for manufacturing a semiconductor device made of a group III nitride semiconductor.

  According to a first aspect of the present invention, there is provided a step of forming a mask at a predetermined position on a surface of a semiconductor layer having a c-plane as a main surface, and comprising etching a semiconductor layer using the mask. Forming a trench groove, ion-implanting n-type or p-type impurities perpendicularly to the surface of the semiconductor layer, and activating the impurities by heat treatment to form n-type regions or p-type regions. A method for manufacturing a semiconductor device, comprising: a step; and a step of wet-etching the semiconductor layer that is a side surface of a trench groove with an alkaline solution.

  The semiconductor layer may be of any conductivity type. Any of n-type, p-type and intrinsic may be used. Further, it may be a single layer or a plurality of layers. In the case of a plurality of layers, a plurality of layers having different compositions may be used. Note that Ga is essential because AlN can be wet-etched with an acid or the like and has no advantage in using the present invention.

  The n-type impurity is Si or the like, and the p-type impurity is Mg or the like.

The etching solution used for the wet etching includes an alkaline solution (for example, TMAH (tetramethylammonium hydroxide: (CH ₃ ) ₄ NOH), KOH, or NaOH) that performs anisotropic etching on the group III nitride semiconductor. Solution). These solutions cannot etch the c-plane of the group III nitride semiconductor, but can etch surfaces other than the c-plane, such as the a-plane, m-plane, and r-plane. In particular, a TMAH aqueous solution may be used. Since it does not contain an alkali metal like KOH or NaOH, it is easy to clean and can be used at a relatively low temperature, so it is easier to handle than KOH and NaOH. It is desirable to use the TMAH aqueous solution at a concentration of 1 to 50% and a temperature of 50 to 100 ° C. If the concentration is less than 1%, the etching rate is slow, which is not desirable. If the concentration exceeds 50%, it may become supersaturated and may cause precipitation, which is undesirable. If the temperature is less than 50 ° C., the etching rate is slow, which is not desirable. If the temperature exceeds 100 ° C., bubbles are generated in the solution and are not desirable because they adhere to the crystal, and the concentration may change due to evaporation of the solvent. There are also undesirable points. A more desirable range is a concentration of 6% to 25% and a temperature of 80 to 100 ° C.

  According to a second invention, in the first invention, the alkaline solution is a solution containing any of TMAH, KOH, and NaOH.

  A third invention is the method of manufacturing a semiconductor device according to the second invention, wherein the alkaline solution is a TMAH aqueous solution.

  A fourth invention is a method of manufacturing a semiconductor device according to any one of the first to third inventions, wherein the semiconductor device is a trench gate type.

  According to the first invention, since only the side surface of the trench groove can be etched by anisotropic etching with respect to the group III nitride semiconductor in an alkaline solution, the n-type or only the bottom of the trench groove is formed in a self-aligned manner with respect to the trench groove. A p-type region can be formed. In particular, when a TMAH aqueous solution is used as in the third invention, handling is easy and etching can be controlled with high accuracy. In addition, as with the fourth invention, by applying the present invention to a method for manufacturing a trench gate type semiconductor device, the breakdown voltage of the semiconductor device can be improved.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to these examples.

  FIG. 1 is a view showing a manufacturing process of a trench gate. Hereinafter, it will be described in detail with reference to FIG.

First, a mask 2 made of SiO ₂ is formed on the surface of the n-GaN layer 1 having the c-plane as a main surface at a position other than a position where a trench groove is formed (FIG. 1a).

  Next, ICP etching is performed using the mask 2 to form the trench groove 3 (FIG. 1b). The c-plane of the n-GaN layer 1 is exposed on the bottom surface 1a of the trench groove 3, and the surface other than the c-plane of the n-GaN layer 1 is exposed on the side surface 1b of the trench groove 3. The side surface 1b is etched so as to be perpendicular to the surface of the n-GaN layer 1, that is, perpendicular to the c-plane.

Next, Mg is ion-implanted perpendicularly to the surface of the n-GaN layer 1 at an acceleration voltage of 50 to 60 KeV and a dose of 10 ¹³ to 10 ¹⁴ / cm ² . Here, the mask 2 also functions as a mask for ion implantation. Therefore, Mg is doped on the bottom surface 1 a and the side surface 1 b of the trench groove 3 and is not doped on the surface 1 c of the n-GaN layer 1 covered with the mask 2. Ideally, the side surface 1b is perpendicular to the surface of the n-GaN layer 1 and is not doped with Mg. However, in practice, the side surface 1b cannot be processed to be strictly perpendicular, or ions formed by the mask 2 can be used. The side surface 1b is also doped with Mg due to the reflection. Thereafter, by performing heat treatment at 1000 ° C. in a nitrogen atmosphere, the doped Mg ions are activated and the p-type region 4 is formed (FIG. 1c).

  Next, the trench groove 3 is wet-etched with a TMAH aqueous solution having a temperature of 80 ° C. and a concentration of 25%. Here, the etching with the aqueous solution of TMAH has anisotropy, and the c-plane of GaN cannot be etched, but the surfaces other than the c-plane such as m-plane, a-plane, and r-plane can be etched. . Therefore, in the p-type region 4, the p-type region 4a formed at the bottom of the trench groove 3 is not removed, but the p-type region 4b formed at the side of the trench groove 3 is removed (FIG. 1d). In this way, the p-type region 4b can be formed in a region substantially coinciding with the trench groove bottom.

  It is desirable that the TMAH aqueous solution used for wet etching has a temperature of 50 to 100 ° C. and a concentration of 1 to 50%. If the concentration is less than 1%, the etching rate is slow, which is undesirable. If it exceeds 50%, it may become supersaturated and may cause precipitation, which is undesirable. Also, if the temperature is less than 50 ° C., the etching rate is slow, which is not desirable. If the temperature exceeds 100 ° C., bubbles are generated in the solution and adhere to the crystal, which is undesirable. The concentration changes due to evaporation of the solvent. It is also undesirable in that there is a risk of losing. More desirably, the concentration is in the range of 6 to 25% and the temperature is in the range of 80 to 100 ° C.

Thereafter, the mask 2 is removed with buffered hydrofluoric acid, a gate insulating film 5 made of SiO ₂ is formed on the inner surface of the trench groove 3 by CVD, and a gate electrode made of polysilicon is formed so as to fill the trench groove 3. 6 is formed (FIG. 1e).

  Through the above steps, a trench gate structure having the p-type region 4a only at the bottom of the trench groove 3 can be formed in a self-aligned manner with respect to the formed trench groove 3.

  The present invention can be applied not only to the trench gate structure as in the first embodiment but also to trench isolation.

  In Example 1, a TMAH aqueous solution is used for wet etching, but an alkaline solution such as KOH or NaOH may be used in addition to the TMAH aqueous solution. Anisotropic etching similar to that of a TMAH aqueous solution is possible. However, the TMAH aqueous solution is easy to clean and can be etched at a low temperature, which is advantageous in that it is easier to handle than KOH or NaOH.

In Example 1, the p-type region 4a is formed at the bottom of the trench groove 3, but the present invention can also be applied to the case where an n-type region is formed at the bottom of the trench groove. The n-GaN layer 1 may be a plurality of layers having different compositions. For example, the lower the n-GaN layer, an upper ⁿ - and -AlGaN ^layer, n - surface trench grooves reach the n-GaN layer is formed from -AlGaN layer, the trench is its n-GaN layer The present invention can also be applied to a case where a p-type region doped with Mg is formed at the bottom. Conversely, when the trench groove is formed as the p-GaN layer instead of the n-GaN layer 1 and the n-type region doped with Si is formed at the bottom of the trench groove as the p-GaN layer, The invention is applicable. Further, p-GaN layer underlying the top layer ^p - and -AlGaN ^layer, p - the trench grooves as reach the p-GaN layer is formed from the surface of the -AlGaN layer, trenches its p-GaN layer The present invention can also be applied to the case where an n-type region doped with Si is formed at the bottom of the substrate.

  The manufacturing method of the present invention can be applied to a trench type semiconductor device made of a group III nitride semiconductor.

FIG. 6 is a diagram showing a trench gate structure forming process according to the first embodiment.

Explanation of symbols

1: n-GaN layer 2: mask 3: trench groove 4: p-type region 5: gate insulating film 6: gate electrode

Claims (4)

A step of forming a mask at a predetermined position on the surface of the semiconductor layer comprising a group III nitride semiconductor essentially containing Ga and having a c-plane as a main surface;
Etching the semiconductor layer to form a trench groove using the mask;
implanting n-type or p-type impurities perpendicularly to the surface of the semiconductor layer;
Activating the impurity by heat treatment to form an n-type region or a p-type region;
A step of wet etching the semiconductor layer, which is a side surface of the trench groove, with an alkaline solution;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the alkaline solution is a solution containing any of TMAH, KOH, and NaOH.   The method of manufacturing a semiconductor device according to claim 2, wherein the alkaline solution is a TMAH aqueous solution.   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a trench gate type.

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