JP5130937B2 - Current abnormality detection circuit - Google Patents

Description

  The present invention relates to a circuit for detecting an abnormality of a current flowing through a load when a driving transistor connected in series with a load is turned on between a power source and a ground.

Patent Document 1 includes a FET that forms a mirror pair with a MOSFET that drives a load as a circuit that detects a rare short (half short) of the load, and detects the current with about a thousandth of the load current. And the structure which detects an abnormality by converting into a voltage with a high precision resistor and comparing with a reference voltage is disclosed.
JP 2006-17696 A

However, the configuration of Patent Document 1 has a problem that an abnormality cannot be detected unless an overcurrent is passed through the load for a certain period of time. In addition, since the current accuracy of the current mirror circuit is guaranteed only for the current value assumed as a normal state, if an excessive current flows through the transistor on the load driving side, The current flowing through the transistor is not necessarily based on the assumed mirror ratio, and more current may flow through the load.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a current abnormality detection circuit capable of detecting an abnormality by shortening the time during which an excessive current is supplied to a load.

  According to the current abnormality detection circuit of claim 1, the current change detection means detects a state in which the current flowing through the load changes when the driving transistor connected in series with the load is turned on, and the abnormality determination means. Determines abnormality when it is detected that the current has changed beyond a predetermined range. In other words, if the current supplied to the load when the driving transistor is turned on is different from the normal state, the slope of the current change exceeds a predetermined range assumed in advance. Even when an excessive current is about to flow, an abnormality can be determined at an extremely early stage, and the time during which an excessive current is supplied to the load can be shortened.

The current change detecting means compares the terminal voltage of the load with the first reference voltage and a second reference voltage set to a potential higher than the first reference voltage, and the terminal voltage is the first reference voltage. The time until the second reference voltage is exceeded from the point in time exceeding is measured by the time measuring means. Then, the abnormality determination means determines an abnormality when the measured time is outside the time corresponding to the predetermined range. In this case, the time measured by the time measuring means indicates the slope of the current change that is applied to the load when the driving transistor is turned on. Therefore, if the measurement time is evaluated, the current change is normal or abnormal. Can be determined.

According to the current abnormality detection circuit of claim 2, the time data measured by the current change detection means is stored in the storage means, and the abnormality determination means includes the previous time data stored in the storage means and the time If the difference from the time data measured this time by the measuring means is outside the time corresponding to the predetermined range, an abnormality is determined. That is, based on the assumption that the time data measured last time and stored in the storage means is normal, if the difference between the previous time data and the time data measured this time is large, the current change falls within a predetermined range. It can be judged that it exceeded.

According to the current abnormality detection circuit of the third aspect, the data value corresponding to the time data difference in the second aspect is stored in advance in the storage means. Then, the abnormality determination unit compares the data obtained by subtracting the data value corresponding to the difference from the previous time data stored in the storage unit with the time data measured this time by the time measurement unit. Therefore, it is possible to easily perform the determination process by setting an allowable value in the case of determining abnormality in advance with data.

According to the current abnormality detection circuit of claim 4, the time measuring means constituting the current change detecting means starts from the time when the output signal of the first comparator that compares the terminal voltage of the load with the first reference voltage changes. The clocking operation is performed until the output signal of the second comparator that compares the terminal voltage with the second reference voltage changes. Therefore, by controlling the time measuring operation of the time measuring means based on the output signals of the two comparators, the measurement time to be evaluated can be easily obtained.

According to the current abnormality detection circuit of the fifth aspect , the time measuring means performs the time measuring operation in a period in which the output signal of the EXOR gate to which the output signals of the first comparator and the second comparator are input has a significant level. In other words, the period in which the output signal of the EXOR gate shows a significant level is a period corresponding to the measurement time to be evaluated, so that the time measurement means performs the time measuring operation only during the period, so that the measurement time to be evaluated is One layer can be easily obtained.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of the current abnormality detection circuit. Between the power source and the ground, a series circuit of a P-channel MOSFET 1 (driving transistor) and a coil 2 as an L load, a series circuit of a current source 3 and a variable resistance element 4, a current source 5 and a variable resistance element 6 Are connected in parallel. The common connection point between the FET 1 and the coil 2 is connected in common to the non-inverting input terminals of the first comparator 7 (current change detection means) and the second comparator 8 (current change detection means). And the variable resistance element 4 are connected to the inverting input terminal of the first comparator 7, and the common connection point of the current source 5 and the variable resistance element 6 is connected to the inverting input terminal of the second comparator 8.
When the constant current I supplied from the current sources 3 and 5 has the same value, the resistance value R1 of the variable resistance element 4 and the resistance value R2 of the variable resistance element 6 are (R1 <R2). Is set.

  The output terminals of the first comparator 7 and the second comparator 8 are connected to the data input terminals IN of the flip-flops 9 and 10, respectively. The data output terminal OUT of the flip-flops 9 and 10 is connected to the EXOR gate 11 (time measuring means). ) Input terminals. The clock input terminal CLK of the flip-flops 9 and 10 is supplied with a clock signal having a predetermined frequency from a clock output circuit (not shown).

  The output terminal of the EXOR gate 11 is connected to the count enable terminal CE of the timer counter 12 (time measuring means), and the count data of the timer counter 12 is given to the write control logic unit 13. The write control logic unit 13 is a hardware logic circuit composed of, for example, a CPLD (Complex Programmable Logic Device), and is set so that when the count data of the timer counter 12 is read, the data is written to the EEPROM 14 (storage means). Has been. The output terminal of the EXOR gate 11 is also connected to the trigger input terminal of the write control logic unit 13, and the write control logic unit 13 uses the falling edge of the signal output from the EXOR gate 11 as a trigger for writing. Control is started.

  The data read from the timer counter 12 by the write control logic unit 13 is latched before being written to the EEPROM 14 and output to the comparators (magnitude comparators) 15U and 15D. Then, the EEPROM 14 outputs the data written by the write control logic unit 13 to the comparators 15U and 15D (abnormality determination means) through the adder / subtractor 16 as comparison threshold data.

  In this case, an allowable value data α for determining a current abnormality is set in advance in the EEPROM 14 with reference to the data CD_O previously written by the write control logic unit 13, and the data CD_O, data α is output. Then, the addition / subtraction unit 16 outputs the data (CD_O + α) obtained by adding both to the comparator 15U, and outputs the data (CD_O−α) obtained by subtracting both to the comparator 15D.

That is, the comparators 15U and 15D compare the time data CD_N measured this time by the timer counter 12 with the result obtained by adding / subtracting the allowable value data α to / from the data CD_O written in the EEPROM 14 last time as a comparison reference. The comparator 15U is
CD_N> (CD_O + α)
If so, the comparison result signal is changed to a high level, and the comparator 15D
CD_N <(CD_O−α)
If so, the comparison result signal is changed to a high level.
The comparison results of the comparators 15U and 15D are respectively supplied to the input terminals of the OR gate 17 (abnormality determination means), and the output signal of the OR gate 17 becomes a high active abnormality determination signal. The above constitutes the current abnormality detection circuit 18.

Next, the operation of this embodiment will be described with reference to FIGS. A PWM signal is output to the gate of the FET 1 by a drive control circuit (not shown), and the FET 1 is ON / OFF controlled by the PWM signal to intermittently energize the coil 2.
FIG. 2 shows changes in the current IL flowing through the coil 2 when the FET 1 is turned on. When the amount of current passed through the FET 1 is normal, the degree of increase in the current IL reaches a predetermined value It1 at time t1 and reaches a predetermined value It2 at time t2, as indicated by a broken line in the figure. It becomes an inclination.

  On the other hand, when the amount of energized current increases due to, for example, a rare short occurring in the coil 2, the degree of increase of the current IL is the time t1 ′ (< The slope becomes steep so as to reach the predetermined value It1 at t1) and the predetermined value It2 at time t2 '(<t2). In FIG. 1, the resistance elements indicated by broken lines so as to be connected in parallel to the coil 2 are images of equivalent resistance when a rare short occurs. In addition, when a dead short occurs, the current change has a steeper slope.

Therefore, in consideration of the resistance of the coil 2, the resistance values of the variable resistance elements 4 and 6 are adjusted,
Vt1 = R1 ・ I, Vt2 = R2 ・ I
Set to be. The voltages Vt1 and Vt2 (first and second reference voltages) correspond to the terminal voltage of the coil 2 when the currents It1 and It2 flow. Then, as shown in FIG. 3, the output signal of the first comparator 7 changes to high level when the current IL exceeds the predetermined value It1, and the output signal of the second comparator 8 has the current IL of the predetermined value It2. It changes to a high level when exceeding.

  Since the EXOR gate 11 takes an exclusive OR of the output signals of the comparators 7 and 8, the output of the EXOR gate 11 from the time when the former signal changes to high level to the time when the latter signal changes to high level. The signal becomes high level (significant). Therefore, the length of the period during which the output signal is at a high level corresponds to the slope of the current IL, indicating that the slope is slow when the period is long, and the slope is steep when the period is short. . This period length varies depending on the individual design, but as an example, it is assumed to be about several ms to several hundreds of μs.

Since the timer counter 12 counts only during the period when the output signal is at a high level, the magnitude of the count data indicates the degree of inclination of the current IL. The write control logic unit 13 is triggered by the falling edge of the output signal of the EXOR gate 11 to start a logic sequence, latches the count data of the timer counter 12, and after the predetermined time elapses, the latched data is stored in the EEPROM 14. Write to.
Then, as described above, the comparators 15U and 15D use the time data CD_N measured this time by the timer counter 12 based on the result obtained by adding / subtracting the allowable value data α to / from the data CD_O written in the EEPROM 14 last time. Compare. FIG. 3A shows a case where the amount of current IL supplied is normal and corresponds to the time (t2-t1) shown in FIG.

On the other hand, FIG. 3B shows a case where the energization amount of the current IL is excessive, and corresponds to the time (t2′−t1 ′) shown in FIG. In this case, the comparator 15U
CD_N <(CD_O−α)
Thus, the comparison result signal is changed to a high level. Therefore, the OR gate 17 outputs an abnormality determination signal.

When an open system failure occurs, the coil 2 is not energized, and the current IL remains “0”. In this case, in the comparator 15D,
CD_N ≧ (CD_O + α)
Thus, the comparison result signal is changed to a high level. Therefore, the OR gate 17 also outputs an abnormality determination signal in this case.

As described above, according to the present embodiment, the current abnormality detection circuit 18 detects a state in which the current IL flowing through the coil 2 changes when the FET 1 is turned on, and the current IL has changed beyond a predetermined range. By detecting this, a current abnormality is determined. Therefore, even when an excessive current is about to flow through the coil 2, an abnormality can be determined at an extremely early stage, and the time during which the overcurrent is energized can be shortened.
Specifically, the terminal voltage of the coil 2 is compared with the first reference voltage Vt1 and the second reference voltage Vt2 by the first comparator 7 and the second comparator 8, respectively, and the terminal voltage exceeds the first reference voltage Vt1. The time from the point in time until the second reference voltage Vt2 is exceeded is measured by the EXOR gate 11 and the timer counter 12.

  Then, the time data measured by the timer counter 12 is stored in the EEPROM 14, the allowable data value α is also stored in the EEPROM 14 in advance, and the comparator 15 stores the current measurement time CD_N and the previous time stored in the EEPROM 14. When the difference from the time data CD_O exceeds α, that is, when the measurement time CD_N changes beyond a predetermined range [(CD_O−α) ≦ CD_N ≦ (CD_O + α)], an abnormality is determined.

  Therefore, the gradient of the current change that is passed through the coil 2 when the FET 1 is turned on is evaluated by the time measured by the timer counter 12 to determine whether the change in the load current IL is normal or abnormal. be able to. Further, on the assumption that the time data CD_O measured last time and stored in the EEPROM 14 is normal, the current change exceeds a predetermined range when the difference from the time data CD_N measured this time is larger than α. Can be judged. Furthermore, it is possible to easily perform the determination process by setting the allowable value α in the case of determining abnormality by data in advance.

  In addition, based on the output signals of the two comparators 7 and 8, the timer counter 12 is controlled so as to perform the time counting operation while the exclusive OR signal obtained through the EXOR gate 11 shows a significant level, thereby evaluating The target measurement time CD_N can be easily obtained.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
Instead of the variable resistance elements 4 and 6, a resistance element having a predetermined resistance value may be used.
The flip-flops 9 and 10 may be arranged as necessary.
Only the comparator 15D may be provided, the OR gate 17 may be deleted, and the abnormality determination may be performed only by the comparison result signal of the comparator 15D.
It is not necessary to store the data value measured by the timer counter 12 in the EEPROM 14 every time and compare the previous data with the current data, and the predetermined reference data (including the amount corresponding to the allowable value α). The reference data may be stored in the EEPROM 14 and the data value measured by the timer counter 12 may be compared. In that case, PROM or zener zap may be used as the storage means.

When the count enable CE of the timer counter 12 is low active, the output signal of the EXOR gate 11 may be inverted and given.
Further, the EXOR gate 11 may be deleted, and the count start and stop of the timer counter 12 may be directly controlled by the output signals of the comparators 7 and 8.
The load is not limited to the coil 2, and, for example, a lower (ground side) MOSFET constituting the H bridge may be used as the load.
The driving transistor may be a P-channel MOSFET or a bipolar transistor, or may be applied to a low-side driving method.

The figure which is one Example of this invention, and shows the whole structure of a current abnormality detection circuit The figure which shows the change of the electric current IL which flows into a coil when FET turns on Timing chart showing circuit operation

Explanation of symbols

  In the drawing, 1 is a P-channel MOSFET (driving transistor), 2 is a coil (load), 7 is a first comparator (current change detection means), 8 is a second comparator (current change detection means), and 11 is an EXOR gate ( (Time measurement means), 12 is a timer counter (time measurement means), 14 is an EEPROM (storage means), 15 is a comparator (abnormality determination means), 17 is an OR gate (abnormality determination means), and 18 is a current abnormality detection circuit. Show.

Claims (5)

A current change detecting means for detecting a state in which a current flowing through the load changes when a driving transistor connected in series with the load is turned on between the power source and the ground;
An abnormality determining means for determining an abnormality when the current change detecting means detects that the current has changed beyond a predetermined range ;
The current change detection means compares the terminal voltage of the load with a first reference voltage and a second reference voltage set to a potential higher than the first reference voltage, and the terminal voltage is the first reference voltage. A time measuring means for measuring the time from when the voltage exceeds the time until the terminal voltage exceeds the second reference voltage,
The current abnormality detection circuit , wherein the abnormality determination means determines an abnormality when a time measured by the time measurement means is outside a time corresponding to the predetermined range . Storage means for storing time data measured by the current change detection means ;
The abnormality determining means determines an abnormality when a difference between the previous time data stored in the storage means and the time data measured this time by the time measuring means is outside the time corresponding to the predetermined range. The current abnormality detection circuit according to claim 1. In the storage means, a data value corresponding to the difference is stored in advance,
The abnormality determination means compares the data obtained by subtracting the data value corresponding to the difference from the previous time data stored in the storage means with the time data currently measured by the time measurement means. The current abnormality detection circuit according to claim 2, wherein: The current change detection means includes
A first comparator for comparing a terminal voltage of the load with the first reference voltage;
A second comparator that compares the terminal voltage of the load with the second reference voltage;
4. The time measuring means performs a time measuring operation from a time point when an output signal of the first comparator changes to a time point when an output signal of the second comparator changes. Current abnormality detection circuit. An EXOR gate to which output signals of the first comparator and the second comparator are input;
5. The current abnormality detection circuit according to claim 4 , wherein the time measuring means performs a time measuring operation during a period in which an output signal of the EXOR gate shows a significant level .

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