JP5130570B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using SRAM (Static Random Access Memory) as a memory cell.

  In recent years, with the widespread use of portable terminal devices, the importance of digital signal processing for processing a large amount of data such as sound and images at high speed has increased. An SRAM capable of high-speed access processing occupies an important position as a semiconductor memory device mounted on such a portable terminal device.

  On the other hand, in semiconductor integrated circuits, the demand for process miniaturization has become more severe, and various improved inventions for SRAM accompanying process miniaturization have been proposed, and a method for adjusting the voltage level of the power supply voltage has been proposed.

  For example, Japanese Patent Application Laid-Open No. 2006-73165 discloses a method for suppressing an increase in leakage current accompanying process miniaturization, and a method for setting a power supply voltage of an inactive word line to a low level. . In Japanese Patent Application Laid-Open No. 2004-5777, when a circuit is driven with a low power supply voltage (about 1.2 V) due to process miniaturization, a threshold of a transistor is suppressed in order to suppress a decrease in operation margin. A method of adjusting the voltage level of the power supply voltage according to the value voltage is disclosed.

Japanese Patent Laid-Open No. 2005-108307 discloses a method of adjusting the voltage level of the power supply voltage in order to suppress data retention failure in a low temperature region.
JP 2006-73165 A JP 2004-5777 A JP 2005-108307 A

  On the other hand, in the improved invention as described above, a method of adjusting the power supply voltage or the like as a whole in order to improve the operation margin or the like in various SRAMs has been disclosed.

  However, when the threshold voltage Vth of the memory cell is entirely within a certain range due to process miniaturization or the like, it is possible to improve the SNM or the like by adjusting the power supply voltage or the like as a whole. However, if the threshold voltage Vth varies widely locally, it is necessary to individually relieve.

  Conventionally, a method of replacing the memory cell (defective memory cell) with a redundant memory cell and relieving it has been adopted.

  However, when a redundant memory cell is provided to relieve a defective memory cell, it is necessary to lay out the redundant memory cell, which causes a problem that the chip area increases with an increase in the layout area of the redundant memory cell.

  The present invention has been made to solve the above problems, and provides a semiconductor memory device capable of relieving locally generated defective memory cells while reducing the layout area. With the goal.

  It is another object of the present invention to provide a semiconductor memory device capable of executing a test for easily determining a defective memory cell in a test mode.

  According to one embodiment of the present invention, a semiconductor memory device corresponds to a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to the memory cell rows, and a memory cell column, respectively. And a plurality of bit lines provided. The semiconductor memory device also includes a selection circuit that sets one of a plurality of word lines to an activated state based on a row selection signal according to an address signal input from the outside, an address signal from the outside, and a preset value And an address comparison circuit including a comparison unit that compares the defective address signal of the defective memory cell.

  Each memory cell includes a flip-flop circuit for setting the first and second storage nodes to one and the other of the first and second potential levels according to data to be stored, a corresponding word line and gate, respectively. And an access transistor for electrically coupling between the corresponding bit line and the flip-flop circuit.

  The address comparison circuit includes a signal generation unit that outputs an instruction signal instructing adjustment of the voltage of the word line based on the comparison result of the comparison unit. A word line voltage supply circuit for adjusting a voltage supplied to the word line in response to the instruction signal at the time of data writing is further provided.

  According to this embodiment, the voltage of the word line is adjusted based on the comparison result of the comparison unit that compares the address signal from the outside with the preset defective address signal of the defective memory cell. That is, the voltage of the word line is adjusted in order to relieve a specific defective memory cell. Therefore, in order to relieve a defective memory cell, it is not necessary to replace a redundant memory cell and relieve it, but to relieve an individual defective memory cell by adjusting characteristics such as a write characteristic. Thus, it is possible to relieve locally generated defective memory cells while reducing the layout area.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram of semiconductor memory device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, semiconductor memory device 1 according to the first embodiment of the present invention includes a test pin 2 to which a test signal TE is input, a fuse signal terminal 3 to which fuse signals FS0 to FS8 are respectively input, and an external Address terminals 4 to which address signals AD0 to AD5 are input. Note that in the normal operation mode, the test signal TE is set to the “L” level, and in the test mode, it is set to the “H” level signal. In the normal operation mode, the fuse signals FS0 to FS8 receive a signal input of a preset logic level as will be described later. On the other hand, in the test mode, fuse signals FS0 to FS8 receive a signal input of an arbitrary logic level.

  The semiconductor memory device 1 also includes control terminals 5 and 6 to which control signals WE and CE are input, a clock terminal 7 to which an external clock ECLK is input, and a data input terminal 8 to which external data Di is input. And a data output terminal 9 for outputting data Qi to the outside, and a command terminal 11 to which an external command CMD is input.

  The semiconductor memory device 1 includes a memory array 15 including a plurality of SRAM memory cells (simply referred to as memory cells) integrated and arranged in a matrix.

  Memory array 15 includes a plurality of word lines provided corresponding to the memory cell rows and a plurality of bit lines provided corresponding to the memory cell columns, respectively. Memory array 15 includes a plurality of power supply lines that are provided corresponding to the memory cell columns, respectively, and supply a power supply voltage that is a cell operating voltage to each memory cell of the corresponding memory cell column.

  In this example, word lines WL0 and WL1 provided corresponding to the memory cell rows are shown as an example. Also, bit line BL0 provided corresponding to the memory cell column, bit line / BL0 complementary to bit line BL0, bit line BL1 provided corresponding to the memory cell column, and complementary to bit line BL1 Bit line / BL1 is shown. In addition, power supply lines ARVDD0 and ARVDD1 provided corresponding to the memory cell columns are shown.

  The semiconductor memory device 1 further includes an address buffer 10 that receives the address signals AD0 to AD5 from the address terminal 4 and performs buffer processing.

  The address buffer 10 buffers the address signals AD0 to AD5 from the address terminal 4 and outputs them to the address comparison circuit 80, the row decoder 20 and the column decoder 30, respectively. In this example, as an example, the address signals AD0 to AD2 are row address signals, and the address signals AD3 to AD5 are column address signals.

  The semiconductor memory device 1 includes an input of an address signal from the address buffer 10 and a row decoder 20 for executing a row selecting operation, a column decoder 30 for executing a column selecting operation, and the entire semiconductor memory device 1. And a control circuit 150 for controlling.

  The row decoder 20 outputs a row selection signal RSL to the word line driver 60 based on the row address signals (address signals AD0 to AD2) buffered by the address buffer 10.

  The column decoder 30 outputs a column selection signal CSL, which is a one-shot pulse signal, to the column selection switch 130 based on the column address signals (address signals AD3 to AD5) buffered by the address buffer 10.

  The semiconductor memory device 1 also includes a CE buffer 40, a read / write buffer 50, a CLK buffer 130, and an input / output buffer 90.

  CE buffer 40 buffers control signal CE input to control terminal 6 and outputs control signal CE #. The word line voltage supply circuit 70 is activated in accordance with the activation (“L” level) of the control signal CE #.

  Read / write buffer 50 buffers control signal WE input to control terminal 5 and outputs control signal WE #. Data writing and data reading are executed according to the logic level of control signal WE #. For example, when the control signal WE # is at “L” level, for example, data writing is executed, and when it is “H” level, operations other than data writing including data reading are executed.

  The CLK buffer 130 buffers the external clock ECLK input from the clock terminal 7 to generate and output the internal clock ICLK.

  The input / output buffer 90 receives the data Di from the data input terminal 8, buffers it, and outputs it as write data WDT to the write driver 110. The input / output buffer 90 receives the read data RDT from the sense amplifier 120 and performs buffer processing to output the data Qi to the data output terminal 9.

  The control circuit 150 controls the entire semiconductor memory device 1 and receives an internal clock ICLK, a command CMD input from the outside via the command terminal 11, and control signals CE # and WE #. The internal memory device 1 is instructed to operate at a predetermined timing in synchronization with the clock ICLK.

  In addition, the semiconductor memory device 1 includes an address comparison circuit 80, a word line driver 60, a word line voltage supply circuit 70, a voltage supply circuit band 100, a write driver 110, a sense amplifier 120, and a column selection switch 130. With.

  The address comparison circuit 80 receives input of the buffered address signals AD0 to AD5, fuse signals FS0 to FS8 and the test signal TE from the address buffer 10 and executes a coincidence comparison operation and the like based on the comparison. Control signals WLUP, WLDWN, VDDWN are output.

  The word line driver 60 selects and drives the corresponding word line WL based on the row selection signal RSL from the row decoder 20.

  The word line voltage supply circuit 70 is a circuit that supplies a voltage for driving the word line WL in the word line driver 60. As will be described later, the word line voltage supply circuit 70 adjusts the voltage level in response to control signals WLUP and WLDWN from the address comparison circuit 80. .

  The voltage supply circuit band 100 includes a voltage supply unit provided corresponding to each of a plurality of power supply lines ARVDD provided corresponding to each memory cell column, which will be described later. In each voltage supply unit, the voltage supply circuit ARVDD The voltage level is adjusted.

  Write driver 110 writes to bit line BL and complementary bit line / BL corresponding to the column selected by column selection switch 130 based on the input of write data WDT buffered in input / output buffer 90. It is driven at a voltage level corresponding to the data WDT.

  The sense amplifier 120 is connected to the bit line BL and the complementary bit line / BL corresponding to the column selected by the column selection switch 130, amplifies read data from the selected memory cell, and supplies it to the input / output buffer 90. Output.

  Column selection switch 130 is connected to bit line BL and complementary bit line / BL corresponding to the column selected in response to input of column selection signal CSL from column decoder 30, and write driver 110 or sense amplifier 120. Control electrical connections.

FIG. 2 is a diagram illustrating a configuration of memory cell MC according to the first embodiment of the present invention.
Referring to FIG. 2, memory cell MC according to the first embodiment of the present invention includes transistors PT1 and PT2 and transistors NT1 to NT4. Transistors PT1 and PT2 are P-channel MOS transistors as an example. Transistors NT1-NT4 are N-channel MOS transistors as an example. Here, transistors NT3 and NT4 are access transistors provided between bit lines BL and / BL and storage nodes nd1 and nd2.

  Transistor PT1 is arranged between power supply line ARVDD to which a power supply voltage is supplied and storage node nd1, and its gate is electrically coupled to storage node nd2. Transistor NT1 is arranged between storage node nd1 and ground voltage GND, and has its gate electrically coupled to storage node nd2. Transistor NT2 is arranged between storage node nd2 and ground voltage GND, and has its gate electrically coupled to storage node nd1. Transistor PT2 is arranged between power supply line ARVDD and node nd2, and has its gate electrically coupled to storage node nd1.

  Transistors PT1, PT2 and NT1, NT2 form two CMOS inverters for holding the signal levels of storage nodes nd1 and nd2 and are cross-coupled to form a CMOS type flip-flop circuit.

  Transistor NT3 is arranged between bit line BL and storage node nd1, and has its gate electrically coupled to word line WL. Transistor NT4 is arranged between storage node nd2 and complementary bit line / BL, and its gate is electrically coupled to word line WL.

  Data writing and reading with respect to storage node nd1 and storage node nd2 are performed by turning on transistors NT3 and NT4 in response to activation (high level) of word line WL, and bits complementary to storage node nd1, bit line BL and storage node nd2. This is performed by electrically coupling the lines / BL.

  For example, when word line WL is deactivated and transistors NT3 and NT4 are turned off, N-type and P-type MOSs in the respective CMOS inverters according to the data levels held at storage nodes nd1 and nd2 One of the transistors is turned on. Thereby, storage nodes nd1 and nd2 are connected to one of power supply voltage corresponding to the “H” level of data and ground voltage GND corresponding to the “L” level of data according to the data level held in the memory cell. Each is electrically coupled to the other. As a result, data can be held in the memory cell in the standby state without periodically turning on the word line and executing the refresh operation.

  FIG. 3 is a diagram illustrating a configuration of column selection gate GS constituting column selection switch 130 according to the first embodiment of the present invention.

  Referring to FIG. 3, here, a part of the configuration of column selection switch 130 according to the first embodiment of the present invention is shown.

Specifically, a column selection gate GS is provided corresponding to each memory cell column.
Column select gate GS includes transfer gates TG1 and TG2 and an inverter IV0.

  The transistor TG1 is provided between the bit line BL and the node N0. Transistor gate TG2 is provided between complementary bit line / BL and node N1. Transfer gates TG1 and TG2 operate in response to input of column selection signal CSL and its inverted signal via inverter IV0.

  For example, when column selection signal CSL is at “H” level, transfer gates TG1 and TG2 are turned off, and bit line BL and complementary bit line / BL and nodes N0 and N1 are electrically disconnected from each other. Has been.

  When column selection signal CSL is at "L" level, transfer gates TG1 and TG2 are turned on, and bit line BL and complementary bit line / BL are electrically coupled to nodes N0 and N1, respectively. The That is, the column selection gate GS is activated when the column selection signal CSL is at the “L” level.

  The node N0 and the node N1 are an output node of the write driver 110 and an input node of the sense amplifier 125.

  The same applies to the other memory cell columns, which are provided corresponding to the memory cell columns, respectively, and a column selection gate GS is provided between the nodes N0 and N1 and the corresponding bit lines.

  At the time of data writing, write driver 110 sets output nodes N0 and N1 to one and the other of power supply voltage VDD and ground voltage GND based on the input of write data WDT.

  Then, the data is supplied to the bit lines BL and / BL corresponding to the selected column via the column selection gate GS. Then, although not shown, the word line WL corresponding to the selected memory cell row is activated, and data writing to the selected memory cell is executed.

  On the other hand, at the time of data reading, column selection gate GS corresponding to the selected column is activated in response to input of column selection signal CSL, and bit lines BL, / BL and sense amplifiers corresponding to the selected column are activated. 125 input nodes N0 and N1 are electrically coupled to each other. Then, although not shown, the word line corresponding to the selected memory cell row is activated and the storage nodes nd1 and nd2 of the selected memory cell and the bit lines BL and / BL are electrically coupled. The sense amplifier 125 amplifies data held in the selected memory cell and outputs it to the input / output buffer 90 as read data RDT in accordance with the voltage levels held in the storage nodes nd1 and nd2 of the selected memory cell.

  FIG. 4 is a diagram illustrating an internal configuration of address comparison circuit 80 according to the first embodiment of the present invention.

  Referring to FIG. 4, address comparison circuit 80 according to the first embodiment of the present invention includes a comparison unit 81, a test mode circuit 82, and a signal generation circuit 83.

  The comparison unit 81 includes a plurality of exclusive logical OR circuits EOR, NOR circuits NR1 and NR2, and an AND circuit AD.

  The comparison unit 81 compares the address signals AD0 to AD5 with the fuse signals FS0 to FS5, and outputs an “H” level control signal HT if all match. If they do not match, the control signal HT is at the “L” level.

  Each exclusive logical OR circuit EOR compares the address signals AD0 to AD5 with the fuse signals FS0 to FS5, respectively.

  The NOR circuit NR1 receives the comparison results for the address signals AD0 to AD2 and the fuse signals FS0 to FS2, and outputs the NOR logic operation result to the AND circuit AD.

  Here, the NOR circuit NR1 outputs an “H” level signal when the address signals AD0 to AD2 and the fuse signals FS0 to FS2 all match. If they do not match, an “L” level signal is output.

  The NOR circuit NR2 receives the comparison results for the address signals AD3 to AD5 and the fuse signals FS3 to FS5, and outputs a NOR logic operation result to the AND circuit AD.

  Here, the NOR circuit NR2 outputs an “H” level signal when the address signals AD3 to AD5 and the fuse signals FS3 to FS5 all match. If they do not match, an “L” level signal is output.

  The AND circuit AD outputs the AND logic operation result of the signals output from the NOR circuits NR1 and NR2 as the control signal HT.

  When the NOR circuits NR1 and NR2 both output “H” level signals, that is, when the comparison results for the address signals AD0 to AD5 and the fuse signals FS0 to FS5 all match, the AND circuit AD sets the control signal HT to “ Output as “H” level. If they do not match, control signal HT is at "L" level.

Test mode circuit 82 includes a NOR circuit NR3 and an inverter IV1.
The NOR circuit NR3 receives the control signal HT and the test signal TE, and outputs the NOR logic operation result to the inverter IV1. Inverter IV1 inverts the output signal of NOR circuit NR3 and outputs control signal HT # to signal generation circuit 83. Test signal TE is set to “L” level in the normal operation mode. Therefore, the NOR circuit NR3 has the same function as the inverter, and is further inverted via the inverter IV1, so that the logic level of the control signal HT is directly output to the signal generation circuit 83 as the control signal HT #. On the other hand, when test signal TE is set to “H” level, control signal HT # is set to “H” level regardless of the logic level of control signal HT.

  The signal generation circuit 83 receives the control signal HT # and outputs control signals WLDWN, WLUP, VDDWN based on the logic levels of the fuse signals FS6 to FS8.

  Here, as will be described later, the control signal WLDWN is a signal for instructing to lower the voltage level of the word line WL by a predetermined voltage. The control signal WLUP is a signal for instructing to increase the voltage level of the word line WL by a predetermined voltage. The control signal VDDWN is a signal for instructing to lower the voltage level of the power supply line ARVDD by a predetermined voltage.

  Note that the fuse signals FS0 to FS8 are fixedly given in advance based on the test results, but it is assumed that the fuse signals can be arbitrarily set during the test.

  FIG. 5 is a diagram illustrating a part of the configuration of word line voltage supply circuit 70 and word line driver 60 according to the first embodiment of the present invention.

  Referring to FIG. 5, word line voltage supply circuit 70 according to the first embodiment of the present invention includes transistors 71, 72 and 74 and an inverter 73. Transistors 71, 72, and 74 are P-channel MOS transistors, respectively.

  In a normal time, the word line voltage supply circuit 70 is set to a state where the voltage level of the power supply voltage VDD is stepped down by a predetermined voltage.

  Transistor 71 is arranged between power supply voltage VDD and output node N2, and has its gate receiving control signal CE #. Transistor 72 is arranged between output node N2 and ground voltage GND, and has a gate receiving control signal WLDWN. Transistor 74 is arranged between output node N 2 and ground voltage GND, and has its gate receiving control signal WLUP via inverter 73.

  Here, the control signal WLUP is normally set to the “H” level, and is input to the gate of the transistor 74 via the inverter 73.

  Therefore, transistor 74 is turned on, and transistor 71 is turned on when control signal CE # is activated ("L" level).

  Therefore, power supply voltage VDD and output node N2 are electrically coupled. Since the transistor 74 is on as described above, the voltage level of the output node N2 is set to a voltage that is a predetermined voltage lower than the power supply voltage VDD.

  Here, when the control signal WLUP is activated and set to the “L” level, an “H” level signal is supplied to the gate of the transistor 74 via the inverter 73, so that the transistor 74 is turned off. The voltage level of output node N2 becomes power supply voltage VDD. Therefore, the voltage of the word line WL can be increased more than usual.

  On the other hand, when control signal WLDWN is activated and set to the “L” level, transistor 72 is turned on. Therefore, the voltage of the word line can be lowered compared to the normal time.

  Word line driver 60 includes a word line driver unit WDR provided corresponding to each memory cell row.

  Word line driver unit WDR includes transistors 61 and 62. Transistors 61 and 62 are connected in series between node N2 and ground voltage GND, and the connection node is connected to the corresponding word line. Each gate receives a row selection signal RSL.

  When row selection signal RSL is at “L” level, transistor 61 is turned on, and node N2 and word line WL are electrically coupled. On the other hand, when row selection signal RSL is at “H” level, transistor 62 is turned on, and word line WL and ground voltage GND are electrically coupled.

  FIG. 6 is a diagram illustrating a part of the configuration of voltage supply circuit band 100 according to the first embodiment of the present invention.

  Voltage supply circuit band 100 according to the first embodiment of the present invention includes a plurality of voltage supply units VDU provided corresponding to the memory cell columns, respectively.

  Voltage supply unit VDU includes transistors 101, 102, 106 and 107, inverters 103 to 106, and a NAND circuit 104.

  Transistor 101 is arranged between power supply voltage VDD and node N 3, and its gate is electrically coupled to an output node of NAND circuit 104 via inverter 103.

  Transistor 102 is arranged between nodes N 3 and N 4, and has its gate electrically coupled to the output node of NAND circuit 104.

Node N3 is electrically connected to power supply line ARVDDi (a natural number of 0 or more).
Transistor 107 is arranged between node N4 and ground voltage GND, and has its gate receiving control signal VDDWN. Transistor 106 is arranged between node N4 and ground voltage GND in parallel with transistor 107, and has a gate receiving control signal WE #.

  NAND circuit 104 receives column selection signal CSL via inverter 106 and control signal WE # via inverter 105, and outputs the NAND logical operation result to transistor 102 and inverter 103.

The operation will be described.
NAND circuit 104 outputs a NAND logic operation result based on column selection signal CSL via inverter 106 and an inverted signal of control signal WE # via inverter 105. When control signal WE # is at “H” level, that is, when data is read, for example, when data is read, NAND circuit 104 outputs “H” level. Therefore, the transistor 102 is turned off, and the transistor 101 is turned on by the input of the “L” level signal through the inverter 103.

  Therefore, power supply line ARVDD is at the same voltage level as power supply voltage VDD, for example, in the case of data reading other than during data writing.

  On the other hand, control signal WE # is set to the “L” level during data writing. Further, the NAND circuit 104 outputs the “L” level based on the input of the column selection signal CSL (“L” level). In that case, the transistor 101 is turned off. Further, the transistor 102 is turned on. Therefore, node N3 and node N4 are electrically coupled. The column selection signal CSL is input as a one-shot pulse signal (“L” level).

  Further, with the input of control signal WE # (“L” level), ground voltage GND and node N4 are electrically coupled. As a result, the voltage level of the power supply line ARVDDi is lower than the power supply voltage VDD.

  When the control signal VDDWN is at “L” level, the transistor 107 is turned on. Therefore, since the transistors 106 and 107 are turned on, the voltage level of the power supply line ARVDDi is further lower than the voltage at the time of normal data writing by a predetermined voltage.

  Hereinafter, setting of fuse signals FS0 to FS5 according to the first embodiment of the present invention will be described.

  In the first embodiment of the present invention, a predetermined test is performed on each memory cell of the memory array before setting the fuse signals FS0 to FS5, and if a defect occurs in the selected memory cell, the result is obtained. In response, fuse signals FS0 to FS5 are set as defective addresses for defective memory cells.

  In this example, for a memory cell selected as an example, a test (also referred to as an SNM test) is performed to determine whether or not a data destruction failure occurs due to a decrease in static noise margin during data reading. Further, a test (also referred to as an SA test) is performed to determine whether or not the data read current amount flowing to sense amplifier 120 is sufficient for the selected memory cell. Also, a test (also referred to as a write test) is performed to determine whether or not a data write failure occurs in the selected memory cell.

  The defect information about the memory cell selected based on the test result is registered in the fuse signal.

  For example, if it is determined by the SNM test that a data destruction failure occurs due to a decrease in static noise margin during data reading, the failure address of the defective memory cell is set in the fuse signals FS0 to FS5, and the fuse signal FS6 is set to “H”. Set to level. For example, as a set of fuse signals, the power supply voltage VDD is connected as a fixed voltage when set to “H” level, and the ground voltage GND is connected as a fixed voltage when set to “L” level. It is possible.

  In response, control signal WLDWN is set to “L” level as fuse signal FS6 is set to “H” level and control signal TE # is set to “H” level.

  Then, the word line voltage supply circuit 70 sets the voltage level of the word line WL from the normal voltage as described above in accordance with the input of the control signal WLDWN when the fuse signal FS6 is set to the “H” level. Also lower. As a result, the transistors NT3 and NT4, which are access transistors, are supplied with a voltage lower than normal, so that the influence of the potential level of the electrically connected bit line BL and the complementary bit line / BL is suppressed. Inversion of the potentials of the storage nodes nd1 and nd2 can be suppressed. That is, it becomes possible to relieve a defective memory cell that is determined to have a data destruction failure due to a decrease in static noise margin during data reading by an SNM test.

  As another example, whether or not the data read current amount flowing to the sense amplifier 120 for the selected memory cell is sufficient is tested (also referred to as an SA test), and the data read current amount is small and sufficient. When it is determined that the amplification operation cannot be performed, the fuse signal FS7 is set to the “H” level.

  In response to this, as the fuse signal FS7 is set to the “H” level and the control signal TE # is set to the “H” level, the control signal WLUP is set to the “L” level.

  By setting the fuse signal FS7 to the “H” level, the voltage level of the word line WL is made higher than the normal voltage.

  As a result, a higher voltage than normal is supplied to the transistors NT3 and NT4 which are access transistors, so that the potential difference between the storage nodes nd1 and nd2 is sufficiently reflected in the potential difference between the bit line BL and the complementary bit line / BL. As a result, the amount of current flowing through the sense amplifier 120 can be increased to ensure an operation margin for the sense amplifier. That is, it becomes possible to relieve a defective memory cell having a lower operation margin than the sense amplifier SA.

  Further, as another example, a test (also referred to as a write test) is performed to determine whether or not a data write failure occurs for the selected memory cell. The defective address of the defective memory cell is set to signals FS0 to FS5, and fuse signal FS8 is set to "H" level.

  As fuse signal FS8 is set to "H" level and control signal TE # is set to "H" level, control signal VDDWN is set to "L" level.

  By setting the control signal VDDWN to the “L” level, the voltage level of the power supply line ARVDD is made lower than the normal voltage.

  As a result, as the operating voltage of the memory cell is lowered, the data retention characteristic is lowered, so that data can be easily written, and a defective memory cell having a low data writing characteristic can be relieved.

  At this point, when it is determined by the writing test that a data writing failure occurs, the defective address of the defective memory cell is set in the fuse signals FS0 to FS5, and the fuse signal FS7 is set to the “H” level. It is also possible to do.

  In this case, as the fuse signal FS7 is set to the “H” level and the control signal TE # is set to the “H” level, the control signal WLUP is set to the “L” level.

  By setting the control signal WLUP to the “L” level, the voltage level of the word line WL is made higher than the normal voltage.

  As a result, a higher voltage than usual is supplied to the transistors NT3 and NT4 which are access transistors, so that data can be easily written to the storage nodes nd1 and nd2, and a defective memory cell having low data writing characteristics is relieved. It becomes possible to do.

  Here, the case where the fuse signal FS8 is set to the “H” level or the fuse signal FS7 is set to the “H” level when the write test is determined to be defective has been described. It is also possible to set both signals FS7 and FS8 to "H" level. By setting both to “H” level, it is possible to improve the write characteristics of a defective memory cell having a low clear data write characteristic.

FIG. 7 is a timing chart illustrating Example 1 of the normal operation mode.
Here, a case will be described in which an address signal input from the outside at the time of data writing accesses not a defective memory cell but a normal memory cell. It is assumed that fuse signals FS0 to FS5 are all set to “L” level. It is assumed that fuse signal FS8 is set to “H” level. The fuse signals FS6 and FS7 are set to the “L” level.

  Referring to FIG. 7, it is assumed that address signal AD0 is set to “H” level and address signals AD1 to AD5 are set to “L” level at time T1. At time T1, control signal WE # changes from “H” level to “L” level to instruct data writing.

  In this case, since the address signals AD0 to AD5 and the fuse signals FS0 to FS5 do not match, the comparison unit 81 outputs the control signal HT as the “L” level.

  Therefore, although the fuse signal FS8 is set at the “H” level, the control signal HT is at the “L” level, so that the signal generation circuit 83 has the control signals WLDWN, WLUP, and VDDWN in the initial state (inactive). The state in which the “H” level is output is maintained.

  Note that the voltage level of the word line WL is set to a voltage that is lower than the power supply voltage VDD by a predetermined voltage because the transistor 74 is turned on as described above with the control signal WLUP being at the “H” level. Yes.

FIG. 8 is a timing chart illustrating Example 2 of the normal operation mode.
Here, a case where an address signal input from the outside at the time of data writing accesses a defective memory cell will be described. It is assumed that fuse signal FS0 is set to “H” level and FS1 to FS5 are all set to “L” level. It is assumed that fuse signal FS8 is set to “H” level. Therefore, the defective memory cell is determined as defective data writing as defective information. The fuse signals FS6 and FS7 are set to the “L” level.

  Referring to FIG. 8, at time T3, address signal AD0 is set to “H” level, and address signals AD1 to AD5 are set to “L” level. In this case, since address signals AD0 to AD5 and fuse signals FS0 to FS5 match, comparison unit 81 outputs control signal HT as “H” level at time T4.

  Since the fuse signal FS8 is at the “H” level and the control signal HT is at the “H” level, the signal generation circuit 83 sets the control signal VDDWN to the “L” level at time T5.

  In response to this, write voltage supply unit VDU turns on transistor 107 at time T6. Therefore, as described above, the voltage level of the power supply line ARVDD is further lowered from the normal voltage to a predetermined voltage.

  Thereby, in the data writing of the defective memory cell, it is possible to improve the writing characteristic of the defective memory cell having a low data writing characteristic by reducing the voltage level of the power supply line ARVDD, thereby enabling the data writing. .

FIG. 9 is a timing chart illustrating Example 3 of the normal operation mode.
Here, a case where an address signal input from the outside at the time of data reading accesses a defective memory cell will be described. It is assumed that fuse signals FS0 to FS5 are all set to “L” level. It is assumed that fuse signal FS7 is set to “H” level. Therefore, the defective memory cell is determined to have a low operation margin of the sense amplifier SA as defect information.

The fuse signals FS6 and FS8 are set to the “L” level.
Referring to FIG. 9, at time T10, address signal AD0 is set from "H" level to "L" level, and address signals AD1-AD5 are set to "L" level. In this case, since address signals AD0 to AD5 and fuse signals FS0 to FS5 match, comparison unit 81 outputs control signal HT as “H” level at time T11.

  Since the fuse signal FS7 is at “H” level and the control signal HT is at “H” level, the signal generation circuit 83 sets the control signal WLUP to “L” level at time T12.

  In response to this, the word line voltage supply circuit 70 turns off the transistor 74 at time T13. Therefore, as described above, the voltage level of the node N2 is further increased from the normal voltage to a predetermined voltage. That is, the voltage level supplied to the word line is the power supply voltage VDD.

  As a result, in the data reading of the defective memory cell, the write characteristics of the defective memory cell determined to have a low operation margin of the sense amplifier SA by raising the voltage level of the word line WL by a predetermined voltage are improved. Can be made possible.

  Therefore, with the configuration according to the first embodiment of the present invention, in order to relieve a defective memory cell, instead of relieving by replacing with a redundant memory cell, writing to each defective memory cell is performed. Since a method of repairing by adjusting characteristics such as characteristics is employed, it is not necessary to lay out redundant memory cells, and an increase in chip area accompanying an increase in the layout area of redundant memory cells can be suppressed. That is, it is possible to relieve locally generated defective memory cells while reducing the layout area.

(Embodiment 2)
In the above, the repair of defective memory cells in the normal operation mode has been described. That is, the case where the address signal and defect information of the defective memory cell are registered in the fuse signal based on the test result has been described.

  In the second embodiment, a system for executing the above test for registering a fuse signal in the test mode in the above configuration will be described.

First, the SNM test at the time of data reading will be described.
During the test, a test signal TE (“H” level) is input. The test mode circuit 82 of the address comparison circuit 80 sets the control signal HT # to the “H” level when the test signal TE (“H” level) is input. Therefore, as described above, control signal HT # (“H” level) is input to signal generation circuit 83 regardless of the comparison result of comparison unit 81.

  The signal generation circuit 83 outputs the control signals WLDWN, WLUP, and VDDWN according to the input of the fuse signals FS6 to FS8 that are input in response to the input of the control signal HT # (“H” level).

  In the SNM test, the fuse signal FS7 is set to the “H” level. Other fuse signals FS6 and FS8 are set to the “L” level. In the test mode, the fuse signals FS0 to FS5 are invalid, and the test is executed by inputting the fuse signals FS6 to FS8 from the outside at a predetermined logic level.

  In response to this, the signal generation circuit 83 activates the control signal WLUP to the “L” level.

  Further, the row decoder 20 and the column decoder 30 perform the above-described row and column selection operation based on the input address signal.

  Specifically, the corresponding word line driver unit WDR of the word line driver 60 is selected based on the input of the address signal. In addition, the column selection gate GS corresponding to the column selection switch 130 is selected.

  Specifically, transistor 61 of the corresponding word line driver unit WDR is turned on according to row selection signal RSL, and node N2 and selected word line WL are electrically coupled. In addition, corresponding column selection gate GS is activated according to column selection signal CSL, and selected bit line BL and complementary bit line / BL are electrically coupled to sense amplifier 125.

  Here, as described above, the word line voltage supply circuit 70 turns off the transistor 74 in response to the input of the control signal WLUP (“L” level). Therefore, the voltage at the node N2 becomes the power supply voltage VDD, and is increased by a predetermined voltage from the normal time.

  Therefore, the selected word line WL is supplied with a word line voltage that is higher than the normal voltage by a predetermined voltage.

  Since the transistors NT3 and NT4, which are access transistors of the selected memory cell, are supplied with a higher voltage than usual, in the case of a defective memory cell with a low SNM, the electrically connected bit line BL and There is a possibility that the potential of storage nodes nd1 and nd2 inverts according to the potential level of complementary bit line / BL, that is, a data destruction failure occurs due to a decrease in static noise margin.

  Then, by comparing the data read from the sense amplifier 120 with the data written in advance, if it is inverted, it is determined that there is a data destruction failure due to a decrease in static noise margin. The defective address of the cell and the defective information of the defective memory cell are registered by a fuse signal.

  Specifically, the defective address of the defective memory cell is set in the fuse signals FS0 to FS5, the fuse signal FS7 is set to the “H” level, and the voltage level of the word line WL is made lower than the normal voltage. . As a result, the transistors NT3 and NT4, which are access transistors, are supplied with a voltage lower than normal, so that the influence of the potential level of the electrically connected bit line BL and the complementary bit line / BL is suppressed. Inversion of the potentials of the storage nodes nd1 and nd2 can be suppressed. That is, a defective memory cell having a low SNM can be relieved.

Next, the SA test at the time of data reading will be described.
As described above, during the test, the test signal TE (“H” level) is input. The test mode circuit 82 of the address comparison circuit 80 sets the control signal HT # to the “H” level when the test signal TE (“H” level) is input. Therefore, as described above, control signal HT # (“H” level) is input to signal generation circuit 83 regardless of the comparison result of comparison unit 81.

  The signal generation circuit 83 outputs the control signals WLDWN, WLUP, and VDDWN according to the input of the fuse signals FS6 to FS8 that are input in response to the input of the control signal HT # (“H” level).

  In the SA test, fuse signal FS6 is set to the “H” level. Other fuse signals FS7 and FS8 are set to "L" level.

  In response to this, the signal generation circuit 83 activates the control signal WLDWN to the “L” level.

  As described above, the row decoder 20 and the column decoder 30 perform a row and column selection operation based on the input address signal.

  In this example, the word line voltage supply circuit 70 turns on the transistor 72 in response to the input of the control signal WLDWN (“L” level). Therefore, the voltage at the node N2 is further lowered from the normal voltage by a predetermined voltage.

  Therefore, a word line voltage that is further lower than the normal voltage by a predetermined voltage is supplied to the selected word line WL.

  The transistors NT3 and NT4, which are access transistors of the selected memory cell, are supplied with a voltage that is lower than the normal voltage by a predetermined voltage. Therefore, the electrically connected bit line BL and complementary bit line / BL If a potential difference according to the potentials of storage nodes nd1 and nd2 is not transmitted during this period, a data read failure in sense amplifier 120 may occur.

  Then, by comparing the data read from the sense amplifier 120 with the data written in advance, if it is inverted, it is determined that there is a data read failure, and the defective address of the defective memory cell and the defective memory cell The defect information is registered by a fuse signal. Specifically, the defective address of the defective memory cell is set in fuse signals FS0 to FS5, and fuse signal FS7 is set to "H" level.

  More specifically, the defective address of the defective memory cell is set in the fuse signals FS0 to FS5, and the fuse signal FS7 is set to the “H” level so that the voltage level of the word line WL is higher than the normal voltage. . As a result, a higher voltage than normal is supplied to the transistors NT3 and NT4 which are access transistors, so that the potential difference between the storage nodes nd1 and nd2 is sufficiently reflected in the potential difference between the bit line BL and the complementary bit line / BL. As a result, the amount of current flowing through the sense amplifier 120 can be increased to ensure an operation margin for the sense amplifier. That is, it becomes possible to relieve a defective memory cell having a lower operation margin than the sense amplifier SA.

Next, a writing test at the time of data writing will be described.
As described above, during the test, the test signal TE (“H” level) is input. The test mode circuit 82 of the address comparison circuit 80 sets the control signal HT # to the “H” level when the test signal TE (“H” level) is input. Therefore, as described above, control signal HT # (“H” level) is input to signal generation circuit 83 regardless of the comparison result of comparison unit 81.

  The signal generation circuit 83 outputs the control signals WLDWN, WLUP, and VDDWN according to the input of the fuse signals FS6 to FS8 that are input in response to the input of the control signal HT # (“H” level).

  Here, in the write test, all the fuse signals FS6 to FS8 are set to the “L” level.

  Therefore, all the signal generation circuits 83 are at “H” level, and voltage adjustment is not executed.

  As described above, the row decoder 20 and the column decoder 30 perform a row and column selection operation based on the input address signal.

  In this state, the bit line BL and the complementary bit line / BL are driven from the write driver 110 at a voltage level corresponding to the write data WDT, and data can be written to the selected memory cell. Test for it. Specifically, a test for writing data opposite to the stored data is performed.

  Data writing cannot be executed for memory cells having low data writing characteristics. On the other hand, data writing can be executed for memory cells having high data writing characteristics.

  Then, after executing the data write, if the data read is executed and the data read from the sense amplifier 120 is compared with the written data, the data write is normal. If not, the data writing is bad.

  Therefore, for the memory cell in which the above test is executed and data writing is determined to be defective, the defect address of the defective memory cell and the defect information of the defective memory cell are registered by the fuse signal. Specifically, the defective address of the defective memory cell is set in fuse signals FS0 to FS5, and fuse signal FS8 is set to the “H” level.

  By setting the fuse signal FS8 to the “H” level, the voltage level of the power supply line ARVDD is made lower than the normal voltage.

  As a result, as the operating voltage of the memory cell is lowered, the data retention characteristic is lowered, so that data can be easily written, and a defective memory cell having a low data writing characteristic can be relieved.

Another writing test will be described.
In another write test, fuse signal FS6 is set to "H" level. Other fuse signals FS7 and FS8 are set to "L" level.

  In response to this, the signal generation circuit 83 activates the control signal WLDWN to the “L” level.

  As described above, the row decoder 20 and the column decoder 30 perform a row and column selection operation based on the input address signal.

  In this example, the word line voltage supply circuit 70 turns on the transistor 72 in response to the input of the control signal WLDWN (“L” level). Therefore, the voltage at the node N2 is further lowered from the normal voltage by a predetermined voltage.

  Therefore, a word line voltage that is further lower than the normal voltage by a predetermined voltage is supplied to the selected word line WL.

  In this state, the bit line BL and the complementary bit line / BL are driven from the write driver 110 at a voltage level corresponding to the write data WDT, and data can be written to the selected memory cell. Test for it. Specifically, a test for writing data opposite to the stored data is performed.

  Since the selected word line WL is supplied with a word line voltage that is further lower than the normal voltage by a predetermined voltage, data writing cannot be executed for a memory cell having low data writing characteristics. On the other hand, data writing can be executed for memory cells having high data writing characteristics.

  Then, after executing the data write, if the data read is executed and the data read from the sense amplifier 120 is compared with the written data, the data write is normal. If not, the data writing is bad.

  Therefore, for the memory cell in which the above test is executed and data writing is determined to be defective, the defect address of the defective memory cell and the defect information of the defective memory cell are registered by the fuse signal. Specifically, the defective address of the defective memory cell is set in fuse signals FS0 to FS5, and fuse signal FS7 is set to "H" level.

  By setting the fuse signal FS7 to the “H” level, the voltage level of the word line WL is made higher than the normal voltage.

  As a result, a higher voltage than usual is supplied to the transistors NT3 and NT4 which are access transistors, so that data can be easily written to the storage nodes nd1 and nd2, and a defective memory cell having low data writing characteristics is relieved. It becomes possible to do.

FIG. 10 is a timing chart illustrating the test mode.
Here, a case will be described in which an access for determining a defective memory cell is executed in the test mode. It is assumed that fuse signals FS0 to FS5 are all set to “L” level. It is assumed that fuse signal FS6 is set to “H” level.

Therefore, the above-described SA test is executed during the test.
First, at time T15, the test signal TE is set to the “H” level.

  The signal generation circuit 83 activates the control signal WLDWN to “L” level based on the test signal TE and the fuse signal FS6 at time T16.

  As described above, the row decoder 20 and the column decoder 30 perform a row and column selection operation based on the input address signal.

  In this example, the word line voltage supply circuit 70 turns on the transistor 72 in response to the input of the control signal WLDWN (“L” level). Therefore, at time T17, the voltage at the node N2 is further lowered from the normal voltage by a predetermined voltage.

  Therefore, a word line voltage that is further lower than the normal voltage by a predetermined voltage is supplied to the selected word line WL.

In this state, the above-described SA test is executed.
Specifically, by comparing the data read from the sense amplifier 120 with the data that has been written in advance, if it is inverted, it is determined that there is a data read failure, the defective address of the defective memory cell, The defect information of the defective memory cell is registered by a fuse signal. Specifically, the defective address of the defective memory cell is set in fuse signals FS0 to FS5, and fuse signal FS7 is set to "H" level.

  By setting the fuse signal FS7 to the “H” level, the voltage level of the word line WL is made higher than the normal voltage.

  As a result, a higher voltage than normal is supplied to the transistors NT3 and NT4 which are access transistors, so that the potential difference between the storage nodes nd1 and nd2 is sufficiently reflected in the potential difference between the bit line BL and the complementary bit line / BL. Thus, it is possible to secure an operation margin of the sense amplifier 120. That is, a defective memory cell having a low operation margin of the sense amplifier SA can be repaired.

  That is, by the method according to the second embodiment of the present invention, it is possible to easily test a defective memory cell in the test mode.

  The above test can be executed one bit at a time by accessing one memory cell, or a plurality of bits can be tested in parallel by providing a plurality of sense amplifiers and a plurality of write drivers. Is also possible.

  In addition, the configuration of registering the defective address signal and defect information of one defective memory cell in the address comparison circuit 80 has been described. However, the present invention is not limited to this. It is possible to rescue the memory cell.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram of a semiconductor memory device 1 according to a first embodiment of the present invention. It is a diagram illustrating a configuration of a memory cell MC according to the first embodiment of the present invention. It is a diagram illustrating a configuration of a column selection gate GS constituting column selection switch 130 according to the first embodiment of the present invention. It is a diagram illustrating an internal configuration of an address comparison circuit 80 according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a part of the configuration of a word line voltage supply circuit 70 and a word line driver 60 according to the first embodiment of the present invention. It is a figure explaining a part of structure of the voltage supply circuit band 100 according to Embodiment 1 of this invention. It is a timing chart explaining Example 1 of a normal operation mode. It is a timing chart figure explaining example 2 of a normal operation mode. It is a timing chart figure explaining example 3 of a normal operation mode. It is a timing chart figure explaining test mode.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 Test pin, 3 Fuse signal terminal, 4 Address terminal, 5, 6 Control terminal, 7 Clock terminal, 8 Data input terminal, 9 Data output terminal, 10 Address buffer, 15 Memory array, 20 Row decoder, 30 column decoder, 40 CE buffer, 50 read / write buffer, 60 word line driver, 70 word line voltage supply circuit, 80 address comparison circuit, 90 input / output buffer, 100 voltage supply circuit band, 110 write driver, 120 sense Amplifier, 130 column selection switch, 150 control circuit.

Claims (5)

A plurality of memory cells arranged in a matrix;
A plurality of word lines provided corresponding to the memory cell rows, and
A plurality of bit lines respectively corresponding to the memory cell columns;
A selection circuit for setting one of the plurality of word lines to an activated state based on a row selection signal according to an address signal input from the outside;
An address comparison circuit including a comparison unit that compares an address signal from the outside with a defective address signal of a preset defective memory cell;
Each of the memory cells
A flip-flop circuit for setting the first and second storage nodes to one and the other of the first and second potential levels, respectively, according to the data to be stored;
A corresponding word line and a gate are electrically coupled, and an access transistor for electrically coupling between the corresponding bit line and the flip-flop circuit,
The address comparison circuit further includes a signal generation unit that outputs an instruction signal instructing adjustment of a voltage of a word line based on a comparison result of the comparison unit,
A semiconductor memory device further comprising a word line voltage supply circuit for adjusting a voltage supplied to the word line in response to the instruction signal during data writing.   The signal generation unit raises or lowers the voltage of the word line by a predetermined voltage or higher than the voltage used during normal time based on the comparison result of the comparison unit and the defect information of the memory cell determined to be defective. 2. The semiconductor memory device according to claim 1, wherein either one of a first instruction signal and a second instruction signal to be instructed is output. The comparison unit outputs a coincidence signal as a comparison result when the external address signal coincides with the defective address signal,
The defect information of the memory cell is given as one of the first and second fixed signals according to the characteristics of the defective memory cell,
The semiconductor memory device according to claim 2, wherein the signal generation unit outputs one of the first and second instruction signals based on the coincidence signal and the one fixed signal. A plurality of memory cells arranged in a matrix;
A plurality of word lines provided corresponding to the memory cell rows, and
A plurality of bit lines respectively corresponding to the memory cell columns;
A plurality of power supply lines provided corresponding to the respective memory cell columns and connected to the power supply nodes of the corresponding memory cells to supply a power supply voltage;
A selection circuit that selects one of the plurality of bit lines based on a column selection signal according to an address signal input from the outside;
A plurality of voltage supply units provided corresponding to the plurality of power supply lines, respectively, for supplying the power supply voltage to the corresponding power supply lines;
An address comparison circuit including a comparison unit that compares the external address signal and a preset defective address signal of a defective memory cell;
Each of the memory cells
A flip-flop circuit for setting the first and second storage nodes to one and the other of the first and second potential levels, respectively, according to the data to be stored;
A corresponding word line and a gate are electrically coupled, and an access transistor for electrically coupling between the corresponding bit line and the flip-flop circuit,
The address comparison circuit further includes a signal generation unit that outputs the instruction signal instructing adjustment of the power supply voltage based on a comparison result of the comparison unit,
Each of the voltage supply units includes a regulation circuit that regulates the power supply voltage based on the instruction signal and the column selection signal.   The instruction signal that instructs the signal generator to lower the power supply voltage by a predetermined voltage from a voltage that is normally used based on a comparison result of the comparator and defect information of the memory cell determined to be defective. The semiconductor memory device according to claim 4, wherein

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