JP2010231853A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimally adjust the faulty operating margin depending on the memory cell characteristics in a static semiconductor memory. <P>SOLUTION: The driver power source voltage selector circuit (VSWi) is set up for each word line driver (WDRi). This driver power source voltage selector circuit (VSWi) is stored in the circuits (32a, 32b) storing the memory cell specific information. One of the voltages (VDD1, VDD2, VDD3) is chosen according to the stored data and transmitted to the driver power node 12. Thus, countermeasures are taken against faulty read-out margins and write-in margins depending on the memory cell characteristics in this voltage selection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration of a static semiconductor memory device capable of stably writing / reading data.

  As transistor elements become finer, the influence of manufacturing parameter fluctuations increases, and variations in threshold voltages of MOS transistors (insulated gate field effect transistors) constituting memory cells increase, resulting in a reduction in operating margin. . As a result, it becomes difficult to perform stable data writing / reading in a semiconductor memory device, particularly a semiconductor memory device that operates at a low power supply voltage.

  A memory cell of a static semiconductor memory device (hereinafter referred to as SRAM) includes a flip-flop circuit configured by an inverter latch and an access transistor that accesses data held by the flip-flop circuit. In the following description, these two inverters and one access transistor are defined as half-cell inverters. Complementary data is held in two storage nodes by two half-cell inverters. The stability of the SRAM cell is evaluated by the transfer characteristic curves of the two half cell inverters. The transfer characteristic curve of this half-cell inverter is usually represented by two symmetrical curves of “glasses” shape. The length of one side of the square inscribed in the area surrounded by the two curves or the diameter of the inscribed circle is usually referred to as a static noise margin SNM. When the static noise margin SNM is large, the stability of the stored data is increased. On the other hand, when the static noise margin SNM is small, the stability of the stored data is decreased. This static noise margin is defined for each of the two storage nodes by two half-cell inverters.

  When the threshold voltage of the memory cell transistor varies due to process variation or the like, the transfer characteristic of the half cell inverter changes and the value of the static noise margin SNM also varies. When this threshold voltage variation is a global variation, and the threshold voltages of the memory cell transistors on the chip all vary similarly, the symmetry of the transfer characteristic curve is preserved. On the other hand, when the variation in the threshold voltage is random, the magnitude and / or sign of the change in the threshold voltage may be different in the memol cells on the same chip. In this case, the transfer characteristic curve becomes asymmetric and the static noise margin is greatly reduced. When the variation in threshold voltage further increases, the intersection of the transfer characteristic curves of the two half-cell inverters becomes one, that is, one of the static noise margins disappears, read stability failure occurs, and data can be held stably. become unable.

  The variation of the static noise margin has a small negative correlation that when one static noise margin increases, the other static noise margin decreases. This data error rate is approximated with a probability that it is outside of Zσ in a normal distribution. Here, σ is a standard deviation, and Zσ is represented by the difference between the total number of samples and the average value. Z is a random variable that follows a standard normal distribution with mean 0 and variance 1.

  The feature of failure due to such random variations in transfer characteristics is that the probability (bit error rate) of defective bits (memory cells) increases, and not all memory cells become defective. Various configurations for stably writing / reading / holding data even under such circumstances have been proposed.

  Japanese Patent Laid-Open No. 2009-20957 discloses a word line power supply circuit that supplies a power supply voltage to a word line driver. In a word line power supply circuit, the word line driver power supply voltage is increased during writing and the word line driver power supply voltage is read during reading. The configuration to be lowered is shown. That is, in Patent Document 1, at the time of data reading, the gate voltage of the access transistor of the memory cell is lowered to reduce the current driving capability to ensure a static noise margin. At the time of data writing, the gate voltage of the access transistor of the memory cell is increased to increase the current driving capability, and the static noise margin is reduced to perform high-speed and stable writing.

  Patent Document 2 (Japanese Patent Laid-Open No. 2009-3983) has a configuration in which the word line driver power supply voltage is changed according to an address signal, and the memory cell power supply is changed for each column between writing and reading. Indicated. In the configuration disclosed in Patent Document 2, the word line driver power supply voltage is set according to whether the defective content of a defective memory cell is a read margin defect or a write margin defect. To detect this defective memory cell, a defective address is programmed, and when this defective address is designated, the word line driver power supply voltage is changed. In addition, the memory cell power supply voltage is set to lower the memory cell power supply voltage for the selected column at the time of data writing, thereby reducing the static noise margin and increasing the write margin. In addition, whether or not to adjust the memory array power supply voltage is specified based on the defective address of the memory cell.

  This patent document 2 identifies a defective memory cell, and adjusts the word line driver power supply voltage and the memory array power supply voltage according to the defective content of the defective memory cell, thereby preventing a write / read failure from occurring. I will try.

  Japanese Patent Laid-Open No. 2007-242124 shows a configuration in which the word line driver power supply voltage and the memory cell power supply voltage are adjusted in units of memory cell blocks. In Patent Document 3, the memory cell block is set to at least one word line unit or at least one bit line unit and bit unit.

  Also in this patent document 3, the word line driver power supply voltage and the memory cell power supply voltage are adjusted according to the operation cycle in units of blocks to increase the write and read margins. In addition, the operation power supply voltage is lowered to reduce power consumption and to ensure stable operation under the low power supply voltage.

  Japanese Patent Laid-Open No. 2006-85786 discloses a configuration in which the memory cell power supply voltage level is changed between writing and reading in units of memory cell columns. In Patent Document 4, a bit line and a memory cell power supply line are coupled by a capacitive element, and the bit line is precharged to a voltage level corresponding to the cell power supply voltage. The voltage of the memory cell power supply line in the selected column is lowered by capacitive coupling by the capacitive element.

JP 2009-20957 A JP 2009-3983 A JP 2007-242124 A JP 2006-85786 A

  In Patent Document 1, the word line driver power supply voltage is changed in accordance with a write mode instruction signal. Accordingly, a countermeasure against the write margin is taken over the entire address space of the SRAM, and the influence of this countermeasure is uniform on the memory cells in the entire address space. Therefore, conversely, this margin countermeasure may cause a problem that a bit (memory cell) in which a read margin defect increases is generated. For example, when data is written to the selected memory cell, the word line voltage of the selected memory cell is increased and the memory cell power supply voltage is decreased. In this state, the memory cells in the selected row and the non-selected column have a word line voltage at a high voltage level and a memory cell power supply voltage at a high power supply voltage level. Therefore, the read margin of the memory cell in the half-selected state of the selected row and non-selected column is deteriorated, and the stored data may be inverted in the worst state.

  In the configuration shown in Patent Document 2, the word line driver power supply voltage and the array power supply voltage are adjusted according to the address signal. The direction of this voltage adjustment is fixedly set by a fuse program. Accordingly, in this case, however, countermeasures against writing margin defects are taken for each word line. Therefore, when margin defects vary on this word line, the margin defect countermeasures assume the worst case. Need to be done. Therefore, when there is a memory cell with a low read margin on the defective word line, this memory cell may become a read margin defective cell.

  In addition, the defective address signal is stored, and the word line driver power supply voltage and the memory cell power supply voltage are selectively adjusted only when the defective address is accessed. In this case, the word line voltage adjustment unit and the memory cell power supply voltage adjustment unit are provided in common for all the memory cells, the relieving read area is defined as a limited area, and the operation margin defect relieving probability is low. There is a possibility.

  In the configuration disclosed in Patent Document 3, the word line selection voltage and the memory cell power supply voltage are adjusted in units of memory cell blocks, that is, in units of minimum word lines or bit lines. However, even in the configuration shown in Patent Document 3, voltage adjustment of the same magnitude is performed for all memory cells regardless of the position of the selected memory cell. A memory cell with a low insertion margin becomes a write margin defective cell, and conversely, a memory cell with a low read margin becomes a read margin defective cell due to a write margin countermeasure.

  In the configuration disclosed in Patent Document 4, the memory cell power supply voltage is adjusted by capacitive coupling. Further, even when write / read margin defects are distributed in the column direction, the same margin defect countermeasures are taken. Therefore, there is a possibility that a memory cell that causes a write / read margin failure occurs.

  Further, in the configurations of these Patent Documents 1 to 4, remedy measures are taken for only one of the write margin failure and the read margin failure. However, the memory cell characteristics vary locally in the memory cell array with miniaturization, and there are cases where memory cells having a read margin defect and a write margin defect coexist in the memory array. Further, even in the case of a memory cell having a defective read margin, the degree of the read margin defect is different for each memory cell and is not necessarily constant. In these cases, the configurations for remedying the margin defect are not considered at all in Patent Documents 1 to 4.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device capable of accurately relieving a write and read margin defective bit.

  Another object of the present invention is to provide a semiconductor device capable of surely taking measures against margin defects without inducing new defective cells.

  In one embodiment, a semiconductor device according to the present invention is arranged in a matrix, each of which is arranged corresponding to a plurality of memory cells storing information and each memory cell row, and a memory cell corresponding to each memory cell is arranged. A plurality of word lines connected to each other, a plurality of word line drivers provided corresponding to the word lines and driving the word lines of the addressed row to a selected state, each corresponding to at least one word line driver And a driver power supply setting circuit that transmits the driver power supply voltage to the driver power supply node of the corresponding word line driver. The driver power supply setting circuit selects a voltage to be transmitted to the corresponding word line driver according to the memory cell characteristic specifying information of the corresponding row, and transmits it to the driver power supply node of the corresponding word line driver. To do. The plurality of candidate voltages include voltages that act as countermeasures against failure modes having different aspects. Each word line driver transmits the voltage of the corresponding driver power supply node to the corresponding word line to drive the corresponding word line to the selected state.

  In another embodiment, a semiconductor device according to the present invention is arranged in a matrix and is arranged corresponding to each of a plurality of memory cells each storing information, and each memory cell row, and a memory corresponding to each memory cell. A plurality of word lines to which the cells are connected, and corresponding to each word line and each having a driver power supply node, and each corresponding to the corresponding word line is addressed when the corresponding word line is addressed A plurality of word line drivers that transmit the voltage of the driver power supply node to the corresponding word line and drive to the selected state, and the plurality of word line drivers are provided in common, and the voltage is applied to the driver power supply node of the word line driver. A drive power supply setting circuit for transmission.

  The driver power supply setting circuit is configured to select a voltage level transmitted to each word line driver according to memory cell characteristic specifying information and a given address signal, independently of the operation mode of the semiconductor device, from a plurality of different voltage levels. Is transmitted to the driver power supply node of the word line driver. This address signal includes row and column address signals.

  In yet another embodiment, a semiconductor device according to the present invention is arranged in a matrix, each having a cell power supply node, and storing a plurality of information at a voltage level corresponding to the voltage of the cell power supply node. A memory cell, a plurality of word lines arranged corresponding to each memory cell row, each of which is connected to a corresponding memory cell, and a memory cell arranged corresponding to each memory cell column and corresponding to each column A plurality of bit line pairs connected to each other, a plurality of memory power supply lines arranged corresponding to each memory cell column, each connected to a cell power supply node of a memory cell in the corresponding column, and each memory power line Correspondingly provided, a memory power setting circuit for transmitting a voltage to a corresponding memory power line is provided. This memory power setting circuit has a plurality of candidates of three or more candidates for the voltage transmitted to the corresponding power supply line in accordance with the characteristic specifying information of the memory cells in the corresponding column, the data write instruction, and the column selection signal generated according to the address signal. The voltage is selected and transmitted to the corresponding memory power line.

  The level of the voltage transmitted to the word line or the memory power supply line is set at least according to the characteristic specifying information of the memory cell. Therefore, a margin defect countermeasure can be applied to the memory cells in the limited address area according to the memory cell characteristics, and the influence of the margin defect countermeasure on other memory cells can be reduced. Thereby, the probability that an operation margin defect will occur can be reduced, and a semiconductor device that operates stably can be realized.

  In addition, by preparing three or more different voltages as candidate voltages, measures against failure modes having different modes can be implemented according to the characteristics of the memory cells.

1 schematically shows an entire configuration of a semiconductor device (SRAM) according to the present invention. FIG. It is a figure which shows roughly the address distribution of the operation | movement margin defect relief of the semiconductor device according to this invention. It is a figure which shows the relationship between the operation margin and frequency distribution in the semiconductor device according to this invention. It is a figure which shows the relationship between the operation margin of the semiconductor device according to this invention, and accumulation frequency. 1 schematically shows an entire configuration of an SRAM according to a first embodiment of the present invention. FIG. FIG. 6 is a diagram schematically showing a configuration of a memory cell shown in FIG. 5. FIG. 6 is a diagram showing a configuration of a word line drive circuit shown in FIG. 5. It is a figure which shows an example of a structure of the fuse shown in FIG. It is a figure which shows the structure of SRAM according to Embodiment 2 of this invention. FIG. 10 is a diagram showing a configuration of a word line drive circuit shown in FIG. 9. FIG. 11 is a diagram showing a list of relationships between fuse storage data and selected word line drive voltages of the word line driver shown in FIG. 10. FIG. 14 schematically shows an overall configuration of SRAM 10 according to the third embodiment of the present invention. It is a figure which shows the structure of the driver voltage selection circuit shown in FIG. It is a figure which shows schematically the structure of the voltage generator shown in FIG. FIG. 14 is a diagram schematically showing a configuration of a portion for generating scan data for the flip-flop shown in FIG. 13. It is a figure which shows roughly the structure of the word line driver voltage selection circuit of the modification of Embodiment 3 of this invention. It is a figure which shows roughly the whole structure of SRAM according to Embodiment 4 of this invention. FIG. 18 schematically shows a configuration of a driver power supply selection circuit shown in FIG. 17. It is a figure which shows roughly the whole structure of SRAM according to Embodiment 4 of this invention. FIG. 20 is a diagram schematically showing a configuration of a driver power supply selection circuit shown in FIG. 19. FIG. 21 is a diagram schematically showing a correspondence between a selected word line driver power supply voltage and an applied address in the driver power supply selection circuit shown in FIG. 20. It is a figure which shows roughly the whole structure of SRAM according to Embodiment 5 of this invention. FIG. 23 is a diagram showing a configuration of an array power supply circuit and a memory cell array shown in FIG. It is a figure which shows roughly the whole structure of SRAM according to Embodiment 6 of this invention. FIG. 25 is a diagram showing a configuration of an array power supply circuit and a memory cell array shown in FIG. 24. 1 schematically shows an entire configuration of a semiconductor device according to the present invention. FIG.

[Principle configuration of the present invention]
FIG. 1 schematically shows an entire configuration of a semiconductor device (SRAM: static type semiconductor memory device) according to the present invention. The SRAM according to the present invention may be used as a single chip as an individual device, or may be integrated on the same semiconductor chip as logic such as other processors. Therefore, in the following description, the term “semiconductor device” is used to refer to both a single SRAM and a device including a built-in SRAM as a macro. The term SRAM is used to refer to both a single memory device and a built-in memory.

  In FIG. 1, the SRAM includes a memory cell array 1 in which memory cells MC are arranged in a matrix. In this memory cell array 1, word lines WL are arranged corresponding to each row of memory cells MC, and bit line pairs BLP are arranged corresponding to each column of memory cells MC. Bit line pair BLP includes complementary bit lines BL and / BL. A memory power line VML is arranged corresponding to the memory cell column. As an example, the voltage level of H data stored in the memory cell MC is set according to the voltage on the memory power supply line VML. The memory power line VML may transmit a voltage defining the voltage level of L data of the storage data to the memory cell MC.

  In order to select a row of the memory cell array 1, a word line selection circuit 2, a word line drive circuit 4, and a row side cell characteristic specifying information storage / voltage setting circuit 3 are provided. The word line selection circuit 2 decodes the applied row address signal RA and generates a word line selection signal designating the word line. The row-side cell characteristic specifying information storage / voltage setting circuit 3 stores information (cell characteristic specifying information) indicating the operation margin state of each memory cell in the memory cell array 1 or for each memory cell row. The row side cell characteristic specifying information storage / voltage setting circuit 3 sets the driver power supply voltage level transmitted to the word line driver included in the word line drive circuit 4 in accordance with the stored information.

  The word line drive circuit 4 applies the set voltage to the word line of the selected row according to the word line selection signal from the word line selection circuit 2 and the driver power supply voltage from the row side cell characteristic specifying information storage / voltage setting circuit 3. Transmit to drive the word line to the selected state. The voltage level of the word line of the selected row is adjusted according to the memory cell characteristics.

  In order to select a memory cell column, a column selection circuit 5 is provided, and column side cell characteristic specifying information storage / setting for setting a voltage transmitted to the memory power supply line VML in accordance with memory cell characteristic specifying information in units of memory cells or columns. A voltage setting circuit 6 and an array power supply circuit 7 for transmitting a memory power supply voltage onto the memory power supply line VML are included.

  Column selection circuit 5 selects bit line pair BLP arranged for the selected column in accordance with column address signal CA. Therefore, column selection circuit 5 selects a selected column as an internal data line (write data line and read data line) in accordance with a column decode circuit for decoding column address signal CA and a column selection signal from the column decode circuit. Including gate.

  Array power supply circuit 7 transmits the voltage set by column side cell characteristic specifying information storing / voltage setting circuit 6 to the array power supply line of the corresponding selected column when write mode instruction signal WE is activated, and the write mode When instruction signal WE is inactive, that is, at the time of standby and data reading, array power supply circuit 7 transmits an array power supply voltage (VDD) at a predetermined level.

  The cell characteristic specifying information stored in the cell characteristic specifying information storage / voltage setting circuits 3 and 6 is a memory cell unit, a memory cell row unit or a memory cell column unit. Therefore, the voltage level of the selected word line or the voltage of the array power supply line can be set in accordance with the operation margin of the memory cell, and the address region where the countermeasure against the operation margin is taken can be limited. This operation margin includes a data write margin, a data read margin, and a data stability holding margin.

  FIG. 2 is a diagram schematically showing the existence area of the operation margin defect bit in the entire address space of the SRAM and the range affected by the margin defect countermeasure. Now, in all address spaces AAR, countermeasures against margin failures are taken for read stability failure (read margin failure) S and write margin failure W, respectively. In this case, since measures are taken in units of memory cells or memory cells / rows / columns in accordance with the memory cell characteristic specifying information, the region WMR in which the measures against the write margin defect act is the write margin in the entire address space AAR. It is localized only in the very peripheral area of the address area where the defective bit W exists. Further, the read margin defect countermeasure for the read stability defect bit S is taken only for the address regions RMRa and RMRb in the vicinity thereof. Therefore, in the entire address space AAR, the operation margin defect countermeasure is applied only to the area where the defect countermeasure is required, and the influence of the margin defect countermeasure on other margin normal memory cells is suppressed. Therefore, the area where the countermeasure against the write margin defect and / or the read margin defect affects the other memory cells is limited, and the probability that the normal memory cell becomes a defective memory cell can be reduced by the defect countermeasure. it can.

  FIG. 3 is a diagram showing the frequency distribution of the operation margin of the memory cell. In FIG. 3, the horizontal axis indicates the operation margin, and the vertical axis indicates the frequency of the memory cell. A curve I1 indicated by a solid line shows the distribution of the operation margin when the margin defect countermeasure is not implemented for the SRAM, and a curve I2 indicated by the dotted line is an operation of the application region when the margin defect countermeasure is partially applied according to the present invention. The frequency distribution of the margin is shown. A curve I3 indicated by an alternate long and short dash line shows a frequency distribution of the operation margin when applied to the whole in the SRAM according to the present invention. A curved line I4 indicated by a broken line shows a frequency distribution when a common operation margin defect countermeasure is collectively applied to all address spaces.

  As shown by the curve I4, when the same countermeasure for the operation margin failure is applied to all the memory cells, the frequency distribution (curve I1) when the countermeasure is not implemented is shifted in the margin failure direction, and the operation margin of all the memory cells is small. Become. As a result, a normal bit may be transformed into a defective bit (operation margin is 0 or less).

  On the other hand, as shown by the curve I2, in the case of partial application, only the operation margin of the region applied only partially shifts, and the operation margin of the memory cell in the non-implemented region does not change. Accordingly, the number of memory cells to which the operation margin is shifted is small, and when viewed as a whole, as shown by the curve I3, the change from the original power distribution curve I1 is very slight, and the memory cell in which the operation margin is reduced. The increase in number is negligible.

  FIG. 4 is a diagram showing the frequency distribution of the operation margin shown in FIG. 3 as a logarithmic cumulative frequency distribution. The horizontal axis indicates the operation margin, and the vertical axis indicates the cumulative frequency. Here, “E” indicates a floating-point display and indicates a power of 10.

  In FIG. 4, a curved line I5 indicated by a solid line indicates the cumulative frequency distribution of the operation margin when the failure countermeasure for the SRAM is not implemented, and a curve I6 indicated by the dotted line indicates a case where the countermeasure against the operation margin failure is partially applied according to the present invention. The cumulative frequency distribution of is shown. A curve I7 indicated by an alternate long and short dash line represents a cumulative frequency distribution of the entire operation margin when the operation margin failure countermeasure is taken according to the present invention. A curved line I8 indicated by a broken line shows a cumulative frequency distribution when a common defect countermeasure is applied to the whole.

In FIG. 4, from the comparison of the curves I5 and I8, the number of memory cells (bits) in which the operation margin is reduced increases when applied to all the memory cells for common operation margin defect countermeasures. On the other hand, as shown by a curve I6, as the number of memory cells to which an operation margin failure countermeasure is applied in the present invention, an operation margin failure countermeasure is taken for memory cells on the order of 10 ⁻³ . Therefore, the cumulative frequency of the operating margin as a whole is only slightly increased from the cumulative frequency distribution in which countermeasures have not been taken, as shown by the curve I7, and the effect is almost negligible. (It only increases from the order of 10 ^{−7 to} the order of 10 ⁻⁶ , and the degree of the increase is almost negligible.

  Accordingly, implementations of the invention include the following features. The smaller the area where the operation margin countermeasure is applied, the smaller the increase in the influence of this countermeasure against the defect can be made. Therefore, margin defective bits can be reduced and the yield is improved. Moreover, since the area where the countermeasure against the defect affects is limited, a more effective countermeasure (a large action) can be taken. In addition, an increase in area can be suppressed as compared with the case where a defective cell is replaced using a redundant decoder. In other words, according to the memory cell characteristic specifying information, the operation margin defect cell can be repaired selectively only to the memory cell to be subjected to this defect countermeasure, and the operation margin defect cell can be relieved and transferred to another memory cell. Thus, an SRAM that operates accurately and stably can be realized. In particular, when memory cell characteristics vary and read margin defective cells and write margin defective cells coexist, adaptive and flexible defect countermeasures according to the defect contents can be taken according to the memory cell characteristic specifying information.

[Embodiment 1]
FIG. 5 schematically shows a whole structure of the SRAM according to the first embodiment of the present invention. 5, SRAM 10 includes a memory cell array MCA in which memory cells MC are arranged in a matrix. The memory cell array MCA corresponds to the memory cell array 1 shown in FIG. 1, and memory cells MC are arranged in (n + 1) rows and (m + 1) columns.

  Corresponding to each row of memory cells MC, word lines WL0 to WLn are provided, and memory cells MC (access transistors) in the corresponding row are coupled to word lines WL0 to WLn. Bit line pairs BL0, / BL0-BLm, / BLm are provided corresponding to the respective columns of memory cells MC. Memory cell MC is a static memory cell, and complementary data is transmitted to a pair of complementary bit lines BL (BL0-BLm), / BL (BL0-BLm).

  A bit line load (BL load) BLL is provided corresponding to each of the bit lines BL, / BL. Bit line load BLL pulls up a corresponding bit line voltage and supplies a column current to corresponding bit lines BL and / BL during memory cell data reading.

  SRAM 10 is further arranged corresponding to a row decoder RD for generating row selection signals WLEN0 to WLENn according to internal row address signal RA and a selected row of memory cell array MCA according to row selection signals WLEN0 to WLENn from row decoder RD. A word line drive circuit WDC for driving the word line WL to be selected to a selected state is included.

  Row decoder RD corresponds to word line selection circuit 2 shown in FIG. It operates by receiving power supply voltage VDD from VDD as an operation power supply voltage, and decodes internal row address signal RA to generate row selection signals WDN0 to WDNn. A row selection signal corresponding to a row designated by internal row address signal RA is driven to a selected state, and the remaining row selection signals are maintained in a non-selected state.

  The row decoder RD may have a configuration for decoding the internal row address signal RA and decoding the predecode signal. External power supply EXT. The internal power supply voltage VDD from VDD may be the same voltage level as the external power supply voltage, or may be a voltage level different from the external power supply voltage.

  Word line drive circuit WDC corresponds to word line drive circuit 4 shown in FIG. 1, and includes word line drivers WDR0 to WDRn provided corresponding to word lines WL0 to WLn, respectively. Word line drivers WDR0-WDRn receive the voltage applied to driver power supply node 12 as an operation power supply voltage, and drive corresponding word lines WL to a selected state in accordance with row selection signals WLEN0-WLENn from row decoder RD. That is, each of word line drivers WDR0-WDRn transmits the voltage applied to driver power supply node 12 to the corresponding word line when selecting the corresponding word line. Therefore, the voltage of the selected word line becomes the voltage level applied to driver power supply node 12.

  The voltage from the driver voltage supply circuit WSC is supplied to the driver power supply node 12 of each of these word line drivers WDR0 to WDRn. The driver voltage supply circuit WSC corresponds to the row side cell characteristic specifying information storage / voltage setting circuit 3 shown in FIG. 1, and is provided inside the driver power supply voltage setting circuits DVS0 to DVSn provided corresponding to the word line drivers WDR0 to WDRn. The voltage levels applied to the corresponding word line drivers WDR0 to WDRn are set according to the cell characteristic specifying information stored in the internal program elements. Therefore, the voltage level of the selected word line can be adjusted in units of rows. The configuration of driver power supply voltage setting circuits DVS0 to DVSn will be described in detail later.

  SRAM 10 further corresponds to a column selection circuit SC for selecting complementary bit line pair BL, / BL corresponding to the selected column in accordance with internal column address signal CA, and to a column selected by column selection circuit SC during data writing. Write circuit WC for transmitting write data to bit line pair BL, / BL to be detected, and at the time of data reading, data from bit line pair BL, / BL corresponding to the column selected by column selection circuit SC is detected. A read circuit RC that amplifies and generates read data is included. Column selection circuit SC corresponds to column selection circuit 5 shown in FIG. 1, and includes a column decode circuit for decoding internal column address signal CA and a column selection gate for selecting a bit line pair in accordance with a column selection signal from this column decode circuit. including.

  Write circuit WC includes an input buffer and a write drive circuit (not shown), generates internal write data according to external write data DI in the data write mode, and internally writes to the bit line pair of the selected column. Communicate data. Read circuit RC includes a sense amplifier circuit and an output buffer (not shown). In the data read mode, data detected and amplified by the sense amplifier circuit is buffered by the output buffer to generate external read data DO. The operations of these write circuit WC and read circuit RC are controlled by the main control circuit CC. Main control circuit CC receives internal row address signal RA, internal column address signal CA and the designated address signal AD, write mode instruction signal WE, read mode instruction signal RE and chip enable signal CE, respectively. Control signals necessary for operation are generated.

  An array power supply circuit ASC is further provided for the memory cell array MCA. The array power supply circuit ASC corresponds to the array power supply circuit 7 shown in FIG. 1, and supplies the array power supply voltage to the high-side power supply node and low-side power supply node of the memory cell MC via the cell power supply line PVL. The voltages supplied to the high-side power supply node and the low-side power supply node of the memory cell are the power supply voltage and the reference voltage (ground voltage) of the memory cell MC, respectively. In FIG. 5, in order to simplify the drawing, the power supply voltage (VDD) and the reference voltage (VSS) are shown to be supplied by a single line.

  In the first embodiment, array power supply circuit ASC supplies an array power supply voltage (high-side power supply voltage) in common to memory cells MC in memory cell array MCA via cell power supply line PVL. Therefore, in the first embodiment, the column side cell characteristic specifying information storage / voltage setting circuit 6 shown in FIG. 1 is not provided. Note that the cell power line PVL corresponds to the array power line VML shown in FIG.

  FIG. 6 is a diagram showing an example of the configuration of the memory cell MC shown in FIG. In FIG. 2, the memory cell MC is formed of a full CMOS single port SRAM cell. That is, memory cell MC includes two CMOS inverters IV1 and IV2 that are cross-coupled. One inverter IV1 includes a P channel MOS transistor (load transistor) PQ1 and an N channel MOS transistor NQ1 (drive transistor). P-channel MOS transistor PQ1 is connected between high-side power supply node VH and storage node ND1, and has its gate connected to storage node ND2. N-channel MOS transistor NQ1 is connected between storage node ND1 and low-side power supply node VL, and has its gate connected to storage node ND2.

  Inverter IV2 includes a P channel MOS transistor (load transistor) PQ2 and an N channel MOS transistor (drive transistor) NQ2. P channel MOS transistor PQ2 is connected between high-side power supply node VH and storage node ND2, and has its gate connected to storage node ND1. N-channel MOS transistor NQ2 is connected between storage node ND2 and low-side power supply voltage VL, and has its gate connected to storage node ND1. The inputs and outputs of these inverters IV1 and IV2 are cross-coupled to form an inverter latch (flip-flop circuit). Therefore, the storage nodes ND1 and ND2 hold complementary data. The voltage level of data stored in storage nodes ND1 and ND2 is set by the voltage levels of high side power supply node VH and low side power supply node VL.

  Memory cell MC further includes N channel MOS transistors (access transistors) NQ3 and NQ4 coupling storage nodes ND1 and ND2 to bit lines BL and / BL, respectively, according to the voltage on word line WL. The word line WL is any one of the word lines WL0 to WLn shown in FIG. 5, and the bit lines BL and / BL are each one of the bit lines BL0 to BLn and / BL0 − / BLn shown in FIG. .

  FIG. 7 is a diagram showing an example of the configuration of the word line driver and driver power supply voltage setting circuit shown in FIG. FIG. 7 representatively shows word line drivers WDRi and WDRi + 1 and driver power supply voltage setting circuits DVSi and DVSi + 1 provided corresponding to word lines WLi and WLi + 1, respectively.

  Since word line drivers WDRi and WDR (i + 1) have the same configuration, the same reference numerals are assigned to the components of word line drivers WDRi and WDR (i + 1) in FIG. Each of word line drivers WDRi and WDR (i + 1) includes a P channel MOS transistor PT0 and an N channel MOS transistor NT0. P channel MOS transistor PT0 has its back gate and source coupled to driver power supply node 12. Word line driver WDRi receives word line selection signal WLENi at the gates of MOS transistors PS0 and NT0, and word line driver WDR (i + 1) receives word line selection signal WLEN (i + 1) at the gates of MOS transistors PT0 and NT0. Therefore, word lines WLi and WLi + 1 transmit a signal obtained by inverting word line selection signals WLENi and WLEN (i + 1) as a word line selection signal.

  Since driver power supply voltage setting circuits DVSi and DVS (i + 1) also have the same configuration, the same reference numerals are assigned to the components of driver power supply setting circuits DVSi and DVS (i + 1). Each of driver power supply voltage setting circuits DVSi and DVS (i + 1) includes a resistance element ZR and N channel MOS transistors NT1 and RAT. Resistance element ZR is connected between power supply node VDD and driver power supply node 12. Here, the node and the voltage thereon are indicated by the same reference numerals. MOS transistors NT1 and RAT are connected in series between driver power supply node 12 and a reference potential node (hereinafter referred to as a ground node).

  N-channel MOS transistor (replica access transistor) RAT is a replica transistor of access transistors NQ3 and NQ4 included in memory cell MC, and unit replica in which the sizes of access transistors NQ3 and NQ4 and the gate insulating film are proportionally reduced at the same rate. It consists of a parallel body of access transistors. That is, the replica access transistor RAT is composed of N unit replica access transistors connected in parallel. Replica access transistor RAT has its gate connected to the power supply node, and functions as a resistance element.

  MOS transistor NT1 has its on / off state set according to the information programmed by fuse FZ. In fuse FZ, information for specifying the operation margin of the memory cell in the corresponding row, that is, memory cell characteristic specifying information is stored. After the SRAM manufacturing process, the write margin and read margin of the memory cell are specified. As an example, information output at H level is stored in the fuse FZ for a row of memory cells having a low write margin, and the output signal of the fuse FZ is set to L level for a memory cell row having no write margin defect. Set to. In the fuse FZ, information for specifying a read margin may be programmed.

  When the output signal of fuse FZ is at L level, MOS transistor NT1 is in an off state, and internal power supply voltage VDD is transmitted to driver power supply node 12. On the other hand, when the output signal of fuse FZ is at the H level, MOS transistor NT1 is turned on, and voltage corresponding to the ratio of the parallel combined on-resistance of resistance element ZR and replica access transistor RAT is transmitted to driver power supply node 12. The This voltage has a voltage level lower than the internal power supply voltage VDD.

  By setting the voltage level of the selected word line to a voltage level lower than internal power supply voltage VDD, read stability of memory cell MC is improved, and read (stability) margin failure is improved. Therefore, the read stability margin countermeasure for the memory cell acts only on the word line corresponding to the fuse whose output signal is programmed to the H level, and the read stability defect countermeasure is applied to the remaining memory cell rows. Not. As a result, it is possible to take measures against the read stability margin failure only for the memory cells in the address region where the memory cell having the read stability margin failure exists, and prevent the margin failure from occurring in other margin normal memory cells. be able to.

  Note that the normal voltage level of the selected word line may be a divided voltage level, and the voltage level of the selected word line for the memory cell row having a poor margin may be set to an internal power supply voltage level higher than the divided voltage. In this case, the word line voltage for the memory cell having a defective write margin is increased to increase the write margin, thereby relieving the write margin defect. In this case, the fuse FZ is configured to generate an H level signal at the time of non-programming in the fuse FZ and output an L level signal at the time of programming.

  Here, the on-resistance of the MOS transistor NT1 may be sufficiently larger than the on-resistance of the MOS transistor RAT, and the on-resistance may be ignored. Alternatively, the voltage levels of the voltages VWLi and VWL (i + 1) of the driver power supply node 12 may be set by the series resistance of the on resistance of the MOS transistor NT1 and the on resistance of the MOS transistor RAT.

  FIG. 8 schematically shows an example of the configuration of fuse FZ shown in FIG. In FIG. 8, a fuse element FS and a high resistance element ZZ are connected in series between a high-side power supply node VDD and a low-side power supply node VSS. An output signal of the fuse FZ appears from the connection node 15 between the fuse element FS and the high resistance element ZZ. When the fuse element FS is blown, the output node 15 is held at the low-side power supply voltage VSS level by the high resistance element ZZ. On the other hand, when fuse FS is not blown, output node 15 is maintained at the H level. Note that fuse element FS may be connected to the ground node, and high resistance element ZZ may be coupled to power supply node VDD.

  In the configuration of the fuse FZ shown in FIG. 8, when the fuse element FS is not blown, a minute current flows from the high-side power supply node VDD to the low-side power supply node VSS. When taking measures against defective read stability margins, the word line selection voltage is lowered when the voltage at output node 15 is at the H level. Therefore, the number of non-blown fuse elements is small, and the leakage current of the entire fuse FZ can be almost ignored. However, in this case, a switching transistor that is selectively turned on in accordance with the word line selection signal WLENi may be provided between the fuse element FS and the output node 15. Only in the driver power supply voltage setting circuit corresponding to the selected row, the output signal of the fuse FZ is set to a voltage level corresponding to the fusing / non-blowing of the fuse element FS, and the output signal of the fuse FZ corresponding to the non-selected row is L Maintained at level.

  Further, the configuration of the fuse FZ shown in FIG. 8 is merely an example, and any configuration may be used as long as the word line voltage level for countermeasure against the failure is adjusted according to the target failure.

  As described above, according to the first embodiment of the present invention, the driver power supply voltage is set for each word line driver according to the characteristics (read stability failure margin or write failure margin) of the memory cell in the corresponding row. is doing. Therefore, margin countermeasures can be taken only for memory cells with defective operation margins such as read stability or write defects, and unnecessary measures need not be taken for memory cells with normal operating margins. As a result, it is possible to prevent a memory cell with a normal operation margin from becoming a defective operation margin cell, to reduce the number of defective bits, and to improve the yield.

[Embodiment 2]
FIG. 9 schematically shows an overall configuration of the SRAM according to the second embodiment of the present invention. The SRAM shown in FIG. 9 differs from the SRAM shown in FIG. 5 in the following points. That is, in the driver voltage supply circuit WSC, one driver power supply voltage setting circuit DVS is provided for each of a plurality of word line drivers. In the configuration shown in FIG. 9, one driver power supply voltage setting circuit is provided for a set of two word line drivers. Specifically, driver power supply voltage setting circuit DVS0 / 1 is provided for word line drivers WDR0 and WDR1, and driver power supply voltage setting circuit DVSn-1 / n is commonly used for word line drivers WDR (n-1) and WDRn. Is provided. The other configuration of the SRAM shown in FIG. 9 is the same as the configuration of the SRAM shown in FIG. 5, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Each of the driver power supply voltage setting circuits DVS0 / 1-DVSn / n + 1 includes a fuse therein, and generates three or more types of driver power supply voltages according to memory cell characteristic specifying information programmed in the fuse.

  FIG. 10 is a diagram showing the configuration of the driver power supply voltage setting circuit shown in FIG. 9 together with the configuration of the word line driver. In FIG. 10, driver power supply voltage setting circuit DVSi / i + 1 is provided in common to word line drivers WDRi and WDR (i + 1). The word line drivers WDRi and WDR (i + 1) have the same configuration as that of the word line driver shown in FIG. 7, and portions corresponding to those of the word line driver shown in FIG. Description is omitted.

  Power supply nodes 12 of word line drivers WDRi and WDR (i + 1) are commonly coupled to driver power supply voltage setting circuit DVSi / i + 1 through local driver power supply line LDVLi. The driver power supply voltage setting circuit DVSi / i + 1 is connected in series between a resistance element ZR provided between the high-side power supply node VDD and the local driver power supply line LDVLi, and between the local driver power supply line NDVLi and the low-side power supply node. N channel MOS transistors NT10 and RAT0, and N channel MOS transistors NT11 and RAT1 connected in series between local driver power supply line LDVLi and the low power supply node.

  MOS transistors (replica access transistors) RAT0 and RAT1 are each configured by a parallel body of unit replica access transistors of access transistors (NQ3, NQ4) included in memory cell MC. 0.5N pieces are connected in parallel. Therefore, the current driving capability of replica access transistor RAT0 is twice that of replica access transistor RAT1, and the on-resistance of replica access transistor RAT0 is ½ times the on-resistance of replica access transistor RAT1.

  Fuses FZ0 and FZ1 are provided for setting the on / off states of MOS transistors NT10 and NT11, respectively. According to the program data of fuses FZ0 and FZ1, a state in which 0, 0.5N, N, and 1.5N unit replica access transistors are connected in parallel to local driver power supply line LDVLi is realized. Therefore, the driver power supply voltage VWL on the local driver power supply line LDVLi can be set in four stages.

  FIG. 11 is a diagram showing a list of correspondence between driver power supply voltage VWL generated by driver power supply setting circuit DVSi / (i + 1) shown in FIG. 10 and stored information of fuses FZ0 and FZ1.

  In FIG. 11, when the output signals of fuses FZ0 and FZ1 are both at the L level, MOS transistors NT10 and NT11 are both in an off state, and driver power supply voltage VWL on local driver power supply line LDVLi is supplied to power supply voltage VDD by resistance element ZR. Maintained at level.

  When the output information (program information) of fuses FZ0 and FZ1 is L level and H level, respectively, MOS transistor NT10 is turned off and MOS transistor NT11 is turned on. In this state, replica access transistor RAT1 is connected to local driver power supply line LDVLi, and 0.5N unit replica access transistors (parallel RAT) are connected in parallel. In this case, the driver power supply voltage VWL on the local driver power supply line LDVLi is VDD · Ra / (0.5N · ZR + Ra). Here, Ra represents the on-resistance of the unit replica access transistor, and the parallel combined on-resistance of the replica access transistor RAT1 is Ra / 0.5N.

  When the output signals of fuses FZ0 and FZ1 are at the H level and the L level, respectively, MOS transistor NT10 is turned on and MOS transistor NT11 is turned off. In this case, replica access transistor RAT0 is connected to local driver power supply line LDVLi, and N unit replica access transistors are connected in parallel. The parallel combined on-resistance of the replica access transistor RAT0 is Ra / N. Therefore, in this case, the voltage VWL on the local driver power supply line LSVLi is VDD · Ra / (N · ZR + Ra).

  When the output signals of fuses FZ0 and FZ1 are both at H level, replica access transistors RAT0 and RAT1 are connected in parallel to local driver power supply line LDVLi, that is, a total of 1.5N unit replica access transistors are connected in parallel. The Therefore, in this case, the voltage VWL on the local driver power supply line LDVLi is VDD · Ra / (1.5N · ZR + Ra).

  Driver power supply voltage VWL decreases as the number of unit replica access transistors connected in parallel to local driver power supply line LDVLi increases. Therefore, the voltage level of this selected word line is set according to the read stability margin defect characteristic of the memory cells connected to word lines WLi and WLi + 1. Thereby, it is possible to more accurately relieve the read stability margin defective memory cell and perform accurate data reading and data holding. In addition, address areas where countermeasures against defects are limited are limited, and the occurrence of defective write margin cells can be suppressed by the countermeasures against the reading stability margin defects. In addition, it is possible to exert a strong countermeasure against reading stability margin failure, and it is possible to increase the repair probability of defective cells.

  When the word line voltage is switched depending on the level of the static noise margin SNM of the memory cell, the static noise margin is improved as the voltage of the selected word line is lowered, and the write margin is decreased. As a probability of measures against this read stability margin failure, the probability that 1.5N unit replica access transistors are connected in parallel is extremely small. Further, since 0.5N replica access transistors can be connected in parallel to perform defect remedy, the number of N unit replica access transistors connected in parallel can be reduced compared to the configuration of the first embodiment. Reduced. Therefore, the probability of avoiding a state in which the selected word line voltage is lowered more than necessary is increased, and the adverse effect of the read stability margin defect countermeasure on the write margin can be suppressed.

  In this case, one driver power supply voltage setting circuit is provided for a plurality of rows of word line drivers, and the area occupied by the driver power supply voltage setting circuit can be reduced.

  Further, the on / off states of replica access transistors RAT0 and RAT1 may be controlled according to the output signals of fuses FZ0 and FZ1. However, in this case, since the gate capacitance driven by the fuses FZ0 and FZ1 increases, it is necessary to increase the current driving force of the fuse.

  Alternatively, replica access transistors RAT0 and RAT1 may be configured to be turned on / off in accordance with a read mode instruction signal.

  Further, the voltage of the normal word line is set by, for example, 0.5N parallel connection of unit replica access transistors, the power supply voltage VDD is selected as a countermeasure against a write margin defect, and N as a countermeasure against a read stability margin defect. Alternatively, it may be realized by parallel connection of 0.5N unit replica access transistors. In this case, both the write margin defect and the read stability margin defect can be remedied.

[Embodiment 3]
FIG. 12 schematically shows a whole structure of the SRAM according to the third embodiment of the present invention. The SRAM 10 shown in FIG. 12 is different from the SRAM 10 shown in FIG. 9 in the following points. That is, in the driver voltage supply circuit WSC, driver power supply voltage selection circuits VSW0 to VSWn are provided corresponding to the word line drivers WDR0 to WDRn, respectively. The driver power supply voltage selection circuits VSW0 to VSWn include scan registers inside, and sequentially shift shift-in data SI input from the outside or from a dedicated register (not shown), so that the characteristics (operation margin) of the memory cells in the corresponding row ) To select the driver power supply voltage. The shift-out SO from the last scan register of the scan register string is also returned to the original dedicated register.

  As this driver power supply voltage, a plurality of types of voltages are supplied from the voltage generator 30 to the driver power supply voltage selection circuits VSW0 to VSWn. In FIG. 12, for simplification of the drawing, one voltage VD is generated from the voltage generator 30. However, the voltage generator 30 is a driver power supply voltage VD. Generate voltages with different voltage levels.

  The other configuration of the SRAM shown in FIG. 12 is the same as that of the SRAM shown in FIG. 9, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 13 shows an example of a structure of a driver power supply voltage selection circuit according to the third embodiment of the present invention. FIG. 13 representatively shows a configuration of driver power supply voltage selection circuit VSWi provided for word line driver WDRi. In FIG. 13, driver power supply voltage selection circuit VSWi includes two-stage flip-flops (FF) 32a and 32b, P-channel MOS transistors 36a-36c for selecting internal voltages VDD1-VDD3, respectively, and flip-flops 32a and 32b. And a NAND gate 38 for receiving the output signal.

  MOS transistors 36a and 36c are selectively turned on according to the output signals of flip-flops 32a and 32b, and MOS transistor 36b is selectively turned on according to the output signal of NAND gate 38. One of internal voltages VDD1-VDD3 selected by these MOS transistors 36a-36c is transmitted to driver power supply node 12 as driver power supply voltage VWLi.

  Flip-flops 32a and 32b are provided corresponding to each word line driver, constitute a scan path similar to a boundary scan register for testing after packaging an integrated circuit, transfer data, and corresponding memory cells Stores characteristic identification data.

  Word line driver WDRi includes MOS transistors PT0 and NT0 as in the previous embodiments, and is selectively supplied from driver power supply voltage selection circuit VSWi on word line WL according to word line selection signal WLENi. The voltage VWLi is transmitted.

  In the driver power supply voltage selection circuit VSWi shown in FIG. 13, one of the three types of internal voltages is selected according to the output signals (program data) of the flip-flops 32a and 32b. As an example, consider a state in which the internal voltages VDD1 to VDD3 are set to a voltage level of VDD1 <VDD2 = VDD <VDD3.

(I) Read stability margin defect countermeasures:
When the memory cell connected to the corresponding word line is a read stability margin defective bit, flip-flops 32a and 32b store information of “0” and “1”, respectively. In this case, MOS transistor 36a is turned on, MOS transistors 36b and 36c are turned off, and internal voltage VDD1 is selected. Driver power supply voltage VWLi is at a voltage level lower than internal power supply voltage VDD, static noise margin SNM at the time of data reading is expanded, and a reading stability margin is increased.

(Ii) Countermeasures for write margin defects:
If there is a write margin failure bit in the memory cell connected to the corresponding word line WLi, “1” and “0” are stored in the flip-flops 32a and 32b, respectively. In this case, both MOS transistors 36a and 36b are turned off, MOS transistor 36c is turned on, and internal voltage VDD3 is selected as driver power supply voltage VWLi. In this case, driver power supply voltage VWLi is at a voltage level higher than internal power supply voltage VDD, the static noise margin is reduced, the write operation margin is increased, and the write margin failure is improved.

(Iii) Otherwise:
When countermeasures against defects are not required, data of “1” is stored in the flip-flops 32a and 32b, the MOS transistor 36b is turned on, the MOS transistors 36a and 36c are turned off, and the internal voltage VDD2 (= VDD) Select. In this case, driver power supply voltage VWLi is at internal power supply voltage VDD level, and the countermeasure for defective operation margin is not applied to the memory cells in the corresponding row.

  A state in which “0” is stored in both flip-flops 32a and 32b is prohibited, and a state in which two internal voltages VDD1 and VDD3 are selected in parallel is prohibited.

  When it is necessary to take only measures against a write operation margin defect in the SRAM, it is necessary to set all the voltages VDD1 to VDD3 to a voltage level higher than the internal power supply voltage VDD and to take only measures against read stability failure. In some cases, the voltages VDD1-VDD3 may be set to a voltage level lower than the internal power supply voltage VDD. In this case, an operation margin defect can be performed in three stages.

  FIG. 14 schematically shows a configuration of voltage generator 30 shown in FIG. In FIG. 14, the voltage generator 30 includes a first voltage generation circuit 40, a second voltage generation circuit 42, and a third voltage generation circuit 44. The first voltage generation circuit 40 generates a first internal voltage VDD1 from the internal power supply voltage VDD, and the second voltage generation circuit 42 generates a second voltage VDD2 from the internal power supply voltage VDD. The third voltage generation circuit 44 generates the third voltage VDD3 from the internal power supply voltage VDD.

  The configurations of the first voltage generation circuit 40 and the second voltage generation circuit 42 differ depending on the voltage levels of the generated internal voltages VDD1, VDD2, and VDD3. In the case of generating a voltage lower than the internal voltage VDD, the corresponding voltage generation circuit (40, 42, 44) is composed of a step-down power supply circuit, and in the case of generating a voltage higher than the internal power supply voltage VDD, Corresponding voltage generation circuits (40, 42, 44) are constituted by boosting circuits. When a voltage having the same voltage level as the internal power supply voltage is generated, the corresponding voltage generation circuit is simply composed of a noise removal filter and a stabilization capacitor.

  Note that the internal power supply voltage VDD is equal to the external power supply EXP. When the external power supply voltage applied to VDD is lower than the external power supply voltage, a word line drive voltage (VDD1-VDD3) higher than the internal power supply voltage may be generated using the external power supply voltage.

  FIG. 15 is a diagram schematically showing an example of a configuration of a part that generates memory cell characteristic specifying information supplied to flip-flops (FF) 32a and 32b. In FIG. 15, a fuse program circuit 45 and a shift register 47 are provided as the memory cell characteristic specifying information storage / setting unit.

  The fuse program circuit 45 stores the information stored in the word line driver power supply voltage selection circuits VSW0 to VSWn according to the operation margin information of the memory cell by blowing or not blowing the fuse. The fuse program circuit 45 transfers the programmed data in parallel according to the reset signal RST.

  The fuse program circuit 45 has the same configuration as a defective address program circuit used when a defective cell is relieved by replacement with a redundant cell, and information of the fuse program circuit 45 is programmed in parallel during the defective address programming. It only has to be done.

  Shift register 47 includes a register circuit provided corresponding to each output node of fuse program circuit 45, and stores program data transferred from fuse program circuit 45 in accordance with reset signal RST in accordance with reset signal RST. After storing the program data from the fuse program circuit 45, the shift register 47 performs a shift operation according to the shift clock signal SCLK and sequentially outputs the serial-in data SI. In FIG. 15, this shift register 47 is shown such that its output node is stored in the input node to form a ring type shift register. However, the serial register data SO of the driver power supply voltage selection circuit VSWn may be applied to the input portion of the shift register 47.

  The reset signal RST is activated when the power is turned on or the system is reset, and the shift clock signal SCLK is also generated at a predetermined cycle when the power is turned on. These reset signal RST and shift clock signal SCLK are generated from the main control circuit CC.

  Further, the fuse program circuit 45 and the shift register 47 may be arranged in a peripheral area in the SRAM 10 as a fuse box in an area similar to other trimming information or defective address information. When the SRAM 10 is integrated as a macro on the same semiconductor chip as other logic, the fuse program circuit 45 and the shift register 47 may be provided in a control circuit outside the macro block.

[Example of change]
FIG. 16 schematically shows a configuration of a modified example of the driver power supply voltage selection circuit shown in FIG. FIG. 16 also representatively shows the configuration of driver power supply voltage selection circuit VSWi provided for word line driver WDRi.

  In the word line driver power supply voltage selection circuit VSWi shown in FIG. 16, one flip-flop (FF) 32 and two P-channel MOS transistors 36a and 36b are provided. The flip-flop 32 takes in the shift-in data SIN given from the previous stage according to the shift clock signal SCLK and transfers it to the next stage as the shift-out data SOUT.

  P-channel MOS transistors 36a and 36b select internal voltages VDD1 and VDD2 according to the output signals of flip-flop 32 and inverter 34, respectively. The inverter 34 inverts the output data of the flip-flop 32.

  Internal voltages VDD1 and VDD2 are given as driver power supply voltage candidates VD from voltage generator 30 shown in FIG. The word line driver WDRi has the same offense as the driver shown in FIG. 13, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The flip-flop (FF) 32 performs a transfer operation according to the shift clock signal SCLK, and stores information according to the operation margin of the memory cell connected to the corresponding word line WLi. MOS transistors 36a and 36b are selectively turned on, and transmit the selected voltage to driver power supply node 12 as driver power supply voltage VWLi.

The voltage levels of driver power supply voltage nodes VDD1 and VDD2 are set according to the contents of countermeasures against defective operation margins:
(A) VDD1 <VDD2 <VDD:
In this case, driver power supply voltage VWLi is at a voltage level lower than internal power supply voltage VDD, and the selected word line voltage is adjusted in two steps in order to take measures against a read stability margin failure.

(B) VDD1>VDD2> VDD:
In this case, since the voltage level of the selected word line is higher than the internal voltage VDD, the write margin is adjusted in two steps to relieve the write margin failure.

(C) VDD1 <VDD <VDD2:
In this case, the voltage level of the selected word line is set when it is higher or lower than the internal voltage VDD. Therefore, when the memory cell for the operation margin defect measures the countermeasure against the write margin defect cell, the higher voltage VDD2 is selected, and when the countermeasure against the read stability margin defect is taken, the lower voltage VDD1. Select.

  Note that one of the voltages VDD1 and VDD2 may be set to be equal to the internal voltage VDD.

  Therefore, in the configuration shown in FIG. 16, either the read stability margin defect countermeasure or the write margin defect countermeasure is implemented for the memory cell. In this case, it is determined whether the read stability margin is low or the write margin is low according to the tendency of the operating characteristics of the memory cells in the entire memory address space, and default countermeasures are implemented according to the determination result (for example, the voltage VDD1 is set). When a defect opposite to the default defect countermeasure due to local variation exists, a local defect countermeasure (for example, voltage VDD2 is selected) is implemented.

  The configurations shown in FIGS. 14 and 15 can be used as the configuration for generating the voltages VDD1 and VDD2 and the portion for generating the scan data SIN for the driver power supply voltage selection circuit VSWi shown in FIG.

  As described above, according to the third embodiment of the present invention, in correspondence with each word line driver, memory cell characteristic specifying information is stored through a scan path using a flip-flop, and each word line driver power supply voltage is stored. The level is set. Therefore, it is not necessary to provide a fuse corresponding to each word line driver, and the area occupied by the portion for selecting the word line driver power supply voltage can be reduced.

  As in the second embodiment, also in the third embodiment, one word line driver power supply voltage selection circuit may be arranged for two or a plurality of word line drivers.

[Embodiment 4]
FIG. 17 schematically shows a whole structure of the SRAM according to the fourth embodiment of the present invention. The SRAM 10 shown in FIG. 17 differs from the SRAM shown in FIG. 9 in the following points. That is, the driver power supply selection circuit 50 is provided as the driver voltage supply circuit WSC that supplies the driver power supply voltage to the word line drivers WDR0 to WDRn. The driver power supply selection circuit 50 selects one of the voltages VDD1 and VDD2 supplied from the voltage generator 30 according to the internal address signal AD supplied from the main control circuit CC, and transmits it as the driver power supply voltage VWL on the driver power supply line DRSL. To do. The other configuration of the SRAM 10 shown in FIG. 17 is the same as that of the SRAM shown in FIG. 9, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 17, the voltage level of driver power supply voltage VWL transmitted on the selected word line is set in accordance with address signal AD. Therefore, it is possible to selectively take countermeasures against defective operation margins only for memory cells in a very limited local area designated by the address signal AD. Address signal AD may be either internal row address signal RA or internal column address signal CA, but preferably includes both internal row address signal RA and internal column address signal CA.

  FIG. 18 schematically shows an example of the configuration of driver power supply selection circuit 50 shown in FIG. In FIG. 18, the driver power supply selection circuit 50 includes a fuse box 52 that stores a defective address, a comparator 54 that compares a storage address of the fuse box 52 with an internal address signal AD from the main control circuit, and an output of the comparator 54. Inverter 56 for inverting the signal and P channel MOS transistors 58a and 58b selectively conducting in accordance with the output signals of comparator 54 and inverter 56, respectively, are included.

  In the fuse box 52, the address of the memory cell to be subjected to countermeasures against the operation margin defect is programmed and stored by a fuse program (melting / non-melting). The comparator 54 compares the defective address stored in the fuse box 52 with the internal address signal AD, and outputs a signal corresponding to the comparison result. As an example, when the comparator 54 detects coincidence, the output signal CMP is set to the H level, and accordingly, the MOS transistor 58b is turned on by the inverter 56. In this state, internal voltage VDD2 is transmitted as driver power supply voltage VWL to driver power supply line DRSL, and is transmitted to word line drivers WDRi, WDR (i + 1).

  On the other hand, when the comparator 54 detects a mismatch, the output signal CMP becomes L level, the MOS transistor 58a is turned on, and the internal voltage VDD1 is transmitted to the driver power supply line DRSL as the driver power supply voltage VWL.

  Consider a case where the voltages VDD1 and VDD2 satisfy the condition of VDD = VDD1> VDD2. Only to the region designated by the defective address stored in the fuse box 52, the voltage VDD2 is transmitted as the driver power supply voltage VWL, and the voltage level of the selected word line is lowered. Therefore, in this case, the data retention / read stability margin can be improved. By storing both the row address and the column address in the fuse box 52, it is possible to implement an operation margin defect countermeasure only for a memory cell in a narrower region.

  In this case, it is also possible to take countermeasures against defective operation margins only for the memory cell regions of a plurality of rows / columns designated by the row address signal and the column address signal. For example, in the configuration shown in FIG. 18, in the fuse box 52, the least significant bit of the row address signal is set to a degenerated state, and all the column address signals are programmed in a bit valid state. As an example, suppose that word lines WLi and WL (i + 1) and bit lines BLj, / BLj are designated by programmed addresses in fuse box 52, for example. In this case, it is possible to take countermeasures against defects in the memory cells of 2 rows and 1 column, for example, memory cells MC0 and MC2, and to set the memory cells MC1 and MC3 to a normal state where countermeasures are not implemented. Conversely, if the row address signal is stored in the fuse box 52 with all the bits valid, and the least significant bit of the column address is programmed in the 1-bit degenerate state, an operation margin failure countermeasure is provided for the memory cell of 1 row and 2 columns. Can be applied. For example, it is assumed that the word line WLi and the bit lines BLj, / BLj, BL (j + 1), / BL (j + 1) are designated. In this case, countermeasures against malfunction in the operation margin can be performed for the memory cells MC0 and MC1, and countermeasures for malfunction can be performed for the remaining memory cells in the memory cells MC2 and MC3. It is possible to limit the scope of the measures.

[Example of change]
FIG. 19 schematically shows an entire configuration of an SRAM according to a modification of the fourth embodiment of the present invention. In SRAM 10 shown in FIG. 19, spare word line SWL is arranged in memory cell array MCA. In spare word line SWL, spare memory cells SMC are arranged corresponding to bit lines BL0, / BL0-BLm, / BLm. Spare memory cell SMC has the same configuration as memory cell MC.

  Corresponding to spare word line SWL, spare word line driver SWDR and row relief circuit 75 are provided. Row repair circuit 75 selectively activates spare word line enable signal SREN in accordance with a match / mismatch between a defective address programmed in a fuse box included in fuse box block 70 and given internal row address signal RA. Specifically, when a memory cell having a defective address programmed in the fuse box block 70 is designated, the row relief circuit 75 activates the spare word line enable signal SREN to drive the spare word line SWL to a selected state. Then, the row decoder RD is set to a disabled state by the spare word line enable signal SREN. As a result, the defective memory cell is replaced with a normal spare memory cell SMC, and the defective cell is relieved equivalently.

  In common with word line drivers WDR0 to WDRn and spare word line driver SWDR of word line drive circuit WDC, driver power supply selection circuit 65 is arranged as drive voltage supply circuit WSC. The driver power supply selection circuit 65 compares the program address of the fuse box block 70 with the address signal AD from the main control circuit CC, and one of the internal voltages VDD1 to VDD4 from the voltage generator 60 based on the comparison result. And the selection voltage is supplied to the driver power supply line DRSL as the driver power supply voltage.

  The other configuration of the SRAM shown in FIG. 19 is the same as the configuration of the SRAM 10 shown in FIG. 17, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In the SRAM 10 shown in FIG. 19, when a memory cell having an operation margin failure can be relieved by measures against a margin failure, it is relieved by the power supply voltage selection of the driver power supply selection circuit 65. For defective memory cells that cannot be remedied by this margin defect countermeasure, redundant replacement is performed using the row remedy circuit 75 to repair the defective cells.

  FIG. 20 schematically shows configurations of driver power supply selection circuit 65 and fuse box block 70 shown in FIG. In FIG. 20, a driver power supply selection circuit 65 includes two comparators 54a and 54b, a two-input NAND gate 77 receiving the output signals of the comparators 54a and 54b, and P for transmitting voltages VDD1-VDD4 when conducting. Channel MOS transistors 58a-58d and transmission gates 78a-78f for switching control signal transmission paths to the gates of MOS transistors 58a-58d are included.

  In the fuse box block 70, fuse boxes 52a to 52c and a fuse box 76 are provided. In the fuse box 76, the row address of the defective memory cell is stored by the fuse program, and the defective address programmed in the fuse box 76 is given to the row relief circuit 75, so that the defective cell is repaired by redundant replacement at the time of accessing the defective row. Done.

  The program addresses of fuse boxes 52a and 52b are applied to comparators 54a and 54b. In fuse box 52c, 1-bit information is stored, and the stored 1-bit information is applied to inverter 79. As an example, the fuse box 52a stores the address of a read / hold stability margin defective memory cell with a small degree of failure, and the fuse box 52b stores an address having a large degree of read / hold stability margin failure. Is done. Instead, the address of the read / hold stability margin defective memory cell is stored in the fuse box 52a, and the address of the write margin defective cell is stored in the fuse box 52b. Therefore, the addresses of defective memory cells are stored in fuse boxes 52a and 52b in accordance with the operation margin of the memory cell to be repaired. In this case, the address signal AD may be a row address signal RA or a column address signal CA, but preferably includes a row and column address signal. Further, at this time, the defective address may be programmed so that a specific bit of the address signal is set in a degenerated state and a plurality of rows or a plurality of columns of memory cells are designated.

  The fuse box 52c stores information corresponding to the characteristics unique to the semiconductor chip or the corresponding SRAM 10. That is, for example, when the read / hold stability margin of the entire chip of the SRAM 10 (the entire memory cell array) is small due to the degree of completion after the completion of the process, for example, it is set to “1”, otherwise “0” is programmed. To do. The program data of the fuse box 52c and the inverter 57 that inverts the output signal (program data) of the fuse box 52c control on / off of the transmission gates 78a to 78f.

  Transmission gate 78a transmits the output signal of comparator 54a to the gate of MOS transistor 58a when on, and transmission gate 78b transmits the output signal of comparator 54a to the gate of MOS transistor 58b when on. To do. Transmission gate 78c transmits the output signal of NAND gate 77 to the gate of MOS transistor 58b when on, and transmission gate 78d transmits the output signal of NAND gate 77 to the gate of MOS transistor 58c when on. To do. Transmission gate 78c transmits the output signal of comparator 54b to the gate of MOS transistor 58c when on, and transmission gate 78f transmits the output signal of comparator 54b to the gate of MOS transistor 58d when on. To do.

  The transmission gates 78a, 78c, 78e are turned on when the storage data (output data) of the fuse box 52c is “0”, and the transmission gates 78b, 78d, and 78f have the storage data of the fuse box 52c “1”. Sometimes it turns on.

  When the program data in the fuse box 52c is “1”, the output signals of the comparator 54a, NAND gate 77, and comparator 54b are transmitted to the gates of the MOS transistors 58b-58d, respectively, and any one of the internal voltages VDD2-VDD4. Is selected and transmitted to the driver power supply line DRSL. On the other hand, when the program data in fuse box 52c is "1", the output signals of comparator 54a, NAND gate 77 and comparator 54b are applied to the gates of MOS transistors 58a-58c, respectively, and internal voltages VDD1-VDD3 are set. Either voltage is selected and transmitted to the driver power supply line DRSL.

  Therefore, a set of voltage VDD1-VDD3 or a set of voltage VDD2-VDD4 is designated according to the operation margin characteristic specifying information of the entire chip (the entire SRAM memory cell array) stored in fuse box 52c, and comparator 54a, NAND gate 77 The comparator 54b determines the voltage selected when the program address is designated. The degree of operation margin failure is set in advance according to the characteristic variation in the entire memory cell array of the SRAM, and failure remedy measures are implemented locally according to the failure addresses stored in the fuse boxes 52a and 52b.

  Comparators 54a and 54b output an L level signal when the applied internal address signal (row and column address signal) AD matches the program address, and the output signal of NAND gate 77 is at an H level. Become. On the other hand, when the applied internal address signal AD and the program address do not match, the output signals of comparators 52a and 52b are at H level, and the output signal of NAND gate 77 is accordingly at L level.

  FIG. 21 schematically shows a word line voltage distribution for countermeasure against defective operation margin in the fourth embodiment of the present invention. In FIG. 21, an address area AD1 is an area designated by an address programmed in the fuse box 52a, and an address area AD2 is an area designated by an address programmed in the fuse box 52b. The address area AD3 is an area designated by the address programmed in the fuse box 76, and the area AD0 is the entire address space.

  In this case, the voltage VDD1 or VDD2 is applied as the selection voltage to the word line in the address region AD1, and the voltage VDD3 or VDD4 is applied as the selection voltage to the word line in the address region AD2. When address area AD3 is designated, spare word line SWL is replaced. The voltage VDD2 or VDD3 is applied to the remaining address area. In this voltage selection, one of the two voltages VDDk and VDDk + 1 is specified by a bit programmed in the fuse box 52c. Here, k is any one of 1 to 4.

  Therefore, in the entire address space AD0, the bit of the fuse box 52c sets the degree of action of the countermeasure against the variation, and the write margin is set for each address area according to one program address of the fuse boxes 52a and 52b. The defect is corrected and countermeasures against the read stability margin defect are performed in accordance with the other program address. By using the internal voltages VDD1 to VDD4, it is possible to execute a countermeasure against a defect according to the degree of the defect of the memory cell more accurately than in the case of the configuration shown in FIG. These internal voltages VDD1-VDD4 include voltages higher and lower than internal power supply voltage VDD.

  These fuse boxes 52a and 52b may be programmed with an address for specifying an address area for implementing a read stability margin defect countermeasure, and an address for designating an address area for performing a write margin defect countermeasure. May be programmed. In this case, even with the same type of margin defect countermeasure, the voltage level of the selected word line is different, and the degree of action of the countermeasure can be set according to the margin defect degree of the corresponding memory cell.

  As described above, according to the fourth embodiment of the present invention, the degree of variation in the characteristics of the entire SRAM (memory cells in the entire memory cell array) is set, and then measures against defects in memory cells at local addresses are taken. A margin defective cell is designated, and a countermeasure against a defect according to the overall characteristics is executed for a local defect. Thereby, it is possible to more flexibly relieve the operation margin defect of the memory cell. Furthermore, memory cells that cannot be relieved due to defective operation margins can be reduced more strictly and accurately by relieving them with normal redundancy replacement, thereby improving yield and stable operation. SRAM can be realized.

[Embodiment 5]
FIG. 22 schematically shows an overall configuration of SRAM 10 according to the fifth embodiment of the present invention. The SRAM 10 shown in FIG. 22 differs from the SRAM 10 shown in FIG. 17 in the following points. That is, the voltage from the driver voltage supply circuit 85 is supplied to the word line drive circuit WDC as the driver power supply voltage via the driver power supply line DRSL. On the other hand, the power supply voltage from the array power supply circuit 82 is supplied to the memory power supply lines PVL0 to PVLm of the memory cell array MCA. Memory power supply lines PVL0 to PVLm are coupled to high-side power supply node VH of memory cells MC in the corresponding column, respectively. Array power supply circuit 82 corresponds to column side cell characteristic specifying information storage / voltage setting circuit 6 and array power supply circuit 7 shown in FIG. 1, and is applied from voltage generator 80 in accordance with write instruction signal WEN and column selection signal CSL. One of the voltages VDH1 and VDH2 to be transmitted is selectively transmitted to memory power supply lines PVL0 to PVLm. Write instruction signal WEN is activated when write mode instruction signal WE is activated. That is, in the fifth embodiment, the voltage of the memory power supply line of the selected column is adjusted during data writing.

  Voltage generator 80 is connected to external power supply EXP. Voltages VDH1 and VDH2 having different voltage levels are generated from the internal power supply voltage VDD supplied from VDD. The other configuration of the SRAM 10 shown in FIG. 22 is the same as that of the SRAM shown in FIG. 19, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 23 schematically shows a configuration of array power supply circuit 82 shown in FIG. 22 together with a configuration of memory cell array MCA. Memory power supply lines PVL0-PVLm are coupled to high-side power supply nodes VH of memory cells MC in the corresponding columns, respectively, and transmit memory power supply voltages VM0-VMm, respectively. Similar to the configuration shown in FIG. 6, memory cell MC has P channel MOS transistors (load transistors) PQ1 and PQ2, N channel MOS transistors (drive transistors) NQ1 and NQ2, and N channel MOS transistors (access transistors) NQ3 and NQ4. including. High side power supply node VH is coupled to the sources of load transistors PQ1 and PQ2. The bit line arrangement and the word line arrangement of this memory cell array MCA are the same as those shown in FIG. 22, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the column selection circuit SC, a multiplexer CMUX is provided. The multiplexer CMUX couples the bit line of the selected column to the internal data line IO according to the column selection signal CSL. Internal data line IO is coupled to write circuit WC and read circuit RC shown in FIG. As internal data line IO, an internal data line for writing and a data line for reading may be provided separately.

  Array power supply circuit 82 corresponds to fuses FZC0 to FZCm provided corresponding to memory cell columns, three-input AND gates G0 to Gm provided corresponding to fuses FZC0 to FZCm, and AND gates G0 to Gm, respectively. Array power supply voltage selection circuits MVSW0 to MVSWm provided.

  Each of fuses FZC0 to FZCm stores information specifying the characteristics of the memory cells in the corresponding column, that is, information indicating a read / hold stability margin or a write operation margin, programmed by fusing fuse elements (not shown). AND gates G0-Gm receive storage data (program data) of corresponding fuses FZC0-FZCm, corresponding column selection signals CSL0-CSLm, and write instruction signal WEN, respectively. Therefore, each of these AND gates G0 to Gm has the program data of the corresponding fuses FZC0 to FZCm at the H level (“1”), and the corresponding column selection signals CSL0 to CSLm are at the H level of the selected state. When the write instruction signal WEN is at the H level indicating writing, the output signal is set at the H level. At the time of data writing, the output signal of the AND gate Gi (any of i = 0-m) provided for the selected column becomes H level, and the output signals of the remaining AND gates are maintained at L level.

  Array power supply voltage selection circuits MVSW0 to MVSWm have the same configuration, and the same reference numerals are assigned to the corresponding components in each selection circuit. Array power supply voltage selection circuit MVSWi (i = 0-m) selectively transmits inverter 85 that receives the output signal of corresponding AND gate Gi and internal voltages VDH1 and VDH2 to corresponding array power supply line PVLi. P channel MOS transistors 86 and 87 are included.

  MOS transistor 86 is turned on when the output signal of inverter 85 is at L level, and transmits first internal voltage VDH1 onto corresponding array power supply line PVLi. MOS transistor 87 is rendered conductive when the output signal of corresponding AND gate Gi is at L level, and transmits second internal voltage VDH2 onto corresponding array power supply line PVLi.

  Consider a state in which the first internal voltage VDH1 is lower than the second internal voltage VDH2. The outputs of the fuses FZC0 to FZCm are L level ("0") before programming (fuse not blown), and the output signals are H level during programming (fuse blown). Therefore, when fuse FZCi is in an unprogrammed state, the output signal of corresponding AND gate Gi is at L level, and the output signal of AND gate Gi is irrespective of the states of corresponding column selection signal CSLi and write instruction signal WEN. At the L level, second internal voltage VDH2 is selected as array power supply voltage VMi. Now, VDH1 <VDH2, and in this case, measures against defective write margin are not taken. Second internal voltage VDD2 may be at the same voltage level as normal array power supply voltage VDD.

  On the other hand, when the fuse FZCi is programmed, its output signal becomes H level (“1”). In the selected column, when data is written, column selection signal CSLi and write instruction signal WEN are at H level, and the output signal of AND gate Gi is at H level. Therefore, in array power supply voltage selection circuit MVSWi, MOS transistor 86 is turned on, first array power supply voltage VDH1 (<VDH2) is selected, and a write margin failure countermeasure is taken in the selected column (static noise margin is reduced). Reduced).

  At the time of data reading, write instruction signal WEN is at L level, and all output signals of AND gates G0 to Gm are at L level. Accordingly, MOS transistor 87 is turned on in array power supply voltage selection circuits MVSW0 to MVSWm, and internal voltage VDH2 is selected and transmitted to corresponding array power supply lines PVL0 to PVLm as array power supply voltages VM0 to VMm. In this case, countermeasures against defective writing margin are not performed. It is assumed that the data holding stability margin or the reading stability margin is sufficiently guaranteed when this voltage VDH2 is transmitted as array power supply voltage VM (VM0-VMm).

  Therefore, in the configuration shown in FIG. 23, the countermeasure against the write margin can be individually executed for each memory cell column.

  Note that instead of the fuses FZC0 to FZCm, similarly to the second embodiment, a flip-flop is used to form a scan path, and memory cell characteristic specifying information is transferred via the scan path and stored in each flip-flop. Good.

  As described above, in the configuration according to the fifth embodiment of the present invention, the implementation / non-execution of the write margin defect countermeasure is set for each column according to the memory cell characteristics, and according to the memory cell characteristics. Thus, the write margin defect countermeasure can be taken only for the area where the write margin defect countermeasure needs to be taken, and the adverse effect of the defect countermeasure on other normal cells can be reduced.

  If a read signal is used in place of write instruction signal WEN and the memory power supply voltage of the selected column is made higher than that in the non-selected state, a read / hold stability margin defect of the memory cell at the time of data read can be remedied. it can.

  Further, when used in combination with the configuration for adjusting the word line driver power supply voltage in any one of the first to fourth embodiments, the countermeasure for defective write margin is implemented in units of columns and the countermeasure for defective read margin is implemented in units of rows. Can do.

[Embodiment 6]
FIG. 24 schematically shows an entire configuration of the SRAM according to the sixth embodiment of the present invention. In FIG. The SRAM shown in FIG. 24 differs from the SRAM shown in FIG. 22 in the following points. That is, the voltage generator 80 generates three types of voltages VDH1, VDH2, and VDH3. The array power supply circuit 90 selects one of the internal voltages VDH1 to VDH3 from the voltage generator 80 according to the memory cell characteristic specifying information of the corresponding column for each column of the memory cell array MCA, and the corresponding array power supply Transmit to lines PVL0-PVLm. The memory cell characteristic specifying information of the array power supply circuit 90 is transferred as scan-in data SI and scan-out data SO via a scan path (not shown) and is sequentially set for each column. Array power supply circuit 90 selectively updates the voltages on array power supply lines PVL0-PVLm for the selected column in accordance with write instruction signal WEN and column select signal CSL, as in the configuration shown in FIG. The other configuration of the SRAM 10 shown in FIG. 24 is the same as that of the SRAM shown in FIG. 22, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 25 shows a configuration of memory cell array MCA and array power supply circuit 90 of SRAM 10 shown in FIG. The arrangement of the memory cells MC in the memory cell array MCA is the same as the arrangement of the memory cell array MCA shown in FIG. 23, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The configuration of the column selection gate circuit (multiplexer) CMUX is the same as that shown in FIG.

  The array power supply circuit 90 includes flip-flops (FF) FFC0 to FFCm provided corresponding to the memory cell columns, column array power supply voltage selection switches CVSW0 to CVSWm provided corresponding to the flip-flops FFC0 to FFCm, AND gates AG0-AGm provided corresponding to the respective cell columns, and array power supply voltage selection circuits MVSWL0-MVSWLm provided corresponding to the respective memory cell columns are included.

  The flip-flops FFC0 to FFCm form a scan path, sequentially transfer the scan-in data SI according to a clock signal (not shown), and store memory cell characteristic specifying information of the corresponding column. The scan-out data SO from the flip-flops FFC0 to FFCm is also transferred to a scan register circuit (not shown) (see FIG. 15).

  Column array power supply voltage selection switches CVSW0 to CVSWm have the same configuration, and the same reference numerals are assigned to corresponding components. Column array power supply voltage selection switch CVSWi (i = 0-m) includes an inverter 95 receiving the output signal of corresponding flip-flop FFCi, a P-channel MOS transistor 96 transmitting internal voltage VDH3 in accordance with the output signal of inverter 95, and a flip-flop P channel MOS transistor 97 transmitting internal voltage VDH2 in accordance with the output signal of FFCi.

  In column array power supply voltage selection switch CVSWi, when output data of corresponding flip-flop FFCi is at L level (“0”), MOS transistor 97 is turned on, and internal voltage VDH2 is selected and transmitted as voltage Vcmi. On the other hand, when the output signal of flip-flop FFCi is at the H level (“1”), MOS transistor 96 is turned on and internal voltage VDH3 is transmitted as array power supply voltage Vcmi.

  Therefore, one of voltages VDH2 and VDH3 is selected as an array power supply voltage candidate according to the data stored in flip-flops FFC0 to FFCm.

  AND gate AGi receives write instruction signal WEN and column selection signal CSLi. At the time of data writing, when the corresponding column is designated, the output signal of AND gate AGi is at H level, and at the time of data reading and when column selection signal CSLi is not selected and in the standby state, the output signal of AND gate AGi is L level.

  Array power supply voltage selection circuits MVSW0 to MVSWm have the same configuration as array power supply voltage selection circuits MVSW0 to MVSWm shown in FIG. 23, and corresponding portions are denoted by the same reference numerals. In array power supply voltage selection circuit MVSWi, when the output signal of corresponding AND gate AGi is at L level, MOS transistor 87 is turned on, internal voltage VDH1 is selected, and array power supply voltage is applied onto corresponding array power supply line PVLi. It is transmitted as VMi. On the other hand, when the output signal of corresponding AND gate AGi is at the H level, MOS transistor 86 is turned on, and voltage Vcmi selected by corresponding column array power supply voltage selection switch CVSWi is selected, and on corresponding array power supply line PVLi. Is transmitted as array power supply voltage VMi.

  Assume that the internal voltages VDH1 to VDH3 satisfy the condition VDDM = VDH1> VDH2> VDH3. The voltage VDDM is the original array power supply voltage when failure countermeasures are not implemented.

  When the data stored in the corresponding flip-flop FFCi is “0”, the MOS transistor 97 is turned on, and the internal voltage VDH2 is set as the voltage Vcmi. When the corresponding column is selected during data writing, the output signal of the corresponding AND gate AGi becomes H level, and the voltage VMi on the array power supply line PVLi becomes the voltage VDH2 by the array power supply voltage selection circuit MVSWi. In this case, the corresponding array power supply voltage is a voltage level close to the original array power supply voltage VDDM, and the action of countermeasure against the write margin failure is set to a weak state. On the other hand, when the data stored in the corresponding flip-flop FFCi is “1” (H level), the MOS transistor 96 is turned on, and the internal voltage VDH3 is selected as the voltage Vcmi. At the time of data writing, in the selected column, the voltage on the array power supply line PVLi is set to a level of the voltage VDH3 lower than that at the time of applying the voltage VDH2, and the countermeasure against the write margin defect is set to a stronger state.

  In reading, standby, and non-selected columns, voltage VDH1 (= VDDM) is selected and transmitted as array power supply voltage onto corresponding array power supply lines PVL0-PVLm.

  Also in the configuration shown in FIG. 25, the write margin defect can be adjusted in two stages, the write characteristic can be compensated according to the memory cell characteristic, and a countermeasure is taken only for the margin defective memory cell. Thus, the area affected by the countermeasure is limited, and a countermeasure against the write margin can be performed while suppressing adverse effects on other memory cells. Thereby, the possibility of defect relief can be increased, and the yield can be increased.

  In the configuration shown in FIG. 25, a fuse may be used instead of flip-flops (FF) FFC0 to FFCm.

  In the fifth and sixth embodiments, by using the read instruction signal (REN) instead of the write instruction signal WEN, a countermeasure for the data retention stability margin can be similarly applied.

  As described above, according to the sixth embodiment of the present invention, the write margin countermeasure failure is applied in a plurality of stages according to the memory cell characteristic specifying information for each column of the memory cell array power supply voltage. Therefore, it is possible to more accurately take measures according to the degree of the defect margin, and prevent the write margin defect countermeasure from further degrading the operation margin (read stability margin) of other memory cells. Therefore, it is possible to correct the defect accurately and improve the yield.

  The scan data for the flip-flops (FF) FFC0 to FFCm corresponding to the array power supply circuit 90 is stored in a fuse box and sequentially turned on when the power is turned on or the system is reset according to a shift clock signal (not shown). (Refer to Form 3).

[Embodiment 7]
FIG. 26 schematically shows an overall configuration of the semiconductor device according to the seventh embodiment of the present invention. In FIG. 26, the semiconductor device includes first and second logics 110 and 112 and an SRAM 114. The first and second logics 110 and 112 are, for example, processors, and each execute predetermined processing. One of these logics 110 and 112 may be a general-purpose processor, and the other may be a coprocessor that executes dedicated processing such as image or sound processing. SRAM 114 has any of the configurations described in the first to sixth embodiments, and internally implements a countermeasure against a no-margin failure for a local region. The logics 110 and 112 execute processing using the SRAM 114 as a work area or a received data storage area.

  These logics 110 and 112 and the SRAM 114 are coupled to an interface circuit (I / F) 116 via an internal bus 118, and at least the logics 110 and 114 execute data transmission / reception with the outside. Logic 110 and 112 can also access SRAM 114 via internal bus 118.

  Logic 110 and 112 are provided with logic power supply control circuits 120 and 122 for receiving external power supply voltage VEX, and SRAM 114 is provided with a power supply adjustment circuit 124. The logic power supply voltage control circuits 120 and 122 set voltage levels for the internal circuits of the logics 110 and 112, and control how the internal power supply voltage is applied to each internal circuit (for example, the operation stops for a long period of time). In the sleep mode, the supply of power supply voltage to the internal circuit is stopped).

  The power supply adjustment circuit 124 includes a voltage generator and a voltage selection circuit that generate the internal voltage described in the first to sixth embodiments, and adjusts and supplies the voltage level independently of the internal power supply voltages of the logics 110 and 112. Is set.

  The semiconductor device 100 is a system LSI (Large Scale Integrated circuit) or a system-on-chip (SoC), and by using the SRAM 114 as an internal memory, the yield of the SRAM 114 is improved. However, the probability of being processed as a defective product due to a defect in the SRAM 114 can be reduced, and the yield of the entire semiconductor device 100 can be improved.

  The SRAM according to the present invention may be provided as a single unit, or may be used as a built-in memory incorporated on the same semiconductor chip as the logic as shown in FIG. 26. By using the SRAM according to the present invention, the operation margin is poor. And the yield is improved accordingly.

  DESCRIPTION OF SYMBOLS 1 Memory cell array, 2 Word line selection circuit, 3 Row side cell characteristic specific information storage / voltage setting circuit, 4 Word line drive circuit, 6 Column side cell characteristic specific information storage / voltage setting circuit, 7 Array power supply circuit, MCA Memory cell array , WSD word line drive circuit, DVS0-DVSn power supply voltage setting circuit, ASC array power supply circuit, FZ fuse, RAT replica access transistor, ZR resistance element, DVS0 / 1-DVSn / n-1 driver power supply voltage setting circuit, WDR0-WDRn Word line driver, FZ0-, FZ1 fuse, RAT0, RAT1 replica access transistor, ZR resistance element, VSW0-VSWn driver power supply voltage selection circuit, 30 voltage generator, 32, 32a, 32b flip-flop, 36a-36c P Nel MOS transistor, 38 NAND gate, 40 First voltage generation circuit, 42 Second voltage generation circuit, 44 Third voltage generation circuit, 45 Fuse program circuit, 47 Shift register, 50 Driver power supply selection circuit, 52 Fuse box, 54, 54a, 54b comparator, 56 inverter, 58a, 58b P-channel MOS transistor, 60 voltage generator, 65 driver power supply selection circuit, 70 fuse box block, 75 row relief circuit, SWDR spare word line driver, 52a-52c fuse box, 76 fuse box, 77 NAND gate, 58a-58f CMOS transmission gate, 79 inverter, 58a-58d P-channel MOS transistor, 80 voltage generator, 85 drive voltage supply circuit Path, 82 array power supply circuit, FZC0-FZCm fuse, G0-Gm AND gate, MVSW0-MVSWm array power supply voltage selection circuit, MC memory cell, 90 array power supply circuit, FFC0-FFCm flip-flop, CVSW0-CVSWm column power supply voltage selection circuit , 100 Semiconductor device, 110 First logic, 112 Second logic, 114 SRAM, 120, 122 Logic power supply control circuit, 124 Power supply adjustment circuit.

Claims (9)

A plurality of memory cells arranged in a matrix, each storing information;
A plurality of word lines arranged corresponding to each memory cell row and connected to the corresponding memory cell,
Provided for each of the word lines, each having a driver power supply node, and transmitting the voltage of the corresponding driver power supply node onto the word line of the addressed row to drive the corresponding word line to a selected state A plurality of word line drivers, each provided corresponding to at least one word line driver, each having a plurality of candidates for a voltage transmitted to the corresponding word line driver according to the characteristic specifying information of the memory cell in the corresponding row A semiconductor device comprising: a driver power supply setting circuit that selects a voltage and transmits it to a driver power supply node of a corresponding word line driver, wherein the plurality of candidate voltages include voltages that act as countermeasures against different modes of different modes. Each of the driver power supply setting circuits is arranged corresponding to a predetermined number of word line drivers larger than one and smaller than all memory cells,
Each of the driver power supply setting circuits
A storage unit for storing a plurality of bits of the memory cell characteristic specifying information;
2. The semiconductor device according to claim 1, further comprising: a voltage generation circuit that selects any one of three or more candidate voltages having different voltage levels according to the storage information of the storage unit and transmits the selected voltage to power supply nodes of a corresponding predetermined number of word line drivers. apparatus. The driver power supply setting circuit is provided corresponding to each word line driver, and the memory cell characteristic specifying information is information of a plurality of bits,
A storage circuit for storing characteristic identification information of the memory cells in the corresponding row;
The semiconductor device according to claim 1, further comprising: a voltage selection circuit that selects one of three or more candidate voltages having different voltage levels according to the storage information of the storage circuit and transmits the selected voltage to a power supply node of a corresponding word line driver. apparatus. A plurality of memory cells arranged in a matrix, each storing information;
A plurality of word lines arranged corresponding to each memory cell row and connected to the corresponding memory cell,
Provided corresponding to each of the word lines, each having a driver power supply node, and when the corresponding word line is addressed, the voltage of the corresponding driver power supply node is transmitted to the corresponding word line to A plurality of word line drivers for driving a corresponding word line to a selected state; and a common address provided to the plurality of word line drivers, the memory cell characteristic specifying information and a given address independently of the operation mode of the semiconductor device A driver power supply setting circuit configured to set a voltage level transmitted to each word line driver according to a signal to any one of a plurality of different voltage levels and transmit the voltage level to a driver power supply node of each word line driver; The semiconductor device, wherein the address signal includes a row address signal and a column address signal. The drive power setting circuit includes:
A memory circuit for storing defective address information as the memory cell characteristic specifying information;
The defective address stored in the storage circuit is compared with the given address signal, and one of the plurality of voltages having different voltage levels is selected in accordance with the comparison result, and the power supply node of each word line driver The semiconductor device according to claim 4, further comprising: a voltage selection circuit for transmitting to the semiconductor device.   The semiconductor device according to claim 5, wherein the memory circuit stores a plurality of defective addresses. The driver power supply setting circuit includes:
A characteristic storage circuit for storing information indicating a characteristic tendency of the plurality of memory cells as the characteristic specifying information;
5. The semiconductor device according to claim 4, further comprising a voltage switching circuit that generates a plurality of different voltages by changing a set of voltages to be selected in accordance with stored information of the characteristic storage circuit. A plurality of memory cells arranged in a matrix, each having a cell power supply node, and storing information of a voltage level corresponding to the voltage of the cell power supply node;
A plurality of word lines arranged corresponding to each memory cell row and connected to the corresponding memory cell,
A plurality of bit line pairs arranged corresponding to each of the memory cell columns, each connected to a memory cell in a corresponding column;
A plurality of memory power supply lines arranged corresponding to each of the memory cell columns, each connected to a cell power supply node of a memory cell in the corresponding column, and each provided corresponding to the memory power supply line, The voltage transmitted to the corresponding memory power supply line is selected from a plurality of candidate voltages of three or more according to the characteristic specifying information of the memory cell in the corresponding column, the data write instruction, and the column selection signal generated according to the address signal. A semiconductor device comprising a memory power setting circuit for transmitting to a corresponding memory power line. The memory power setting circuit includes:
A memory circuit for storing specific information of the memory cell;
A first voltage selection circuit for selecting one of a plurality of voltages at a voltage level according to the storage information of the storage circuit;
2. A second voltage generation circuit that selects one of the voltage selected by the voltage selection circuit and a fixed voltage according to the write instruction and the column selection signal and transmits the selected voltage to a corresponding memory power supply line. The semiconductor device described.

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