JP2014099225A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which allows a stable acceleration test of data corruption in a standby state within a prescribed time.SOLUTION: The semiconductor device comprises: SRAM cells arrayed in matrix; a word line WL provided corresponding to each row of the SRAM cells; and a bit line pair BB, BT provided corresponding to each column of the SRAM cells. In a low standby mode, a control circuit/decoder 50 drives the word line WL to a non-selection state and sets the bit line pair BB, BT into a floating state. In a low standby test mode in which acceleration test of data corruption in the low standby mode is performed, the control circuit/decoder 50 drives the word line WL to the non-selection state, and activates a control signal T1 and turns on NMOS transistors MN7, MN8 to thereby fix the potential of the bit line pair BB, BT at "L" level (ground voltage VSS).

Description

  The present invention relates to a semiconductor device and is suitably used for a semiconductor device having a normal operation mode and a standby mode.

  In an SRAM (Static Random Access Memory), in order to detect a data retention defect due to a manufacturing failure of a transistor constituting a static memory cell (hereinafter also referred to as an SRAM cell) arranged in a matrix, Various manufacturing quality tests are performed. In one of these manufacturing quality tests, the SRAM cell is usually read after writing a predetermined data pattern into the SRAM cell and providing a test delay interval that allows the charge stored in the internal node of the SRAM cell to be discharged. Verify the stored data pattern. If the data written to the SRAM cell does not match the data read from the SRAM cell, the SRAM cell is considered to have a data retention defect.

  For example, in Japanese Patent No. 3701973 (Patent Document 1), a stress circuit for detecting a data retention defect of an SRAM cell is provided in the SRAM, and data is retained in the SRAM cell by applying stress to the SRAM cell during an access cycle to the SRAM. A memory circuit configured to detect a defect is disclosed. The memory circuit described in Patent Document 1 includes an access circuit for accessing a memory cell, and a discharge circuit for discharging a pair of bit lines coupled to the memory cell when accessing the memory cell. . The access circuit executes a stress cycle that stresses the charge storage function of the memory cell by activating a stress signal that controls the discharge circuit simultaneously with activating the word line of the memory cell.

  As described above, when the test delay interval is provided in the manufacturing quality test, the time required to test each integrated circuit is remarkably increased, resulting in a problem that the test efficiency is lowered. Therefore, in Patent Document 1, a desired test efficiency is maintained by forcibly discharging the bit line during the access cycle to the SRAM and applying stress to the memory cell.

Japanese Patent No. 3701973 JP-A-6-5096

  Conventionally, in SRAM, bit lines are precharged when the SRAM is in a standby state (a period in which the SRAM is not accessed). However, with the thinning of the gate oxide film due to recent device miniaturization, when the bit line is precharged, the current flowing in the gate oxide film in the standby state (hereinafter also referred to as leakage current) tends to increase. It is in. This increase in leakage current increases power consumption in the standby state. Therefore, in order to reduce the leakage current in the standby state, a technique for setting the bit line in the floating state in the standby state is being adopted.

  However, when the bit line is in a floating state, it takes time due to a current leak path formed in the bit line until the potential of the bit line is stabilized. Since the magnitude of the leak current flowing through this current leak path changes according to the wiring parasitic resistance of the bit line, the time required for the bit line potential to stabilize varies depending on the finish of the semiconductor device in the actual process. Occurs. Therefore, the time required for the potential of the bit line to stabilize varies among the plurality of SRAMs.

  On the other hand, in order to detect a data retention defect of a memory cell in the standby state, it is necessary to set a test time so that the standby state is maintained for a predetermined time after the potential of the bit line is stabilized. However, since the time required for the potential of the bit line to stabilize is indefinite as described above, it is not possible to uniquely determine how much time is required for the test time. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment has a standby mode and a test mode for performing a data destruction test in the standby mode. In the semiconductor device, the word line is deselected and the bit line is floated in the standby mode. On the other hand, in the test mode, the semiconductor device deselects the word line and fixes the potential of the bit line to a predetermined potential.

  According to the above-described embodiment, in the test mode for performing the data destruction test in the standby state, the potential of the bit line is stabilized within a short time so that the semiconductor device can be After maintaining the standby state, the data retention characteristics of the memory cell can be stably tested.

It is a figure which shows schematically the whole structure of a general semiconductor device. FIG. 2 is a circuit diagram showing an example of a configuration of a memory cell MC, a bit line precharge circuit, and a data read / write circuit in FIG. 2 is a timing chart showing an operation in a standby mode in the semiconductor device shown in FIG. 1. It is a figure which shows the time change of the electric potential of a bit line when a current leak path | pass is formed. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment. 3 is a timing chart showing the operation of the semiconductor device according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment. 6 is a timing chart illustrating an operation of the semiconductor device according to the second embodiment. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to a third embodiment. 12 is a timing chart illustrating an operation of the semiconductor device according to the third embodiment. FIG. 6 is a circuit diagram showing a main part of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram showing a main part of a semiconductor device according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to a fourth embodiment. 10 is a timing chart illustrating an operation of the semiconductor device according to the fourth embodiment. 10 is a timing chart showing an operation of a comparative example of the semiconductor device according to the fourth embodiment.

  Hereinafter, an embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
In describing a semiconductor device according to an embodiment, problems in a general semiconductor device will be described first. Next, main parts of the semiconductor device according to the embodiment constructed from the viewpoint of solving the problem will be described.

[Overall configuration of semiconductor device]
FIG. 1 is a diagram schematically showing an overall configuration of a general semiconductor device.

  Referring to FIG. 1, the semiconductor device includes a memory cell array 10 in which a plurality of memory cells MC are arranged in a matrix in m rows × n columns (m, n: natural numbers). Memory cell MC generically indicates memory cells MC1, MC2 to MCm × n (not shown).

  A word line WL is provided corresponding to each row of memory cells MC, and each memory cell MC is connected to a word line in the corresponding row. The word line WL generically indicates the word lines WL1 to WLm. Bit lines BB and BT are provided corresponding to each column of memory cells MC. Bit lines BB and BT generically indicate bit lines BB1 to BBn and BT1 to BTn. As will be described with reference to FIG. 2, the memory cell MC is an SRAM cell, and complementary data is transmitted to the bit line pair BB, BT.

  The semiconductor device further includes a word line driver 20, a data write / read circuit 30, a control circuit / decoder 50, and a bit line precharge circuit 60.

  In the control circuit / decoder 50, the control circuit controls the internal operation of the semiconductor device. Specifically, the control circuit generates a row address signal, a column address signal, and a control signal necessary for each operation in accordance with an external address signal and a write instruction signal. The control circuit defines the operation timing and operation sequence of the decoder.

  The decoder generates a row selection signal in accordance with a row address signal and a bit line pair corresponding to the selected column in accordance with the column address signal in order to drive the addressed word line WL in the memory cell array 10 to a selected state. And a column decoder to be selected. Specifically, the row decoder decodes a row address signal and generates a row selection signal during a read operation or a write operation. The column decoder decodes the column address signal and generates a column selection signal during a read operation or a write operation.

  The word line driver 20 drives the corresponding word line WL to the selection level “H” level (internal power supply voltage VDD) according to the row selection signal from the row decoder. As a result, the memory cell MC connected to the selected word line WL is activated.

  Bit line precharge circuit 60 is provided corresponding to each bit line pair. The bit line precharge circuit 60 sets the bit lines BB and BT to “H” when the bit line precharge signal CPC input from the control circuit / decoder 50 is at the “L” level (ground voltage VSS) of the activation level. ”Level (internal power supply voltage VDD).

  FIG. 2 is a circuit diagram showing an example of the configuration of memory cell MC, bit line precharge circuit 60, and data write / read circuit 30 in FIG.

  Memory cell MC has a configuration of a full CMOS single port SRAM cell. Since the memory cells MC1 to MCm × n have the same configuration, the configuration of the memory cell MC1 connected to the word line WL1 will be described as a representative example.

  2, memory cell MC1 includes PMOS (Positive-channel Metal Oxide Semiconductor) transistors MP1 and MP2 which are load transistors, NMOS (Negative-channel Metal Oxide Semiconductor) transistors MN1 and MN2 which are driver transistors, It includes NMOS transistors MN3 and MN4 which are access transistors.

  The sources of load transistors MP1 and MP2 are both connected to a line of internal power supply voltage VDD (hereinafter also referred to as VDD line), their drains are connected to storage nodes MB1 and MB2, respectively, and their gates are connected to storage nodes MT1 and MT1, respectively. Connected to MB1. The sources of driver transistors MN1 and MN2 are both connected to a line of ground voltage VSS (hereinafter also referred to as VSS line), their drains are connected to storage nodes MB1 and MT1, respectively, and their gates are connected to storage nodes MT1 and MB1, respectively. Connected to. The sources of access transistors MN3 and MN4 are connected to storage nodes MB1 and MT1, respectively, their drains are connected to corresponding bit lines BB and BT, respectively, and their gates are connected to corresponding word line WL1.

  PMOS transistor MP1 and NMOS transistor MN1 form an inverter, and output an inverted signal of data written in storage node MT1 to storage node MB1. PMOS transistor MP2 and NMOS transistor MN2 form an inverter, and output an inverted signal of data written in storage node MB1 to storage node MT1. Therefore, PMOS transistors MP1 and MP2 and NMOS transistors MN1 and MN2 form a latch circuit that holds data written in storage nodes MB1 and MT1.

  At the time of data writing, as described above, the word line WL1 becomes the “H” level (internal power supply voltage VDD) of the selected level, and the access transistors MN3 and MN4 are turned on (conductive). Thereby, bit line BB and storage node MB1 are connected, and bit line BT and storage node MT1 are connected. In this state, one of the bit lines BB and BT is set to the “H” level (internal power supply voltage VDD) and the other bit line is set to the “L” level (ground voltage) according to the write data. VSS), and write data is written to storage nodes MB1 and MT1. When the word line WL1 becomes the “L” level (ground voltage VSS), which is a non-selection level, and the access transistors MN3 and MN4 are turned off (non-conducting), the data written to the storage nodes MB1 and MT1 is a PMOS transistor. It is held by MP1 and MP2 and NMOS transistors MN1 and MN2.

  In the read operation, after both bit lines BB and BT are precharged to “H” level, word line WL1 is set to “H” level of the selection level and access transistors MN3 and MN4 are turned on. When the storage nodes MB1 and MT1 are set to the “H” level and the “L” level, respectively, the PMOS transistor MP1 and the NMOS transistor MN2 are on, so that the VSS is supplied from the bit line BT through the NMOS transistors MN4 and MN2. Current flows out to the line, and the potential of the bit line BT decreases. On the other hand, when the storage nodes MB1 and MT1 are set to the “L” level and the “H” level, respectively, the PMOS transistor MP2 and the NMOS transistor MN1 are on, so that the NMOS transistors MN3 and MN1 from the bit line BB are turned on. Current flows out to the VSS line through the bit line, and the potential of the bit line BB decreases. Therefore, the data stored in memory cell MC1 can be read by amplifying and detecting the voltage between bit lines BB / BT.

  Bit line precharge circuit 60 includes PMOS transistors MPP0 to MPP2. The PMOS transistor MPP0 has its source and drain connected to the bit lines BB and BT, respectively. The PMOS transistor MPP1 has a source connected to the VDD line and a drain connected to the bit line BB. The PMOS transistor MPP2 has a source connected to the VDD line and a drain connected to the bit line BT. The gates of PMOS transistors MPP0 to MPP3 are both connected to a signal line (hereinafter also referred to as CPC line) that transmits bit line precharge signal CPC from control circuit / decoder 50. When the bit line precharge signal CPC is at the activation level “L”, the PMOS transistors MPP0 to MPP3 are both turned on, whereby the bit lines BB and BT are precharged to the “H” level.

  Data write / read circuit 30 has a write circuit 32 for transmitting write data to the bit line pair corresponding to the selected column at the time of data writing, and a bit line pair corresponding to the selected column at the time of data read. A read circuit 34 that detects and amplifies data to generate read data, NMOS transistors MN5 and MN6, and PMOS transistors MP3 and MP4 are included.

  The NMOS transistor MN5 has a drain connected to the bit line BB and a source connected to the write circuit 32. The NMOS transistor MN6 has a drain connected to the bit line BT and a source connected to the write circuit 32. The gates of NMOS transistors MN5 and MN6 are both connected to a signal line (hereinafter also referred to as WC1 line) for transmitting data write signal WC1 from control circuit / decoder 50. At the time of data writing, when data write signal WC1 becomes “H” level of the activation level, NMOS transistors MN5 and MN6 are turned on, and the bit line pair and write circuit 32 are electrically connected.

  The PMOS transistor MP3 has a source connected to the bit line BB and a drain connected to the read circuit 34. The PMOS transistor MP4 has a source connected to the bit line BT and a drain connected to the read circuit 34. The gates of PMOS transistors MP3 and MP4 are both connected to a signal line (hereinafter also referred to as RC1 line) for transmitting data read signal RC1 from control circuit / decoder 50. At the time of data reading, when data read signal RC1 becomes “L” level of the activation level, PMOS transistors MP3 and MP4 are turned on, and the bit line pair and read circuit 34 are electrically connected.

  Write circuit 32 includes an input buffer and a write drive circuit (not shown), and generates internal write data according to external write data when data is written. Read circuit 34 includes a sense amplifier circuit and an output buffer (not shown). When reading data, internal data detected and amplified by the sense amplifier circuit is further buffered by an output buffer to generate external read data.

  Write circuit 32 and read circuit 34 may respectively write and read data having a plurality of bits, and memory cell array 10 corresponds to 1-bit input / output data. The read circuit 34 may be configured to input and output 1-bit data. At the time of writing / reading multi-bit data, memory cell array 10, write circuit 32 and read circuit 34 are arranged corresponding to each data bit.

Next, the operation of the semiconductor device shown in FIG. 1 will be briefly described.
The semiconductor device has, as operation modes, a normal operation mode in which data writing / reading described above is performed and a standby mode in which data is simply held and no external data access is performed. This standby mode includes a mode corresponding to a standby cycle (standby state during a write / read cycle (access cycle) during normal operation) and a mode corresponding to a sleep state (long-term standby state). . In the standby mode, the word line WL is driven to the “L” level (ground voltage VSS) which is a non-selection level.

  In the following description, in order to distinguish each standby mode, the standby mode corresponding to the standby cycle is also referred to as “normal standby mode”, and the standby mode corresponding to the sleep state is also referred to as “low standby mode”.

  FIG. 3 is a timing chart showing the operation in the standby mode in the semiconductor device. FIG. 3 shows temporal changes in the potentials of word line WL, bit line precharge signal CPC, bit lines BB and BT, and storage nodes MT1 and MB1 of memory cell MC1. It is assumed that storage nodes MT1 and MB1 of memory cell MC1 hold “H” level and “L” level data, respectively.

  Referring to FIG. 3, in the normal standby mode, control circuit / decoder 50 activates bit line precharge signal CPC to "L" level. As a result, the PMOS transistors MPP0 to MPP2 of the bit line precharge circuit 60 are turned on, and the bit lines BB and BT are precharged to the “H” level (power supply voltage VDD). At the time of data writing or data reading, control circuit / decoder 50 cancels the precharge of bit lines BB and BT by deactivating bit line precharge signal CPC to “H” level.

  On the other hand, when the bit lines BB and BT are held at the “H” level in the low standby mode, the leakage current from the bit line BB or BT to the memory cell MC increases. In order to reduce this leakage current, the bit lines BB and BT are brought into a floating state in the low standby mode. Specifically, control circuit / decoder 50 inactivates bit line precharge signal CPC to “H” level when it receives a command to switch to the low standby mode from the outside at time t1. As a result, the PMOS transistors MPP0 to MPP2 of the bit line precharge circuit 60 are turned off, and the precharge of the bit lines BB and BT is released. Further, control circuit / decoder 50 sets data write signal WC1 to the “L” level of the inactivation level and sets data read signal RC1 to the “H” level of the inactivation level. Thus, the bit line pair is electrically disconnected from data write / read circuit 30. As a result, the bit lines BB and BT are in a floating state.

  When the bit lines BB and BT are brought into a floating state, the bit lines BB and BT take an arbitrary potential. The potentials of the bit lines BB and BT at this time are stabilized in a state where the leakage current is the smallest according to the data held in the memory cells MC connected to the bit lines.

  However, if the bit lines BB and BT are in a floating state, a minute current may flow from the bit lines BT and BB to the ground voltage VSS through the wiring parasitic resistance of the bit lines BB and BT. FIG. 2 shows a current leak path rt1 through the wiring parasitic resistance of the bit line BT as an example. FIG. 4 shows temporal changes in the potentials of the bit lines BB and BT when the current leak path rt1 is formed. As described above, the bit lines BB and BT are stabilized at an arbitrary potential in the low standby mode. However, the leakage current flows through the current leakage path rt1, so that the potential of the bit line BT gradually decreases. After a certain time has elapsed after switching to the low standby mode (time t1), the bit line BT becomes “L” level (ground voltage VSS) (time t3).

  Here, consider a case where, for example, in the memory cell MC2 connected to the bit line BT, the access transistor MN4 is defective (pinch-off characteristic is defective). It is assumed that storage nodes MT2 and MB2 of memory cell MC2 hold “H” level and “L” level data, respectively. Since the access transistors MN3 and MN4 are turned off in the low standby mode, if the access transistor MN4 is normal, the potential of the storage node MT2 is held at the “H” level. On the other hand, when access transistor MN4 is defective, current leak path rt2 is formed between storage node MT2 and bit line BT via access transistor MN4. As described above, as the potential of the bit line BT gradually decreases, the potential difference between the storage node MT2 and the bit line BT increases, so that the leakage current flowing through the current leakage path rt2 also increases. As a result, the potential of storage node MT2 gradually decreases from the “H” level. In the memory cell MC2, the latch circuit composed of the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 is inverted when the potential of the storage node MT2 falls below a predetermined threshold value. As a result, the data retention characteristic of the memory cell MC2 is deteriorated, resulting in data destruction.

  If the memory cell MC is defective as described above, the memory cell MC may cause data destruction in the low standby mode. In the semiconductor device according to the first embodiment, the data retention characteristic of the memory cell MC in the low standby mode is tested in order to prevent this data destruction.

  Hereinafter, the configuration of the semiconductor device according to the first embodiment will be described in detail with reference to the drawings. In the semiconductor device according to the first embodiment, the above test is performed as the final step of the chip manufacturing process, for example, before shipping the semiconductor device. In the following description, an operation mode for performing a data destruction test in the low standby mode is also referred to as “low standby test mode”.

[Configuration of Semiconductor Device According to First Embodiment]
FIG. 5 is a circuit diagram showing a configuration of the semiconductor device according to the first embodiment. Since the overall configuration of the semiconductor device according to the first embodiment is the same as that of the general semiconductor device shown in FIG. 1, detailed description will not be repeated. The configuration of memory cell MC, bit line precharge circuit 60 and data write / read circuit 30 is also the same as that of FIG. 2, and therefore detailed description will not be repeated.

  Referring to FIG. 5, the semiconductor device according to the first embodiment is obtained by providing NMOS transistors MN7 and MN8 in the circuit diagram shown in FIG.

  The NMOS transistor MN7 has a drain connected to the bit line BB and a source connected to the VSS line. The NMOS transistor MN8 has a drain connected to the bit line BT and a source connected to the VSS line. The gates of the NMOS transistors MN7 and MN8 are both connected to a signal line (hereinafter referred to as a T1 line) for transmitting a control signal T1 from the control circuit / decoder 50.

  The control circuit / decoder 50 sets the control signal T1 to the “H” level of the activation level in the low standby test mode. On the other hand, in the normal operation mode, normal standby mode, and low standby mode, control circuit / decoder 50 sets control signal T1 to the “L” level of the inactivation level.

  Thus, in the low standby test mode, the NMOS transistors MN7 and MN8 are turned on in response to the “H” level control signal T1. Therefore, the potentials of the bit lines BB and BT are fixed to the “L” level (ground voltage VSS).

  Next, the operation of the semiconductor device according to the first embodiment will be described with reference to the timing chart shown in FIG.

  Referring to FIG. 6, in order to test the data retention characteristic of memory cell MC in the low standby mode, first, the semiconductor device according to the first embodiment first tests memory cell MC (for example, memory cell MC1 and Data is written (time t12 to t13). Specifically, the control circuit / decoder 50 sets the bit line precharge signal CPC to the “H” level of the inactivation level. Thereby, the precharge of the bit lines BB and BT is released. Control circuit / decoder 50 sets word line WL1 corresponding to memory cell MC1 to the “H” level of the selection level. Access transistors MN3 and MN4 of memory cell MC1 are turned on, and bit lines BB and BT and storage nodes MB1 and MT1 are connected to each other.

  In this state, write circuit 32 sets one of the bit line pairs (for example, bit line BT) to the “H” level according to the internal write data, and the other of the bit line pairs (for example, bit line BB). To “L” level. Thereby, the write data is written into storage nodes MT1 and MB1 of memory cell MC1. Subsequently, when the word line WL1 is set to the “L” level of the non-selection level and the access transistors MN3 and MN4 are turned off, the data written in the storage nodes MT1 and MB1 is held by the latch circuit.

  When the write operation to memory cell MC1 is completed, the semiconductor device is switched to the normal standby mode (time t13 to t14). In the normal standby mode, the control circuit / decoder 50 sets the word line WL1 to the “L” level which is the non-selection level and sets the bit line precharge signal CPC to the “L” level which is the activation level. As a result, the bit lines BB and BT are precharged to the “H” level.

  Next, in response to an external switching command, the control circuit / decoder 50 switches the semiconductor device from the normal standby mode to the low standby test mode (time t14). In the low standby test mode, a data destruction test in the low standby mode is performed. Specifically, control circuit / decoder 50 sets data write signal WC1 to the “L” level of the inactivation level and bit data read signal RC1 to the “H” level of the inactivation level. The line pair is electrically disconnected from the data write / read circuit 30. Further, the control circuit / decoder 50 activates the control signal T1 to the “H” level to forcibly set the potentials of the bit lines BB and BT to the “L” level (ground voltage VSS). Then, the state where the bit lines BB and BT are fixed to the “L” level is maintained for a predetermined time (time t14 to t15).

  At this time, if the memory cell MC1 is defective, a current leak path rt2 is formed between the storage node MT1 and the bit line BT as shown in FIG. Therefore, the leakage current flows through the current leakage path rt2 for a certain time, so that the potential of the storage node MT1 gradually decreases. When the potential of the storage node MT1 becomes lower than the threshold value, the latch circuit in the memory cell MC1 is inverted and data destruction occurs.

  When a certain time elapses (time t15), the low standby test mode ends, and data held in the memory cell MC1 is read (time t15 to t16). Specifically, control circuit / decoder 50 sets bit line precharge signal CPC to the “L” level of the activation level. As a result, the bit lines BB and BT are precharged to the “H” level. Control circuit / decoder 50 sets data write signal WC1 to the activation level “H” level and sets data read signal RC1 to the activation level “L” level, thereby setting the bit line pair to the data level. Electrically connected to the write / read circuit 30.

  Subsequently, the control circuit / decoder 50 activates the memory cell MC1 by setting the word line WL1 corresponding to the memory cell MC1 to the “H” level of the selection level. Further, the control circuit / decoder 50 sets the bit line precharge signal CPC to the “H” level of the inactivation level, and releases the precharge of the bit lines BB and BT.

  The potentials of the bit lines BB and BT change according to data held in the activated memory cell MC1. When memory cell MC1 is normal, as shown in FIG. 6, the potential of bit line BT connected to storage node MT1 is at “H” level, while the potential of bit line BB connected to storage node MB1 is shown. Falls from the “H” level. Although illustration is omitted, when the memory cell MC1 is defective, data destruction occurs within a certain time corresponding to the low standby test mode. Therefore, the potential of the bit line BT decreases while the potential of the bit line BB indicates the “H” level. Whether or not the memory cell MC1 is normal is determined based on changes in the potentials of the bit lines BB and BT.

  Here, as described above, in the low standby mode, the bit lines BB and BT are set in a floating state. In this state, it takes time to stabilize the potentials of the bit lines BB and BT due to the current leak path rt1 (FIG. 2) formed in the bit line. In addition, since the magnitude of the leak current flowing through the current leak path rt1 changes according to the wiring parasitic resistance of the bit line, the time required for stabilizing the potentials of the bit lines BB and BT is the semiconductor device in the actual process. It will vary depending on the finish. Therefore, the time required for stabilizing the potentials of the bit lines BB and BT differs among a plurality of semiconductor devices, and the time cannot be uniquely determined.

  On the other hand, in order to determine the data retention characteristic of the memory cell MC in the low standby mode, it is necessary to set a test time so that the standby state is maintained for a certain time after the potentials of the bit lines BB and BT are stabilized. is there. However, since the time required for stabilizing the potentials of the bit lines BB and BT is indefinite as described above, it is difficult to determine how much time is required for the test time.

  In contrast, the semiconductor device according to the first embodiment has a low standby test mode as an operation mode for performing a data destruction test in the low standby mode. The potentials of the bit lines BB and BT are forcibly fixed to the “L” level. In this way, by forcibly stabilizing the potentials of the bit lines BB and BT within a short time, the data retention characteristics of the memory cell MC are tested after the semiconductor device is maintained in the standby state for a certain period thereafter. It can be performed stably.

<Embodiment 2>
FIG. 7 is a circuit diagram showing a configuration of the semiconductor device according to the second embodiment. Since the overall configuration of the semiconductor device according to the second embodiment is similar to that of the general semiconductor device shown in FIG. 1, detailed description will not be repeated. The configuration of memory cell MC, bit line precharge circuit 60 and data write / read circuit 30 is also the same as that of FIG. 2, and therefore detailed description will not be repeated.

  Referring to FIG. 7, the semiconductor device according to the second embodiment is obtained by providing NMOS transistors MN7 and MN8, MVSS line and MVSS control circuit 70 in the circuit diagram shown in FIG. The MVSS control circuit 70 includes NMOS transistors MN9 and MN10. Since the configuration and operation of NMOS transistors MN7 and MN8 are the same as those of the semiconductor device according to the first embodiment shown in FIG. 5, detailed description will not be repeated.

  In the second embodiment, the sources of the driver transistors MN1 and MN2 of the memory cell MC are connected to a source line different from the VSS line (hereinafter also referred to as MVSS line). NMOS transistors MN9 and MN10 are connected between the MVSS line and the VSS line.

  The gate of the NMOS transistor MN9 is connected to the MVSS line to form a MOS diode. The NMOS transistor MN10 constitutes a switching element for switching the potential of the MVSS line to either the “L” level (ground voltage VSS) or the “L + ΔL” level. NMOS transistor MN10 receives control signal T2 from control circuit / decoder 50 at its gate.

  Control circuit / decoder 50 sets control signal T2 to the “H” level of the activation level in the normal operation mode and the normal standby mode. On the other hand, in the low standby mode and in the low standby test mode, the control signal T2 is set to the “L” level of the inactivation level. Thus, in the normal operation mode and the normal standby mode, the NMOS transistor MN10 is turned on in response to the “H” level control signal T2. As a result, the potential of the MVSS line becomes “L” level (ground voltage VSS).

  On the other hand, in the low standby mode and the low standby test mode, the NMOS transistor MN10 is turned off in response to the "L" level control signal T2. When the NMOS transistor MN10 is turned off, the MVSS line rises from the ground voltage VSS due to the leakage current of the memory cell MC. When the potential of the MVSS line rises above the threshold voltage of the NMOS transistor MN9, the NMOS transistor MN9 is turned on, and the potential of the MVSS line is clamped to the threshold voltage of the NMOS transistor MN9.

  At this time, in the NMOS transistors MN1 to MN4 of the memory cell MC, the p-well is biased to the ground voltage VSS and the source is biased to a positive voltage, so that the threshold voltage rises due to the substrate effect. As a result, the leakage current of the memory cell MC is reduced.

  Next, the operation of the semiconductor device according to the second embodiment will be described with reference to the timing chart shown in FIG.

  Referring to FIG. 8, the semiconductor device according to the second embodiment performs the same processing as the semiconductor device according to the first embodiment described above in order to test the data retention characteristics of memory cell MC in the low standby mode. Specifically, in the semiconductor device according to the second embodiment, data is first written to the memory cell MC to be tested (time t12 to t13), and the normal standby mode is set after the writing is completed (time). t13-t14). At this time, the bit lines BB and BT are precharged to the “H” level. In the write operation and in the normal standby mode, the MVSS line is set to the “L” level (ground voltage VSS).

  Next, when the normal standby mode is switched to the low standby test mode (time t14), in the semiconductor device according to the second embodiment, the control signal T2 is switched to the “L” level of the inactivation level, whereby the MVSS line Is pulled up from the “L” level to the “L + ΔL” level. This is to match the low standby mode. As a result, in the memory cell MC1, the potential of the storage node MB1 on the low potential side is pulled up from the “L” level to the “L + ΔL” level.

  In the low standby test mode (time t14 to t15), the potentials of the bit lines BB and BT are forcibly set to the “L” level. When a certain time elapses with the bit lines BB and BT fixed at the “L” level, the low standby test mode ends, and data held in the memory cell MC1 is read (time t15 to t16). Whether or not the memory cell MC1 is normal is determined based on changes in the potentials of the bit lines BB and BT.

  As described above, in the semiconductor device according to the second embodiment, the leakage current is reduced by pulling up the potential of the MVSS line to a potential higher than the “L” level (“L + ΔL” level) in the low standby mode. . In the low standby test mode in which the data destruction test in the low standby mode is performed, the potential of the MVSS line is pulled up and the potentials of the bit lines BB and BT are forcibly set to the “L” level. Thereby, the same effect as Embodiment 1 is acquired.

<Embodiment 3>
FIG. 9 is a circuit diagram showing a configuration of the semiconductor device according to the third embodiment. Since the overall configuration of the semiconductor device according to the third embodiment is the same as that of the general semiconductor device shown in FIG. 1, detailed description will not be repeated. The configuration of memory cell MC, bit line precharge circuit 60 and data write / read circuit 30 is also the same as that of FIG. 2, and therefore detailed description will not be repeated.

  Referring to FIG. 9, the semiconductor device according to the third embodiment is obtained by providing NMOS transistors MN11 and MN12, MVSS line and MVSS control circuit 70 in the circuit diagram shown in FIG. Since the configuration and operation of MVSS line and MVSS control circuit 70 are the same as those of the semiconductor device according to the second embodiment shown in FIG. 7, detailed description will not be repeated.

  The NMOS transistor MN11 has a drain connected to the MVSS line and a source connected to the bit line BB. The NMOS transistor MN12 has a drain connected to the MVSS line and a source connected to the bit line BT. The gates of the NMOS transistors MN11 and MN12 are both connected to the T1 line.

  Similarly to the first embodiment, control circuit / decoder 50 sets control signal T1 to the “H” level of the activation level in the low standby test mode. On the other hand, in the normal operation mode, normal standby mode, and low standby mode, control circuit / decoder 50 sets control signal T1 to the “L” level of the inactivation level. Thus, in the low standby test mode, the NMOS transistors MN11 and MN12 are turned on in response to the “H” level control signal T1, and the bit lines BB and BT are both electrically connected to the MVSS line.

  As described in the second embodiment, in the low standby test mode, the potential of the MVSS line is set to the potential difference ΔL corresponding to the threshold voltage of the NMOS transistor MN9 by the MVSS control circuit 70 rather than the “L” level. Pulled up to a high potential (L + ΔL). Therefore, the potentials of the bit lines BB and BT in the low standby test mode are also pulled up to the “L + ΔL” level.

  Next, the operation of the semiconductor device according to the third embodiment will be described using the timing chart shown in FIG.

  Referring to FIG. 10, the semiconductor device according to the third embodiment performs the same process as the semiconductor device according to the first and second embodiments described above in order to test the data retention characteristics of memory cell MC in the low standby mode. Do. Specifically, in the semiconductor device according to the third embodiment, data is first written to the memory cell MC to be tested (time t12 to t13), and the normal standby mode is set after the writing is completed (time). t13-t14).

  Next, when the normal standby mode is switched to the low standby test mode (time t14), in the semiconductor device according to the third embodiment, the potential of the MVSS line is changed from the “L” level as in the semiconductor device according to the second embodiment. Pulled up to “L + ΔL” level. As a result, the potential of storage node MB1 of memory cell MC1 is also pulled up from the “L” level to the “L + ΔL” level.

  Furthermore, in the semiconductor device according to the third embodiment, in the low standby test mode (time t14 to t15), the potentials of bit lines BB and BT are forcibly set according to control signal T1 activated to "H" level. “L + ΔL” level. That is, the bit lines BB and BT are fixed to the same potential as the storage node MB1 on the low potential side of the memory cell MC1. When a certain time elapses in this state, the low standby test mode ends, and data held in the memory cell MC1 is read (time t15 to t16). Whether or not the memory cell MC1 is normal is determined based on changes in the potentials of the bit lines BB and BT.

  As described above, in the semiconductor device according to the third embodiment, the potentials of bit lines BB and BT in the low standby test mode are fixed to the potential of storage node MB1 on the low potential side of memory cell MC1. This is different from the semiconductor device according to the second embodiment in which the potentials of the bit lines BB and BT in the low standby test mode are fixed to the ground voltage VSS. Due to this difference, the semiconductor device according to the third embodiment also has the following effects in addition to the effects of the semiconductor device according to the second embodiment.

  The effects produced by the semiconductor device according to the third embodiment will be described in detail below in comparison with the semiconductor device according to the second embodiment.

  FIG. 11 is a circuit diagram showing the main part of the semiconductor device according to the second embodiment. FIG. 12 is a circuit diagram showing the main part of the semiconductor device according to the third embodiment. First, a current leak path (FIG. 11A) formed in the low standby mode and a current leak path (FIG. 11B) formed in the low standby test mode will be described with reference to FIG. In the following description, it is assumed that storage nodes MB1 and MT1 of memory cell MC1 hold data of “H” level and “L + ΔL” level, respectively. Further, it is assumed that storage nodes MB2 and MT2 of memory cell MC2 hold data of “L + ΔL” level and “H” level.

  Referring to FIG. 11A, in the low standby mode, the potentials of storage node MB1 of memory cell MC1 and storage node MB2 of memory cell MC2 are different, and storage node MT1 of memory cell MC1 and memory cell MC2 When the potential of the storage node MT2 differs, a current leak path is formed between the memory cells MC1 and MC2 in addition to the inside of each memory cell MC.

  Specifically, a current leak path rt3 in which a leak current flows from the storage node MB1 to the MVSS line via the driver transistor MN1, and storage from the storage node MB1 via the access transistor MN3, the bit line BB, and the access transistor MN3 of the memory cell MC2 A current leak path rt4 in which a leak current flows in the node MB2 and a current leak path rt5 in which a leak current flows in the storage node MB2 via the load transistor MP1 are formed.

  Furthermore, a leakage current rt6 flows through the storage node MT1 via the load transistor MP2, and a leakage current flows from the storage node MT2 to the storage node MT1 via the access transistor MN4, the bit line BT, and the access transistor MN4 of the memory cell MC1. A flowing current leak path rt7 and a current leak path rt8 in which a leak current flows from the storage node MT2 to the MVSS line via the driver transistor MN2 are formed.

  On the other hand, referring to FIG. 11B, in the low standby test mode, NMOS transistors MN7 and MN8 are turned on, and bit lines BB and BT are fixed at "L" level (ground voltage VSS). . As a result, among the current leak paths rt3 to rt8, the current leak paths rt4 and rt7 formed between the memory cells MC1 and MC2 are respectively formed so that the leak current flows from the memory cell MC to the ground voltage VSS. , Rt10.

  Thus, in the semiconductor device according to the second embodiment, there is a difference in the amount of leak current flowing into the MVSS line between the low standby mode and the low standby test mode. Therefore, when the MVSS control circuit 70 that controls the potential of the MVSS line is configured to adjust the potential of the MVSS line in accordance with the amount of leakage current flowing through the MVSS line, the MVSS line in the low standby test mode The potential is set to a potential different from the potential of the MVSS line in the low standby mode. As a result, the data retention characteristic of the memory cell MC changes between the low standby test mode and the low standby mode, and it is difficult to accurately determine the data retention characteristic in the low standby mode.

  In contrast, in the semiconductor device according to the third embodiment, the potentials of bit lines BB and BT in the low standby test mode are fixed to the potential of the storage node on the low potential side of memory cell MC. As a result, the amount of leakage current flowing into the MVSS line is made equal in the low standby mode and in the low standby test mode.

  Specifically, referring to FIG. 12A, in the low standby mode, a current leak path is formed between memory cells MC1 and MC2 in addition to the inside of each memory cell MC. The current leak paths rt3 to rt8 shown in the figure are the same as the current leak paths rt3 to rt8 shown in FIG.

  Referring to FIG. 12B, in the low standby test mode, NMOS transistors MN7 and MN8 are turned on and bit lines BB and BT are electrically connected to the MVSS line. Thereby, the bid lines BB and BT are fixed to the “L + ΔL” level.

  With such a configuration, of the current leak paths rt3 to rt8, the current leak path rt4 formed between the memory cells MC1 and MC2 causes a leak current to flow from the memory cell MC1 to the MVSS line via the NMOS transistor MN11. The current leak path rt11 formed as described above is replaced. The current leak path rt7 is replaced with a current leak path rt12 formed so that a leak current flows from the memory cell MC2 to the MVSS line via the NMOS transistor MN12.

  That is, according to the semiconductor device of the third embodiment, since all the leakage current flows in the MVSS line in the low standby test mode, the amount of leakage current flowing in the MVSS line is the leakage current flowing in the MVSS line in the low standby mode. Is equal to the amount of current. Thereby, the MVSS control circuit 70 sets the potential of the MVSS line in the low standby test mode to the same potential as the potential of the MVSS line in the low standby mode. As a result, the data retention characteristics of the memory cells MC are equal in the low standby test mode and in the low standby mode, so that the data retention characteristics in the low standby mode can be accurately determined.

<Embodiment 4>
FIG. 13 is a circuit diagram showing a configuration of the semiconductor device according to the fourth embodiment. Since the overall configuration of the semiconductor device according to the fourth embodiment is the same as that of the general semiconductor device shown in FIG. 1, detailed description will not be repeated. The configuration of memory cell MC, bit line precharge circuit 60 and data write / read circuit 30 is also the same as that of FIG. 2, and therefore detailed description will not be repeated.

  Referring to FIG. 13, the semiconductor device according to the fourth embodiment is obtained by providing NMOS transistors MN11 and MN12, MVSS line and MVSS control circuit 70, and NMOS transistors MN13 and MN14 in the circuit diagram shown in FIG. . Since the configuration and operation of MVSS line and MVSS control circuit 70 are the same as those of the semiconductor device according to the second embodiment shown in FIG. 7, detailed description will not be repeated. The configuration and operation of NMOS transistors MN11 and MN12 are the same as those of the semiconductor device according to the third embodiment shown in FIG. 9, and therefore detailed description will not be repeated.

  The NMOS transistor MN13 has a drain connected to the bit line BB and a source connected to the VSS line. The NMOS transistor MN14 has a drain connected to the bit line BT and a source connected to the VSS line. The gates of the NMOS transistors MN11 and MN12 are both connected to a signal line (hereinafter also referred to as T3 line) for transmitting a control signal T3 from the control circuit / decoder 50.

  The control circuit / decoder 50 generates a control signal T3 that becomes the “H” level of the activation level for a predetermined time when the semiconductor device is switched to the low standby test mode. The generated control signal T3 is input to the gates of the NMOS transistors MN13 and MN14. When the NMOS transistors MN13 and MN14 receive the control signal T3 and are turned on for a predetermined time, the bit lines BB and BT are pulled down to the “L” level (ground voltage VSS) for a predetermined time.

  On the other hand, in the normal operation mode, the normal standby mode, and the low standby mode, control circuit / decoder 50 sets control signal T3 to the “L” level of the inactivation level.

  Next, the operation of the semiconductor device according to the fourth embodiment will be described using the timing chart shown in FIG.

  Referring to FIG. 14, the semiconductor device according to the fourth embodiment performs the same process as the semiconductor device according to the first to third embodiments to test the data retention characteristics of memory cell MC in the low standby mode. Do. Specifically, in the semiconductor device according to the fourth embodiment, data is first written to the memory cell MC to be tested (time t12 to t13), and the normal standby mode is set after the writing is completed (time). t13-t14).

  Next, when the normal standby mode is switched to the low standby test mode (time t14), in the semiconductor device according to the fourth embodiment, the control circuit / decoder 50 first sets the control signal T3 to the “H” level for a predetermined time. By activating, the bit lines BB and BT are pulled down to the “L” level (ground voltage VSS). Further, the control circuit / decoder 50 pulls up the potential of the MVSS line by setting the control signal T2 to the “L” level of the inactivation level.

  When the control signal T3 is switched from the “H” level to the “L” level (time t140), the control circuit / decoder 50 changes the control signal T1 to the activation level “H” level. As a result, the NMOS transistors MN11 and MN12 are turned on, and the bit lines BB and BT are both electrically connected to the MVSS line.

  At this time, in the MVSS line, the potential that has risen after time t14 is temporarily lowered to the “L” level by being connected to the bit lines BB and BT pulled down to the “L” level. Thereafter, the potential of the MVSS line continues to rise and reaches the “L + ΔL” level. The potentials of the bit lines BB and BT also receive the potential of the MVSS line and reach the “L + ΔL” level. When a certain time elapses in this state, the low standby test mode ends, and data held in the memory cell MC1 is read (time t15 to t16). Whether or not the memory cell MC1 is normal is determined based on changes in the potentials of the bit lines BB and BT.

  As described above, in the semiconductor device according to the fourth embodiment, at the time of switching from the normal standby mode to the low standby test mode, the bit lines BB, BT are temporarily set to the “L” level after the potentials of the bit lines BB, BT are temporarily set. The BT and MVSS lines are electrically connected. The effect of the semiconductor device according to the fourth embodiment will be described with reference to a comparative example shown in FIG.

  Referring to FIG. 15, at the time of switching from the normal standby mode to the low standby test mode (time t14), control circuit / decoder 50 sets bit line precharge signal CPC to the “H” level of the inactivation level. Thus, the precharge of the bit lines BB and BT is released. Further, the data write signal WC1 (not shown) is set to the “L” level of the inactivation level, and the data read signal RC1 is set to the “H” level of the inactivation level, whereby the bit line pair is set to the data write / It is electrically disconnected from the readout circuit 30. Since the bit lines BB and BT are in a floating state, the potentials of the bit lines BB and BT gradually decrease after time t14.

  Further, when switching to the low standby test mode (time t14), the control circuit / decoder 50 sets the control signal T2 to the “L” level of the inactivation level and pulls up the potential of the MVSS line. At subsequent time t140, control circuit / decoder 50 electrically connects bit lines BB, BT and MVSS lines by setting control signal T1 to the “H” level of the activation level.

  The potentials of the bit lines BB and BT gradually increase from the “H” level during the time from the time when switching to the low standby test mode (time t14) to the time when the bit lines BB, BT and MVSS lines are connected (time 140). descend. On the other hand, the potential of the MVSS line gradually increases toward the “L + ΔL” level. At this time, a leakage current may flow transiently between the bit lines BB and BT and the memory cell MC according to the potential difference between the bit lines BB and BT and the MVSS line.

  For example, when the potentials of the bit lines BB and BT are higher than the potential of the MVSS line, as shown in FIG. 15, from the bit line BB or BT toward the storage nodes MB1 and MB2 on the low potential side of the memory cells MC1 and MC2. Leakage current flows in temporarily. As a result, a phenomenon occurs in which the potentials of the storage nodes MB1 and MB2 temporarily increase. As a result, depending on the data retention characteristics of the memory cell MC, there is a possibility that the latch circuit is inverted and data destruction occurs.

  In order to avoid such a problem, in the semiconductor device according to the fourth embodiment, from the time of switching to the low standby test mode (time t14) to the time of connection of bit lines BB, BT and MVSS lines (time 140). In time, the bit lines BB and BT are pulled down to the “L” level (ground voltage VSS). Thereby, the potentials of the bit lines BB and BT can be surely made lower than the potential of the storage node on the low potential side of the memory cell MC, so that the above-described data destruction of the memory cell MC can be suppressed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, the configuration in which the bit lines BB and BB are fixed to the ground voltage VSS or the potential on the low potential side of the memory cell MC in the low standby test mode has been described. The point that the bit lines BB and BT in the low standby mode only need to be fixed to a predetermined potential will be described. Therefore, the bit lines BB and BT can be fixed to the “H” level (power supply voltage VDD) in the low standby test mode.

  10 memory cell array, 20 word line driver, 30 data write / read circuit, 32 write circuit, 34 read circuit, 50 control circuit / decoder, 60 bit line precharge circuit, 70 MVSS control circuit, MC memory cell, WL word Line, BB, BT Bit line.

Claims (7)

A semiconductor device having a normal operation mode and a standby mode as operation modes,
A plurality of memory cells arranged in a matrix;
A word line provided corresponding to each row of the memory cells;
A bit line pair provided corresponding to each column of the memory cells;
A control circuit for setting the word line to a non-selected state and setting the bit line pair to a floating state when executing the standby mode;
The semiconductor device further includes a test mode for performing a data destruction test when the standby mode is executed,
The control circuit is a semiconductor device in which the potential of the bit line pair is fixed to a predetermined potential when the test mode is executed.   The semiconductor device according to claim 1, wherein the control circuit puts the word line into a non-selected state when the test mode is executed. The plurality of memory cells include first and second storage nodes that hold potentials complementary to each other,
The semiconductor device according to claim 1, wherein the control circuit fixes the potential of the bit line pair to a potential of a storage node on a low potential side when the test mode is executed. A first transistor connected between the source line for supplying the potential on the low potential side and each bit line of the bit line pair;
4. The semiconductor device according to claim 3, wherein the control circuit turns on the first transistor when the test mode is executed. The source line is configured to supply a potential higher than a ground potential when the test mode is executed,
A second transistor connected between a ground node for supplying a ground potential and each bit line of the bit line pair;
When the test mode is executed, the control circuit temporarily turns on the second transistor, switches the second transistor from an on state to an off state, and then turns the first transistor on. The semiconductor device according to claim 4.   2. The semiconductor device according to claim 1, wherein the control circuit determines a data retention characteristic of the memory cell after a predetermined time has elapsed since the potential of the bit line pair was fixed to the predetermined potential. Each of the plurality of memory cells includes
First and second storage nodes that hold potentials complementary to each other;
A pair of cross-coupled inverters coupled to the first and second storage nodes;
A first transistor connected between the first storage node and one bit line of the bit line pair and having a gate connected to the word line;
2. The semiconductor device according to claim 1, comprising: a second transistor connected between the second storage node and the other bit line of the bit line pair and having a gate connected to the word line.

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