JP5125796B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a plurality of cascaded amplifier circuits.

  2. Description of the Related Art Conventionally, there is a semiconductor integrated circuit device having a plurality of stages of amplifier circuits connected in cascade to amplify a minute voltage signal.

  FIG. 7 shows a circuit configuration diagram of an example of a conventional semiconductor integrated circuit device. In the figure, a minute voltage signal input from a terminal 1 is supplied to an amplifier circuit 2 and amplified. The output signal of the amplifier circuit 2 is supplied to the monitor terminal 3 and also supplied to the amplifier circuit 4 and amplified. The output signal of the amplifier circuit 4 is supplied to the monitor terminal 5 and is also supplied to the amplifier circuit 6 and amplified. The output signal of the amplifier circuit 6 is supplied to the monitor terminal 7 and is output from the terminal 9 through the switch 8.

It is known that a plurality of amplifier circuits constituting a multistage amplifier are provided, and the output of each amplifier circuit is switched and output by a switch (see, for example, Patent Document 1).
JP-A-8-18348

  Conventionally, a test voltage is input to a terminal 1 from a measuring device, and the voltages of the terminals 3, 5, and 7 are monitored by the measuring device, and each of the amplifier circuits 2, 4, and 6 is evaluated.

  Here, when the voltage gain of the amplifier circuit 2 is A1, the voltage gain of the amplifier circuit 4 is A2, the voltage gain of the amplifier circuit 6 is A3, and the input voltage at the terminal 1 is vin, each of the amplifier circuits 2, 4, 6 The monitor voltages vamp1, vamp2, and vamp3 output from are expressed by the following equations.

vamp1 = A1 × vin (1a)
vamp2 = A1 × A2 × vin (2a)
vamp3 = A1 × A2 × A3 × vin (3a)
For this reason, the following equation is obtained.

vin = vamp1 / A1 (1b)
vin = vamp2 / (A1 × A2) (2b)
vin = vamp3 / (A1 × A2 × A3) (3b)
Here, since the maximum value of the monitor voltage vamp3 is limited by the dynamic range of the amplifier circuit 6, it is necessary to make the input voltage vin extremely small when evaluating the amplifier circuit 6 in the subsequent stage.

  However, there is a case where the input voltage vin of a desired small signal cannot be generated depending on the measuring device. In such a case, there is a problem that the amplifier circuit 6 cannot be evaluated.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit device capable of evaluating a subsequent stage amplifier circuit connected in cascade.

A semiconductor integrated circuit device according to an embodiment of the present invention is a semiconductor integrated circuit device including a plurality of amplifier circuits connected in cascade.
A switch (14, 15) provided between each of the plurality of amplifier circuits (11, 12, 13);
It is connected to a connection point between the switch (14, 15) and the input terminal of the subsequent amplifier circuit (12, 13), and when the switch (14, 15) is turned on, the plurality of amplifier circuits (11, 12, The external terminals (22) are in an output state in which the output signal of 13) is output, and in which the input signal is input to the amplifier circuit (12, 13) subsequent to the switch when the switch (14, 15) is turned off. , 23, 24)
On / off control is performed by supplying a control signal to each of the switches (14, 15).

A semiconductor integrated circuit device according to another embodiment of the present invention is a semiconductor integrated circuit device including a plurality of cascaded amplifier circuits.
A plurality of external terminals (62, 63, 64) connected to output terminals of the plurality of amplifier circuits (51, 52, 53);
Wherein the plurality of one of the amplifier circuits (51, 52, 53), said one of the amplifier circuit and an output terminal to a high impedance state when the control signal indicates the operation stop is supplied to the respective (51, 52 The external terminals (62, 63) connected to the output terminals of () are set in the input state, and when the control signal instructs an operation, the external terminals (51, 52) connected to the output terminals of any one of the amplifier circuits (51, 52) 62, 63) is the output state .

  Preferably, each of the amplifier circuit (11, 12, 13) and the switch (14, 15) is composed of a MOS transistor circuit.

  Preferably, any one (13) of the plurality of amplifier circuits has a variable gain.

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, it is possible to evaluate a subsequent stage amplifier circuit connected in cascade.

<First Embodiment>
FIG. 1 is a circuit configuration diagram of a first embodiment of a semiconductor integrated circuit device according to the present invention. In the figure, a semiconductor integrated circuit device 10 has amplifier circuits 11, 12, 13 connected in cascade. Each of the amplifier circuits 11, 12, and 13 includes an operational amplifier OPA to which a signal is input to a non-inverting input terminal and two resistors R1 to R6 for setting the amplification degree are connected to the inverting input terminal.

  Of the two resistors of the amplifier circuit 13, the resistor R6 to which the reference voltage Vref is supplied is a variable resistor, and the gain of the amplifier circuit 13 can be varied.

  A switch 14 is provided between the amplifier circuits 11 and 12, and a switch 15 is provided between the amplifier circuits 12 and 13. A switch 16 is provided between the amplifier circuit 13 and the external terminal 20.

  A minute voltage signal input from the external terminal 21 of the semiconductor integrated circuit device 10 is supplied to the amplifier circuit 11 and amplified. The output signal of the amplifier circuit 11 is supplied to the monitor external terminal 22 through the switch 14 and also supplied to the amplifier circuit 12 and amplified. The output signal of the amplifier circuit 12 is supplied to the monitor external terminal 23 through the switch 15 and also supplied to the amplifier circuit 13 and amplified. The output signal of the amplifying circuit 13 is supplied to the external terminal 24 for monitoring, is output from the terminal 20 through the switch 16, and is supplied to the control unit 30.

  The external terminal 25 of the semiconductor integrated circuit device 10 is connected to the positive electrode of the constant voltage circuit 17. A control signal is supplied from the control unit 30 to the external terminals 26, 27, and 28 and supplied to the switches 14, 15, and 16, respectively.

  The control unit 30 controls the switches 14, 15, and 16 of the semiconductor integrated circuit device 10 and performs A / D conversion of signals supplied from the external terminal 20 of the semiconductor integrated circuit device 10 and other circuits (not shown). Import it and execute various processes. The switch 16 is turned on when the control unit 30 captures an output signal of the semiconductor integrated circuit device 10 and is turned off when a signal from another circuit is captured.

  FIG. 2 is a circuit configuration diagram of the first embodiment of the operational amplifier OPA used in the amplifier circuits 11, 12, and 13. In the figure, p-channel MOSFETs (hereinafter referred to as MOS transistors) M1 and M2 and resistors R10 and R11 constitute a first differential circuit that differentially amplifies by receiving input signals from terminals 41 and 42. The MOS transistors M3 and M4 and the n-channel MOS transistors M5 and M6 constitute a second differential circuit that is supplied with the output of the first differential circuit and differentially amplifies it. The n-channel MOS transistor M7 amplifies the output of the second differential circuit by a class A operation and outputs it from the terminal 43.

  The terminals 45 and 46 are supplied with the power supply voltage Vcc and the ground voltage GND. The constant current circuit 48, p-channel MOS transistors M8, M9, M10, and M11 having a current mirror configuration, n-channel MOS transistors M12 and M13 having a current mirror configuration, and p-channel MOS transistors M14 and M15 having a current mirror configuration are configured as a first differential. The circuit, the second differential circuit, and the power supply circuit for supplying the operating current to the MOS transistor M7 are configured.

  FIG. 3 shows a circuit configuration diagram of an embodiment of the switches 14, 15, 16. In the figure, the source and drain of a p-channel MOS transistor M16 and an n-channel MOS transistor M17 are connected between an input terminal a and an output terminal b.

  The control terminal c is connected to the gate of the MOS transistor M17 and is connected to the gate of the MOS transistor M16 through the inverter 49, and the MOS transistors M16 and M17 constitute a transmission gate. When a high level signal is supplied to the control terminal c, the terminals a and b are brought into conduction, and when a low level signal is supplied to the control terminal c, the terminals a and b are cut off.

  FIG. 4 is a diagram for explaining switch control by the control unit 30. In the figure, in the normal mode, the switches 14 and 15 are both turned on by a control signal supplied from the control unit 30 to the external terminals 26 and 27, and all the external terminals 22, 23 and 24 are in the output state.

  In the test mode 1, the switch 14 is turned on, the switch 15 is turned off, the external terminal 22 is in the output state, the external terminal 23 is in the input state, the external terminal 24 is in the output state, and the input signal from the external terminal 21 is amplified. Through the external terminal 22 and an input signal from the external terminal 23 through the amplifier circuit 13 and output from the external terminal 24, so that each of the amplifier circuits 11 and 13 can be evaluated as a single unit.

  In the test mode 2, the switch 14 is turned off, the switch 15 is turned on, the external terminal 22 is in the input state, the external terminals 23 and 24 are in the output state, and the input signal from the external terminal 22 is passed through the amplifier circuit 12 from the external terminal 23. It is possible to evaluate the amplification circuit 12 alone.

  In the test mode 3, the switch 14 is turned off, the switch 15 is turned off, the external terminal 22 is in the input state, the external terminal 23 is in the input state, the external terminal 24 is in the output state, and the input signal from the external terminal 23 is amplified. The output from the external terminal 24 is made possible, and the amplification circuit 13 can be evaluated as a single unit.

  Thus, since each of the amplifier circuits 11, 12, and 13 can be evaluated alone, it is not necessary to set the test input voltage to a very small voltage, and the test voltage can be generated even in an existing measuring instrument.

Second Embodiment
FIG. 5 shows a circuit configuration diagram of a second embodiment of the semiconductor integrated circuit device of the present invention. In the figure, the same parts as those in FIG. In FIG. 5, the semiconductor integrated circuit device 50 includes amplifier circuits 51, 52, and 53 connected in cascade. Each of the amplifier circuits 51, 52, and 53 includes an operational amplifier OPA to which a signal is input to a non-inverting input terminal and two resistors R1 to R6 that set the amplification degree are connected to the inverting input terminal.

  Of the two resistors of the amplifier circuit 53, the resistor R6 to which the reference voltage Vref is supplied is a variable resistor, and the gain of the amplifier circuit 53 can be varied. A switch 56 is provided between the amplifier circuit 53 and the external terminal 60.

  A minute voltage signal input from the external terminal 61 of the semiconductor integrated circuit device 50 is supplied to the amplifier circuit 51 and amplified. The output signal of the amplifier circuit 51 is supplied to the monitor external terminal 62 and also supplied to the amplifier circuit 52 and amplified. The output signal of the amplifier circuit 52 is supplied to the monitor external terminal 63 and also supplied to the amplifier circuit 53 and amplified. The output signal of the amplifying circuit 53 is supplied to the external terminal 64 for monitoring, is output from the terminal 60 through the switch 56, and is supplied to the control unit 30.

  The external terminal 65 of the semiconductor integrated circuit device 50 is connected to the positive electrode of the constant voltage circuit 57. A control signal is supplied from the control unit 30 to the external terminals 66, 67, and 68 and supplied to the amplifier circuits 51 and 52 and the switch 56, respectively.

  The control unit 30 controls the amplifier circuits 51 and 52 and the switch 56 of the semiconductor integrated circuit device 50 and performs A / D conversion of signals supplied from the external terminal 60 of the semiconductor integrated circuit device 50 and other circuits not shown. Go to the inside and execute various processes. The switch 56 is turned on when the control unit 30 captures an output signal of the semiconductor integrated circuit device 50, and is turned off when a signal from another circuit is captured.

  FIG. 6 shows a circuit configuration diagram of the second embodiment of the operational amplifier OPA used in the amplifier circuits 51, 52, and 53. In the figure, the same parts as those in FIG.

  In FIG. 6, p-channel MOSFETs M1 and M2 and resistors R10 and R11 constitute a first differential circuit that differentially amplifies by receiving input signals from terminals 41 and 42, and includes p-channel MOS transistors M3 and M4 and an n-channel MOS. The transistors M5 and M6 constitute a second differential circuit that is supplied with the output of the first differential circuit and differentially amplifies it. The n-channel MOS transistor M7 amplifies (class A operation) the output of the second differential circuit and outputs it from the terminal 43.

  The terminals 45 and 46 are supplied with the power supply voltage Vcc and the ground voltage GND. The constant current circuit 48, p-channel MOS transistors M8, M9, M10, and M11 having a current mirror configuration, n-channel MOS transistors M12 and M13 having a current mirror configuration, and p-channel MOS transistors M14 and M15 having a current mirror configuration are configured as a first differential. The circuit, the second differential circuit, and the power supply circuit for supplying the operating current to the MOS transistor M7 are configured.

  A control signal is supplied to the terminal 70. The control signal is supplied to the gates of the p-channel MOS transistors M20 and M21, inverted by the inverter 72, and supplied to the gate of the n-channel MOS transistor M22.

  The source and drain of the MOS transistor M20 are connected to the source and drain of the MOS transistor M8, respectively. When the control signal is at a high level, the MOS transistor M20 is cut off and the MOS transistor M8 is turned on to bring the power supply circuit into an operating state. When the control signal is at a low level, the MOS transistor M20 is turned on, the source and drain of the MOS transistor M8 are short-circuited, and the power supply circuit is deactivated.

  The source and drain of the MOS transistor M21 are connected to the source and drain of the MOS transistor M14, respectively. When the control signal is at a high level, the MOS transistor M21 is cut off, the MOS transistor M14 is turned on, and the power supply circuit that supplies an operating current to the MOS transistor M15 is set in an operating state. When the control signal is at a low level, the MOS transistor M21 conducts, the source and drain of the MOS transistor M14 are short-circuited, and the power supply circuit is deactivated.

  The source and drain of the MOS transistor M22 are connected to the sources and drains of the MOS transistors M5 to M7, respectively. When the inversion control signal is at a low level (the control signal is at a high level), the MOS transistor M22 is cut off, the MOS transistor M5 is turned on, and the power supply circuit that supplies an operating current to the MOS transistors M5 to M7 is set in an operating state. When the inversion control signal is at a high level (the control signal is at a low level), the MOS transistor M22 is turned on, the source and drain of the MOS transistor M5 are short-circuited, and the power supply circuit is inactivated.

  As a result, the operational amplifier OPA of the amplifier circuits 51 and 52 operates when the control signal is high level, and the operational amplifier OPA of the amplifier circuits 51 and 52 stops operating when the control signal is low level and the output terminal is in the high impedance state. Become. A high level fixed control signal is supplied to the amplifier circuit 53.

  Therefore, as in FIG. 3, in the normal mode, the amplifier circuits 51 and 52 operate together with the control signal supplied from the control unit 30 to the external terminals 66 and 67, and the external terminals 62, 63 and 64 are all in the output state. Become.

  In test mode 1, the amplifier circuit 51 is in the operating state, the amplifier circuit 52 is in the non-operating and output high impedance state, the external terminal 62 is in the output state, the external terminal 63 is in the input state, and the external terminal 64 is in the output state. The input signal from 61 is output from the external terminal 62 through the amplifier circuit 51, and the input signal from the external terminal 63 is output from the external terminal 64 through the amplifier circuit 53, so that each of the amplifier circuits 61 and 63 can be evaluated as a single unit.

  In the test mode 2, the amplifier circuit 51 is inactive and in the output high impedance state, the amplifier circuit 52 is in the operating state, the external terminal 62 is in the input state, the external terminals 63 and 64 are in the output state, and the input signal from the external terminal 62 is Is output from the external terminal 63 through the amplifier circuit 52, and the amplification circuit 52 can be evaluated alone.

  In the test mode 3, the amplifier circuits 51 and 52 are inactive and in the output high impedance state, the external terminal 62 is in the input state, the external terminal 63 is in the input state, the external terminal 64 is in the output state, and the input signal from the external terminal 63 Is output from the external terminal 64 through the amplifier circuit 53, and the amplification circuit 53 can be evaluated as a single unit.

  As described above, since each of the amplifier circuits 51, 52, and 53 can be evaluated independently, it is not necessary to set the test input voltage to a very small voltage, and the test voltage can be generated even in an existing measuring instrument. In addition, since it is not necessary to provide a switch between the amplifier circuits 51, 52, and 53, the number of electronic components can be reduced.

  In the above embodiment, three stages of amplifier circuits are cascaded, but the number of cascaded amplifier circuits may be two or four or more, and is limited to the above embodiment. is not.

1 is a circuit configuration diagram of a first embodiment of a semiconductor integrated circuit device of the present invention. It is a circuit block diagram of 1st Embodiment of an operational amplifier. It is a circuit block diagram of one Embodiment of a switch. It is a figure for demonstrating switch control. It is a circuit block diagram of 2nd Embodiment of the semiconductor integrated circuit device of this invention. It is a circuit block diagram of 2nd Embodiment of an operational amplifier. It is a circuit block diagram of an example of the conventional semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 50 Semiconductor integrated circuit device 11, 12, 13, 51, 52, 53 Amplifier circuit 14-16, 56 Switch 17, 57 Constant voltage circuit 30 Control part

Claims (4)

In a semiconductor integrated circuit device having a plurality of amplifier circuits connected in cascade,
A switch provided between each of the plurality of amplifier circuits;
The switch is connected to a connection point between the switch and the input terminal of the amplifier circuit in the subsequent stage, and is in an output state in which output signals of the plurality of amplifier circuits are output when the switch is turned on. Having a plurality of external terminals in an input state for inputting an input signal to the amplifier circuit ;
A semiconductor integrated circuit device that performs on / off control by supplying a control signal to each of the switches. In a semiconductor integrated circuit device having a plurality of amplifier circuits connected in cascade,
A plurality of external terminals connected to output terminals of the plurality of amplifier circuits;
Wherein any of the plurality of amplifier circuits, input a connected external terminal an output terminal to an output terminal of said one of the amplifier circuit to the high impedance state when the control signal supplied to each of which instructs the operation stop A semiconductor integrated circuit device, wherein an external terminal connected to an output terminal of any one of the amplifier circuits is set to an output state when the control signal instructs an operation . The semiconductor integrated circuit device according to claim 1.
Each of the amplifier circuit and the switch is composed of a MOS transistor circuit. The semiconductor integrated circuit device according to claim 3.
The semiconductor integrated circuit device according to any one of the plurality of amplifier circuits, wherein the gain is variable.

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