JP5125482B2 - Receiver, control method and program - Google Patents

Description

  The present invention relates to a receiver, a control method, and a program for reducing power consumption.

Patent Document 1 discloses a synchronization signal detection device that reduces power consumption (paragraph 0007 of Patent Document 1). The synchronization signal detection apparatus includes a correlation detection unit that detects reception timing of an FSW (Frame Synchronized Word) from a correlation value between a reception signal and a reference FSW, a bit string of the reception signal, and a bit string of a reference FSW And an error bit number detection unit that detects the error bit number based on the error bit number (reference numerals 11 and 12 in FIG. 2 of Patent Document 1 are correlation detection units, and reference numerals 13 and 14 are error bit number detection units. Normally, the detection timing of the FSW is detected by a correlation detection unit with low power consumption, and detection by the error bit number detection unit is performed only when detection by the correlation detection unit is difficult (Patent Document 1). Paragraph 0059).
JP 2004-40222 A

  The synchronization signal detection apparatus in Patent Document 1 uses a correlation detection unit instead of the error bit number detection unit to reduce power consumption. This is because the correlation detection unit itself or the error bit number detection unit itself receives the received signal. It is not a power-saving type according to the reception state.

  On the other hand, in the receiver, various processes are performed to achieve the function, but the predetermined process is performed in a period where the remaining battery power is sufficient, and is not performed in a period where the remaining battery power is low. It is often performed to save power while allowing performance degradation due to non-implementation, but depending on the reception status of the received signal while obtaining the appropriate processing result for the predetermined processing It does not reduce power consumption.

  An object of the present invention is to provide a receiver, a control method, and a program that can save power while ensuring an appropriate processing result.

  According to the present invention, for example, when the reception state of a reception signal is good, attention is paid to a predetermined process that can shorten the processing time required to obtain a predetermined accuracy of the processing result. Then, in a period in which the reception state of the received signal is good, the process is completed quickly.

The receiver of the present invention has a good reception state on the basis of the processing execution means for performing the recovery processing of the clock for synchronization detection, the difference in symbol rate between the transmitter and the receiver, and the electric field strength of the received signal. A period in which the condition is satisfied on the condition that the electric field strength is equal to or greater than a first threshold and the difference between the symbol rates is less than the second threshold continuously for a predetermined number of times or more. Is detected as a period with a high degree of goodness, and in the period with the high degree of goodness, the execution frequency of the reproduction processing of the clock for synchronization detection by the processing execution unit is decreased, and the condition is not satisfied Operation period control means for shortening the operation time of the processing execution means compared to a period of low goodness.

According to the receiver control method of the present invention , the reception state is based on the processing execution step of performing the recovery processing of the synchronization detection clock, the difference in symbol rate between the transmitter and the receiver, and the electric field strength of the received signal. The condition is satisfied on the condition that the electric field strength is equal to or higher than the first threshold and the difference between the symbol rates is continuously lower than the second threshold for a predetermined number of times or more. In the goodness detection step for detecting the period as a high goodness period, and in the high goodness period, the frequency of performing the synchronization detection clock regeneration processing in the processing execution step is decreased, and the condition is satisfied. An operation period control step for shortening the operation time of the processing execution step than a period of low goodness.

  The program of the present invention causes a computer to function as each means of the above-described receiver of the present invention.

  According to the present invention, during a period in which the reception state of the received signal is good, the processing time for the predetermined processing can be shortened, so that the power consumption can be suppressed for the shortened amount.

  FIG. 1 is a block diagram of a reception system of the radio device 10. The wireless device 10 is a digital wireless device equipped with not only a receiver but also a transmitter function, but the transmission system is not shown in FIG. The wireless device 10 is also compliant with APCO P25 (APCO Project 25). In FIG. 1, a signal path indicated by a broken line, a reception state determination processor 30 and a DSP operation clock controller 31 are added to the conventional reception system.

  A radio wave of a digital modulation signal such as quaternary FSK or π / 4 shift QPSK is captured by the antenna 11 and is supplied to the detector 12 as an RF signal. The detector 12 extracts an RF signal having a frequency corresponding to the selected channel and supplies the detected signal to the baseband filter 13. The detector 12 also supplies a signal related to the RF signal having a frequency corresponding to the selected channel to an RSSI (Receiving Signal Strength Indicator) detector 14, and the RSSI detector 14 is configured based on the supplied signal. The RSSI of the RF signal is detected.

  The baseband filter 13 sends a detection signal obtained by sufficiently removing the detection signal related to the channel adjacent to the selected channel to the symbol determination unit 18, the clock regenerator 19 and the FS (frame synchronization) detection processor 20. The clock regenerator 19 regenerates a clock signal for symbol value detection based on the detection signal from the baseband filter 13 and supplies it to the symbol determiner 18. The symbol determiner 18 extracts a symbol value from the detection signal from the baseband filter 13 at a timing based on the clock signal from the clock regenerator 19.

  The FS detection processor 20 performs FS detection so as to know where the synchronization detection timing is in the bit string from the symbol determiner 18 to the CAI (Common Air Interface) decode processor 24. The CAI decode processor 24 performs CAI decode processing on the bit string from the symbol determiner 18 to generate audio data and sends it to the vocoder decode processor 25. In this CAI decoding process, error detection and error correction are performed based on FEC (Forward Error Correction).

  The vocoder decoding processor 25 decodes the audio data from the CAI decoding processor 24, converts it into an analog audio signal, and supplies it to the speaker 26. Thus, the other party's voice is output from the speaker 26.

  The reception state determination processor 30 is supplied with predetermined information from the RSSI detector 14, the clock regenerator 19 and the FS detection processor 20, and based on these information, the clock regenerator 19, the FS detection processor 20 and the DSP operation clock control. A control signal is sent to the device 31. The clock regenerator 19 and the FS detection processor 20 based on the information sent from the RSSI detector 14, the clock regenerator 19 and the FS detection processor 20 to the reception state determination processor 30 and the control signal from the reception state determination processor 30. The operation of the DSP operation clock controller 31 will be described with reference to FIGS.

  FIG. 2 is a schematic explanatory diagram of a power saving method adopted in the radio device 10. The power saving method is divided into two, reception state determination processing S1 and reception state setting processing S2. The reception status determination process S1 further includes a reception status detection step for confirming the reception status and a reception status determination step based on the reception status. The reception state setting process S2 is performed based on the determination result of the reception state determination process S1.

  Examples of the reception status in the reception state determination processing S1 include RSSI, FS detection processing, clock recovery processing, symbol determination processing, and the number of FEC error bits.

  In the wireless device 10, the good reception state corresponds to, for example, the following state. However, the state corresponding to the good reception state varies depending on the modulation scheme and protocol used.

(A) The electric field strength of the received signal is good.
(B) The difference between the reference oscillation frequency of the transmitter and the reference oscillation frequency of the receiver is small. Note that the reference oscillation frequency is a base clock (VCXO: Voltage Controlled Xtal Oscillator) that each terminal of the transmitter or receiver individually has, and causes a shift (phase difference) of the symbol clock for each terminal. Hereinafter, the “difference between the reference oscillation frequency of the transmitter and the reference oscillation frequency of the receiver” will be referred to as “the difference in symbol rate between the transmitter and the receiver” as appropriate.
(C) The bit error rate is low.

  The signal level of the radio frequency can be evaluated by RSSI. In general, if RSSI is good, the bit error rate may be low, and it becomes easy to accurately detect the difference in symbol rate between the transmitter and the receiver. Therefore, as an example of this method, first, the RSSI is evaluated, and then it is determined whether or not the state is (b) or (c). The states of (b) and (c) can be detected through the FS detection process mentioned as the reception status.

  In the FS detection process, a method of performing detection determination by comparing a frame synchronization bit string serving as a reference and a bit string of a received signal is generally used. Can be evaluated.

  Since error detection and correction are generally performed by FEC in CAI decoding processing, the bit error rate according to (c) can also be evaluated from error detection during FEC decoding processing.

  In the reception state setting process S2, the determination parameters of the frame synchronization detection process and the clock recovery process are changed using the reception state determination result obtained in the reception state determination process S1.

  In frame synchronization detection, the number of symbols used for determination can be reduced when frame synchronization is detected according to the bit error rate. If the bit error rate is low, the frame synchronization bit error rate will also be low, and the possibility of erroneous detection by frame synchronization detection will also be low, so even if the number of symbols used in the frame synchronization detection process is reduced moderately The synchronization detection performance is considered to have almost no effect. In general, the frame synchronization detection process is performed by obtaining a correlation with reference data or obtaining a bit error rate with reference bit data. Therefore, if the number of symbols in the frame synchronization detection process can be reduced, the processing load can be reduced at a rate corresponding to the reduced number of symbols in the correlation process, the symbol determination process, and the bit error determination process.

  In clock recovery, the frequency of clock recovery processing is adjusted according to the difference in symbol rate between the transmitter and the receiver. For example, when the difference is small, it can be considered that the frequency can be sufficiently followed even if the frequency of clock recovery is moderately reduced. There is no. If the frequency of the clock recovery process can be halved, for example, the processing load in the clock recovery can be reduced to about ½.

  FIG. 3 is a flowchart of the wireless device power saving control method 35. The wireless device power saving control method 35 is performed in the reception state determination processor 30 in accordance with the power saving method described in FIG. The radio device power saving control method 35 is performed every time each frame is received. In S36, the electric field strength of the received signal is acquired based on the detection signal of the RSSI detector 14. In S37, it is determined whether the reception state of the received signal is good based on the acquired electric field strength. If the determination is positive, the process proceeds to S38, and if not, the process proceeds to S43.

  In S38, a difference in symbol rate between the transmitter and the radio 10 is detected based on the input signal from the clock regenerator 19. As described above, the difference in symbol rate between the transmitter and the radio device 10 is caused by the difference in the oscillation frequency between the reference oscillation signal in the transmitter and the reference oscillation signal in the radio device 10. . The reference oscillation signal in the radio device 10 is involved in the clock recovery of the clock regenerator 19, and the symbol rate difference between the transmitter and the radio device 10 as the receiver is detected from the correction amount of the clock signal in the clock regenerator 19. be able to. It means that the larger the correction amount or the greater the number of corrections, the greater the difference in symbol rate between the transmitter and the radio 10 as the receiver.

  In S42, it is determined whether or not the symbol rate difference acquired in S38 has the same tendency as the previous time. If the determination is positive, the process proceeds to S46, and if not, the process proceeds to S43. The symbol rate difference acquired in S38 has the same tendency as the previous time. For example, the symbol rate difference acquired in S38 for the current frame and the symbol rate difference acquired in S38 for the previous frame are both less than a predetermined threshold α. It is supposed to be. A positive determination in S38 means that the reception state of the received signal is good for both the previous and current frames.

  In S43, the determination parameters set for the clock regenerator 19, the FS detection processor 20, and the DSP operation clock controller 31 in the reception state determination processor 30 are reset and returned to their initial values. When the determination parameter of the clock regenerator 19 is set to an initial value, the reception state determination processor 30 maintains the clock regenerator 19 in an always operating state. As a result, the clock regenerator 19 always executes a timing correction process for the recovered clock.

  When the determination parameter of the FS detection processor 20 is set to an initial value, the reception state determination processor 30 performs bit error determination from the first bit to the last bit for the frame synchronization word extracted from the received signal. The FS detection processor 20 is maintained in the operating state until the end. Thereby, the FS detection processor 20 counts the number of error bits during the input period of all the bits of the frame synchronization word, and if the number of error bits is less than the predetermined threshold E, it is assumed that the frame synchronization word is detected. . When the determination parameter of the DSP operation clock controller 31 is set to an initial value, the reception state determination processor 30 issues an instruction to the DSP operation clock controller 31 to set the operation clock frequency to the maximum value. The clock pulse generated by the DSP operation clock controller 31 is used for the operation timing of a DSP (Digital Signal Processor). As the operation clock frequency increases, the DSP processing capability increases and the power consumption of the DSP also increases.

  In S46, it is determined whether or not the last consecutive N (N ≧ 3) times including the current symbol rate difference have the same tendency with respect to the symbol rate difference acquired in S38. If the determination is positive, the process proceeds to S47. If not, the process proceeds to S48. The same tendency means that, similarly to the same tendency in S42, the symbol rate difference of each time is less than a predetermined threshold value α, and the determination in S47 is positive that all of the N most recent symbol rate differences are predetermined. It is less than the threshold value α.

  In S47, the determination parameter set for the clock regenerator 19 in the reception state determination processor 30 is set to the operation frequency corresponding to the difference in symbol rate. As the symbol rate difference is smaller, the operating frequency of the clock regenerator 19 is decreased, and the stop period of the clock regenerator 19 is increased, thereby saving power. Illustrative specific numerical values for the operating frequency are as follows. As an example, in the APCO P25 system (4800 sps (Symbol Per Second)), the following settings are made. The following values are obtained with 0.05 symbol as the symbol clock to be adjusted in one clock recovery process.

When the symbol rate difference is ± 8 sps to ± 4 sps, once every 30 symbols. When the symbol rate difference is ± 4 sps to ± 2 sps, once every 60 symbols. The symbol rate difference is ± 2 sps to ± 1 sps. Once in 120 symbols-Once in 240 symbols if the symbol rate difference is within ± 1 sps

  In S48, the bit error rate in the frame synchronization detection process of the FS detection processor 20 is acquired. The frame synchronization detection process includes a process in which the bit value of the received signal is compared with a given, ie, reference, frame synchronization word bit, and the bit error rate can be obtained based on this comparison. In S49, the bit error rate in FEC error detection of the CAI decode processor 24 is acquired.

  In S50, it is determined whether or not the bit error rate acquired in S48 and S49 has the same tendency as the previous time. If the determination is positive, the process proceeds to S50, and if not, the process proceeds to S43. The bit error rate acquired in S48, 49 has the same tendency as the previous time, for example, the bit error rate β1, γ1 acquired in S48, S49 for the current frame and the bit error acquired in S48, 49 for the previous frame. It is assumed that the rates β2 and γ2 are both less than predetermined threshold values βo and γo (β1 <βo, β2 <βo, γ1 <γo, γ2 <γo). A positive determination in S48 and S49 means that the reception state of the reception signal is good both in the previous time and this time.

  In S54, it is determined whether or not the last consecutive N frames including this time have the same tendency with respect to the bit error rate acquired in S48 and S49. If the determination is positive, the process proceeds to S55. Then, the radio power saving control method 35 is terminated. The same tendency means that, similarly to the same tendency in S50, it means that it is less than the predetermined threshold values βo and γo. In S47, all bit error rates for the N most recent frames are predetermined for both the β and γ sequences. Is less than the threshold value βo and less than γo. In this embodiment, both S46 and S54 determine the latest N times, but the number of consecutive times of S46 and S54 may be different from each other.

  In S55, the determination parameter set for the FS detection processor 20 in the reception state determination processor 30 is set to the number of symbols corresponding to the bit error rate. As the bit error rate is lower, the number of symbols (= number of bits) that are subject to bit error determination in the FS detection processor 20 is decreased. That is, when the determination parameter is set to the initial value in S43, the number of bits subject to bit error determination in the FS detection processor 20 is all from the first bit to the last bit of the frame synchronization word. On the other hand, in the parameter changed by the process of S55, the number of bits subject to bit error determination in the FS detection processor 20 is the number of bits from the first bit of the frame synchronization word to the intermediate predetermined bit, Decrease.

  For example, if the bit error rate is not 0%, it is determined that the reception state is in a bad period, and all bits of the frame synchronization word are subject to error determination. On the other hand, if the bit error rate is N consecutive times and 0%, it is assumed that the reception state is good, and in the next frame, the number of bits subject to error determination is the first in the frame synchronization word. Reduce to half of the bit to the middle bit. Since the frame length is known, synchronization can be detected without any trouble even if the number of bits subject to error determination is reduced. On the other hand, if one of the N bit error rates is not 0%, or if this time is the first synchronization detection, all bits of the frame synchronization word are subject to error determination. As the number of bits subject to bit error determination in the frame synchronization detection process is reduced, the power consumption of the FS detection processor 20 is reduced.

  After S55, the radio power saving control method 35 is terminated. Before the wireless device power saving control method 35 ends, that is, after the determination in S54 is negative, or after the execution of S55, before the wireless device power saving control method 35 ends, the reception state determination processor 30 It is possible to add a step of changing the determination parameter for the operation clock of the DSP operation clock controller 31 in accordance with the reduction of the processing load of the DSP. With the execution of S47 and S55, the load on the DSP is reduced. Therefore, even if the frequency of the DSP operation clock is lowered, there is little problem in the DSP processing. Therefore, when S47 and / or S55 is executed, the frequency of the DSP operation clock is reduced in accordance with the accompanying decrease in the DSP load. Thereby, the power consumption of the DSP can be reduced without hindering its operation.

  FIG. 4 is a block diagram of the receiver 60. The above-described wireless device 10 is an example of the receiver 60. The receiver 60 is typically portable, but may be stationary. The receiver 60 is typically equipped with a rechargeable battery as a power source, but may be equipped with a dry battery instead of a rechargeable battery, or may be driven by a commercial power source. The receiver 60 may be a mobile phone. The receiver 60 includes processing execution means 61, goodness degree detection means 62, and operation period control means 63.

  The process execution means 61 performs a predetermined process. The goodness detection means 62 detects the goodness of the reception state of the received signal. The operation period control means 63 shortens the operation period of the process execution means 61 in the period with high goodness than in the low period.

  The operation period control means 63 may be one that continuously changes the operation period of the processing execution means 61 according to the degree of goodness, or may be switched in three or more stages. It may be switched in stages. Power consumption of the receiver 60 can be reduced by adjusting the operation period of the processing execution means 61 to the minimum necessary according to the goodness of the reception state of the reception signal.

  In this manner, the receiver 60 can reduce the power consumption of the receiver 60 by shortening the processing period for the predetermined processing during a period in which the reception state of the received signal is good.

  Typically, the predetermined processing is processing in which, when the processing time is the same, the accuracy of the processing result is higher in the high-quality period than in the low-period.

  As a specific example of the predetermined process, a synchronization detection clock regeneration process in the clock regenerator 19 of the wireless device 10 can be cited. In this case, the goodness detection means 62 detects, for example, the goodness of the reception state of the received signal based on the difference between the reference oscillation frequency of the transmitter and the reference oscillation frequency of the receiver 60 (example: wireless device in FIG. 3). S38 of the power saving control method 35). In addition, the operation period control unit 63 shortens the operation period of the processing execution unit 61 by decreasing the operation frequency of the processing execution unit 61 (example: S47 of the wireless device power saving control method 35 in FIG. 3).

  Another specific example of the predetermined process includes a frame synchronization detection process in the FS detection processor 20 of the wireless device 10. In this case, for example, the goodness detection means 62 determines the goodness of the reception state of the received signal based on the bit error rate related to the frame synchronization word in the frame synchronization detection processing and / or the bit error rate in the forward error correction of the CAI decoding processing. (Example: S48, S49 of the wireless device power saving control method 35 in FIG. 3). Moreover, the operation period control means 63 shortens the operation period of the process execution means 61 by shortening the operation period per time of the process execution means 61 (example: S55 of the wireless device power saving control method 35 in FIG. 3). .

  The operation period control means 63 can lower the operating frequency that defines the operation timing of the processing execution means 61 during the period when the goodness is high than when it is low. In a period when the degree of goodness is high, even if the processing capability of the processing execution means 61 is reduced, the desired accuracy can be ensured for the processing result. Can be planned.

  Preferably, when the electric field strength of the received signal is less than a predetermined threshold value, the goodness degree detection means 62 outputs a detection value that the operation period control means 63 determines to be a low goodness period. A specific example is S37 of the wireless device power saving control method 35 (FIG. 3). If the RSSI is less than the threshold value, the bit error rate cannot be reduced, and it is difficult to detect the difference between the reference oscillation frequency of the transmitter and the reference oscillation frequency of the receiver 60 as to whether the reception state of the received signal is good. . Therefore, the goodness degree detection means 62 can omit useless processing such as calculation of a bit error rate and a reference oscillation frequency difference in the operation period control means 63 by outputting a detection value corresponding to a sufficiently low goodness degree. it can.

  FIG. 5 is a flowchart of the receiver control method 70. The receiver control method 70 is applied to the receiver 60. In S71, the goodness of the reception state of the received signal is detected.

  In S72 to S74, a process for shortening the operation period of the predetermined process is performed in the period of high goodness than in the low period. That is, in S72, the degree of goodness is evaluated. If the degree of goodness is equal to or greater than the threshold value R, the process proceeds to S73, and if the degree of goodness <the threshold value R, the process proceeds to S74. In S73, the operation period of the predetermined process is made short, and in S74, the operation period of the process is made long.

  The predetermined processing in S73 and S74 means processing performed by the processing execution means 61 (FIG. 4). The processing of S71 corresponds to the function of the goodness detection means 62, and the specific mode described regarding the function of the goodness detection means 62 is applicable as a specific mode of the processing of S71. Moreover, the process of S72-S74 respond | corresponds to the function of the operation period control means 63, and the specific aspect described about the function of the operation period control means 63 is applicable as a specific aspect of the process of S72-S74.

  The program to which the present invention is applied causes a computer to function as each unit of the receiver 60. Another program to which the present invention is applied causes a computer to execute each step of the receiver control method 70.

  This specification discloses various inventions. The invention includes not only each device and each method described in the section of the best mode of the invention, but also one or a plurality of effects and effects independent of each device and each method within the obvious range of those skilled in the art. What extracted the element, what changed one or several elements in the obvious range, and what replaced the combination of one or several elements between each apparatus and between each method are included.

It is a block diagram of the receiving system of a radio. It is a schematic explanatory drawing of the power-saving method employ | adopted as the radio | wireless machine. It is a flowchart of the radio | wireless machine power saving control method. It is a block diagram of a receiver. It is a flowchart of a receiver control method.

Explanation of symbols

60: Receiver, 61: Processing execution means, 62: Goodness degree detection means, 63: Operation period control means, 70: Receiver control method.

Claims (4)

And processing means for executing reproduction processing of synchronous detection clock,
A goodness of reception state is detected based on the difference in symbol rate between the transmitter and the receiver and the electric field strength of the received signal, the electric field strength being equal to or higher than a first threshold, and the symbol rate and a good degree detecting means for detecting a period in which the condition is satisfied as a high period of goodness on the condition that the difference is less than the second threshold value continuously for a predetermined number of times or more,
In the period when the goodness level is high, the execution frequency of the reproduction processing of the synchronization detection clock by the processing execution means is decreased, and the operation time of the processing execution means is made longer than the low-quality time period when the condition is not satisfied. An operating period control means for shortening;
A receiver comprising: 2. The receiver according to claim 1, wherein the operation period control unit reduces an operating frequency that defines an operation timing of the processing execution unit during a period in which the condition is satisfied.
A process execution step for performing a recovery process of the synchronization detection clock ; and
A goodness of reception state is detected based on the difference in symbol rate between the transmitter and the receiver and the electric field strength of the received signal, the electric field strength being equal to or higher than a first threshold, and the symbol rate A goodness detection step of detecting a period in which the condition is satisfied as a period of high goodness on the condition that the difference is less than the second threshold continuously for a predetermined number of times ,
In the period in which the goodness level is high, the execution frequency of the synchronization detection clock regeneration processing in the processing execution step is decreased, and the operation time of the processing execution step is set to be shorter than the low-quality time period in which the condition is not satisfied. An operating period control step to shorten;
A reception control method comprising: Claim 1 or the program causing a computer to function as each means of a receiver 2 according.

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