JP5121090B2 - Method for depositing amorphous carbon layer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an amorphous carbon film, the use of the film in integrated circuit manufacturing and a method for depositing the film.
[0002]
[Prior art]
Integrated circuits have evolved into complex devices that can include multiple transistors, capacitors and resistors on a single chip. Advances in chip design constantly require faster circuit configurations and higher circuit densities. The demand for faster circuits with greater circuit density places corresponding demands on the materials used in the manufacture of such integrated circuits. That is, as integrated circuit component dimensions are reduced (eg, sub-micron dimensions), a low resistivity conductive material (eg, copper) and a low dielectric constant insulating material (less than about 4.5 dielectric constant). In use, there is a need to improve the electrical performance of these components.
[0003]
The demand for high density integrated circuits also imposes requirements on the process sequences used in integrated circuit manufacturing. For example, in a process sequence using conventional lithographic techniques, a layer of energy sensitive resist is formed on the deposition of the material layer on the substrate. A pattern image is introduced into the energy sensitive resist layer. Thereafter, the pattern introduced into the energy sensitive resist layer is transferred to one or more material deposition layers formed on the substrate using the energy sensitive resist layer as a mask. The pattern introduced in the energy sensitive resist can be transferred to one or more material deposition layers using a chemical etchant. Chemical etchants are designed to have greater etch selectivity for material deposition layers than energy sensitive resists. That is, a chemical etchant etches one or more material deposition layers at a much faster rate than it etches an energy sensitive resist. Typically, the high etch rate for one or more material deposition layers prevents the energy sensitive resist material from being consumed before the pattern transfer is complete.
[0004]
However, demands for greater circuit density on integrated circuits require smaller pattern dimensions (eg, submicron dimensions). As pattern dimensions are reduced, the thickness of the energy sensitive resist must be correspondingly reduced in order to control pattern resolution. Such thinner resist layers (less than about 6000 mm) may be insufficient for the mask of the underlying material layer during the pattern transfer step using chemical etching.
[0005]
An intermediate oxide layer called a hard mask (eg, silicon dioxide, silicon nitride) is often used between the energy sensitive resist layer and the underlying material layer to facilitate pattern transfer to the underlying material layer. However, some material structures (eg, damascene structures) include silicon dioxide and silicon nitride. This type of material structure cannot be patterned using a silicon dioxide or silicon nitride hard mask as an etching mask.
[0006]
The problem of resist patterning is further facilitated when using a lithographic imaging tool of deep ultraviolet (DUV) imaging wavelength to form a resist pattern. Since the influence of diffraction at a short wavelength is reduced in the DUV imaging wavelength, the resist pattern resolution is improved. However, since the reflectivity is increased by many base materials (for example, polysilicon or metal silicide) at this DUV wavelength, the quality of the obtained resist pattern may be deteriorated.
[0007]
One technique proposed to minimize reflection from the underlying material layer is to use an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. ARC suppresses reflections from the underlying material layer during resist imaging and provides an accurate pattern copy in the energy sensitive resist layer.
[0008]
[Problems to be solved by the invention]
Several ARC materials have been proposed for use in combination with energy sensitive resists. For example, Pranickick et al., US Pat. No. 5,626,967, issued May 6, 1997, discloses the use of an antireflective coating of titanium nitride. However, since titanium nitride becomes more metallic when the exposure wavelength is below 248 nm, titanium nitride has a high reflectivity for DUV radiation and is not an effective antireflection film for DUV wavelengths.
[0009]
US Pat. No. 5,710,067 issued to Foote et al., Issued January 20, 1998, discloses the use of an antireflective coating of silicon oxynitride. The silicon oxynitride film is difficult to remove in the sense that it leaves behind residues that may interfere with subsequent integrated circuit fabrication steps.
[0010]
Therefore, there is a need in the art for a material layer that is useful for integrated circuit fabrication with good etch selectivity with oxides. In particular, the material layer is preferably ARC with respect to the DUV wavelength, and stripping is easy.
[0011]
[Means for Solving the Problems]
The present invention provides a method of forming an amorphous carbon layer for use in the manufacture of integrated circuits. The amorphous carbon layer is formed by thermally decomposing a mixed gas containing a hydrocarbon compound and an inert gas. A mixed gas, optionally containing additional gas, is introduced into the process chamber, the hydrocarbon compound is plasma pyrolyzed proximate to the substrate surface, and an amorphous carbon layer is deposited on the substrate surface.
[0012]
As-depo. Amorphous carbon layers deposited according to the process of the present invention can be adjusted for carbon: hydrogen ratios in the range of about 10% hydrogen to about 60% hydrogen. The amorphous carbon layer also has a light absorption coefficient k that can vary from about 0.1 to about 1.0 at wavelengths less than about 250 nm, and the amorphous carbon layer can be used as an antireflective film at DUV wavelengths. To be suitable for.
[0013]
This amorphous carbon layer is compatible with integrated circuit manufacturing processes. In one integrated circuit manufacturing process, the amorphous carbon layer is used as a hard mask. In this embodiment, the preferred deposition sequence comprises the deposition of an amorphous carbon layer on the substrate. After the amorphous carbon layer is deposited on the substrate, an intermediate layer is formed thereon. The intermediate layer is patterned and transferred to the amorphous carbon layer. The pattern is then transferred to the substrate using the amorphous carbon layer as a hard mask. Furthermore, patterns formed in amorphous carbon hard masks can be incorporated into integrated circuit structures such as damascene structures.
[0014]
In another integrated circuit manufacturing process, an amorphous carbon layer is used as a single-layer antireflective coating for DUV lithography. In such embodiments, a suitable process sequence includes the formation of an amorphous carbon layer on the substrate. The amorphous carbon layer has a refractive index (n) of about 1.5 to 1.9 and a light absorption coefficient (k) of about 0.1 to about 1.0 for wavelengths less than about 250 nm. The refractive index (n) and the light absorption coefficient (k) of the amorphous carbon ARC can be adjusted in the sense that they are variable within a desirable range as a function of the temperature and composition of the mixed gas during layer formation. After the amorphous carbon layer is formed on the substrate, an energy sensitive resist material layer is formed thereon. A pattern is formed in the energy sensitive resist at a wavelength of less than about 250 nm. Thereafter, the pattern formed in the energy sensitive resist is transferred to the amorphous carbon layer. After the amorphous carbon layer is patterned, such a pattern is optionally transferred to the substrate.
[0015]
In yet another integrated circuit manufacturing process, multilayer amorphous carbon antireflective coatings are used for DUV lithography. In such an embodiment, a suitable processing sequence includes forming a first amorphous carbon layer on the substrate. The first amorphous carbon layer has a refractive index in the range of about 1.5 to about 1.9 and a light absorption coefficient (k) in the range of about 0.5 to about 1.0 at wavelengths less than about 250 nm. Have After the first amorphous carbon layer is formed on the substrate, a second amorphous carbon layer is formed thereon. The second amorphous carbon layer has a refractive index of about 1.5 to about 1.9 and a light absorption coefficient in the range of about 0.1 to about 0.5. The refractive index (n) and light absorption coefficient (k) of the first and second amorphous carbon layers are adjusted in the sense that they can be varied within a desirable range as a function of the temperature and composition of the mixed gas during layer formation. Is possible. A layer of energy sensitive resist material is formed on the second amorphous carbon layer. A pattern is formed in the energy sensitive resist layer at a wavelength of less than about 250 nm. The pattern formed in the energy sensitive resist material is then transferred to the second amorphous carbon layer followed by the first amorphous carbon layer. After the first amorphous carbon layer is patterned, such a pattern is optionally transferred to the substrate.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
[0017]
The present invention provides a method of forming an integrated circuit using an amorphous carbon layer. The amorphous carbon layer is formed by thermally decomposing a mixed gas containing a hydrocarbon compound and an inert gas. A gas mixture, optionally including additional gases, is introduced into the process chamber where an amorphous carbon layer is deposited on the substrate surface as a result of plasma pyrolysis of the hydrocarbon compounds proximate to the substrate surface. The amorphous carbon layer is compatible with the integrated circuit manufacturing process discussed below.
[0018]
FIG. 1 is a schematic diagram of a wafer processing system 10 that can be used to perform deposition of an amorphous carbon layer in accordance with the present invention. The apparatus typically includes a process chamber 100, a gas panel 130, and a control unit 110 along with other hardware components such as a power supply and a vacuum pump. Details of the system 10 used in the present invention are described in a US patent application entitled “High Temperature Chemical Vapor Deposition Chamber” filed Dec. 14, 1998, Ser. No. 09 / 211,998. The salient features of this system 10 are briefly described below. Examples of system 10 include the CENTURA system, PRECISION 5000 system, and PRODUCER system available from Applied Materials, Inc., Santa Clara, California.
[0019]
Process chamber 100 generally includes a pedestal 150 that is used to support a substrate, such as a semiconductor wafer 190. The pedestal 150 can be moved vertically in the chamber 100 using a transposition mechanism (not shown). Depending on the particular process, the wafer 190 may be heated to some desired temperature prior to the process. In the present invention, the wafer pedestal 150 is heated by the embedded heater element 170. For example, the pedestal 150 can be resistance-heated by applying a current from the AC power source 106 to the heater element 170. The wafer 190 is then heated by the pedestal 150. In the conventional method, a temperature sensor 172 such as a thermocouple is also embedded in the wafer pedestal 150 to monitor the temperature of the pedestal 150. The measured temperature is used in a feedback loop to control the power supply 16 of the heater element 170 so that the wafer temperature can be maintained or controlled at a desired temperature suitable for a particular processing application. The pedestal 150 is optionally heated using a plasma or by a radiant heat sink (not shown).
[0020]
A vacuum pump 102 is used to evacuate the process chamber 100 and maintain a proper gas flow rate and pressure within the chamber 100. A showerhead 120 that introduces process gas into the chamber 100 is disposed above the wafer pedestal 150. The showerhead 120 is connected to a gas panel 130 that controls and supplies various gases used at different stages of the process sequence.
[0021]
Shower head 120 and wafer pedestal 150 also form a pair of spaced electrodes. When an electric field is generated between these electrodes, the process gas introduced into the chamber 100 is excited by plasma. Typically, an electric field is generated by connecting wafer pedestal 150 to a radio frequency (RF) power source (not shown) via a matching network (not shown). Alternatively, the RF power source and matching network may be coupled to the showerhead 120, or to both the showerhead 120 and the wafer pedestal 150.
[0022]
In plasma enhanced chemical vapor deposition (PECVD), an electric field is applied to a reaction zone near the substrate surface to promote excitation and separation of the reaction gas and generate plasma of a reactive species. Since the reactivity of the species in the plasma is high, the energy required for the chemical reaction is lowered and the temperature required for this PECVD process is lowered.
[0023]
In this embodiment, the deposition of the amorphous carbon layer is propylene (C_ThreeH₆) It is realized by plasma pyrolysis of hydrocarbon compounds. Propylene is introduced into the process chamber 100 under the control of the gas panel 130. The hydrocarbon compound is introduced into the process chamber as a gas at a defined flow rate.
[0024]
Appropriate control and adjustment of the gas flow rate are performed by the gas panel 130 by a mass flow control device (not shown) and a control unit 110 such as a computer. The shower head 120 allows the process gas from the gas panel 130 to be uniformly distributed and introduced into the process chamber 100. By way of example, the control unit 110 comprises a central processing unit (CPU) 112, an auxiliary circuit 114, and a memory 116 containing associated control software. The control unit 110 has a function of automatically controlling a number of steps necessary for wafer processing, such as wafer transfer, gas flow rate control, temperature control, and chamber exhaust. Bidirectional communication between the control unit 110 and the various components of the system 10 is handled through a number of signal cables 118, collectively referred to as a signal bus, some of which are illustrated in FIG.
[0025]
The heated pedestal 150 used in the present invention is made of aluminum and includes a heater element 170 embedded at a distance below the wafer support surface 151 of the pedestal 150. The heater element 170 may be made from a nickel chrome wire encapsulated in an incoloy sheath tube. By properly adjusting the current applied to the heater element 170, the wafer 190 and pedestal 150 can be maintained at a relatively constant temperature during film deposition. This is accomplished by a feedback control loop where the temperature of the pedestal 150 is constantly monitored by a thermocouple 172 embedded in the pedestal 150. This information is transferred to the control unit 110 through the signal bus 118, which responds by sending the necessary signals to the heater power supply. Adjustments are subsequently made in the current supply 106 to maintain and control the pedestal 150 at a desired temperature, that is, a temperature suitable for a particular processing application. As the mixed process gas exits the showerhead 120, plasma pyrolysis of the hydrocarbon compound occurs on the heated surface 190 of the wafer 190, resulting in an amorphous carbon layer being deposited on the wafer 190.
[0026]
Formation of amorphous carbon layer
In one embodiment of the present invention, the amorphous carbon layer is formed from a mixed gas of a hydrocarbon compound and an inert gas such as argon (Ar) or helium (He). Hydrocarbon compounds have the general formula C_xH_yWhere x is in the range of 2-4 and y is in the range of 2-10. For example, propylene (C_ThreeH₆), Propyne (C_ThreeH_Four), Propane (C_ThreeH₈), Butane (C_FourH_Ten), Butylene (C_FourH₈), Butadiene (C_FourH₆) Or acetylene (C₂H₂) As well as these compounds can be used as hydrocarbon compounds. Similarly, hydrogen (H₂), Nitrogen (N₂), Ammonia (NH_Three), Or these compounds may be added to the mixed gas as required. Ar, He and N₂Is used to control the density and deposition rate of the amorphous carbon layer. H₂And / or NH_ThreeCan be used to control the hydrogen fraction of the amorphous carbon layer as discussed below.
[0027]
  In general, the following deposition process parameters can be used to form an amorphous carbon layer. The process parameters include a wafer temperature of about 100 ° C. to about 500 ° C., a chamber pressure of about 1 Torr to about 20 Torr, a hydrocarbon gas (CxHy) flow rate of about 50 sccm to about 500 sccm (per 8 inch wafer), about0.5W /cm ² ~about3W /cm ² RF power, and about0.76cm~about1.52cmThe plate interval. The above process parameters provide a typical deposition rate of an amorphous carbon layer of about 100 / min to about 1000 / min and can be performed on a 200 mm substrate in a deposition chamber commercially available from Applied Materials.
[0028]
Other deposition chambers are within the scope of the invention, and the parameters listed above can vary depending on the particular deposition chamber used to form the amorphous carbon layer. For example, the volume of other deposition chambers may be larger or smaller, in which case higher and lower gas flow rates are required than illustrated for a commercial deposition chamber from Applied Materials.
[0029]
The as-deposited amorphous carbon layer can adjust the carbon: hydrogen ratio in the range of about 10% hydrogen to about 60% hydrogen. Controlling the hydrogen ratio of the amorphous carbon layer is desirable to adjust etch selectivity as well as its optical properties. In particular, as the hydrogen ratio decreases, the optical properties of the as-deposited layer, such as the refractive index (n) and the light absorption coefficient (k), increase. Similarly, the etching resistance of the amorphous carbon layer improves as the hydrogen ratio decreases.
[0030]
The light absorption coefficient k of the amorphous carbon layer can vary between about 0.1 and about 1.0 at wavelengths less than about 250 nm, and the amorphous carbon layer can be used as an anti-reflection coating (ARC) at DUV wavelengths. Adapt. The light absorption coefficient of the amorphous carbon layer is variable as a function of the deposition temperature. In particular, as the temperature increases, the light absorption coefficient of the as-deposited layer increases as well. For example, when propylene is a hydrocarbon compound, the k value of the as-deposited amorphous carbon layer can be increased from about 0.2 to about 0.7 by increasing the deposition temperature from about 150 ° C. to about 480 ° C. Is possible.
[0031]
The light absorption coefficient of the amorphous carbon layer can also vary as a function of the additive used in the gas mixture. In particular, H₂, NH_Three, N₂Alternatively, when these compounds are present in the gas mixture, the k value can be increased by about 10% to about 100%.
[0032]
Integrated circuit manufacturing process
A. Amorphous carbon hard mask
2a to 2e show schematic cross-sectional views of the substrate 200 at different stages of an integrated circuit manufacturing sequence incorporating an amorphous carbon layer as a hard mask. Here, the substrate 200 refers to any workpiece on which processing is performed, and the substrate structure 250 is used to represent both the substrate 200 and other layers of material formed on the substrate 200. Depending on the particular stage of processing, the substrate 200 may correspond to a silicon substrate or other material layer formed on the substrate. FIG. 2a represents a cross-sectional view of a substrate structure 250, for example, with a material layer 202 conventionally formed thereon. The material layer 202 is an oxide (eg, SiO₂). In general, the substrate 200 may include a silicon layer, a silicon compound layer, a metal layer, or other material layer. FIG. 2a represents an embodiment in which the substrate 200 is silicon and a silicon dioxide layer is formed thereon.
[0033]
FIG. 2b represents an amorphous carbon layer 204 deposited on the substrate structure 250 of FIG. 2a. The amorphous carbon layer 204 is formed on the substrate structure 250 according to the process parameters described above. The thickness of the amorphous carbon layer is variable depending on the specific processing stage. Usually, the amorphous carbon layer has a thickness of about 50 mm to about 1000 mm.
[0034]
An intermediate layer 206 is formed on the amorphous carbon layer 204 in response to the etching chemistry of the energy sensitive resist material used in the manufacturing sequence. The intermediate layer 206 serves as a mask for the amorphous carbon layer 204 when the pattern is transferred therein. The intermediate layer 206 is formed on the amorphous carbon layer 204 as usual. The intermediate layer 206 may be an oxide, nitride, silicon oxynitride, silicon carbide, amorphous silicon, or other material.
[0035]
An energy sensitive resist material layer 208 is formed on the intermediate layer 206. The energy sensitive resist material layer 208 can be spin coated onto the substrate to a thickness in the range of about 2000 to about 6000 inches. Most energy sensitive resist materials are sensitive to ultraviolet (UV) radiation having a wavelength of less than about 450 nm. DUV resist materials are sensitive to UV radiation having a wavelength of 245 nm or 193 nm.
[0036]
A pattern image is introduced into the energy sensitive resist material layer 208 by exposing such energy sensitive resist material layer 208 to UV radiation through a mask 210. The pattern image introduced into the energy sensitive resist material layer 208 is developed in a suitable development apparatus to form a pattern in the layer as shown in FIG. 2c. Thereafter, referring to FIG. 2 d, the pattern formed in the energy sensitive resist material layer 208 is transferred to the intermediate layer 206 and the amorphous carbon layer 204. The pattern is transferred to the intermediate layer 206 using the energy sensitive resist material 208 as a mask. The pattern is transferred to the intermediate layer 206 by etching the intermediate layer 206 using a suitable chemical etchant. The pattern is then transferred to the amorphous carbon layer 204 using the intermediate layer 206 as a mask. The pattern is transferred to the amorphous carbon layer 204 by etching the amorphous carbon layer 204 using a suitable chemical etchant (eg, ozone plasma, oxygen plasma or ammonia plasma).
[0037]
FIG. 2e represents the completion of the integrated circuit fabrication sequence by transferring the pattern formed in the amorphous carbon layer 204 to the silicon oxide layer 202 using the amorphous carbon layer 204 as a hard mask.
[0038]
After the silicon dioxide layer 202 is patterned, the amorphous carbon layer 204 can optionally be stripped from the substrate 200 by etching in ozone plasma, oxygen plasma, or ammonia plasma.
[0039]
In a specific example of a manufacturing sequence, a pattern formed in an amorphous carbon hard mask can be incorporated into an integrated circuit structure such as a damascene structure. Damascene structures are typically used to form metal interconnects on integrated circuits.
[0040]
FIGS. 3 a-3 e represent schematic cross-sectional views of the substrate 260 at different stages during the manufacturing sequence of a damascene structure including an amorphous carbon layer. Depending on the stage of processing, the substrate 260 may coincide with a silicon substrate or other material layer formed on the substrate. FIG. 3a represents, for example, a cross-sectional view of a substrate 260 having a dielectric layer 262 formed thereon. The dielectric layer 262 may be an oxide (eg, silicon dioxide, fluorosilicate glass). In general, the substrate 260 may include a silicon layer, a silicon compound layer, a metal layer, or other material layer.
[0041]
FIG. 3a represents an embodiment in which the substrate 260 is silicon and a fluorosilicate glass layer is formed thereon. The dielectric layer 262 has a thickness of about 5,000 mm to about 10,000 mm depending on the size of the substrate to be manufactured. An amorphous carbon layer 264 is formed on the dielectric layer 262. An amorphous carbon layer is formed on the dielectric layer 262 according to the process parameters described above. The amorphous carbon layer 264 has a thickness of about 200 mm to about 1000 mm.
[0042]
Referring to FIG. 3b, the amorphous carbon layer 264 is patterned and etched to form contact / via openings 266, and the dielectric layer 262 is exposed to the extent that contact / via openings are to be formed. The amorphous carbon layer 264 is patterned using conventional lithography techniques and etched using oxygen plasma or ammonia plasma.
[0043]
The contact / via opening 266 formed in the amorphous carbon layer 264 is then transferred to the dielectric layer 262 using the amorphous carbon layer 264 as a hard mask, as shown in FIG. 3c. Contact / via opening 266 is etched using reactive ion etching or other anisotropic etching techniques. After the contact / via opening 266 is transferred to the dielectric layer 262, the amorphous carbon layer is stripped from the dielectric layer 262 by etching in ozone plasma, oxygen plasma, or ammonia plasma, as shown in FIG. 3d.
[0044]
Referring to FIG. 3e, a metallization structure is formed in the contact / via 266 using a conductive material 274 such as aluminum, copper, tungsten, or a compound thereof. Usually, because of its low resistance (about 1.7 μΩcm), copper is used to form metallization structures. The conductive material 274 is deposited using chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form a damascene structure. Preferably, a barrier layer 272 such as tantalum, tantalum nitride, or other suitable barrier is first deposited for the metallization structure to prevent metal migration to the surrounding dielectric material layer 262. Further, the dielectric layer 262 desirably has a low dielectric constant (dielectric constant less than about 4.5) to prevent electrostatic coupling between adjacent contacts / vias 266 of the metallization structure.
[0045]
B. Amorphous carbon antireflection coating (ARC)
4a-4c represent schematic cross-sectional views of the substrate 300 at different stages of an integrated circuit manufacturing sequence that incorporates an amorphous carbon layer as an anti-reflective coating (ARC). In general, the substrate 300 applies to any workpiece on which film processing is performed, and the substrate structure 350 is generally used to represent both the substrate 300 and other material layers formed on the substrate 300. Depending on the particular stage of processing, the substrate 300 represents a silicon substrate or other material layer formed on the substrate. FIG. 4a represents a cross-sectional view of a substrate structure 350, for example, where the substrate 300 is an oxide layer formed on a silicon wafer.
[0046]
An amorphous carbon layer 302 is formed on the substrate 300. The amorphous carbon layer 302 is formed on the substrate 300 according to the process parameters described above. The amorphous carbon layer has a refractive index (n) in the range of about 1.5 to 1.9 and a light absorption coefficient (k) in the range of about 0.1 to about 1.0 at a wavelength of less than about 250 nm. The amorphous carbon layer is suitable as an ARC at the DUV wavelength. The refractive index (n) and the light absorption coefficient (k) of the amorphous carbon ARC can be adjusted because they are variable as a function of temperature and gas mixture composition in the desired range during layer formation. The thickness of the amorphous carbon layer is variable depending on the specific processing stage. Typically, the amorphous carbon layer has a thickness of about 200 to about 1100.
[0047]
FIG. 4b represents an energy sensitive resist material layer 304 formed on the substrate structure 350 of FIG. 4a. The energy sensitive resist material layer can be spin coated onto the substrate to a thickness in the range of about 2000 mm to about 6000 mm. The energy sensitive resist material is sensitive to DUV radiation having a wavelength of less than 250 nm.
[0048]
By exposing this energy sensitive resist material layer 304 to DUV radiation through a mask 306, a pattern image is introduced into the energy sensitive resist material layer 304. The pattern image introduced into the energy sensitive resist material layer 304 is developed in a suitable developing device to form a pattern in the layer. Thereafter, referring to FIG. 4 c, the pattern formed in the energy sensitive resist material 304 is transferred to the amorphous carbon layer 302. The pattern is transferred to the amorphous carbon layer 302 using the energy sensitive resist material 304 as a mask. The pattern is transferred to the amorphous carbon layer 302 by etching the amorphous carbon layer 302 using a suitable chemical etchant (eg, ozone plasma, oxygen plasma or ammonia plasma).
[0049]
After the amorphous carbon 302 is patterned, such a pattern is optionally transferred to the substrate 300. Typically, when the substrate 300 comprises an oxide layer on a silicon substrate, the etch selectivity of the oxide layer to the resist mask is from about 3: 1 to about 5: 1. Specifically, the oxide etches about 3-5 times faster than the resist. In contrast, the amorphous carbon ARC layer of the present invention has an etch selectivity greater than about 10: 1 to oxide. That is, the oxide etches 10 times or more faster than the amorphous carbon ARC. Thus, the amorphous carbon ARC layer also provides greater etch selectivity without additional process complexity, such as requiring an intermediate hard mask layer as a hard mask for oxide patterning.
[0050]
In an alternative embodiment, the amorphous carbon layer can have a light absorption coefficient (k) that varies across the thickness of the layer. That is, the amorphous carbon layer can have a gradient of light absorption coefficient formed therein. Such a gradient is formed as a function of temperature and gas mixture composition during layer formation.
[0051]
Reflection can occur at the interface between the two material layers due to the difference in their refractive index (n) and light absorption coefficient (k). The gradient of the amorphous carbon ARC can be adjusted so that the refractive index (n) and the light absorption coefficient (k) of the two material layers can be adapted, and the maximum transmission to the amorphous carbon ARC is possible with the minimum reflection. Become. As a result, the refractive index (n) and light absorption coefficient (k) of the amorphous carbon ARC can be adjusted step by step so as to absorb all of the light transmitted through it.
[0052]
C. Multi-layer amorphous carbon anti-reflective coating (ARC)
5a-5d represent schematic cross-sectional views of the substrate 400 at different stages of an integrated circuit manufacturing sequence that incorporates a multilayer amorphous carbon anti-reflective coating (ARC) structure. In general, the substrate 400 applies to any workpiece on which film processing is performed, and the substrate structure 450 is generally used to represent both the substrate 400 and other layers of material formed on the substrate 400. Depending on the particular stage of processing, the substrate 400 represents a silicon substrate or other material layer formed on the substrate. FIG. 5a represents a cross-sectional view of a substrate structure 450, for example, where the substrate 400 is a silicon wafer.
[0053]
A first amorphous carbon layer 402 is formed on the substrate 400. The first amorphous carbon layer 402 is formed on the substrate 400 according to the process parameters described above. The first amorphous carbon layer 402 is designed mainly for light absorption. Accordingly, the first amorphous carbon layer 402 has a refractive index in the range of about 1.5 to about 1.9 and an absorption coefficient (k) in the range of about 0.5 to about 1.0 at wavelengths less than about 250 nm. have. The thickness of the first amorphous carbon layer 402 is variable depending on the specific processing stage. Typically, the first amorphous carbon layer 402 has a thickness in the range of about 300cm to about 1500mm.
[0054]
A second amorphous carbon layer 404 is formed on the first amorphous carbon layer 402. The second amorphous carbon layer 404 is also formed according to the process parameters described above. The second amorphous carbon layer 404 is designed mainly for the purpose of canceling the phase shift. That is, the second amorphous carbon layer is designed to generate a reflection that eliminates the reflection generated at the interface with the overlying material layer (eg, energy sensitive resist material). Accordingly, the second amorphous carbon layer 404 has a refractive index of about 1.5 to about 1.9 and a light absorption coefficient in the range of about 0.1 to about 0.5.
[0055]
The thickness of the second amorphous carbon layer 404 is also variable depending on the specific processing stage. Typically, the second amorphous carbon layer 404 has a thickness in the range of about 300cm to about 700mm. The refractive index (n) and light absorption coefficient (k) of the first and second amorphous carbon layers can be adjusted because they are variable as a function of temperature and gas mixture during film formation.
[0056]
Additional amorphous carbon layers may be included in the multilayer amorphous carbon ARC structure. For example, one or more top layers can be used to cancel reflections that occur, for example, at the interface with an energy sensitive resist material, while one or more bottom layers can be used to absorb light transmitted therein. Thus, reflection at the interface between the multilayer amorphous carbon ARC structure and the underlying material layer such as a low dielectric constant oxide can be minimized.
[0057]
FIG. 5b represents an energy sensitive resist material layer 406 formed on the substrate structure 450 of FIG. 5a. The energy sensitive resist material layer can be spin coated onto the substrate to a thickness in the range of about 2000 to about 6000 inches. The energy sensitive resist material is sensitive to DUV radiation having a wavelength of less than 250 nm.
[0058]
Exposing the energy sensitive resist material 406 to DUV radiation through a mask 408 introduces a pattern image into the energy sensitive resist material layer 406.
[0059]
The pattern image introduced into the energy sensitive resist material layer 406 is developed in a suitable developing device to form a pattern in the layer as shown in FIG. 5c. Subsequently, referring to FIG. 5d, the pattern formed in the energy sensitive resist material 406 is transferred to the amorphous carbon layers 404, 402 using the energy sensitive resist material 406 as a mask. The pattern is transferred to the amorphous carbon layers 404, 402 by etching using a suitable chemical etchant (eg, ozone plasma, oxygen plasma or ammonia plasma). After the multilayer ARC is patterned, such a pattern is optionally transferred to the substrate.
[0060]
The multi-layer amorphous carbon ARC structure described with reference to FIGS. 5a to 5d further complicates the process, as already described for single-layer amorphous carbon ARC, requiring an additional intermediate hard mask layer. Without providing etching selectivity as a hard mask for patterning an underlying material layer such as a low dielectric constant oxide.
[0061]
While several preferred embodiments have been shown and described in detail which incorporate the teachings of the present invention, those skilled in the art can readily devise numerous other embodiments that further incorporate these teachings. Let's go.
[Brief description of the drawings]
FIG. 1 is a schematic representation of an apparatus that can be used to practice the present invention.
FIGS. 2a-2e are schematic cross-sectional views of substrate structures at various stages of integrated circuit fabrication incorporating an amorphous carbon layer as a hard mask. FIGS.
FIGS. 3a-3e are schematic cross-sectional views of damascene structures at various stages of integrated circuit fabrication incorporating an amorphous carbon layer as a hard mask. FIGS.
FIGS. 4a-4c are schematic cross-sectional views of substrate structures at various stages of integrated circuit fabrication incorporating an amorphous carbon layer as an anti-reflective coating (ARC). FIGS.
FIGS. 5a-5d are schematic cross-sectional views of substrate structures at different stages in the manufacture of integrated circuits incorporating multilayer amorphous carbon ARC structures. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Wafer processing system, 100 ... Process chamber, 102 ... Vacuum pump, 106 ... AC power supply, 110 ... Control unit, 112 ... Central processing unit (CPU), 114 ... Auxiliary circuit, 116 ... Memory, 118 ... Signal cable, DESCRIPTION OF SYMBOLS 120 ... Shower head, 130 ... Gas panel, 150 ... Pedestal, 170 ... Embedded heater element, 172 ... Temperature sensor, 190 ... Semiconductor wafer, 191 ... Surface, 200 ... Substrate, 202 ... Material layer, 204 ... Amorphous carbon layer, 206 ... intermediate layer, 208 ... energy sensitive resist material layer, 210 ... mask, 250 ... substrate structure, 260 ... substrate, 262 ... dielectric layer, 264 ... amorphous carbon layer, 266 ... contact / via opening, 272 ... barrier layer, 300 ... Substrate, 302 ... amorphous carbon layer, 3 4 ... energy sensitive resist material layer, 306 ... mask, 350 ... substrate structure, 400 ... substrate, 402 ... first amorphous carbon layer, 404 ... second amorphous carbon layer, 406 ... energy sensitive resist material, 408 ... mask, 450 ... Board structure

Claims (26)

A device forming method comprising:
Forming a dielectric layer on the substrate;
Forming a hard mask including one or more amorphous carbon layers in the dielectric layer by chemical vapor deposition;
Forming an intermediate layer comprising silicon carbide on the hard mask;
Forming a pattern in at least one region of the intermediate layer;
Forming a pattern in at least one region of the hard mask . The method of claim 1, further comprising: transferring a pre-pattern formed on at least one region of the hard mask to the substrate . The method of claim 2, further comprising removing the hard mask from the substrate. Forming a pattern in at least one region of the intermediate layer ;
Forming an energy sensitive resist material layer on the intermediate layer;
Introducing a pattern image into the energy sensitive resist material layer by exposing the energy sensitive resist material layer to patterned radiation;
Developing a pattern image introduced into the energy sensitive resist material layer;
The method according to claim 1, further comprising: transferring the pattern to the hard mask . Forming a pattern in at least one region of the intermediate layer;
Forming an energy sensitive resist material layer on the intermediate layer;
Introducing a pattern image into the energy sensitive resist material layer;
Developing a pattern image;
Transferring the pattern image developed in the energy sensitive resist material layer to the intermediate layer using the energy sensitive resist material as a mask;
The method of claim 4 further comprising : The method according to claim 5 , wherein the intermediate layer is an oxide. One or more amorphous carbon layers, ozone plasma or oxygen plasma or by using the NH ₃ plasma process according to claim 3 which is removed from the substrate.   The method of claim 1, wherein the one or more amorphous carbon layers are antireflective films at wavelengths less than 250 nm. 9. The method of claim 8 , wherein each of the one or more amorphous carbon layers has a light absorption coefficient in the range of 0.1 to 1.0 at a wavelength of less than 250 nm. The method of claim 9 , wherein the light absorption coefficient varies between 0.1 and 1.0 over the thickness of the one or more amorphous carbon layers. The method of claim 8 , wherein the one or more amorphous carbon layers each have a refractive index of 1.5 to 1.9. Placing the substrate in the deposition chamber;
Supplying a gas mixture having one or more hydrocarbon compounds and an inert gas to the deposition chamber;
One or more amorphous carbon layers are formed on the substrate by heating the mixed gas and thermally decomposing one or more hydrocarbon compounds in the mixed gas to form one or more amorphous carbon layers on the substrate. The method of claim 1 formed. The method according to claim 12 , wherein the one or more hydrocarbon compounds in the mixed gas are of the general formula CxHy, where x is 2-4 and y is 2-10. One or more hydrocarbon compounds include propylene (C ₃ H ₆ ), propyne (C ₃ H ₄ ), propane (C ₃ H ₈ ), butane (C ₄ H ₁₀ ), and butylene (C ₄ H The method of claim 13 selected from the group consisting of ₈ ), butadiene (C ₄ H ₆ ), acetylene (C ₂ H ₂ ), and mixtures thereof. The method of claim 12 , wherein the one or more amorphous carbon layers each have a carbon: hydrogen ratio in the range of 10% hydrogen to 60% hydrogen. The method of claim 12 , wherein the inert gas is selected from the group consisting of helium, argon, and mixtures thereof. The method according to claim 12 , wherein the mixed gas further contains an additive gas. The method of claim 17 , wherein the additive gas is selected from the group consisting of ammonia, nitrogen, hydrogen, and mixtures thereof. The method of claim 12 , wherein the substrate is heated to a temperature of 100 ° C. to 500 ° C. The method of claim 12 , wherein the deposition chamber is maintained at a pressure between 1 Torr and 20 Torr. The method of claim 12 , wherein the gas mixture is supplied to the deposition chamber at a flow rate between 50 sccm and 500 sccm. The method of claim 12 , wherein the gas mixture is heated by applying an electric field. 23. The method of claim 22 , wherein the electric field applied to the gas mixture is radio frequency (RF) power. The method of claim 23 RF power is ^{0.5W / cm 2 ~3W / cm 2} .   The method of claim 1, wherein each of the one or more amorphous carbon layers has a thickness in the range of 50 to 1500 inches. The method of claim 4 , wherein the patterned radiation has a wavelength of less than 250 nanometers (nm).

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