JP5117526B2 - Battery internal state estimation device and battery internal state estimation method - Google Patents

Description

  The present invention relates to a battery internal state estimation device and a battery internal state estimation method.

  Patent Document 1 discloses a method of measuring the voltage and current of a lead storage battery a plurality of times and estimating the characteristics of the lead storage battery based on the average value of the measurement results.

JP 58-192270 A

  By the way, when a load is connected to the battery, there is a problem in that an accurate estimation cannot be performed because an error is included in the measured value when a current flows through the load during measurement.

  Therefore, an object of the present invention is to provide a battery internal state estimation device and a battery internal state estimation method that can accurately estimate the state of the battery.

In order to solve the above problems, a battery internal state estimation device according to the present invention is a battery internal state estimation device that estimates an internal state of a battery, a measurement unit that measures an impedance value of the battery at a predetermined period, and the measurement A storage means for storing the impedance value measured by the means, and a determination for determining whether or not the difference value of the impedance value pair as a set of impedance values measured before and after time is greater than a predetermined threshold value And when there are a plurality of impedance value pairs for which the difference value is determined to be larger than a predetermined threshold by the determination means, the measurement error is calculated for the impedance value commonly included in the impedance value pair. Exclusion means excluded as including, and the battery based on the impedance value not excluded by the exclusion means It characterized in that it has an estimating means for estimating an internal state, a.
According to such a configuration, the state of the battery can be accurately estimated.

According to another invention, in addition to the above-described invention, the excluding unit includes a case where there is an impedance value pair for which the difference value is determined to be larger than a predetermined threshold by the determining unit, and the measurement is started. If it is an impedance value pair at the time or at the end of measurement, the first or last impedance value included in the impedance value pair is excluded.
According to such a configuration, when an impedance value including a measurement error exists at the beginning or end, the value can be reliably excluded.

In addition to the above-mentioned invention, another invention is characterized in that the measuring means discharges the current to the battery and measures the impedance value based on a voltage value and a current value at that time.
According to such a configuration, it is possible to reduce power consumed by remeasurement by excluding impedance values having measurement errors and estimating internal states based on other impedance values.

According to another aspect of the invention, in addition to the above-described invention, the excluding unit may include the two impedance values when there are two consecutive impedance value pairs for which the difference value is determined to be larger than a predetermined threshold value. Impedance values that are commonly included in value pairs are excluded as including measurement errors.
According to such a configuration, when two impedance value pairs exist in succession, it is possible to reliably exclude an impedance value having a measurement error by excluding an impedance value that is commonly included in these pairs. it can.

According to another aspect of the invention, in addition to the above-described invention, the excluding unit may include the two impedance value pairs that are determined to have a difference value larger than a predetermined threshold, with two intervals therebetween. Impedance values constituting an impedance value pair existing between impedance value pairs are excluded as including measurement errors, and the measured timings of the two impedance value pairs are excluded except for the first and last impedance values. It is characterized by that.
According to such a configuration, when there are continuous impedance values having measurement errors, it is possible to perform more accurate measurement by excluding impedance values that are uncertain.

Further, in addition to the above invention, in another invention, bit information is associated with each impedance value pair, and the determination means is for an impedance value pair whose difference value is larger than a predetermined threshold value. The corresponding bit information is inverted, and when there are a plurality of impedance value pairs in which the corresponding bit information is inverted, the excluding means determines a measurement error for the impedance value that is commonly included in the impedance value pair. Is excluded as including.
According to such a configuration, by using the bit information, it is possible to surely know the impedance value including a measurement error with a small storage capacity.

According to another aspect of the present invention, there is provided a battery internal state estimation method for estimating an internal state of a battery, a measurement step of measuring the impedance value of the battery at a predetermined period, and an impedance value measured by the measurement step being stored in a memory. A storage step; a determination step that determines whether or not a difference value of an impedance value pair as a set of impedances measured before and after time is greater than a predetermined threshold; and When there are a plurality of impedance value pairs determined to be larger than a predetermined threshold value, an exclusion step of excluding an impedance value commonly included in the impedance value pair as including a measurement error; and the exclusion step The internal state of the battery based on the impedance value not excluded in And having a an estimation step of estimating a.
According to such a method, the state of the battery can be accurately estimated.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the battery internal state estimation apparatus and battery internal state estimation method which can estimate a battery state correctly.

It is a figure which shows the structural example of the battery internal state estimation apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows the structural example of the control part shown in FIG. It is a flowchart for demonstrating the flow of the process performed in 1st Embodiment. It is a figure which shows the relationship between an electric current and a voltage, and a sampling period. It is a figure which shows an example of an actual measured value. It is a flowchart for demonstrating the detail of the "exclusion process" of step S22 of FIG. It is a figure for demonstrating an example of a table. It is a figure for demonstrating another example of a table. It is a flowchart for demonstrating an example of the process performed in 2nd Embodiment. It is a figure for demonstrating the content of the determination in case an abnormal impedance value appears continuously.

  Next, an embodiment of the present invention will be described.

(A) Description of Configuration of First Embodiment FIG. 1 is a diagram illustrating a configuration example of a battery internal state estimation device according to a first embodiment of the present invention. As shown in FIG. 1, the battery internal state estimation device 1 of the first embodiment includes a control unit 10, a voltage detection unit 11 (corresponding to a part of “measurement means” in the claims), a current detection unit 12 ( Corresponding to a part of “measurement means” in the claims) and the discharge circuit 14 as main components, the internal state of the lead storage battery 13 (corresponding to “battery” in the claims) is estimated. In this example, an alternator 15, a cell motor 16, and a load 17 are connected to the lead storage battery 13 via the current detection unit 12. In the present embodiment, the case where the battery internal state estimation device 1 is mounted on a vehicle such as an automobile will be described as an example. Needless to say, it may be used for other purposes.

  As shown in FIG. 2, the control unit 10 includes a CPU (Central Processing Unit) 10a (corresponding to “determination means”, “exclusion means”, and “estimation means” in the claims), ROM (Read Only Memory) 10b, RAM (Random Access Memory) 10c (corresponding to “storage means” in claims), and I / F (Interface) 10d (corresponding to a part of “measuring means” in claims) As an element. The CPU 10a controls each part of the apparatus based on a program 10ba stored in the ROM 10b. The ROM 10b is constituted by a semiconductor memory, and stores the program 10ba and other information. The RAM 10c is composed of a semiconductor memory, and stores a measurement value 10ca and other information indicating an impedance value and the like described later in a rewritable manner. The I / F 10d converts detection signals from the voltage detection unit 11 and the current detection unit 12 into digital signals and inputs them, and supplies a control signal to control the discharge circuit 14.

  The voltage detection unit 11 detects the terminal voltage of the lead storage battery 13 and notifies the control unit 10 of it. The current detection unit 12 detects a current flowing through the lead storage battery 13 and notifies the control unit 10 of the current. The discharge circuit 14 includes, for example, a semiconductor switch, and discharges the lead storage battery 13 by turning on or off the semiconductor switch in accordance with the control of the control unit 10. The alternator 15 is driven by a prime mover (not shown) such as a reciprocating engine, for example, and generates DC power to charge the lead storage battery 13. The cell motor 16 is constituted by, for example, a DC motor, and is rotated by DC power supplied from the lead storage battery 13 to start the prime mover. The load 17 is composed of, for example, an automobile headlight, a wiper, a direction indication light, a navigation device, and other devices.

(B) Description of Operation of First Embodiment Next, operation of the first embodiment will be described. FIG. 3 is a flowchart for explaining the flow of processing executed in the first embodiment shown in FIG. When the processing of this flowchart is started, the following steps are executed.

  In step S10, the CPU 10a assigns “0” as an initial value to a variable i for counting the number of processes.

  In step S11, the CPU 10a controls the discharge circuit 14 to discharge the electric power stored in the lead storage battery 13. More specifically, the lead storage battery 13 changes to the discharge circuit 14 by turning on or off the discharge circuit 14 at a predetermined cycle (for example, 10 ms cycle) and at a predetermined duty ratio (for example, 50% duty ratio). Through current.

  In step S <b> 12, the CPU 10 a calculates the internal impedance Z of the lead storage battery 13 based on the detection values obtained by the voltage detection unit 11 and the current detection unit 12. Specifically, when the discharge circuit 14 is in the on state, for example, the detection values obtained by the voltage detection unit 11 and the current detection unit 12 are sampled at a period of 0.1 [mS], and the obtained measurement values are obtained. Thus, adaptive learning is executed using a simulation model showing the lead storage battery 13 to obtain an impedance value.

  In this specification, “adaptive learning” refers to a method in which a flexible and general model having parameters is prepared and the parameters are optimized statistically and adaptively by learning. As adaptive learning, for example, there is a method using an extended Kalman filter. Note that the present invention is not limited only to the extended Kalman filter. For example, adaptive learning using a neural network model, adaptive learning using a genetic algorithm model, or the like can be used. That is, any method can be used as long as it creates a learning target model and optimizes the parameters constituting the model based on the results obtained by observation.

  FIG. 4 is a diagram illustrating an example of the sampling operation. In the example of this figure, discharge is executed at a predetermined period τ, and sampling is executed a plurality of times (for example, 50 times) during each discharge operation to obtain a measured value. The impedance value in each discharge operation is calculated by adaptive learning based on the measured values (for 50 times). In the following, a period in which sampling is performed a plurality of times during the discharge operation is referred to as a sampling period and is described as sampling periods # 0 to # 4. In the example of FIG. 4, it is assumed that, for example, 50 times of sampling are executed in each of the sampling periods # 0 to # 4.

  In step S13, the CPU 10a stores the value of the impedance Z calculated in step S12 as the measured value 10ca at the i-th array S []. In this example, it is assumed that N times of sampling are executed, and the value of the variable i changes between 0 and (N−1). For example, since i = 0 in the first process, the impedance value calculated based on the measurement value obtained in the first sampling (sampling period # 0) is stored in the array S [0]. Note that the value of N can be selected, for example, from several to several tens. Of course, other values may be used.

  In step S14, the CPU 10a increments the value of the variable i for counting the number of processes by “1”.

  In step S15, the CPU 10a determines whether or not the value of the variable i is greater than or equal to the value of the constant N. If the value of the variable i is greater than or equal to the value of the constant N (step S15: YES), the process proceeds to step S16. In other cases (step S15: NO), the process returns to step S11 and the same processing as described above is repeated. N impedance values are stored in the arrays S [0] to S [N−1] by repeating the processes in steps S11 to S15. For example, in the example of FIG. 4A, five impedance values respectively calculated in the sample periods # 0 to # 4 are stored as the 0th to 4th elements of the array S [].

  In step S <b> 16, the CPU 10 a substitutes an initial value “0” for a variable i for counting the number of processes, and also substitutes an initial value “0” for a variable E for specifying a position where a measurement error occurs. Details of the variable E will be described later.

  In step S17, the CPU 10a stores a value obtained by subtracting the (i + 1) th element of the array S [] from the i-th element of the array S [] in a variable D that stores the difference value. Specifically, for example, when i = 0, a value obtained by subtracting the first element of the array S [] from the 0th element of the array S [] is stored in the variable D. Here, the impedance value of S [i] and the impedance value of S [i + 1] correspond to the “impedance value pair” in the claims.

  In step S18, the CPU 10a determines whether or not the absolute value ABS (D) of the difference value D obtained in step S17 is larger than a predetermined threshold Th, and when ABS (D)> Th is satisfied. In step S18: YES, the process proceeds to step S19. In other cases (step S18: NO), the process proceeds to step S20. Specifically, when the absolute value ABS (D) of the difference value D is larger than 0.5 mΩ, which is the threshold Th, for example, the process proceeds to step S19. The threshold Th may be a value other than those described above, and an appropriate value can be selected according to the capacity of the lead storage battery 13 or the like.

In step S19, the CPU 10a updates the value of the variable E with a value obtained by adding 2 ⁱ to the current value of the variable E. For example, as shown in FIG. 4A, in the case where five measurements are performed, if all measured values are normal and ABS (D)> Th is not satisfied, five processing loops are performed. Since the calculation in step S19 is never executed, the value of the variable E remains 0. Further, as shown in FIG. 4B, when the measurement is performed five times, if the measurement value in the sampling period # 2 becomes abnormal at the time t during the measurement, the sampling is performed as shown in FIG. The difference value between the periods # 1 and # 2 and the difference value between the sampling periods # 2 and # 3 are larger than the threshold value Th (greater than 0.5 mΩ). As a result, variable E stores 6 which is the sum of 2 ¹ and 2 ² . In the example of FIG. 4 (B), for example, current starts to flow to the load 17 at time t, so that the current and voltage thereafter deviate from the normal state. In the sampling period # 3 and the sampling period # 4, the voltage and current deviate from the normal state, but since adaptive learning is performed, the impedance value is accurately determined by eliminating the influence of the current flowing through the load 17. Can be requested. On the other hand, in the sampling period # 2, since the current flows to the load 17 during the adaptive learning and the measured value changes significantly, an error occurs even though the adaptive learning is performed. Therefore, the impedance value obtained in the sampling period # 2 is excluded as will be described later.

  In step S20, the CPU 10a increments the value of the variable i for counting the number of processes by “1”.

  In step S21, the CPU 10a determines whether or not the value of the variable i is (N-1) or more. If the value of the variable i is (N-1) or more (step S21: YES), the step is executed. The process proceeds to S22, and in other cases (step S21: NO), the process returns to step S17 and the same process as described above is repeated. By repeating the processes of steps S17 to S21, the difference values of all the impedance values stored in the arrays S [0] to S [N-1] are calculated, and the variable E is compared with the threshold value Th. The value is updated.

  In step S22, the CPU 10a executes an “exclusion process” that is a process of excluding an impedance value having an error. Specifically, the CPU 10a specifies the impedance value of the sampling period having an error based on the value stored in the variable E, and excludes the impedance value from the calculation target. For example, in the example of FIG. 5, since the value “6” is stored in the variable E as described above, it is possible to specify that the impedance value obtained in the sampling period # 2 has an error. As shown in the bottom row of FIG. 5, the impedance value corresponding to the sampling period # 2 is invalidated (INVALID). As shown in FIG. 4A, when all the measured values are normal and ABS (D)> Th is not satisfied, the calculation in step S19 is not executed, so the value of the variable E is 0. Will remain. In that case, there is no impedance value to be excluded.

  In step S23, the CPU 10a calculates an average value of the impedance values stored in the array S [] that are not excluded (not "INVALID"), and ends the process. Thereby, for example, in the example of FIG. 4A, the average value of all impedance values for five sampling periods # 0 to # 4 is calculated. In the example of FIG. 4A, the average value of the impedance values other than the sampling period # 2 is calculated. As a result, an abnormal impedance value can be quickly detected and excluded from the average value calculation target. Further, when a measurement error occurs, only the impedance value in which the error has occurred can be excluded and other impedance values can be used effectively. For this reason, as in the prior art, when a measurement error occurs, power wasted can be reduced by performing the measurement again.

  Next, details of the process of step S22 shown in FIG. 3 will be described with reference to FIG. When the process of the flowchart shown in FIG. 6 is executed, the following steps are executed.

  In step S30, the CPU 10a searches the table stored in the ROM 10b for information indicating the sampling period corresponding to the value of the variable E obtained by the process shown in FIG. FIG. 7 is a table (corresponding to FIG. 4) corresponding to a measurement having five sampling periods. The value of the variable E is stored in the left column in FIG. 7, and the value indicating the sampling period corresponding to the value in the left column is stored in the right column. Specifically, “1” is stored in the left column of the first row, and “0” is stored in the right column. This indicates that when the value of the variable E is “1”, the impedance value of the sampling period # 0 is abnormal. Note that “others” in the last row indicates that an abnormality occurred in a plurality of sampling periods for values other than those described in the table. FIG. 8 is a table corresponding to a measurement having eight sampling periods. Also in the example of this figure, as in the case of FIG. 7, the value of the variable E is stored in the left column, and the value indicating the sampling period corresponding to the value of the left column is stored in the right column. ing.

  In step S31, the CPU 10a acquires the value of i corresponding to the value of the variable E (value indicating the sampling period) based on the search in step S30. For example, as described above, when the value “6” is stored in E, the value “2” is acquired as shown in FIG.

  In step S32, the CPU 10a determines whether or not the value acquired in step S31 is "multiple occurrences". If multiple occurrences (step S32: YES), the process proceeds to step S33, and otherwise (steps) In S32: NO), the process proceeds to Step S34. Specifically, if an abnormality has occurred in a plurality of sampling periods, since the occurrence is obtained from the table in step S31, the process proceeds to step S33 in that case.

  In step S33, the CPU 10a executes error processing. Specifically, when abnormality has occurred in a plurality of sampling periods, it is determined that accurate impedance calculation is difficult, and, for example, the process returns to step S10 in FIG. 3 and the same processing is repeated.

  In step S34, the CPU 10a stores "INVALID" as the i-th element of the array S []. Specifically, when the value of the variable E described above is “6”, “2” is acquired in step S31 and i = 2, so in the process of step S34, the second of the array S [] is obtained. “INVALID” is stored as the second element. And it returns (returns) to the process of step S23. In the process of step S23, the average impedance is calculated for the impedance value in which “INVALID” is not stored. Specifically, in the above-described example, the average impedance is calculated for objects other than the second element of the array S [].

  As described above, in the present embodiment, a difference value between impedance values measured before and after is obtained, and if the difference value is greater than a predetermined threshold value, it is determined that an abnormality has occurred. Therefore, an abnormal impedance value can be found quickly. In addition, when an abnormality occurs, a value peculiar to the sampling period is stored in the variable E, and the sampling period is specified by comparison with the table. Therefore, it is easy to specify the period in which the abnormality has occurred. In addition, it is possible to reliably exclude an impedance value having an abnormality. Moreover, by excluding the impedance value in which an abnormality has occurred and using it, it is possible to prevent the power of the lead storage battery 13 from being wasted compared to the case where all measured values are discarded and remeasured.

(C) Second Embodiment The second embodiment differs from the first embodiment in the contents of the exclusion process shown in FIG. 6 (the contents of the process in step S22 in FIG. 3). The rest is the same as in the case of the first embodiment. That is, in the first embodiment, the sampling period in which an abnormality has occurred is identified with reference to the tables shown in FIGS. 7 and 8. In the second embodiment, as shown in the flowchart of FIG. The sampling period in which an abnormality has occurred is specified based on the bit information stored in the. This will be specifically described. When the process of the flowchart shown in FIG. 9 is executed, the following steps are executed. In the following, it is assumed that the information stored in the variable E represents binary bit information (information of “1” or “0”). Specifically, when the decimal value “6” is stored in E, the bit information is, for example, “00110”. Further, E _(i) described in the flowchart indicates information on the i-th bit when the LSB (Least Significant Bit) of the variable E is set to the 0th bit. For example, when the value “6” is stored in E, E ₍₀₎ = E ₍₃₎ = E ₍₄₎ = 0 and E ₍₁₎ = E ₍₂₎ = 1. In the example described above, the case where the variable E is 5 bits has been described as an example, but it goes without saying that the variable E may be other than this.

  In step S50, the CPU 10a substitutes an initial value “0” for a variable i for counting the number of processes.

In step S51, the CPU 10a determines whether E _(i) = 1 and E _{(i + 1)} = 1 is satisfied, and if so (step S51: YES), the process proceeds to step S52. In other cases (step S51: NO), the process proceeds to step S53. Specifically, when the value of the variable E is “6” (the third case from the top in FIG. 7), when i = 1, E ₍₁₎ = 1 and E _{(2 )} = 1 holds, in which case the process proceeds to step S52.

  In step S52, the CPU 10a stores (overwrites) “INVALID” as the (i + 1) th element of the array S []. In the previous example (E = 6, i = 1), “INVALID” is overwritten as the second element of the array S []. Thereby, as shown in FIG. 5, “8.5 mΩ” is overwritten by “INVALID”.

  In step S53, the CPU 10a increments the value of the variable i for counting the number of processes by “1”.

  In step S54, the CPU 10a determines whether or not the value of the variable i is equal to or greater than the value of (N-1), and when the value of the variable i is equal to or greater than the value of (N-1) (step S54: YES). ), The process proceeds to step S55. In other cases (step S54: NO), the process returns to step S51 and the same processing as described above is repeated. If there is a continuous bit in the variable E by repeating the processes in steps S51 to S54, the element of the corresponding array S [] is set to “INVALID”.

In step S55, the CPU 10a determines whether E ₍₀₎ = 1 and E ₍₁₎ = 0 is satisfied, and if so (step S55: YES), the process proceeds to step S56. In other cases (step S55: NO), the process proceeds to step S57. Specifically, when the value of the variable E is “1” (when S [0] is abnormal), E ₍₀₎ = 1 and E ₍₁₎ = 0 hold. In that case, the process proceeds to step S56.

  In step S56, the CPU 10a overwrites “INVALID” with respect to the 0th element of the array S []. In the previous example, “INVALID” is overwritten on the 0th element of the array S [].

In step S57, the CPU 10a determines whether E _(N-1) = 1 and E _(N-2) = 0, and if so (step S57: YES), the step is step. The process proceeds to S58, and in other cases (step S57: NO), the process returns (returns) to the process of step S23. Specifically, when the value of the variable E is “8” (when S [4] is abnormal), E ₍₄₎ = 1 and E ₍₃₎ = 0 hold. In that case, the process proceeds to step S58.

  In step S58, the CPU 10a overwrites “INVALID” as the (N−1) th element of the array S []. In the previous example, “INVALID” is overwritten as the fourth element of the array S []. And it returns (returns) to the process of step S23.

  According to the above processing, an abnormal impedance value stored in the array S [] can be found based on the bit information of the variable E. According to such an embodiment, it is possible to process an arbitrary number of impedance values. In addition, since the table is unnecessary, the storage capacity of the memory can be reduced.

  In addition, in the second embodiment, even when there are two or more abnormalities, the average value of the impedance values can be obtained without executing error processing, so the measurement processing is re-executed. It is possible to prevent the power of the lead storage battery 13 from being wasted.

(D) Modified Embodiments Each of the above-described embodiments is an example, and there are various modified embodiments other than this. For example, in each of the above embodiments, it is not assumed that abnormalities occur continuously. However, if abnormalities occur continuously, these impedances are all ignored, for example. Also good. This will be described with reference to FIG. In FIG. 10A, an abnormality has occurred in sampling period # 2 and sampling period # 3. In this case, “NG” is determined in the determination of step S18 for the sampling periods # 1 and # 2 and the determination for the sampling periods # 3 and # 4. However, in the same determination for the sampling periods # 2 and # 3, the abnormality may or may not be determined depending on how the abnormality occurs during these periods. For example, in the example of FIG. 5, when “8.6 mΩ” is measured instead of “6.7 mΩ” in the sampling period # 3, this is an abnormal value, but in the relationship with the sampling period # 2, the difference is Since the value is “0.1 mΩ”, it is determined to be normal. Further, when it is measured as “4.5 mΩ”, it is determined to be abnormal. In other words, the determination for the sampling periods # 2 and # 3 is determined according to the measured value, and so is “undefined”.

  FIG. 10B shows an example in which an abnormality occurs three times in succession. In this example, the determinations for sampling periods # 2 and # 3 and sampling periods # 3 and # 4 are “undefined”. Therefore, when there are two sampling periods determined to be abnormal, the impedance value corresponding to the period sandwiched between these two sampling periods is determined to be invalid, so that the impedance that is “indefinite” The value can be prevented from being used for calculation. Of course, if the number of impedance values that can be used is reduced by excluding impedance values that are “indeterminate” (for example, 50% or more), the accuracy of the average value itself is reduced, so that it is excluded. If the number of target impedance values is large, the measurement may be performed again.

  Moreover, although the case where adaptive learning was performed using an extended Kalman filter was described as an example in the above embodiment, other methods may be used. Specifically, adaptive learning may be performed using a neural network model, or adaptive learning may be performed using a genetic algorithm model. Moreover, you may make it measure an impedance value directly, without using a model.

  In the above embodiment, the impedance value is measured, but the real component (resistance component) or imaginary component (reactance component) of the impedance is measured alone, or other values (for example, lead The CPE (Constant Phase Element) included in the equivalent circuit of the storage battery 13 may be measured.

  Further, in the above embodiment, adaptive learning is executed based on the discharge current from the discharge circuit 14, but adaptive learning may be executed based on a current flowing through a load other than this. For example, when a current flowing through the cell motor 16 is used or when a motor for driving the vehicle (for example, a motor of a hybrid vehicle) exists, adaptive learning is performed based on the current flowing through the motor. May be. In addition, for example, in the case of a photovoltaic power storage battery used in a general household, it is possible to use a current flowing in various loads used in the household (for example, an air conditioner in which a large current flows at startup). . Furthermore, the measurement may be performed based on the charging current when charging instead of discharging.

  Moreover, although the above embodiment demonstrated lead acid battery as an example, it is possible to apply this invention also about batteries other than this (for example, nickel cadmium battery etc.). In this case, the simulation model may be changed according to the type of battery.

  In the above embodiment, the control unit 10 is configured by a CPU, a ROM, a RAM, and the like, but may be configured by, for example, a DSP (Digital Signal Processor).

DESCRIPTION OF SYMBOLS 1 Battery internal state estimation apparatus 10 Control part 10a CPU (judgment means, exclusion means, estimation means)
10b ROM
10c RAM (storage means)
10d I / F (part of measuring means)
11 Voltage detector (part of measuring means)
12 Current detector (part of measuring means)
13 Lead acid battery (battery)
14 Discharge circuit 15 Alternator 16 Cell motor 17 Load

Claims (7)

In the battery internal state estimation device for estimating the internal state of the battery,
Measuring means for measuring the impedance value of the battery at a predetermined period;
Storage means for storing the impedance value measured by the measurement means;
Determination means for determining whether or not a difference value of an impedance value pair as a set of impedance values measured before and after time is greater than a predetermined threshold;
If there are a plurality of impedance value pairs for which the difference value is determined to be greater than a predetermined threshold by the determination means, the impedance values that are commonly included in the impedance value pair are excluded as including measurement errors. Exclusion means to
Estimating means for estimating the internal state of the battery based on impedance values not excluded by the excluding means;
A battery internal state estimation device comprising:   The exclusion means is a case where there is a single impedance value pair for which the difference value is determined to be larger than a predetermined threshold by the determination means, and when the impedance value pair is at the start of measurement or at the end of measurement, 2. The battery internal state estimating device according to claim 1, wherein a leading or trailing impedance value included in the impedance value pair is excluded.   3. The battery internal state estimation device according to claim 1, wherein the measuring unit discharges current to the battery and measures the impedance value based on a voltage value and a current value at that time.   In the case where there are two consecutive impedance value pairs for which the difference value is determined to be greater than a predetermined threshold, the excluding means, for the impedance values that are commonly included in these two impedance value pairs, The battery internal state estimation device according to any one of claims 1 to 3, wherein a measurement error is excluded as being included.   The exclusion means configures an impedance value pair that exists between the two impedance value pairs when there are two impedance value pairs that are determined to have a difference value larger than a predetermined threshold with a gap between them. 5. The impedance value to be excluded is excluded as including a measurement error, and the measured timing is excluded from the two impedance value pairs other than the first and last impedance values. The battery internal state estimation apparatus according to item 1. Bit information is associated with each impedance value pair,
The determination means inverts corresponding bit information for an impedance value pair whose difference value is larger than a predetermined threshold value,
When there are a plurality of impedance value pairs in which the corresponding bit information is inverted, the exclusion means excludes the impedance values that are commonly included in the impedance value pairs as including measurement errors,
The battery internal state estimation apparatus according to any one of claims 1 to 5, wherein In the battery internal state estimation method for estimating the internal state of the battery,
A measurement step of measuring the impedance value of the battery at a predetermined period;
A storing step of storing the impedance value measured by the measuring step in a memory;
A determination step of determining whether or not a difference value of an impedance value pair as a set of impedances measured before and after in time is greater than a predetermined threshold;
If there are a plurality of impedance value pairs for which the difference value is determined to be larger than a predetermined threshold in the determination step, the impedance values that are commonly included in the impedance value pair are excluded as including measurement errors. An exclusion step to
An estimation step for estimating an internal state of the battery based on an impedance value not excluded in the exclusion step;
A battery internal state estimation method comprising:

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