JP5110840B2 - Coreless substrate and semiconductor device mounting structure using the same - Google Patents

Description

  The present invention relates to a prepreg obtained by impregnating and drying a resin in a glass cloth, a coreless substrate having a so-called core substrate excellent in rigidity function such as a metal plate, and a semiconductor element mounting structure using the same.

  Conventionally, resin wiring boards are known as wiring boards for mounting semiconductor elements such as IC (Integrated Circuit) and LSI (Large Scale Integration) on the upper surface.

  As such a wiring board, one in which an insulating layer and a conductor are laminated on a core board as a reinforcing material has been proposed. In recent years, a thin wiring board has been demanded in response to a demand for downsizing of electronic devices.

As a thin wiring board, a coreless board without a core board has been proposed (see Patent Document 1 below).
JP 2004-281999 A

  However, in the case of the above-described conventional coreless substrate, since the rigidity is weaker than that of the wiring substrate having the core substrate, there is a problem that when a force is applied to the coreless substrate, the coreless substrate is easily broken and destroyed.

  The present invention has been made in view of the above-described problems, and can provide a coreless substrate having excellent reliability and a mounting structure for a semiconductor element using the coreless substrate that can effectively suppress the destruction of the coreless substrate. The purpose is to do.

In order to solve the above problems, a coreless substrate of the present invention includes a first insulator having a first fiber layer composed of a plurality of first fiber bundles arranged in a first direction in plan view, and the first insulator A second insulator having a second fiber layer disposed on the insulator and having a plurality of second fiber bundles arranged in a second direction orthogonal to the first direction in plan view; A third fiber layer formed by weaving a plurality of third fiber bundles arranged on the insulator and arranged along the first direction and a plurality of fourth fiber bundles arranged along the second direction a third insulator having a, characterized by comprising a conductor made is interposed between the second insulator and the first insulator.

  According to the present invention, the coreless substrate can be effectively prevented from being destroyed by providing the fiber layer having excellent rigidity inside the insulator and improving the rigidity of the insulator.

  Embodiments of a coreless substrate and a semiconductor element mounting structure using the same according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1A is a cross-sectional view of a first embodiment of a semiconductor element mounting structure of the present invention, and FIG. 1B is a plan view of a fiber layer described later.

<< First Embodiment >>
As shown in FIG. 1, the semiconductor element mounting structure according to the present embodiment includes a coreless substrate 1 and a semiconductor element 2 such as an IC or LSI mounted on the coreless substrate 1. Here, the semiconductor element 2 is mounted on the coreless substrate 1 via a bonding material 3 such as solder. Hereinafter, the coreless substrate 1 will be mainly described.

<Coreless substrate>
The coreless substrate 1 is used for electronic devices such as various audiovisual devices, home appliances, communication devices, computer devices and peripheral devices, and has a conductor 4 and first insulators 5a and second insulators in the thickness direction. The body 5b is laminated and provided. The conductor 4 is interposed between the first insulator 5a and the second insulator 5b. Moreover, the 1st insulator 5a and the 2nd insulator 5b are named generically the insulator 5, when not distinguishing both.

  The conductor 4 has conductivity and has a function as a transmission path for transmitting an electrical signal. The conductor 4 is made of a conductive material such as copper, silver, gold, aluminum, nickel, or chromium. The conductor 4 is formed on a plane in plan view, and is partially formed on the plane in order to form a wiring pattern. The thickness of the conductor 4 is 3 to 10 μm.

  The insulator 5 includes a fiber layer 6 formed on a plane in plan view and a resin layer 7 that covers the fiber layer 6 from both sides in the thickness direction. In addition, as shown in FIG. 1, the fiber layer 6 located in the lower part in the thickness direction is referred to as a fiber layer 6a, and the fiber layer 6 located in the upper part is referred to as a fiber layer 6b. The fiber layer 6 is a generic name when the fiber layers 6a and 6b are not distinguished from each other.

  The fiber layers 6a and 6b include a first fiber bundle 6p arranged along the first direction X in plan view and a second fiber arranged along a second direction Y different from the first direction X in plan view. The bundle 6q is knitted into a planar shape.

  The first fiber bundle 6p and the second fiber bundle 6q have rigidity, and are composed, for example, of polybenzoxazole, wholly aromatic polyamide, or wholly aromatic polyester as a main component. Here, the main component in this specification is a substance having the largest number of moles among a plurality of substances constituting the layer. The fiber layer 6 shown in FIG. 1 is in a state in which a single first fiber bundle 6p and a second fiber bundle 6q are knitted, but a plurality of first fiber bundles 6p and a plurality of second fiber bundles 6q are knitted. It may be configured by.

  Moreover, the 1st fiber bundle 6p and the 2nd fiber bundle 6q are cylindrical shape, The diameter is 5-12 micrometers. Therefore, the main surface or the other main surface of the fiber layer 6 is formed to be uneven.

  The resin layer 7 has adhesiveness before being solidified, and is composed of, for example, any one of polyimide, aramid, and polyimide benzoxazole as a main component. The resin layer 7 is attached to the main surface or the other main surface of the fiber layer 6 by being heated and pressed using a heating press device in a state where the resin layer 7 is laminated on the fiber layer 6. Moreover, the resin layer 7 is formed so that the thickness after drying may be 10-30 micrometers.

  Moreover, since the resin layer 7 is comprised from the organic material similarly to the fiber layer 6, the fiber layer 6 and the resin layer 7 adhere | attach the organic materials firmly, and the gap in both interface is effective. Suppressed. As a result, peeling between the fiber layer 6 and the resin layer 7 can be effectively prevented.

  Furthermore, the resin layer 7 is formed in close contact with the concavo-convex surface of the fiber layer 6, and is attached to the surface area of the fiber layer 6 rather than the main surface or the other main surface of the fiber layer 6. Is big. As a result, the resin layer 7 has higher adhesion than the so-called flat surface, and effectively suppresses the peeling of the interface between the fiber layer 6 and the resin layer 7. be able to.

  The insulator 5 has an opening 8 in the thickness direction, and an opening conductor 9 having conductivity is embedded in the opening 8. On the coreless substrate 1, conductors 4 and insulators 5 are alternately laminated according to the number of layers of a desired wiring pattern. When a plurality of conductors 4 and insulators 5 are stacked, the conductors 4 having different layers are electrically connected by the opening conductor 9.

  According to the embodiment described above, the fiber bundle 6 having excellent rigidity of the fiber layer 6 can effectively suppress the destruction of the coreless substrate 1 by improving the rigidity of the entire insulator 5.

<Manufacturing method>
The coreless substrate 1 according to this embodiment is manufactured through the following processes, for example.

  First, the insulator 5 is produced. The fiber bundle is formed into a thread by bundling single fibers. And the fiber layer 6 is formed by plain-weaving a fiber bundle with a loom, and heat-pressing what was plain-woven in the thickness direction using a press apparatus etc.

  Next, a resin material (for example, a precursor of an epoxy resin) is prepared, and a varnish is prepared by mixing a spherical silica powder subjected to a silane coupling treatment in advance with a solvent. And the produced varnish is impregnated into the fiber layer 6, and the insulator 5 which coat | covered the fiber layer 6 with the resin 7 from the both sides of the thickness direction is produced.

  Then, a low thermal expansion substrate 10 is prepared. The substrate 10 is made of, for example, Fe—Ni—Co based Kovar, Fe—Ni based Invar, permalloy, molybdenum, tungsten, CFRP (carbon fiber reinforced plastic), or the like. Moreover, the thickness of the board | substrate 10 is 0.1-1.5 mm, for example.

  As shown in FIG. 2A, the cover film 11 is formed on the substrate 10 by, for example, a spin coating method, a printing method, or the like. The cover film 11 is made of, for example, copper, silver, gold, etc., and the thickness is, for example, 0.1 μm to 1 μm.

  Next, after the cover film 11 is dried and solidified, the copper plating 4a is formed on the cover film 11 by, for example, spin coating, die coating, curtain coating, printing, lamination, or the like.

  After the copper plating 4a is dried, as shown in FIG. 2-1 (b), a resist 12 is applied on the copper plating 4a, and the resist 12 is patterned by a photolithography process or the like. The resist 12 is formed only in the region where the copper plating is left, and the region not covered with the resist 12 is etched. Then, the remaining resist 12 is peeled off, and the conductor 4 can be formed on the cover film 11. Further, after removing the resist 12, the conductor 4 is cleaned. The conductor 4 may be formed by patterning a plating resist on the cover film 11 and depositing copper by electroforming.

  As shown in FIG. 2C, the prepared insulator 5 is laminated on the conductor 2 formed on the cover film 11. Then, the insulator 5 is fixed to the cover film 11 with a high pressure while applying a temperature by, for example, a laminating method. At this time, since the thermal expansion coefficient of the resin layer 7 of the insulator 5 is larger than that of the fiber layer 6 and the substrate 10, it expands by heating. After that, when the insulator 5 is cooled, the resin layer 7 has a large coefficient of thermal expansion as described above, and therefore has a large force to contract. However, the fiber layer 6 and the substrate 10 are difficult to contract because the coefficient of thermal expansion is small. As a result, since the resin layer 7 is cooled while being sandwiched between the fiber layer 6 and the substrate 10 which are difficult to shrink, the resin layer 7 is solidified in a state where tensile stress to be contracted is acting in the resin layer 7, and the insulator 5 is provided with residual stress.

  Next, as shown in FIG. 2D, an opening 8 is formed in the insulator 5 by a laser, a drill, or the like. Here, the fiber layer 6 and the resin layer 7 have a melting point of about 500 degrees. On the other hand, in the case of glass fiber, the melting point is 1000 degrees or more. Therefore, when the fiber layer 6 is made of glass fiber, the melting point of the glass fiber is much larger than that of the resin layer 7. Therefore, when the opening 8 is formed at a high temperature, the resin melts more than necessary, and the opening 8 Is difficult to form in a desired size, and if the opening 8 is formed at a low temperature, the glass fiber cannot be burned out sufficiently. Therefore, it is desirable that the fiber layer 6 is made of polybenzoxazole or the like having a melting point close to that of the thermosetting resin and easy to process.

  Then, as shown in FIG. 2E, an opening conductor 9 is provided on the formed opening 8 by electroless plating, electroplating, or the like, and a copper foil 4b is formed on the insulator 5.

  Further, the copper foil 4 b is processed into a predetermined pattern by photolithography and etching, and a new conductor 4 ′ is formed on the insulator 5. Then, as shown in FIG. 2-2 (f), the substrate 10 and the cover film 11 are separated.

  Thereafter, the cover film 11 is removed by etching or the like, and the coreless substrate 1 can be obtained. Moreover, the insulator 5 and the conductor 4 can be further laminated on the obtained coreless substrate 1 by a build-up method, so that a multilayer coreless substrate can be manufactured. Further, a semiconductor element 2 such as an IC or LSI is mounted on the coreless substrate 1 to complete a semiconductor element mounting structure. At this time, when the semiconductor element 2 is mounted on the coreless substrate 1, heat such as solder is applied to the coreless substrate 1 in order to fix the semiconductor element 2 to the coreless substrate 1 with solder or the like. Normally, when heat is applied to the substrate, the substrate expands according to the coefficient of thermal expansion. However, when heat is applied to the insulator 5 of the coreless substrate 1, the residual stress that the insulator 5 tries to shrink is relaxed. Until it disappears, the insulator 5 hardly expands, and the expansion amount of the entire wiring board 1 can be reduced.

<< Second Embodiment >>
Hereinafter, a second embodiment of the semiconductor element mounting structure according to the above embodiment will be described with reference to FIG. In addition, about the structure shown in the above-mentioned FIG. 1, the same referential mark is attached | subjected and description is abbreviate | omitted and a different location is demonstrated.

  The fiber bundle 6r which comprises the fiber layer 6 which concerns on 2nd Embodiment is arranged along the plane direction in planar view. Here, the fiber bundle 6r is made of the same material as the first fiber bundle 6p and the second fiber bundle 6q described above, and the fiber bundle 6r is arranged in a state along the planar direction in plan view, and then as described above. The fiber bundle 6r can be formed by covering the resin layer with 7 from both sides in the thickness direction.

  The insulating fiber bundle 6r positioned below the pair of insulators 5 stacked in the thickness direction and the insulating fiber bundle 6r 'positioned above are arranged so as to be orthogonal to each other in plan view. Also good. In that case, since the resin layer 7 is unlikely to expand in the direction along the fiber bundles 6r and 6r ', it is possible to reduce the vertical and horizontal expansion in a plan view and to effectively suppress the expansion of the entire coreless substrate.

  The fiber layer 6c made of the fiber bundle 6r can be made thinner than the one formed by weaving the first fiber bundle 6p and the second fiber bundle 6q. The fiber layers 6a and 6b in which the fiber bundles are knitted must form at least two fiber bundles in the thickness direction, whereas the fiber layers 6c are simply arranged along the plane direction without knitting the fiber bundles. Since the thickness of one fiber bundle can be reduced, the thickness of the insulator 5c can be further reduced. As a result, it is possible to realize the coreless substrate 1 that is sufficiently compatible with downsizing of electronic devices.

  Moreover, since the fiber layers 6a and 6b are formed by bending the fiber bundle, they are formed so as to be elastically deformable. As a result, since the fiber layers 6a and 6b are more contracted by thermal expansion than the fiber layer 6c, the residual stress is reduced. For this reason, the fiber layer 6c can make the residual stress of the insulator 5c larger than the fiber layers 6a and 6b.

<< Third Embodiment >>
Hereinafter, a third embodiment of the semiconductor element mounting structure according to the above-described embodiment will be described with reference to FIG. In addition, about the structure shown in above-mentioned FIG.1 and FIG.2, the same referential mark is attached | subjected and description is abbreviate | omitted and a different location is demonstrated.

  The fiber layer 6d according to the third embodiment has a structure in which a plurality of fiber layers arranged in the planar direction in a plan view are stacked. Since the fiber bundles are cylindrical and all of the arranged fiber bundles have substantially the same size, when the fiber bundles are arranged, the arranged fiber layer has irregularities on its main surface and other main surfaces. Is done. And the unevenness | corrugation of the main surface of the 1st fiber layer 61 is arrange | positioned so that the unevenness | corrugation of the other main surface of the 2nd fiber layer 6m formed on the 1st fiber layer 61 may be fitted. Furthermore, it is desirable to dispose the main surface of the second fiber layer 6m so as to fit the other main surface of the third fiber layer 6n formed on the second fiber layer 6m.

  The thickness in the thickness direction of the fiber layer 6d can be reduced not by the thickness of the three fiber bundles but by the thickness of the fitted portion as described above. Therefore, it is possible to improve the rigidity of the insulator 5 and effectively suppress the coreless substrate 1 from becoming thick. Note that the number of fiber layers 6d is not limited to the three layers described above, and can be appropriately selected based on the relationship between the rigidity and thickness of the coreless substrate 1.

<< Fourth Embodiment >>
Below, with reference to FIG. 5, 4th Embodiment of the mounting structure of the semiconductor element which concerns on the said embodiment is described. In addition, about the structure shown in the above-mentioned FIG.1, FIG.2, FIG.3, the same referential mark is attached | subjected and description is abbreviate | omitted and a different location is demonstrated.

  As shown in FIG. 5, the coreless substrate having three layers of the insulator 5 is located at the lower part in the thickness direction, the insulator 5x having the fiber layer 6x in which the fiber bundle is knitted, and the middle part in the thickness direction. And the insulator 5y having the fiber layer 6y arranged in the first direction X in the plan view and the upper part in the thickness direction, and the fiber bundle arranged in the second direction Y in the plan view. And an insulator 5z having a fiber layer 6z. In addition, the fiber bundle which the fiber layer 6x has includes the 1st fiber bundle 6p arrange | positioned along the 1st direction X, and the 2nd fiber bundle 6q arrange | positioned along the 2nd direction Y.

  The coreless substrate formed by laminating the insulator 5 has a thickness of the coreless substrate that is thin and rigid when the number of layers of the insulator 5 is four or less and there is no fiber layer in which a fiber bundle is knitted into the insulator 5. Therefore, it is difficult to keep the entire coreless substrate flat, and the entire coreless substrate may bend. Therefore, when the number of the insulator layers is four or less, it is desirable to provide the insulator 5x having the fiber layer 6x in which at least one of the layers is woven.

  Further, when the number of layers of the insulator 5 is three, as shown in FIG. 5, the insulator 5x located at the lower part in the thickness direction has a fiber layer 6x in which a fiber bundle is knitted, and the upper part of the insulator 5x. It is desirable that the insulators 5y and 5z positioned in the are arranged so that the fiber bundles of the fiber layers 6y and 6z are orthogonal to each other in plan view. One of the insulators 5 located on the main surface or the other main surface of the core substrate has a fiber layer 6x in which the first fiber bundle 6p and the second fiber bundle 6q are knitted, so that it is rigid in the direction along the fiber bundle. Since it is excellent, it is possible to suppress vertical and horizontal contractions in a plan view.

  Further, in the insulators 5y and 5z located in the middle and upper part in the thickness direction, the fiber bundles 6y and 6z are arranged along the plane direction, and as described above, it is difficult to thermally expand in the direction along the fiber bundle. However, since the bonding force between the fiber bundles is usually small in the direction orthogonal to the fiber bundle in plan view, thermal expansion is likely to occur when heat is applied. However, a part of the conductor 4 is formed between the insulator 5y and the insulator 5z, but the insulator 5y and the insulator 5z are in direct contact with each other except where the conductor 4 is formed. Therefore, the force with which the insulator 5y and the insulator 5z try to contract each other can be reduced by the rigidity of the fiber bundles.

  In FIG. 5, the fiber layer 6x in which the fiber bundle is knitted is formed on the side opposite to the mounting side of the semiconductor element 2, but the laminated structure of the insulator 5 is turned upside down so as to be mounted on the mounting side of the semiconductor element 2. The fiber layer 6x may be formed.

  As described above, according to the fourth embodiment, it is possible to form a coreless substrate having a certain degree of rigidity while reducing the thickness of the insulator.

  In addition, this invention is not limited to the above-mentioned embodiment, It cannot be overemphasized that a various change and improvement are possible within the scope of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The 1st Embodiment which concerns on the mounting structure body of the semiconductor of this invention is shown, (a) is sectional drawing, (b) is a top view of a fiber layer. An example of the manufacturing method which concerns on the mounting structure of the semiconductor element of this invention is shown. An example of the manufacturing method which concerns on the mounting structure of the semiconductor element of this invention is shown. The 2nd Embodiment which concerns on the mounting structure of the semiconductor element of this invention is shown, (a) is sectional drawing, (b) is a top view of a fiber layer. Sectional drawing of 3rd Embodiment which concerns on the mounting structure of the semiconductor element of this invention is shown. Sectional drawing of 4th Embodiment which concerns on the mounting structure of the semiconductor element of this invention is shown.

Explanation of symbols

1 Coreless Substrate 2 Semiconductor Element 3 Bonding Material 4 Conductor 5 Insulator 6 Fiber Layer 7 Resin Layer 8 Opening 9 Opening Conductor 10 Substrate 11 Cover Film 12 Resist

Claims (4)

A first insulator having a first fiber layer composed of a plurality of first fiber bundles arranged in a first direction in plan view;
A second insulator having a second fiber layer that is disposed on the first insulator and is formed of a plurality of second fiber bundles arranged in a second direction orthogonal to the first direction in plan view;
A plurality of third fiber bundles arranged on the second insulator and arranged along the first direction; and a plurality of fourth fiber bundles arranged along the second direction. A third insulator having three fiber layers;
A coreless substrate, comprising: a conductor formed between the first insulator and the second insulator. The coreless substrate according to claim 1,
The coreless substrate, wherein the first fiber layer and the second fiber layer are mainly composed of polybenzoxazole, wholly aromatic polyamide, or wholly aromatic polyester. The coreless substrate according to claim 1,
The first insulator or the second insulator includes a resin layer formed by covering the first fiber layer or the second fiber layer from both sides in the thickness direction,
The core layer substrate is characterized in that the resin layer is mainly composed of polyimide, aramid, or polyimide benzoxazole.   A semiconductor element mounting structure comprising: the coreless substrate according to claim 1; and a semiconductor element mounted on the coreless substrate.

Images