JP5109258B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

Conventionally, a semiconductor device in which a semiconductor element (semiconductor chip) is mounted on a substrate has been used.
As a substrate used in such a semiconductor device, a substrate having a core layer and a buildup layer is used. A conductor layer (copper via wiring) is formed in the via hole in the buildup layer.
In such a substrate, in order to prevent disconnection of the conductor layer due to thermal shock and improve connection reliability, it has been proposed that the linear expansion coefficient α of the prepreg constituting the substrate be 10 to 80 ppm / ° C. or less. (For example, refer to Patent Document 1).

JP 2002-285015 A

However, in recent years, a finer via hole is formed in the build-up multilayer wiring layer, and a fine conductor layer is provided.
Therefore, there is a need for a technique that can more reliably prevent the conductor layer from being cut.

    The objective of this invention is providing the semiconductor device which can prevent the cutting | disconnection of a conductor layer reliably.

The inventors focused on the linear expansion coefficient in the region above the glass transition point (Tg) of the substrate.
It is considered that the resin constituting the substrate becomes rubbery at a temperature of Tg or higher. For this reason, in the rubber-like region of Tg or more, it was considered that the linear expansion coefficient was a value close to substantially zero, and the substrate was in a substantially no stress state.
In order to connect the substrate and the semiconductor element, when the solder bump or the gold wire (bonding portion) is melted, the substrate is heated to Tg or more of the substrate. However, since the substrate is heated for a relatively short time, the joining operation between the substrate and the semiconductor element is completed and the substrate is cooled before the substantially stress-free state is reached.
Conventionally, the substrate was considered to be substantially stress-free at temperatures above Tg, but in reality, the substrate was above Tg and had a predetermined linear expansion coefficient, and the stress was not sufficiently relaxed. I found out that In particular, it has been confirmed that the substrate rapidly expands in the thickness direction when the temperature becomes equal to or higher than Tg with respect to the Tg of the substrate.
Furthermore, in order to sufficiently prevent the conductor layer from being cut, the present inventors are more effective in controlling the amount of deformation equal to or greater than Tg in the thickness direction of the substrate, not the amount of deformation in the in-plane direction of the substrate. I found out.
The reason is not clear, but is presumed to be as follows.
When the substrate and the semiconductor element are connected, if the solder bump or the gold wire (joining portion) is melted, the substrate becomes a high temperature of Tg or higher.
At this time, the substrate expands in the in-plane direction of the substrate and the substrate thickness direction. Here, it is considered that the expansion in the in-plane direction of the substrate is suppressed by the conductor layer and the conductor wiring layer in the substrate. However, the expansion in the thickness direction of the substrate is not suppressed by the conductor layer or the conductor wiring layer, and is greatly expanded in the thickness direction of the substrate because the expansion in the in-plane direction of the substrate is suppressed. It is presumed that the rapid expansion in the thickness direction of the substrate when the temperature is equal to or higher than Tg is a factor for cutting the conductor layer in the substrate.
In other words, in the conventional substrate, the deformation amount after Tg is very large compared to the deformation amount in the thickness direction of the substrate before Tg, and the deformation amount after Tg is dominant in cutting the conductor layer. It is considered to be.
The present invention has been invented based on such knowledge.
That is, the present invention incorporates the idea of deformation in the thickness direction of the substrate itself after Tg, which has not been considered in the past, and reflects it in the design of the substrate.

According to the present invention, in a semiconductor device having a substrate, a semiconductor element mounted on the substrate, and a bonding portion containing a metal that connects the substrate and the semiconductor element, the substrate includes a cyanate resin. Insulating layers and conductor wiring layers are alternately stacked, and each of the conductor wiring layers is connected by a conductor layer formed in a via hole of the insulating layer, and an insulating layer containing cyanate resin A through hole having a conductor layer formed therein is formed, and the conductor layer in the through hole has a core layer connected to the conductor wiring layer of the buildup layer, and the glass transition of the substrate When the linear expansion coefficient in the thickness direction of the substrate at a temperature T2 higher than the point (Tg) is α _2Z , the melting point of the joint is Tm, and the glass transition point of the substrate is Tg, α _2Z (Tm−Tg ) Is 0.1 × ^{10 -2} or more state, and are 1.05 × ^{10 -2} or less, the linear expansion coefficient in the in-plane direction of the substrate at a lower temperature T1 than the glass transition point (Tg) of the substrate alpha _{1X When -Y} is provided , a semiconductor device in which the α _1X-Y is 19 ppm / ° C. or less is provided.
The insulating layer of the buildup layer includes a cyanate resin.
The build-up layer is easily affected by heat when the bonding portion connecting the substrate and the semiconductor element is melted. Therefore, by using a cyanate resin as the resin of the insulating layer of the buildup layer, it is possible to more reliably suppress the amount of deformation at or above the Tg of the substrate.
The insulating layer of the core layer also contains a cyanate resin. Therefore, the deformation amount in the substrate thickness direction at or above the Tg of the substrate can be more reliably suppressed.

Here, the temperature T2 is an intermediate temperature between the glass transition point Tg of the substrate and the melting point Tm of the bonded portion.
T2 = (Tg + Tm) × 1/2.

According to this invention, α _2Z (Tm−Tg) is set to 0.1 × 10 ⁻² or more and 1.05 × 10 ⁻² or less, thereby suppressing the deformation amount in the substrate thickness direction in the range of Tg to Tm. can do. This prevents the conductor layer (via wiring) formed in the via hole of the substrate from being cut by melting the bonding portion and receiving heat when bonding the semiconductor element and the substrate. it can.

In this case, if the linear expansion coefficient in the in-plane direction of the substrate at a lower temperature T1 than the glass transition point (Tg) of the substrate was set to alpha _1X-Y, said alpha _1X-Y is the 6 ppm / ° C. or less Is preferred.
Above all, this or arbitrariness that is 15ppm / ℃ or more.
Here, the temperature T1 is an intermediate temperature between the glass transition point Tg of the substrate and −55 ° C.,
T1 = (Tg−55 ° C.) × 1/2.
According to this configuration, since α _1X-Y is 6 ppm / ° C. or more and 19 ppm / ° C. or less, expansion in the in-plane direction of the substrate can be suppressed at a temperature lower than Tg.

Here, it is preferable that the joining portion is a bump disposed between the substrate and the semiconductor element.
In a state where semiconductor elements are mounted on a substrate, these substrates and semiconductor elements may be further mounted on a mother board. In this case, since the mother board and the substrate are fixed by solder or the like, the substrate and the semiconductor element are heated to a high temperature in a state where the semiconductor element is mounted on the substrate.
Generally, the linear expansion coefficient in the thickness direction of the conventional substrate and the linear expansion coefficient in the thickness direction of the semiconductor element are largely different from each other, and the linear expansion coefficient in the thickness direction of the conventional substrate is different from the linear expansion coefficient in the thickness direction of the semiconductor element. It is larger than the coefficient.
Therefore, cracks may occur at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, and the like.
On the other hand, in the present invention, since the deformation amount in the substrate thickness direction is suppressed, the occurrence of cracks at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, and the like can be suppressed.

Furthermore, it has an underfill filled around the bump, and the underfill is preferably made of a resin material having an elastic modulus at room temperature of 1.5 GPa or more and 12 GPa or less.
Furthermore, the semiconductor element includes a silicon substrate, an insulating film including a low dielectric constant film having a relative dielectric constant of 3.3 or less provided on the silicon substrate, and a wiring provided in the insulating film. Is preferred.
As described above, conventionally, when heat is applied while a semiconductor element is mounted on a substrate, cracks may occur at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, or the like.
Thus, it has been proposed to fill the bumps with a high modulus underfill. However, the high modulus underfill may damage the low-k film of the semiconductor element.
On the other hand, in the semiconductor device of the present invention, it is possible to suppress the occurrence of cracks at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, etc. A low elastic underfill made of a resin material having a rate of 1.5 GPa or more and 12 GPa or less can be used, and damage to the low-k film of the semiconductor element can be prevented.

Moreover, it is preferable that the thickness of a board | substrate is 800 micrometers or less.
Further, the substrate has a through hole in which a conductor layer is provided inside an insulating layer, and the conductor layer in the through hole has a core layer connected to the conductor wiring layer of the buildup layer. You may have.

Especially, it is preferable that the said cyanate resin is a novolak-type cyanate resin.
When the resin of the insulating layer contains a cyanate resin, particularly a novolac-type cyanate resin, the amount of deformation at Tg or higher of the substrate can be reliably suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can prevent the cutting | disconnection of a conductor layer is provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a semiconductor device 1 according to the present embodiment.
First, an outline of the semiconductor device 1 will be described.
The semiconductor device 1 includes a substrate 3, a semiconductor element (semiconductor chip) 4 mounted on the substrate 3, and a joint (solder bump) 5 containing a metal that connects the substrate 3 and the semiconductor element 4. . The semiconductor device 1 is mounted on a printed wiring board (motherboard) 2 via solder bumps B.
As shown in FIG. 2, the substrate 3 of the semiconductor device 1 is formed by alternately laminating insulating layers 311 containing resin and conductor wiring layers 312. Each conductor wiring layer 312 is connected by a conductor layer 313 formed in the via hole 311 </ b> A of the insulating layer 311.
Here, the linear expansion coefficient in the thickness direction of the substrate 3 at a temperature T2 higher than the glass transition point (Tg) of the substrate 3 is α _2Z , the melting point of the joint (solder bump) 5 is Tm, and the glass transition point of the substrate 3 Is Tg, α _2Z (Tm−Tg) is 0.1 × 10 ⁻² or more and 1.05 × 10 ⁻² or less.
The temperature T2 is an intermediate temperature between the glass transition point Tg of the substrate 3 and the melting point Tm of the solder bump 5.
T2 = (Tg + Tm) × 1/2.

[substrate]
First, the substrate 3 will be described.
As shown in FIG. 2, the substrate 3 has a build-up layer 31 in which insulating layers 311 containing a resin and conductor wiring layers 312 are alternately stacked. For example, in the present embodiment, the buildup layer 31 includes a plurality (six layers) of insulating layers 311 and a plurality (six layers) of conductor wiring layers 312 that are alternately stacked. This substrate 3 does not have a core layer.
The substrate 3 is mounted on the printed wiring board (motherboard) 2 via the solder bumps B (see FIG. 1). Furthermore, the thickness of the substrate 3 is 800 μm or less, preferably 500 μm or less.

The insulating layer 311 is made of only a resin composition, not a prepreg obtained by impregnating carbon fiber, glass fiber woven fabric, or fibers aligned in one direction with various resins. That is, the insulating layer 311 is not reinforced with fibers such as carbon fiber and glass fiber.
Here, examples of the resin constituting the insulating layer 311 include an epoxy resin, a BT resin, and a cyanate resin. Among these, it is preferable to use a cyanate resin. Examples of the cyanate resin include novolak type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethylbisphenol F type cyanate resin. Among these, it is preferable to use a novolac type cyanate resin.
As the novolac-type cyanate resin, those listed by the following chemical formula can be used. In the formula, n represents a positive number.

Such a novolak-type cyanate resin can be obtained, for example, by reacting a novolac-type phenol with a compound such as cyanogen chloride or cyanogen bromide.
Moreover, as a weight average molecular weight of novolak-type cyanate resin, it is preferable that it is 500-4500, for example. Furthermore, it is preferable that it is 600-3000.
If the weight average molecular weight is less than 500, the mechanical strength may decrease. On the other hand, when the weight average molecular weight exceeds 4500, the curing rate of the resin composition is increased, so that the storage stability may be deteriorated.

  Moreover, you may use the prepolymer of cyanate resin as cyanate resin. A cyanate resin or a prepolymer may be used alone, or a cyanate resin and a prepolymer may be used in combination. Here, the prepolymer is usually obtained by, for example, trimerizing a cyanate resin by a heat reaction or the like. Although it does not specifically limit as a prepolymer, For example, what has a trimerization rate of 20 to 50 weight% can be used. This trimerization rate can be determined using, for example, an infrared spectroscopic analyzer.

  Moreover, you may add an epoxy resin, a phenoxy resin, etc. with respect to cyanate resin. As an epoxy resin, what has a biphenyl alkylene skeleton is preferable.

Of the conductor wiring layers 312, the lowermost conductor wiring layer 312A is, for example, a copper wiring layer, and has a structure as shown in FIG. In FIG. 3, black portions indicate copper wiring.
The remaining copper ratio of the conductor wiring layer 312A (the ratio occupied by the conductor wiring layer 312A covering the insulating layer) is 80%.
The conductor wiring layer 312B disposed on the conductor wiring layer 312A has a planar shape as shown in FIG. 4, and a plurality of substantially circular openings 312B1 are formed. 4 is an enlarged view of the conductor wiring layer 312B.
The diameter of the opening 312B1 is, for example, 500 μm. Also. The residual copper ratio of this conductor wiring layer 312A is 60 to 90%, and preferably 75 to 85%.
Here, the pair of conductor wiring layers 312 arranged with the insulating layer 311 interposed therebetween is connected by a copper conductor layer 313 formed in the via hole 311A of the insulating layer 311.

In such a substrate 3, the linear expansion coefficient in the thickness direction of the substrate at a temperature T2 higher than the glass transition point (Tg) of the substrate 3 is α _2Z , the melting point of the solder bump 5 is Tm, and the glass transition point of the substrate 3 is In the case of Tg, α _2Z (Tm−Tg) is 0.1 × 10 ⁻² or more and 1.05 × 10 ⁻² or less .

  The glass transition point Tg of the substrate 3 is measured according to ISO-11359-2. A 5 mm square sample is cut from the substrate 3, and a probe of a TMA apparatus (TA Instruments Co., Ltd.) is placed on this sample, and the sample is displaced in the thickness direction while the sample is heated from room temperature at 5 ° C./min. Measure. And the tangent of the curve before and behind the glass transition point of the curve which shows temperature and the displacement amount of the thickness of a sample is taken, and a glass transition point is calculated from the intersection of this tangent.

The linear expansion coefficient α _{2Z in} the thickness direction of the substrate 3 can be measured as follows.
A sample of 5 mm square is cut out from the substrate 3, and the amount of displacement in the thickness direction of the sample is measured while the sample is heated from room temperature at 5 ° C./min using a TMA apparatus (TA Instruments Co., Ltd.) The linear expansion coefficient in the thickness direction is calculated. Then, the linear expansion coefficient in the thickness direction of the substrate at T2 is calculated.
The temperature T2 is an intermediate temperature between the glass transition point Tg of the substrate 3 and the melting point Tm of the solder bump 5.
T2 = (Tg + Tm) × 1/2.

Here, the solder bumps 5 are arranged between the substrate 3 and the semiconductor chip 4 to connect them. Examples of the solder bumps 5 include Pb-free solder. In this embodiment, tin-silver solder is used. The constituent material of the bump is not limited to this, and for example, a tin-bismuth system, a tin-zinc system, or the like can be used. As the solder bump 5, for example, one having a linear expansion coefficient of 10 ppm / ° C. or more and 25 ppm / ° C. or less can be used.
Furthermore, when the linear expansion coefficient in the in-plane direction of the substrate 3 at a temperature T1 lower than the glass transition point (Tg) of the substrate 3 is α _1X-Y , α _1X-Y is 6 ppm / ° C. or more, 19 ppm / ° C. It is as follows. Among them, arbitrariness preferred to be at 15ppm / ℃ or more.
The temperature T1 is an intermediate temperature between the glass transition point Tg of the substrate and −55 ° C.
T1 = (Tg−55 ° C.) × 1/2.
Here, the alpha _1X-Y linear expansion coefficient in the in-plane direction of the substrate 3 can be measured as follows.
A 5 mm square sample is cut out from the substrate 3 and the amount of displacement of the sample in the in-plane direction of the substrate is measured while the sample is heated from room temperature at 5 ° C./min using a TMA device (TA Instruments Co., Ltd.). Then, the linear expansion coefficient at the temperature T1 is calculated.

[Semiconductor chip]
As shown in FIG. 1, the semiconductor chip 4 includes a wiring layer 42 made of a so-called low-k film on a silicon substrate 41. The function is not particularly limited, and examples thereof include a logic device, a memory device, and mixed mounting thereof.
The low-k film is provided as an interlayer insulating film. Here, the low-k film refers to a film having a relative dielectric constant of 3.3 or less. Examples of the low-k film include organic films such as SiOC, MSQ (methylsilsesquioxane) and benzocyclobutene, and inorganic films such as HSQ (hydroxysilsesquioxane), and these are made porous. The film made is also preferably used.

[Underfill]
The underfill 6 is filled around the solder bump 5 that joins the substrate 3 and the semiconductor chip 4.
As a constituent material of the underfill 6, a liquid thermosetting resin or a film-like thermosetting resin can be used. Among these, a liquid thermosetting resin is preferable. This is because the gap between the substrate 3 and the semiconductor chip 4 can be efficiently filled. In this embodiment, the underfill 6 is made of a resin material having an elastic modulus of 1.5 GPa or more and 12 GPa or less.
The elastic modulus was obtained by forming a paste of underfill 6 to a width of 10 mm, a length of about 150 mm, and a thickness of 4 mm, curing in an oven at 200 ° C. for 30 minutes, and then using a Tensilon tester at a speed of 1 mm / min in an atmosphere of 125 ° C. The elastic modulus is calculated from the initial gradient of the stress-strain curve obtained by the measurement in (1).

  Various resin materials can be used for the underfill 6. For example, an epoxy resin, BT resin, cyanate resin, or the like can be used. As the cyanate resin, the novolac type cyanate resin described in the section of the substrate material is preferably used.

  The resin material constituting the underfill 6 preferably contains a polyfunctional epoxy resin. Thereby, the crosslink density of the resin cured body is improved, and a high elastic modulus can be realized.

  The underfill 6 may contain an inorganic filler such as silica particles. By doing so, the linear expansion coefficient can be reduced, and damage between the semiconductor chip 4 and between the semiconductor chip 4 and the substrate 3 can be more effectively reduced.

  The underfill 6 may include a coupling agent. By doing this, the adhesion between the bump or inorganic filler and the underfill is improved, the coefficient of linear expansion is further reduced, and the damage between the semiconductor chip and the semiconductor chip and the substrate 3 is more effectively reduced. Can do. As the coupling agent, a silane coupling agent such as epoxy silane or aminosilane, a titanate coupling agent, or the like can be used. A plurality of these may be used. The coupling agent may be dispersed in the binder portion of the underfill, or may be in a form attached to the surface of an inorganic filler such as silica particles. Or these forms may be mixed. For example, when silica particles are blended, the silica surface may be treated with a coupling agent in advance.

  The linear expansion coefficient of the underfill is preferably 40 ppm / ° C. or less, and more preferably 30 ppm / ° C. or less. It is possible to suppress the damage of the low-k film and the damage around the bump 5 more effectively.

Next, a method for manufacturing the semiconductor device 1 as described above will be described. This will be described with reference to FIGS.
First, the conductor wiring layer 312C having a predetermined pattern is formed on the surface of the copper plate C having a predetermined thickness.
The conductor wiring layer 312C has a two-layer structure, and includes a first metal layer 312C1 and a second metal layer 312A that is laminated on the first metal layer and forms the conductor wiring layer 312A described above.
For example, the first metal layer 312C1 is made of nickel, and the second metal layer 312A is made of copper as described above. The pattern of the conductor wiring layer 312C is the pattern shown in FIG.
Next, the surface of the copper plate C and the conductor wiring layer 312C are roughened with a chemical solution, and the insulating layer 311 is laminated on the conductor wiring layer 312C (laminating step).
A via hole 311A is formed by a laser at a predetermined position of the insulating layer 311 (via hole forming step).

Next, a conductor layer 313 in the via hole 311A and further a conductor wiring layer 312B as shown in FIG. 4 are formed by a semi-additive method.
Specifically, a copper film (seed film) is formed to approximately 1 μm on the entire surface of the insulating layer 311 by electroless plating. Next, a photoresist (mask) having a predetermined pattern is formed on the insulating layer 311. Thereafter, a plating film is formed on a portion where the mask is not formed (for example, via hole 311A) by electrolytic plating. As a result, the conductor layer 313 is formed in the via hole 311A, and further, the conductor wiring layer 312B is formed (process for forming the conductor layer 313 and the conductor wiring layer 312B).
Thereafter, the mask is removed, and the exposed seed film is removed by removing the mask.

Next, the conductor wiring layer 312B is roughened, and the above-described laminating step, via hole forming step, conductor layer 313 and conductor wiring layer 312B forming step are performed.
By repeating such an operation, a buildup layer 31 having a plurality (six layers) of insulating layers 311 and a plurality (six layers) of conductor wiring layers 312 is obtained as shown in FIG.
Thereafter, an etching resist film (not shown) is formed on the uppermost conductor wiring layer 312B. Then, the copper plate C is removed by etching.
Further, the first metal layer 312C1 is removed with a nickel removing liquid. Thereby, the substrate 3 as shown in FIG. 2 is obtained.

Next, the semiconductor chip 4 is mounted on the substrate 3 thus obtained. Solder bumps 5 are provided in advance on the back surface of the semiconductor chip 4. The semiconductor chip 4 is placed on the substrate 3 via the solder bumps 5 and the solder bumps 5 are melted in a reflow furnace, so that the semiconductor chip 4 is fixed on the substrate 3.
Next, an underfill 6 is filled between the substrate 3 and the semiconductor chip 4.
The semiconductor device 1 is obtained by the process as described above.
The semiconductor device 1 obtained in this way is mounted on the printed wiring board 2 via the solder bumps B as shown in FIG.

Next, the effect of this embodiment will be described.
In this embodiment, α _2Z (Tm−Tg) of the substrate 3 is set to 0.1 × 10 ⁻² or more and 1.05 × 10 ⁻² or less, whereby the deformation amount in the substrate thickness direction in the range of Tg to Tm. Can be suppressed. As a result, the substrate 3 is put into a reflow furnace, the solder bumps 5 are melted, and the conductor formed in the via hole 311A of the substrate 3 is subjected to heat when the semiconductor chip 4 and the substrate 3 are joined. It is possible to prevent the layer 313 (via wiring) from being cut.
The build-up layer 31 of the substrate 3 is very close to the solder bump 5 and is easily affected by heat when the solder bump 5 is melted. Therefore, the amount of deformation in the substrate thickness direction in the range of Tg to Tm of the substrate 3 can be more reliably suppressed by including the cyanate resin as the resin of the insulating layer 311 constituting the buildup layer 31 of the substrate 3. it can. In particular, by using a novolac-type cyanate resin, the amount of deformation in the substrate thickness direction in the range of Tg to Tm can be more effectively suppressed.

Further, the substrate 3 of the alpha _1X-Y is 6 ppm / ° C. or higher, 19 ppm / ° C. or less, preferably, because it is the 15 ppm / ° C. or more, suppressing the expansion in the in-plane direction of the substrate 3 at a temperature lower than Tg be able to.

When mounting the semiconductor device 1 on the printed wiring board 2, the semiconductor device 1 and the printed wiring board 2 are put in a reflow furnace, and the solder bumps B are melted.
Here, the linear expansion coefficient in the thickness direction of the substrate of the conventional semiconductor device and the linear expansion coefficient in the thickness direction of the semiconductor chip are generally greatly different, and the linear expansion coefficient in the thickness direction of the substrate is the thickness of the semiconductor element. It is larger than the linear expansion coefficient in the direction.
Therefore, when heat is applied with the semiconductor element mounted on the substrate in the reflow furnace, cracks may occur at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, and the like.
On the other hand, in this embodiment, since the deformation amount in the substrate thickness direction is suppressed, the generation of cracks at the interface between the solder bump 5 and the substrate 3, the interface between the solder bump 5 and the semiconductor chip 4, etc. is suppressed. it can.

Conventionally, when heat is applied in a state where a semiconductor element is mounted on a substrate, cracks may occur at the interface between the bump and the substrate, the interface between the bump and the semiconductor element, or the like.
Thus, it has been proposed to fill the bumps with a high modulus underfill. However, the high modulus underfill may damage the low-k film of the semiconductor element.
On the other hand, in the semiconductor device 1 of the present embodiment, the occurrence of cracks at the interface between the solder bump 5 and the substrate 3, the interface between the solder bump 5 and the semiconductor chip 4, etc. can be suppressed. The low-modulus underfill 6 made of a resin material having an elastic modulus of 1.5 GPa or more and 12 GPa or less can be used, and the low-k film of the semiconductor chip 4 can be prevented from being damaged.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in the above-described embodiment, the substrate 3 has only the build-up layer 31. However, the substrate 3 is not limited to this, and may be a substrate 7 as shown in FIG. This substrate 7 is formed with a build-up layer 31 similar to that of the above embodiment and a through hole 712 in which a conductor layer 711 is provided, and the conductor layer 711 in the through hole 712 is connected to the conductor wiring layer 312. The core layer 71 may be included.

Here, the core layer 71 has an insulating layer in which prepregs (not shown) are stacked. The prepreg is obtained by impregnating a glass cloth with a resin composition containing an epoxy resin or a cyanate resin (for example, a novolac-type cyanate resin). A through hole 712 is formed in the insulating layer.
In the substrate 7, a pair of buildup layers 31 are arranged so as to sandwich the core layer 71. The buildup layer 31 (buildup layer 31A) disposed on one side of the core layer 71 includes an insulating layer 311 and a conductor wiring layer 312B. The buildup layer 31 (buildup layer 31B) disposed on the other side of the core layer 71 includes an insulating layer 311, a conductor wiring layer 312B, and a conductor wiring layer 312A.

In such a substrate 7, the linear expansion coefficient in the thickness direction of the substrate 7 at a temperature T2 higher than the glass transition point (Tg) is α _2Z , the melting point of the joint 5 is Tm, and the substrate 7 When the glass transition point is Tg, α _2Z (Tm−Tg) is 0.1 × 10 ⁻² or more and 1.05 × 10 ⁻² or less.
In the substrate 7 shown in FIG. 7, it is preferable that the buildup layer 31 that is most easily affected by heat when the solder bumps 5 are melted is made of cyanate resin (particularly, novolac-type cyanate resin). Thereby, the deformation | transformation amount of the board | substrate thickness direction in the range of Tg-Tm of the board | substrate 7 can be suppressed more reliably.
Furthermore, the insulating layer of the core layer 71 also contains a cyanate resin (particularly a novolac-type cyanate resin), thereby further reliably suppressing the amount of deformation in the substrate thickness direction in the range of Tg to Tm of the substrate 7. Can do.
In addition, as resin which comprises the insulating layer of the core layer 71, you may use not only cyanate resin but another resin. For example, an epoxy resin, BT resin, etc. are mentioned.

Furthermore, in the said embodiment, although the thickness of the board | substrate 3 was 800 micrometers or less, Preferably it was 500 micrometers or less, It is not restricted to this, You may exceed 800 micrometers.
Moreover, in the said embodiment, although the board | substrate 3 and the semiconductor chip 4 were connected by the solder bump 5, it is not restricted to this. For example, you may connect the board | substrate 3 and the semiconductor chip 4 with metal wires (joining part).

Next, examples of the present invention will be described.
Example 1
The substrate 3 was manufactured by the same method as in the previous embodiment.
A conductive wiring layer 312C was formed on one side of a copper plate C having a thickness of 1.0 mm using an additive method. The thickness of the conductor wiring layer 312C is 20 μm, the first metal layer 312C1 is 2 μm, and the second metal layer 312A is 18 μm.
Next, as in the above embodiment, the surface of the copper plate C and the conductor wiring layer 312C were roughened with a chemical solution, and the insulating layer 311 was laminated on the conductor wiring layer 312C.
As the roughening solution, a bond film manufactured by Atotech Japan Co., Ltd. was used.
The insulating layer 311 is 40 μm thick and has the composition shown in Table 1 below.
For the lamination, MVLP-500 manufactured by Meiki Seisakusho Co., Ltd. was used.
Next, the laminated insulating layer 311 was pre-cured at 175 ° C. for 45 minutes, and a via hole 311A having a diameter of 70 μm was formed at a predetermined position by a laser processing machine.
Thereafter, the insulating layer 311 was roughened by a desmear process. Further, the conductor layer 313 in the via hole 311A and further the conductor wiring layer 312B were formed by the same method as in the above embodiment.
Here, the conductor wiring layer 312B is entirely made of copper and has a thickness of 18 μm. Thereafter, the insulating layer 311 was cured at 200 ° C. for 1 hour.
Next, the conductor wiring layer 312B was roughened and the above-described steps were repeated to obtain a buildup layer 31 having a plurality (six layers) of insulating layers 311 and a plurality (six layers) of conductor wiring layers 312. .
Thereafter, an etching resist film was formed on the uppermost conductor wiring layer 312B. Then, the copper plate was removed by etching.
Further, the first metal layer 312C1 was removed with a nickel removing solution.
Next, the etching resist film that protects the conductor wiring layer 312B is removed, and a solder resist (PSR-4000 AUS-703 manufactured by Taiyo Ink Manufacturing Co., Ltd.) is formed to have a thickness of 20 μm on both sides thereof. A substrate 3 was obtained by opening a predetermined position by a technique. The thickness of the substrate 3 was 323 μm.

The manufacturing method of the insulating layer 311 is as follows.
25 parts by weight of cyanate resin A, 25 parts by weight of epoxy resin, 5 parts by weight of phenoxy resin A, 5 parts by weight of phenoxy resin B, and 0.4 parts by weight of curing catalyst were dissolved and dispersed in methyl ethyl ketone. Furthermore, 40 parts by weight of an inorganic filler and 0.2 part by weight of a coupling agent were added, and the mixture was stirred for 10 minutes using a high-speed stirrer to prepare a resin varnish having a solid content of 50% by weight.
The resin varnish obtained above was coated on one side of a 38 μm thick PET (polyethylene terephthalate) film using a comma coater so that the thickness of the insulating film after drying was 60 μm. The substrate was dried for 10 minutes with a drying device at 0 ° C. to produce an insulating sheet with a substrate, and the PET film was peeled off to obtain an insulating layer 311.

(Example 2)
The insulating layer 311 having a thickness of 40 μm having the composition shown in Table 2 was used. Other conditions are the same as those in the first embodiment.
The thickness of the obtained substrate 3 was 334 μm.

The manufacturing method of the insulating layer 311 is as follows.
15 parts by weight of cyanate resin A, 10 parts by weight of cyanate resin B, 25 parts by weight of epoxy resin, 10 parts by weight of phenoxy resin A, and 0.4 parts by weight of curing catalyst were dissolved and dispersed in methyl ethyl ketone. Furthermore, 40 parts by weight of an inorganic filler and 0.2 part by weight of a coupling agent were added, and the mixture was stirred for 10 minutes using a high-speed stirrer to prepare a resin varnish having a solid content of 50% by weight.
An insulating layer 311 was obtained in the same manner as in Example 1 using this resin varnish.

(Example 3)
In this example, the substrate 7 shown in FIG. 7 was produced.
First, a subtractive method after forming a through hole 712 at a predetermined position of a double-sided copper-clad laminate (ELC-4785GS manufactured by Sumitomo Bakelite Co., Ltd. (a laminate in which the core layer 71 is a cyanate resin)) having a thickness of 60 μm. Thus, the conductor wiring layer 312B was formed on each of the two surfaces. The conductor wiring layer 312B was made of copper and had a thickness of 21 μm.
Next, the pair of conductor wiring layers 312B was roughened with a chemical solution, and the insulating layers 311 were laminated. The chemical solution used was a bond film manufactured by Atotech Japan. As the insulating layer 311, an insulating layer 311 having the same composition as that of Example 1 was used. For the lamination, MVLP-500 manufactured by Meiki Seisakusho Co., Ltd. was used.
Next, after pre-curing the insulating layer 311 at 175 ° C. for 45 minutes, a via hole 311A having a diameter of 70 μm was formed by a laser processing machine. Thereafter, the insulating layer 311 was roughened. Then, the conductor layer 313 in the via hole 311A and further the conductor wiring layer 312B were formed by the same method as in Example 1. The conductor wiring layer 312B is made of copper and has a thickness of 18 μm. Thereafter, the insulating layer 311 was cured at 200 ° C. for 1 hour.
Next, each conductor wiring layer 312B is roughened, and the above-described steps are repeated to form insulating layers 311 on each conductor wiring layer 312B, and further, conductor wiring layers 312B are provided on this insulating layer 311. .
Thereafter, an insulating layer 311 was further provided on each conductor wiring layer 312B, a conductor wiring layer 312B was provided on one insulating layer 311, and a conductor wiring layer 312A was provided on the other insulating layer 311.
A solder resist (PSR-4000 AUS-703 manufactured by Taiyo Ink Manufacturing Co., Ltd.) is formed on both sides of the laminate thus obtained to a thickness of 20 μm, and a predetermined position is opened by a photolithography technique. Thus, a substrate 7 was obtained.
The thickness of the substrate 7 was 422 μm.

(Comparative example)
A substrate different from that in Example 1 in which the resin constituting the insulating layer was manufactured.
First, in the same manner as in Example 1, a conductor wiring layer was provided on a copper plate, and a film (40 μm) having an insulating layer and an 18 μm-thick copper foil provided on the surface of the insulating layer on the conductor wiring layer. Thickness (with an insulating layer having a 18 μm thick copper foil) was laminated. The composition of the insulating layer of this film is shown in Table 3.
Next, after the insulating layer of the film was cured at 175 ° C. for 120 minutes, the entire surface of the copper foil was etched.
Thereafter, via holes were formed in the insulating layer by the same method as in the above embodiment, and a conductor layer was further provided in the via holes. Furthermore, a conductor wiring layer was laminated on the insulating layer. Here, the conductor wiring layer on the insulating layer was all made of copper as in Example 1, and the thickness thereof was 18 μm. Next, the conductor wiring layer was roughened. Thereafter, laminating the film (40 μm thick (with 18 μm thick copper foil on the surface of the insulating layer))), curing of the insulating layer of the film, etching of the copper foil, formation of the via hole, formation of the conductor layer in the via hole Filling and lamination of the conductor wiring layers were repeated to obtain a buildup layer having a plurality (six layers) of insulating layers and a plurality (six layers) of conductor wiring layers.
Thereafter, an etching resist film was formed on the uppermost conductor wiring layer. Then, the copper plate was removed by etching.
Further, the first metal layer was removed with a nickel removing solution.
Next, the etching resist layer that protects the conductor wiring layer is removed, and a solder resist (PSR-4000 AUS-703 manufactured by Taiyo Ink Manufacturing Co., Ltd.) is formed on both sides so as to have a thickness of 20 μm. A substrate was obtained by opening a predetermined position. The thickness of the substrate was 323 μm.

Moreover, the manufacturing method of the said film (what attached 18 micrometers thick copper foil to the surface of the insulating layer) is as follows.
Terminal hydroxyl group-modified amorphous polyethersulfone (average molecular weight 24000) 40 parts by weight, bisphenol S type and biphenyl type copolymer epoxy resin (weight average molecular weight 34000, bisphenol S: biphenyl (molar ratio) = 5: 4) 30 weights Parts, biphenyl skeleton type epoxy resin (weight average molecular weight 800, epoxy equivalent 275) 25 parts by weight, novolac type epoxy resin (weight average molecular weight 320, epoxy equivalent 175) 25 parts by weight, diaminodiphenyl sulfone 9.5 parts by weight, curing As an accelerator, 0.5 part by weight of 2-methylimidazole was stirred and dissolved in a MEK / DMF mixed solvent. An adhesive varnish was prepared by adding 0.2 parts by weight of titanate coupling agent and 20 parts by weight of barium sulfate to 100 parts by weight of resin solids in the varnish and stirring until uniformly dispersed. This adhesive varnish was applied to the anchor surface of a copper foil having a thickness of 18 μm with a comma coater to obtain the film.

(Evaluation of Examples 1 to 3 and Comparative Example)
The Tg of the substrates 3 and 7 obtained in Examples 1 to 3 and the comparative example, and the thermal expansion coefficient in the substrate thickness direction and in the substrate plane were measured by the TMA method (method shown in the above embodiment). did.
Table 2 shows α _2Z (Tm−Tg) and α _1X-Y . Here, as a solder bump for connecting the substrate and the semiconductor chip, tin silver solder was assumed, and Tm was set to 210 ° C.

Next, a semiconductor chip was mounted on the substrates obtained in Examples 1 to 3 and the comparative example. The size of the mounted semiconductor chip is 15 × 15 mm. The bump diameter is 100 μm, the bump pitch is 200 μm, and the bump metal is tin silver solder.
Thereafter, an underfill was filled between the semiconductor chip and each substrate and cured to obtain a semiconductor device. As the underfill, CRP-4152D1 (elastic modulus 10.3 GPa) manufactured by Sumitomo Bakelite was used.
A TC (temperature cycle) test of the semiconductor device thus obtained was performed.
The TC test was carried out under the condition B defined in JEDC JESD22-a104-A104.
In Examples 1 to 3, after 1500 cycles, the semiconductor device was observed under magnification and SAT (Scanning Acoustic Tomograph).
In Examples 1 to 3, it was confirmed that the semiconductor device was not damaged, and in particular, the conductor layer provided in the via hole of the substrate was not cut.
It was also found that the solder bumps between the semiconductor chip and the substrate were not damaged.

On the other hand, in Comparative Example 1, after 750 cycles, the semiconductor device was observed with magnification and SAT (Scanning Acoustic Tomograph).
In the comparative example, it was found that the conductor layer provided in the via hole of the substrate of the semiconductor device was cut and the solder bump was damaged.

It is a mimetic diagram showing a semiconductor device concerning one embodiment of the present invention. It is sectional drawing which shows a board | substrate. It is a top view which shows the conductor wiring layer of a board | substrate. It is a top view which shows the conductor wiring layer of a board | substrate. It is sectional drawing which shows the manufacturing process of a board | substrate. It is sectional drawing which shows the manufacturing process of a board | substrate. It is sectional drawing which shows the board | substrate concerning the modification of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Printed wiring board 3 Substrate 4 Semiconductor chip (semiconductor element)
5 Solder bump (joint)
6 Underfill 7 Substrate 31 Buildup layer 31A Buildup layer 31B Buildup layer 41 Silicon substrate 42 Wiring layer 71 Core layer 311 Insulating layer 311A Via hole 312 Conductor wiring layer 312A Conductor wiring layer (second metal layer)
312B Conductor wiring layer 312C Conductor wiring layer 312C1 First metal layer 312B1 Opening 313 Conductor layer 711 Conductor layer 712 Through hole B Solder bump C Copper plate

Claims (7)

A substrate,
A semiconductor element mounted on the substrate;
In a semiconductor device having a bonding portion containing a metal connecting the substrate and the semiconductor element,
The substrate is
Insulating layers containing a cyanate resin and conductor wiring layers are alternately laminated, and each of the conductor wiring layers is connected by a conductor layer formed in a via hole of the insulating layer, and a buildup layer,
A through hole in which a conductor layer is provided inside an insulating layer containing a cyanate resin is formed, and the conductor layer in the through hole is connected to the conductor wiring layer of the buildup layer, Have
Α _2Z is the linear expansion coefficient in the thickness direction of the substrate at a temperature T2 higher than the glass transition point (Tg) of the substrate,
When the melting point of the joint is Tm and the glass transition point of the substrate is Tg,
α _2Z (Tm-Tg) is 0.1 × ^{10 -2} or more state, and are 1.05 × ^{10 -2} or less,
When the linear expansion coefficient in the in-plane direction of the substrate at a temperature T1 lower than the glass transition point (Tg) of the substrate is _α1X-Y ,
A semiconductor device in which the α _1X-Y is 19 ppm / ° C. or less . The semiconductor device according to claim 1,
When the linear expansion coefficient in the in-plane direction of the substrate at a temperature T1 lower than the glass transition point (Tg) of the substrate is _α1X-Y ,
The semiconductor device wherein alpha _1X-Y is the 6 ppm / ° C. or less. The semiconductor device according to claim 1 or 2,
The semiconductor device is a semiconductor device in which the bonding portion is a bump disposed between the substrate and the semiconductor element. The semiconductor device according to claim 3.
Having an underfill filled around the bump;
The underfill is a semiconductor device made of a resin material having an elastic modulus at room temperature of 1.5 GPa or more and 12 GPa or less. The semiconductor device according to claim 4,
The semiconductor element includes a silicon substrate,
An insulating film including a low dielectric constant film having a relative dielectric constant of 3.3 or less provided on the silicon substrate;
A semiconductor device including a wiring provided in the insulating film; The semiconductor device according to claim 1,
A semiconductor device having a thickness of the substrate of 800 μm or less. The semiconductor device according to claim 1,
The semiconductor device, wherein the cyanate resin is a novolac-type cyanate resin.

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