JP3992524B2 - Multilayer wiring board, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which secures fine interlayer connection as well as the formation of a fine wiring pattern, and which is highly reliable. <P>SOLUTION: In the multilayer wiring board in which a wiring pattern 104 embedded in an interlayer dielectric 105 and a portion to be connected of a layer to be connected are bonded by a conduction post formed on the interlayer dielectric and a metal bonding material layer, and the interlayer dielectric and layer to be connected are adhered by a metal bonding adhesive layer, the interlayer dielectric is provided by laminating interlayer dielectric having melting viscosity of 500 to 20,000 Pa-s. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board, a method for manufacturing the same, and a semiconductor device. More particularly, the present invention relates to a multilayer wiring board on which a semiconductor chip is mounted and a manufacturing method thereof, and to a semiconductor device using the multilayer wiring board.
[0002]
[Prior art]
In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.
[0003]
Against this background, in recent years, build-up multilayer wiring boards have been adopted. The build-up multilayer wiring board is formed while stacking an interlayer insulating material layer and a conductor. As a method for forming vias, in place of conventional drilling, various methods such as laser method, plasma method, photo method, etc. are used, and small-diameter via holes are freely arranged to achieve high density. Examples of the interlayer connection include a buried via and a buried via (Buried Via: a structure in which a via is filled with a conductor), and a buried via hole capable of forming a stacked via on the via is particularly noticeable. Has been. The burred via hole is divided into a method of filling the via hole with plating and a case of filling with a conductive paste or the like. On the other hand, as a method of forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method by electrolytic copper plating (additive method), and the like, and an additive method that can cope with a higher wiring density is particularly preferable. It has begun to attract attention.
[0004]
Further, in a semiconductor package substrate on which a semiconductor is directly mounted, warpage and thermal stress due to a difference in thermal expansion coefficient between the semiconductor and the semiconductor package substrate become a problem. Since the glass cloth cannot be used when the thickness of the resin layer is as thin as 50 μm or less, a method of blending an inorganic filler for reducing the thermal expansion has been taken. Inorganic fillers are mixed using a three-roll, homogenizer, ball mill, three-one motor, rotation / revolution mixer, vacuum / revolution / revolution mixer, etc., but the resin is completely impregnated with the inorganic filler at any blending ratio. It is technically difficult to disperse and disperse. In particular, when the average particle size of the inorganic filler is 1 μm or less, the specific surface area per unit weight is large, and the interaction between the inorganic fillers is large. Therefore, it is a technology to completely disperse the inorganic filler in the resin without aggregation. Is difficult.
[0005]
As described above, the thermal expansion can be reduced to some extent by filling the insulating resin with the inorganic filler. However, as the interlayer insulating material layer becomes thinner, the filling rate of the inorganic filler is limited from the viewpoint of insulation reliability and workability. Therefore, in order to achieve lower thermal expansion, the thermal expansion of the insulating resin itself The coefficient needs to be lowered.
[0006]
On the other hand, from the viewpoint of controlling the impedance of the semiconductor package substrate, film thickness control of the interlayer insulating material layer, that is, flatness is also important. In the method of directly applying the insulating resin to the package substrate, it is difficult to control the film thickness. Therefore, the dry film type with a known thickness in which an interlayer insulating material layer is previously formed on a support film such as PET is used for film thickness control. Is suitable. When a vacuum press apparatus is used, it is possible to embed an uneven surface on which a circuit pattern is formed smoothly without voids, but it is not preferable from the viewpoint of productivity because a long time is required for one vacuum press. On the other hand, when a vacuum roll laminating apparatus is used, productivity is good because continuous lamination is possible, but it is difficult to embed a circuit smoothly without voids without being affected by unevenness of the circuit.
[0007]
[Problems to be solved by the invention]
In view of such current problems of interlayer connection, wiring pattern formation, and workability / reliability of interlayer insulating material layers in a multilayer wiring board on which a semiconductor chip is mounted, the present invention can reliably perform interlayer connection, An object of the present invention is to provide a multilayer wiring board capable of forming a fine wiring pattern and excellent in workability and reliability of an interlayer insulating material layer.
[0008]
[Means for Solving the Problems]
  In the present invention, a wiring pattern formed embedded in the surface of an interlayer insulating material layer and a connected portion of the connected layer are bonded to a conductor post formed on the interlayer insulating material layer by a metal bonding material layer. In the multilayer wiring board in which the interlayer insulating material layer and the connected layer are bonded with a metal bonding adhesive layer, the interlayer insulating material layer is40% or less of the cyanate group of the cyanate compound represented by the general formula (2) contains 100 parts by weight of a cyanate compound trimerized, 5 parts by weight or more and 400 parts by weight or less of soluble polyimide siloxane, andA multilayer wiring board obtained by laminating an interlayer insulating material layer having a melt viscosity of 500 Pa · s or more and 20,000 Pa · s or less.
[Formula 4]
(In formula (2), R ₁ ~ R _Three Each independently represents a hydrogen atom, a methyl group, a fluoroalkyl group or a halogen atom, and n represents an integer of 0-6. )
[0009]
In the multilayer wiring board of the present invention, preferably, the joining metal material layer is made of solder or solder formed by electrolytic plating, and more preferably, the conductor post is made of copper.
[0010]
  TheFurthermore, preferably, the soluble polyimide siloxane (b) is 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-benzophenonetetracarboxylic dianhydride, An aromatic tetracarboxylic acid component selected from 4,4′-oxydiphthalic dianhydride and 4,4′-diphenylsulfone tetracarboxylic dianhydride, and a diaminopolysiloxane 10 represented by the general formula (3) It is a soluble polyimide siloxane synthesized by reacting a diamine component composed of 20% by mole or more and 80% by mole or less and 20% by mole or more and 90% by mole or less of an aromatic diamine.
[Chemical formula 5]
(In formula (3), R₇Represents a divalent hydrocarbon group, R₈~ R₁₁Represents a lower alkyl group or a phenyl group, and n represents an integer of 1 to 20. )
[0011]
In the multilayer wiring board of the present invention, preferably, the interlayer insulating material further comprises 5 parts by weight or more and 400 parts by weight or less of silica filler (c), more preferably 1 μm or less of silica filler (c). The silica filler (c) is preferably dispersed in advance in a solvent (d) in which the polyimidesiloxane resin (b) is soluble. More preferably, the solvent (d) is N-methyl-2-pyrrolidone.
[0012]
In the multilayer wiring board of the present invention, preferably, the interlayer insulating material further comprises 0.0001 part by weight or more and 0.1 part by weight or less of metal acetylacetonate (e), more preferably metal acetylacetonate. Coordination metal in which the nate (e) is selected from among divalent copper, manganese, nickel, cobalt, lead, zinc and tin, trivalent aluminum, iron, cobalt and manganese, and tetravalent titanium Comprising.
[0013]
In the multilayer wiring board of the present invention, preferably, the metal bonding adhesive is an essential component of a resin (A) having at least one phenolic hydroxyl group and a resin (B) that acts as a curing agent thereof, More preferably, the resin (A) having a phenolic hydroxyl group is a resin selected from a phenol novolak resin, an alkylphenol novolak resin, a resole resin, a cresol novolac resin, and a polyvinyl phenol resin, and more preferably a phenolic resin. The resin (A) having a hydroxyl group is contained in the metal bonding adhesive in an amount of 20 wt% to 80 wt%.
[0014]
The present invention also includes a step of forming a wiring pattern by electrolytic plating using the metal layer as a lead for electrolytic plating,
A step of laminating an interlayer insulating sheet composed of an interlayer insulating material layer and at least one or more peelable protective film layers on the wiring pattern by a vacuum roll laminating device, and forming an interlayer insulating material layer;
Forming a via in the interlayer insulating material layer so that a part of the wiring pattern is exposed;
Forming a metal post as a lead for electrolytic plating and forming a conductor post by electrolytic plating;
Forming a bonding metal material layer on at least one of the surface of the conductor post or the surface of the bonded portion facing the conductor post;
Forming a metal bonding adhesive layer on at least one of the surface of the interlayer insulating material layer or the surface of the connected layer;
The conductor post and the part to be joined, which are opposed to each other through the metal bonding adhesive layer, are bonded by the bonding metal material layer, and the interlayer insulating material layer and the connection layer are bonded by the metal bonding adhesive layer. And a process of
Removing the metal layer by etching;
In the method for producing a multilayer wiring board comprising the multilayer wiring board, the melt viscosity of the interlayer insulating material layer in the step of forming the interlayer insulating material layer is 500 Pa · s or more and 20,000 Pa · s or less A manufacturing method of a board.
[0015]
The method for producing a multilayer wiring board of the present invention preferably includes a step of forming a resist metal layer by electrolytic plating between the metal layer and the wiring pattern, using the metal layer as a lead for electrolytic plating, More preferably, the joining metal material layer is made of solder or solder formed by electrolytic plating.
[0016]
Furthermore, the present invention is a semiconductor device using the multilayer wiring board according to any one of the above or the multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of the above.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
  The multilayer wiring board of the present invention includes a wiring pattern formed by being embedded in the surface of an interlayer insulating material layer, and a connected portion of the connected layer, a conductor post formed on the interlayer insulating material layer, and a metal bonding material A multilayer wiring board bonded with a layer, and the interlayer insulating material layer and the connected layer are bonded with a metal bonding adhesive layer, the interlayer insulating material layer,40% or less of the cyanate group of the cyanate compound represented by the general formula (2) contains 100 parts by weight of a cyanate compound trimerized, 5 parts by weight or more and 400 parts by weight or less of soluble polyimide siloxane, andA multilayer wiring board obtained by laminating an interlayer insulating material layer having a melt viscosity of 500 Pa · s or more and 20,000 Pa · s or less.
[0018]
Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto. 1 to 3 are diagrams for explaining an example of a multilayer wiring board and a method for manufacturing the multilayer wiring board according to an embodiment of the present invention, and FIG. 3 (n) is a cross-sectional view showing the structure of the resulting multilayer wiring board. FIG.
[0019]
As a method for manufacturing a multilayer wiring board according to the present invention, first, a patterned plating resist 102 is formed on a metal layer 101 (FIG. 1A). The plating resist 102 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal layer 101, selectively exposing it using a negative film or the like, and then developing it.
The material of the metal layer 101 may be any material as long as it is suitable for this manufacturing method. In particular, the metal layer 101 is resistant to the chemical used, and can be finally removed by etching. It is necessary. Examples of the material of the metal layer 101 include copper, a copper alloy, a 42 alloy, and nickel.
[0020]
Next, a resist metal 103 is formed by electrolytic plating using the metal layer 101 as an electroplating lead (feeding electrode) (FIG. 1B). By this electrolytic plating, a resist metal 103 is formed on a portion of the metal layer 101 where the plating resist 102 is not formed.
The material of the resist metal 103 may be any material as long as it is suitable for this manufacturing method. In particular, the resist metal 103 may be resistant to a chemical solution used when the metal layer 101 is finally removed by etching. is necessary. Examples of the material of the resist metal 103 include nickel, gold, tin, silver, solder, palladium, and the like.
The purpose of forming the resist metal 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being eroded and corroded by the chemical solution used when the metal layer 101 is etched. Therefore, when the wiring pattern 104 shown in FIG. 1C is resistant to the chemical used when etching the metal layer 101, the resist metal 103 is unnecessary. The resist metal 103 does not have to be the same pattern as the wiring pattern 104, and the resist metal 103 may be formed on the entire surface of the metal layer 101 before the plating resist 102 is formed on the metal layer 101.
[0021]
Next, the wiring pattern 104 is formed by electroplating using the metal layer 101 as an electroplating lead (power feeding electrode) (FIG. 1C). By this electrolytic plating, a wiring pattern 104 is formed on a portion of the metal layer 101 where the plating resist 102 is not formed.
The wiring pattern 104 may be made of any material as long as it is suitable for this manufacturing method. In particular, the wiring pattern 104 should be resistant to a chemical solution used when the resist metal 103 is finally removed by etching. is required. Actually, since the wiring pattern 104 finally exists in the multilayer wiring board 113, it is a good idea to select the resist metal 103 that can be etched with a chemical solution that does not erode or corrode the wiring pattern 104.
Examples of the material of the wiring pattern 103 include copper, nickel, gold, tin, silver, and palladium. Furthermore, a stable wiring pattern 104 with low resistance can be obtained by using copper.
[0022]
Next, the plating resist 102 is removed (FIG. 1D), and then an interlayer insulating material layer 105 is formed on the formed wiring pattern 104 (FIG. 1E).
The formation of the interlayer insulating material layer 105 is obtained by laminating an interlayer insulating sheet composed of an interlayer insulating material layer and at least one or more peelable protective film layers using a vacuum roll laminator. In the vacuum roll laminating method, the interlayer insulating material layer is temporarily pressed onto the wiring pattern 104 in a vacuum, and then heat-treated in the air, whereby the melt viscosity of the interlayer insulating resin is lowered and the unevenness of the wiring pattern 104 can be embedded. it can. Furthermore, the interlayer insulating material layer is flattened by a force for flattening the peelable protective film layer during heat treatment in the atmosphere. Finally, if the support film is peeled off, the interlayer insulating material layer 105 can be obtained a very smooth surface without being affected by the unevenness of the wiring pattern 104. At this time, it is important that the melt viscosity of the interlayer insulating material layer is 500 Pa · s or more and 20,000 Pa · s or less. The melt viscosity of the interlayer insulating material layer is measured using, for example, RDSII (manufactured by Rheometric Scientific F.E.) as a rheometer under the conditions of a frequency of 10 rad / s and a strain of 1% at a vacuum roll laminating temperature. can do. When the melt viscosity is larger than the above upper limit value, it is difficult to perform temporary pressure bonding, and due to heat treatment in the atmosphere, the interlayer insulating material layer cannot flow sufficiently, resulting in poor circuit embedding, and further flattening becomes difficult. . On the other hand, if it is lower than the lower limit value, the interlayer insulating material layer flows too much at the time of vacuum roll laminating, and the interlayer insulating resin protrudes from the laminating region, making accurate film thickness control difficult. As an advantage of this method, by using a dry film having a known thickness in advance, the thickness of the interlayer insulating material layer can be reliably controlled, and a flat interlayer insulating material layer can be easily formed. Furthermore, since the vacuum roll laminating apparatus can continuously laminate, productivity is remarkably increased when compared with a vacuum press. The mechanism of the flattening has not been elucidated.
[0023]
Next, a via 106 is formed in the interlayer insulating material layer 105 (FIG. 1F). The via 106 may be formed by any method suitable for this manufacturing method, and more preferably a carbon dioxide laser, UV-YAG laser, or excimer laser.
[0024]
Next, the conductor post 107 is formed by electroplating using the metal layer 101 as an electroplating lead (feeding electrode) (FIG. 2G). By this electrolytic plating, a conductor post 107 is formed in a portion of the interlayer insulating material layer 105 where the via 106 is formed. If the conductor post 107 is formed by electrolytic plating, the shape of the tip of the conductor post 107 can be freely controlled.
The material of the conductor post 107 may be any material suitable for this manufacturing method, and examples thereof include copper, nickel, gold, tin, silver, and palladium. Furthermore, by using copper, a stable conductor post 107 can be obtained with low resistance.
[0025]
Next, the bonding metal material layer 108 is formed on the surface (tip) of the conductor post 107 (FIG. 2H).
As a method of forming the bonding metal material layer 108, a method of forming by electroless plating, a method of forming the metal layer 101 by electrolytic plating using an electroplating lead (power supply electrode), and a paste containing a bonding metal material is used. The method of printing is mentioned. In the printing method, it is necessary to accurately align the printing mask with respect to the conductor post 107. However, in the method using electroless plating or electrolytic plating, the bonding metal material layer 108 is formed in addition to the surface of the conductor post 107. Therefore, the conductor posts 107 can be easily miniaturized and densified. In particular, the electrolytic plating method is very suitable because the metal that can be plated is more diverse and the chemical solution can be easily managed than the electroless plating method.
The material of the bonding metal material layer 108 may be any metal as long as it can be metal-bonded to the bonded portion 112 shown in FIG. 2 (j), for example, solder. Among solders, it is preferable to use Sn or In, or solder composed of at least two of Sn, Ag, Cu, Zn, Bi, Pd, Sb, Pb, In, and Au. More preferably, it is an environmentally friendly Pb-free solder. 2H shows an example in which the bonding metal material layer 108 is formed on the surface of the conductor post 107. The purpose of forming the bonding metal material layer 108 is to form the conductor post 107 and the bonded portion 112. Therefore, the bonding metal material layer 108 may be formed on the bonded portion 112. Of course, it may be formed on both surfaces of the conductor post 107 and the bonded portion 112.
[0026]
Next, a metal bonding adhesive layer 109 is formed on the surface (tip) of the interlayer insulating material layer 105 (FIG. 2 (i)).
The metal bonding adhesive layer 109 may be formed by a method suitable for the resin to be used. The metal bonding adhesive varnish may be directly applied by printing, curtain coating, bar coating, or the like for a dry film with a support film. Examples thereof include a method of laminating the metal bonding adhesive layer 109 by a method such as vacuum lamination or vacuum press. Although FIG. 1 (i) shows an example in which the metal bonding adhesive layer 109 is formed on the surface of the interlayer insulating material layer 105, the metal bonding adhesive layer 109 may be formed on the surface of the connected layer 111. I do not care. Of course, the interlayer insulating material layer 105 may be formed on both surfaces of the connected layer 111.
[0027]
Next, the connection layer 110 and the connection layer 111 obtained by the above-described steps are aligned (FIG. 2 (j)).
The alignment can be performed by a method in which a positioning mark formed in advance on the connection layer 110 and the layer to be connected 111 is read and aligned by an image recognition device, a method of positioning by a positioning pin, or the like. . 2J shows an example in which a core substrate such as FR-4 used for providing the rigid property to the multilayer wiring board 113 shown in FIG. It is also possible to use a metal layer 101 shown in FIG. 1D in which a wiring pattern 104 is formed. In addition, a multilayer wiring board 113 shown in FIG.
[0028]
Next, the connection layer 110 and the connection layer 111 are stacked (FIG. 2K).
As a laminating method, for example, using a vacuum press, the conductor post 107 is heated and pressurized until it is bonded to the bonded portion 112 by the bonding metal material layer 108, excluding the metal bonding adhesive layer 109, and the conductor The post 107 and the part to be joined 112 are metal-joined. Subsequently, the bonding layer 110 and the bonded layer 111 are further bonded by heating. It is essential that the final heating temperature is equal to or higher than the melting point of the bonding metal material.
[0029]
Next, the metal layer 101 is removed by etching (FIG. 3L). A resist metal 103 is formed between the metal layer 101 and the wiring pattern 104, and the resist metal 103 is resistant to a chemical solution used when the metal layer 101 is removed by etching. Even if the metal layer 101 is etched, the resist metal 103 is not eroded and corroded, and as a result, the wiring pattern 104 is not eroded and corroded.
When the material of the metal layer 101 is copper and the material of the resist metal is nickel, tin, or solder, a commercially available ammonia-based etching solution can be used. When the material of the metal layer 101 is copper and the material of the resist metal is gold, most etching solutions including a ferric chloride solution and a cupric chloride solution can be used.
[0030]
Next, the resist metal 103 is removed by etching (FIG. 3M). Since the wiring pattern 104 is resistant to a chemical used when the resist metal 103 is removed by etching, the wiring pattern 104 is not eroded or corroded. Therefore, the wiring pattern 104 is exposed by removing the resist metal 103. The resist metal 103 may be left without being removed as necessary.
When the wiring pattern 104 is made of copper and the resist metal is made of nickel, tin, or solder, a commercially available solder / nickel remover (for example, Mitsubishi Gas Chemical Co., Ltd., trade name) can be used. When the material of the wiring pattern 104 is copper and the material of the resist metal 103 is gold, it is difficult to etch the resist metal 103 without eroding and corroding the wiring pattern 104. In this case, the step of etching the resist metal 103 may be omitted.
[0031]
Finally, the multilayer wiring board 113 is obtained by repeating the above-described steps, that is, FIGS. 1 (a) to 3 (m) (FIG. 3 (n)). That is, a connection layer is formed on both surfaces of the core substrate by performing the laminating process shown in FIG. 2 (j) using the multilayer wiring board 113 shown in FIG. A multilayer wiring board 113 can be obtained by performing the laminating process shown in FIG. 2 (j) using the obtained layer as a connected layer, and further repeating these steps.
FIG. 3N shows a multilayer wiring board 113 in which two connection layers are laminated on both surfaces of the core substrate 116, and solder resist 115 is formed on both surfaces of the multilayer wiring board 113. In the solder resist 115, the inner pad 114a and the outer pad 114b are opened.
[0032]
Through the above-described steps, a multilayer wiring board in which the wiring patterns 104 of each layer and the conductor posts 107 are metal-bonded by the bonding metal material layer 108 and the respective layers are bonded can be manufactured.
[0033]
The semiconductor device 201 can be obtained by mounting the semiconductor chip 202 on the inner pad 114a side and mounting the solder ball on the outer pad 114b side of the multilayer wiring board 113 obtained by the above-described steps (FIG. 4). ).
[0034]
The interlayer insulating material for forming the interlayer insulating material layer used in the present invention preferably contains a cyanate compound (I) and a soluble polyimide siloxane (B), and the blending ratio is 100 parts by weight of the cyanate compound (I). On the other hand, soluble polyimidesiloxane is preferably 5 parts by weight or more and 400 parts by weight or less, more preferably 15 parts by weight or more and 200 parts by weight or less, and further preferably 20 parts by weight or more and 90 parts by weight or less. . When the amount of the soluble polyimide siloxane is less than the lower limit, the hard and brittle nature that is a defect of the cyanate compound cannot be compensated, and the film property in an uncured state may be deteriorated. When the amount is larger than the upper limit value, there is a possibility that low-temperature processability and reliability during heat cannot be sufficiently ensured.
[0035]
  As the cyanate compound used for the interlayer insulating material in the present invention,,oneCompound represented by general formula (2)ThingCyanate compounds having at least two or more cyanate groups in which 40% or less of the cyanate groups are trimerized are preferred. Specifically, bisphenol-A dicyanate ethylidene bis-4,1-phenylene dicyanate, tetraorthomethyl Bisphenol-F dicyanate, phenol novolac polycyanate, cresol novolac polycyanate, dicyclopentadienyl bisphenol dicyanate, hexafluorobisphenol A dicyanate and the like, and compounds obtained by trimerizing these cyanate groups within the above range. Of these, phenol novolac polycyanate and cresol novolac polycyanate are particularly preferable. Among these, at least one kind or two or more kinds are used.
  By using the cyanate compound, an interlayer insulating material having high workability at low temperature, high heat elastic modulus, excellent heat resistance reliability at high temperatures exceeding 200 ° C., low thermal expansion coefficient, low dielectric constant and dielectric loss tangent A layer can be obtained.
[0036]
The soluble polyimide siloxane used for the interlayer insulating material in the present invention is 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-benzophenonetetracarboxylic dianhydride, An aromatic tetracarboxylic acid component which is at least one selected from the group consisting of 4,4′-oxydiphthalic dianhydride and 4,4′-diphenylsulfone tetracarboxylic dianhydride, and a general formula (3) High molecular weight polyimide obtained by polymerization and imidization of the diaminopolysiloxane represented by 10 mol% or more and 80 mol% or less and a diamine component consisting of aromatic diamine 20 mol% or more and 90 mol% or less Siloxane is preferred.
By using a solvent-soluble polyimide resin, it is possible to obtain an insulating resin sheet excellent in sheet properties in an uncured state and excellent in film strength and flexibility of a cured product.
[0037]
Examples of the diaminopolysiloxane represented by the general formula (3) include 1,3-bis (3-aminopropyl) tetramethylsiloxane and α, ω-bis (3-aminopropyl) polydimethylsiloxane. The resulting polyamic acid and polyimide resin contribute to solubility in organic solvents and thermoplasticity. Further, by using this structure, the glass transition temperature can be lowered, and is particularly suitable for applications requiring low-temperature processing.
The amount ratio in the diamine component can be used in the range of 10 mol% or more and 80 mol% or less of the total diamine component from the viewpoint of solubility and thermoplasticity, but 10 mol% from the viewpoint of heat resistance. As mentioned above, it is more preferable that it is in the range of 50 mol% or less. In particular, when 1,3-bis (3-aminopropyl) tetramethylsiloxane is used, solubility and thermoplasticity are improved without degrading heat resistance, which is preferable.
[0038]
Examples of the aromatic diamine used in the polyimidesiloxane resin include p-phenylenediamine, m-phenylenediamine, 1,5-diaminonaphthalene, 2,6-diaminonaphthalene, 2,4-diaminotoluene and 2,5-diaminotoluene. 2,5-diamino-p-xylene, 2,5-diamino-m-xylene, 2,5-diaminopyridine, 2,6-diaminopyridine, 3,3′-diaminodiphenylmethane, 4,4′-diaminodiphenylmethane 3,3′-diaminodiphenylpropane, 4,4′-diaminodiphenylpropane, 3,3′-diaminodiphenylhexafluoropropane, 4,4′-diaminodiphenylhexafluoropropane, 3,3′-diaminodiphenyl ether, 4, , 4'-diaminodiphenyl ether, 3,4'-diaminodiphenyl ether Benzidine, 3,3′-diaminobiphenyl, 3,3′-diaminodiphenyl sulfide, 4,4′-diaminodiphenyl sulfide, 3,3′-diaminodiphenyl sulfone, 4,4′-diaminodiphenyl sulfone, 4,4 ′ -Diaminobenzanilide, 4,4'-methylenedi-o-toluidine, 4,4'-methylenedi-2,6-xylidine, 4,4'-methylenedi-2,6-diethylaniline, 3,3'-dimethyl- 4,4′-diaminobiphenyl, 3,3′-dimethoxybenzidine, 1,3-bis (3-aminophenoxy) benzene, 1,3-bis (4-aminophenoxy) benzene, 1,4-bis (4- Aminophenoxy) benzene, 2,2-bis [4- (4-aminophenoxy) phenyl] propane, 2,2-bis [4- (4-aminophenoxy) phenyl] hexaph Olopropane, bis [4- (4-aminophenoxy) phenyl] sulfone, bis [4- (3-aminophenoxy) phenyl] sulfone, 4,4′-bis (4-aminophenoxy) biphenyl, bis [4- (4 -Aminophenoxy) phenyl] ether and the like. It is preferable to use one or two or more aromatic diamines selected from these.
[0039]
The equivalent ratio of the aromatic tetracarboxylic acid component to the total diamine component in the polymerization reaction of the polyimidesiloxane resin is an important factor that determines the molecular weight of the resulting polyimidesiloxane. It is well known that there is a correlation between the molecular weight and physical properties of polymers, especially the number average molecular weight and mechanical properties. The higher the number average molecular weight, the better the mechanical properties. Therefore, in order to obtain a practically excellent strength, it is necessary to have a certain high molecular weight.
In the present invention, the equivalent ratio r of the acid component and the amine component is preferably a molar ratio of 0.95 ≦ r ≦ 1.05. Moreover, the range of 0.97 <= r <= 1.03 is more preferable from both mechanical strength and heat resistance. There is no problem even if an end cap agent is used to control the molecular weight. Examples of the end cap agent include phthalic anhydride and trimellitic anhydride.
[0040]
The reaction between the aromatic tetracarboxylic acid component and the diamine component is carried out by a known method in an aprotic polar solvent, and the final imide ring closure is better as the degree is higher. It is not preferable because imidization occurs due to heat and water is generated. Therefore, it is desirable to achieve an imidization ratio of 95% or more, more preferably 98% or more.
[0041]
In addition to the above components, a silica filler can be used for the interlayer insulating material used in the present invention in order to reduce the thermal expansion coefficient, heat resistance, and flame retardancy. It is preferable that a silica filler contains 5 to 400 weight part with respect to 100 weight part of cyanate compounds. More preferably, it is 10 to 300 weight part, More preferably, it is 50 to 250 weight part. When there are more silica fillers than the said upper limit, there exists a possibility that the workability of the interlayer insulation material sheet in an uncured state may fall.
The silica filler preferably has an average particle size of 1 μm or less and a maximum particle size of 6 μm or less. When the average particle size is larger than 1 μm and the maximum particle size is larger than 6 μm, it is not possible to cope with an increase in the wiring density of the multilayer wiring board and there is a possibility that sufficient insulation reliability cannot be ensured.
[0042]
The silica filler is preferably used by dispersing in advance in a solvent (d) in which the polyimidesiloxane resin (b) is soluble. By previously dispersing the silica filler in the solvent, the silica filler can be completely dispersed in the resin. When the surface of the silica filler is sufficiently wetted by the solvent, it is also easy to mix the solvent-soluble polyimide resin (b) and the silica filler (c) solution.
[0043]
The solvent (d) used in the present invention may be any solvent in which the polyimide resin (b) is soluble. For example, N, N-dimethylformamide, N, N-dimethylacetamide, N, -methyl-2-pyrrolidone 1,4-dioxane, gamma-butyllactone, diglyme, anisole, cyclohexanone, toluene, xylene and the like. In particular, N-methyl-2-pyrrolidone is preferable due to excellent solubility of the polyimide resin. Further, since it is a polar solvent, it is suitable for wetting and dispersing silica filler.
[0044]
To disperse the silica filler in the solvent, add the silica filler to the solvent and use ultrasonic, 3-roll, three-one motor, homogenizer, ball mill, rotation / revolution mixer, vacuum / revolution / revolution mixer, etc. And a method of dispersing them.
Moreover, as a ratio in the solvent of a silica filler, 30 to 75 weight% of the total weight of a silica filler solution is preferable. If it is less than 30% by weight, the viscosity of the silica filler solution may be low and the filler may be easily precipitated, and if it exceeds 75% by weight, the silica filler solution may have a high viscosity and may be difficult to handle.
[0045]
In addition to the above components, metal acetylacetonate can be used for the interlayer insulating material used in the present invention. Metal acetylacetonate acts as a curing catalyst for the cyanate compound, can freely control the reactivity of the interlayer insulating material depending on the amount of the compound, and is excellent in storage stability.
The compounding amount of the metal acetylacetonate is preferably 0.0001 parts by weight or more and 0.1 parts by weight or less, more preferably 0.005 parts by weight or more and 0.05 parts by weight or less with respect to 100 parts by weight of the cyanate compound. It is. When less than the said lower limit, there exists a possibility that the reactivity of a cyanate compound may be inadequate.
Metal acetylacetonate is a metal chelate in which two or more acetylacetonate ligands are bonded to a central metal atom. Examples of preferred coordinating metals are divalent copper, manganese, nickel, cobalt, lead, zinc and tin, trivalent aluminum, iron, cobalt and manganese, and tetravalent titanium. .
[0046]
In addition to the above components, additives such as a leveling agent and an antifoaming agent can be used for the interlayer insulating material used in the present invention, depending on the purpose.
[0047]
The interlayer insulating material used in the present invention is dissolved in a solvent and used as a varnish. As the solvent, a solvent that can dissolve the polyimide resin or a solvent that is used for producing polyimide siloxane can be used as it is. Specifically, N, N-dimethylformamide, N, N-dimethylacetamide, N, -methyl-2-pyrrolidone, 1,4-dioxane, gamma-butyllactone, diglyme, anisole, cyclohexanone, toluene, xylene, etc. is there. Only one type of solvent may be used, or two or more types may be mixed and used. The heat curing temperature of the interlayer insulating material layer is preferably 120 ° C. or higher and 300 ° C. or lower, and more preferably 130 ° C. or higher and 250 ° C. or lower.
[0048]
  In the present invention, the peelable protective film layer used for the interlayer insulating material sheet can be peeled off without impairing the form and function of the interlayer insulating material layer.AhAlthough not particularly limited, for example, protection made of resin such as polyester, polyolefin, polyphenylene sulfide, polyvinyl chloride, polytetrafluoroethylene, polyvinylidene fluoride, polyvinyl fluoride, polyvinyl alcohol, polycarbonate, polyimide, polyether ether ketone, etc. Examples thereof include films, and these may be coated with a release agent such as silicone or a fluorine compound.
[0049]
The interlayer insulating material sheet used in the present invention can be used as an uncured or semi-cured sheet. This uncured or semi-cured sheet can be peeled from an interlayer insulating material varnish, for example, polyester. It can apply | coat on a protective film and it can obtain by drying the coating layer for 20 second or more and 30 minutes or less at the temperature of 80 degreeC or more and 200 degrees C or less. The residual solvent amount is preferably 2% by weight or less, and more preferably 0.5% by weight or less. The thickness is preferably 10 μm or more and 50 μm or less. The uncured or semi-cured sheet of the interlayer insulating material composition thus produced has flexibility and can be wound around a paper tube or cut with a cutter. Furthermore, it is excellent in preservability and can sufficiently withstand use after one month storage at room temperature.
[0050]
The metal bonding adhesive used in the present invention is preferably an adhesive having a surface cleaning function and high insulation reliability. Examples of the surface cleaning function include a function of removing an oxide film present on the surface of the bonding metal material layer and the surface of the metal to be connected, and a function of reducing the oxide film. Due to the surface cleaning function of the metal bonding adhesive, the wettability with the surface for connecting to the bonding metal material layer is sufficiently enhanced. Therefore, the metal bonding adhesive must be in contact with the surface for connecting with the bonding metal material layer in order to clean the metal surface. By cleaning both surfaces, the metal material layer for joining works to wet and spread the surface to be joined, and the metal material layer for joining uses the force of wetting and spreading to join the metal at the metal joint. Adhesive is eliminated. Accordingly, in the metal bonding using the metal bonding adhesive, the resin residue hardly occurs and the electrical connection reliability is high.
[0051]
The metal bonding adhesive used in the present invention preferably includes a composition comprising as essential components a resin (A) having at least one phenolic hydroxyl group and a resin (B) acting as a curing agent. In the resin (A) having a phenolic hydroxyl group, the phenolic hydroxyl group removes dirt such as a metal material layer for joining and an oxide on the metal surface or reduces the oxide by metal surface bonding. Acts as a flux. Furthermore, since a good cured product can be obtained by the resin (B) that acts as the curing agent, it is not necessary to wash and remove after metal bonding, and maintains electrical insulation even in high temperature and high humidity atmospheres. Enables highly reliable metal bonding.
[0052]
The resin (A) having at least one or more phenolic hydroxyl groups used for the metal bonding adhesive in the present invention is selected from phenol novolac resins, alkylphenol novolac resins, resole resins, cresol novolac resins, and polyvinylphenol resins. Are preferred, and one or more of these can be used.
[0053]
As the resin (B) that acts as a curing agent of the resin (A) having a phenolic hydroxyl group used for the metal bonding adhesive in the present invention, an epoxy resin, an isocyanate resin, or the like is used. Specifically, all are based on phenolic resins such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol and resorcinol, and skeletons such as aliphatic, cycloaliphatic and unsaturated aliphatic And modified epoxy compounds and isocyanate compounds.
[0054]
The resin (A) having a phenolic hydroxyl group used for the metal bonding adhesive in the present invention contains a preferable lower limit of 20 wt% and a preferable upper limit of 80 wt% in the adhesive, and a more preferable upper limit. Is 60 wt%. If it is less than the lower limit, the effect of cleaning the metal surface may be reduced. On the other hand, if the amount is larger than the upper limit, a sufficient cured product may not be obtained, and in that case, the bonding strength and reliability are lowered. On the other hand, the resin (B) acting as a curing agent is preferably contained in the adhesive at 20 wt% or more and 80 wt% or less. Moreover, you may add a coloring agent, a curing catalyst, an inorganic filler, various coupling agents, a solvent, etc. to resin used for a metal bonding adhesive.
[0055]
The maximum features of the multilayer wiring board and the method of manufacturing the multilayer wiring board according to the present invention are shown below.
(1) There is no need to polish the insulating layer, and the insulating layer can be formed with a stable thickness.
(2) A highly reliable interlayer connection can be obtained.
(3) The wiring pattern 104 and the body post can be formed by electrolytic plating.
(4) Since the metal layer 101 to be finally removed is used as an electroplating lead, a special electroplating lead is provided on the wiring pattern 104, or electroplating is performed by electroless plating or sputtering after the wiring pattern 104 is formed. There is no need to form a lead.
[0056]
【Example】
Hereinafter, the present invention will be described more specifically with reference to examples, but the present invention is not limited thereto.
[0057]
In order to confirm the effectiveness of the multilayer wiring board of the present invention, the multilayer wiring boards of Examples 1 to 13 shown below were manufactured, and the circuit embedding property / surface flatness of the interlayer insulating material layer, and the cross-sectional observation of the metal joint portion The temperature cycle test and the insulation reliability test were conducted, and the evaluation results are summarized in Table 2. Further, the melt viscosity at 130 ° C. of the interlayer insulating material layer of the interlayer insulating sheet was measured with a rheometer. The rheometer was RDSII (manufactured by Rheometric Scientific F.E.) and was measured under the conditions of a frequency of 10 rad / s and a strain of 1%. The evaluation results are shown in Table 1.
[0058]
(Synthesis of polyimide siloxane (PI) -1)
791 g of dehydrated and purified N-methyl-2-pyrrolidone (NMP) is placed in a four-necked flask equipped with a dry nitrogen gas inlet tube, a cooler, a thermometer, and a stirrer, and stirred vigorously for 10 minutes while flowing nitrogen gas. Next, 2,2-bis (4- (4-aminophenoxy) phenyl) propane (BAPP) 73.8926 g (0.180 mol), 1,3-di (3-aminophenoxy) benzene (APB) 17. 5402 g (0.060 mol), α, ω-bis (3-aminopropyl) polydimethylsiloxane (APPS) 50.2200 g (average molecular weight 837, 0.060 mol) were added, and the system was heated to 60 ° C., Stir until uniform. After homogeneous dissolution, the system was cooled to 5 ° C. with an ice-water bath, and 43.1330 g (0.150 mol) of 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride (BPDA), 3,3 ′ , 4,4′-benzophenonetetracarboxylic dianhydride (BTDA) 48.4110 g (0.150 mol) was added in powder form over 15 minutes, and stirring was continued for 3 hours. During this time, the flask was kept at 5 ° C.
Thereafter, the nitrogen gas inlet tube and the cooler were removed, a Dean-Stark tube filled with xylene was attached to the flask, and 198 g of xylene was added to the system. Instead of the oil bath, the system was heated to 175 ° C., and generated water was removed from the system. When heated for 4 hours, no water was observed from the system. After cooling, this reaction solution was put into a large amount of methanol to precipitate polyimidesiloxane. The solid content was filtered and then dried under reduced pressure at 80 ° C. for 12 hours to remove the solvent to obtain 227.79 g (yield 92.1%) of a solid resin. When the infrared absorption spectrum was measured by the KBr tablet method, an absorption of 5.6 μm derived from a cyclic imide bond was observed, but an absorption of 6.06 μm derived from an amide bond could not be recognized, 100% imidation was confirmed.
[0059]
(Synthesis of polyimide siloxane (PI) -2)
As the diamine component, 4,5-methylenedi-2,6-xylidine (MDX) 0.15 mol, 2,2-bis (4- (4-aminophenoxy) phenyl) propane (BAPP) 0.09 mol, 1, 0.03 mol of 3-bis (3-aminopropyl) tetramethylsiloxane (APDS), 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride (BPDA) as an aromatic tetracarboxylic acid component A soluble polyimide siloxane was synthesized in the same manner as the polyimide resin PI-1, except that 135 mol, 0.013 mol of 3,3 ′, 4,4′-benzophenonetetracarboxylic dianhydride (BTDA) was used. did.
[0060]
[Example 1]
100 g of m, p-cresol novolak resin (Nippon Kayaku Co., Ltd. PAS-1, OH group equivalent 120) and bisphenol F type epoxy resin (Nippon Kayaku Co., Ltd. RE-404S, epoxy equivalent 165) 140 g Then, dissolved in 60 g of cyclohexanone, 0.2 g of triphenylphosphine (manufactured by Hokuko Chemical Co., Ltd.) was added as a curing catalyst to prepare a metal bonding adhesive varnish.
[0061]
Subsequently, phenol novolac polycyanate resin (Lonza Co., Ltd., trade name: Primaset PT-15, cyanate group trimerization rate 0%) 100 g, N-methylpyrrolidone 121 g and spherical synthetic silica filler (Admatex Co., Ltd. SE2060, Silica filler solution in which 225 g of an average particle size of 0.5 μm and a maximum particle size of 6.0 μm are dispersed and mixed by ultrasonic waves, 50 g of the above polyimidesiloxane-2 (PI-2), cobalt (III) acetylacetonate (Co ( AA)) (manufactured by Wako Pure Chemical Industries, Ltd.) 0.02 g and NMP 200 g were mixed and stirred and dissolved in a rotating / revolving mixer to prepare an insulating resin material varnish.
[0062]
Roll laminated a dry film resist (Asahi Kasei Co., Ltd., AQ-2058: trade name) on a 150 μm thick rolled copper plate (metal layer 101) having a roughened surface (made by Furukawa Electric, EFTEC-64T: trade name), Exposure and development were performed using a predetermined negative film, and a plating resist (plating resist 102) necessary for forming the wiring pattern 104 was formed. Next, using a rolled copper plate as a lead for electrolytic plating, nickel (resist metal 103) was formed by electrolytic plating, and further, electrolytic wiring was formed to form a wiring pattern (wiring pattern 104). The wiring pattern was line width / line spacing / thickness = 20 μm / 20 μm / 10 μm. The interlayer insulating material varnish obtained above was applied to a polyester (PET) film and then dried at 80 ° C. for 10 minutes and at 130 ° C. for 10 minutes to form an interlayer insulating material layer having a thickness of 25 μm. The interlayer insulating material layer with a PET film is vacuum-bonded by passing it between laminate rolls heated to 130 ° C. while applying pressure, and further subjected to heat treatment with a dryer at 130 ° C. for 5 minutes, thereby providing wiring. The pattern was embedded and the PET film was peeled off to form an interlayer insulating material layer (interlayer insulating material layer 105) having a thickness of 25 μm. This cross section was observed with an electron microscope (SEM), and the circuit embedding property of the interlayer insulating material layer was evaluated. Moreover, the surface flatness after interlayer insulation layer formation was measured with the ultra-deep shape measuring microscope (VK-8500: Keyence Corporation make). Line width / between lines = 20 μm / 20 μm in the region where the circuit is present and where there is no step is 2 μm or less, ○, and larger than the above value ×. The results are summarized in Table 2. After forming the interlayer insulating material layer, it was cured by heat treatment at 150 ° C. for 30 minutes, 200 ° C. for 60 minutes, and 250 ° C. for 180 minutes in a nitrogen atmosphere.
[0063]
Next, a 45 μm diameter via (via 106) was formed by a UV-YAG laser. Subsequently, the via was filled with copper by performing electrolytic copper plating using the rolled copper plate as a lead for electrolytic plating, thereby forming a copper post (conductor post 107).
Next, Sn—Pb eutectic solder (joining metal material layer 108) was formed on the copper post by electrolytic plating using the rolled copper plate as a lead for electrolytic plating. Next, the metal bonding adhesive varnish obtained above is applied by bar coating to the surface of the interlayer insulating material layer, that is, the surface on which the Sn—Pb eutectic solder is formed, and then dried at 80 ° C. for 20 minutes, and 10 μm A thick metal bonding adhesive layer (metal bonding adhesive layer 109) was formed. The connection layer (connection layer 110) was able to be obtained by the previous steps.
[0064]
On the other hand, a glass epoxy resin copper clad laminate (made by Sumitomo Bakelite) equivalent to FR-5 on which a 12 μm thick copper foil is formed is used as the core substrate, and the copper foil is etched to form a wiring pattern and a pad (bonded portion 112). ) And a connected layer (connected layer 111) could be obtained. Next, the connection layer obtained by the above-mentioned process and the positioning mark formed in advance in the layer to be connected were read by an image recognition device, both were aligned, and temporarily pressed at a temperature of 100 ° C. Furthermore, the above-mentioned alignment / temporary pressure bonding was performed again to obtain a material in which the connection layer was temporarily pressure-bonded on both surfaces of the connected layer. This was heated and pressed by a press at a temperature of 220 ° C., and the copper post penetrated the metal bonding adhesive layer and was solder-bonded to the pad to bond the connection layer to both surfaces of the connection layer. Next, post-curing was performed at 220 ° C. for 2 hours to cure the metal bonding adhesive layer. Next, the rolled copper plate was removed by etching using an ammonia-based etchant, and nickel was removed by etching using a solder / nickel stripper (Mitsubishi Gas Chemical Co., Ltd./Petax: trade name). Finally, a solder resist (solder resist 115) was formed to obtain a multilayer wiring board (multilayer wiring board 113).
[0065]
The obtained multilayer wiring board is designed so that 60 metal joints are connected in series on both sides for a temperature cycle test. Further, on the multilayer wiring board, a comb-like wiring pattern of line width / line spacing = 20 μm / 20 μm is simultaneously formed for an insulation resistance test.
[0066]
The cross section of the metal joint portion of the obtained multilayer wiring board was observed with an electron microscope (SEM), and the metal joint state was evaluated.
[0067]
After confirming the continuity of the obtained multilayer wiring board, a temperature cycle test was conducted in which one cycle was −55 ° C. for 10 minutes and 125 ° C. for 10 minutes. The number of samples was 10. Table 2 summarizes the results of the number of defective disconnections after 1000 cycles of the temperature cycle test.
[0068]
After measuring the initial insulation resistance of the obtained multilayer wiring board, a DC voltage of 5.5 V was applied in an atmosphere of 85 ° C./85% RH, and the insulation resistance after 1000 hours was measured. The applied voltage during measurement was 11 V for 1 minute, and the initial insulation resistance and post-treatment insulation resistance are shown together in Table 2.
[0069]
[Example3~ 12]
  A laminate was manufactured in the same manner as in Example 1 except that the composition of the interlayer insulating material was as shown in Table 1. The evaluation results are summarized in Table 2.
[0070]
[Table 1]
[0071]
  In Table 1, RealPrimaset PT30 of Examples 3 to 6 is a phenol novolac polycyanate resin manufactured by Lonza Corporation, and SE3060 of Examples 4 to 6 is a spherical synthetic silica filler manufactured by Admatex Corporation (average particle size of 0.9 μm). The maximum particle size is 6.0 μm). In addition, SE3060 was used by being previously dispersed in N-methylpyrrolidone so that the content of the inorganic filler was 65% by weight with respect to the total weight of the inorganic filler solution.. FruitZn (AA) of Example 8 is Zn (II) acetylacetonate, Al (AA) of Example 9 is Al (III) acetylacetonate, and Fe (AA) of Example 10 is Fe (III) acetylacetonate, Ni (AA) of Example 11 is Ni (II) acetylacetonate, and Mn (AA) of Example 12 is Mn (II) acetylacetonate.
[0072]
[Example 13]
In Example 1, instead of 100 g of m, p-cresol novolak resin used in the production of the metal bonding adhesive varnish, 100 g of bisphenol A type novolak resin (LF 4781 manufactured by Dainippon Ink and Chemicals, OH equivalent 120) A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 of the multilayer wiring board except that was used. The evaluation results are shown in Table 2.
[0073]
[Example 14]
In Example 1, instead of 100 g of m, p-cresol novolak resin used for the production of the metal bonding adhesive varnish, 100 g of polyvinylphenol resin (Maruka Rinka-M, OH equivalent 120 manufactured by Maruzen Petrochemical Co., Ltd.) is used. A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 of the multilayer wiring board except for the above. The evaluation results are shown in Table 2.
[0074]
[Example 15]
120 g of bisphenol A type novolak resin (LF4871, manufactured by Sumitomo Durez Co., Ltd., OH equivalent 120), 35 g of diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 220), and dicyclopentadiene type Except that 210 g of novolak epoxy resin (XD-1000L manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 250) was dissolved in 100 g of methyl ethyl ketone to produce a metal bonding adhesive varnish, the same as Example 1 of the multilayer wiring board A multilayer wiring board was obtained and evaluated. The evaluation results are shown in Table 2.
[0075]
[Example 16]
100 g of m, p-cresol novolak resin (Nippon Kayaku Co., Ltd. PAS-1, OH equivalent 120) and bisphenol F type epoxy resin (Nippon Kayaku Co., Ltd. RE-404S, epoxy equivalent 165) 140 g, A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 of the multilayer wiring board except that it was dissolved in 60 g of cyclohexanone to prepare a metal bonding adhesive varnish. The evaluation results are shown in Table 2.
[0076]
[Example 17]
106 g of phenol novolak resin (PR-HF-3, manufactured by Sumitomo Durez Co., Ltd., OH equivalent 106), 35 g of diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 220), and dicyclo The same as Example 1 of the multilayer wiring board except that 210 g of pentadiene type novolac epoxy resin (XD-1000L, Nippon Kayaku Co., Ltd., epoxy equivalent 250) was dissolved in 100 g of methyl ethyl ketone to prepare a metal bonding adhesive varnish. A multilayer wiring board was obtained and evaluated. The evaluation results are shown in Table 2.
[0077]
[Example 18]
106 g of phenol novolak resin (PR-53647 manufactured by Sumitomo Durez Co., Ltd., OH equivalent 106), 35 g of diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 220), and dicyclopentadiene type Except that 210 g of novolak epoxy resin (XD-1000L manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 250) was dissolved in 100 g of methyl ethyl ketone to prepare a metal bonding adhesive varnish, the same as Example 1 of the multilayer wiring board A multilayer wiring board was obtained and evaluated. The evaluation results are shown in Table 2.
[0078]
[Example 19]
100 g of phenol novolac resin (PR-51470 manufactured by Sumitomo Durez Co., Ltd., OH equivalent 105) and 210 g of diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 220) are dissolved in 80 g of cyclohexanone. Except that 0.3 g of 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-PW manufactured by Shikoku Kasei Kogyo Co., Ltd.) was added as a curing catalyst to produce a metal bonding adhesive varnish. A multilayer wiring board was obtained and evaluated in the same manner as in Example 1. The evaluation results are shown in Table 2.
[0079]
[Table 2]
[0080]
As can be seen from the evaluation results shown in Table 2, the multilayer wiring board of the present invention and the multilayer wiring board manufactured by the manufacturing method of the multilayer wiring board of the present invention are excellent in workability and reliability of the interlayer insulating material layer. In the temperature cycle test, no disconnection failure occurred, and the insulation resistance test did not lower the insulation resistance. Therefore, the effects of the multilayer wiring board and the manufacturing method thereof of the present invention are obvious.
[0081]
【The invention's effect】
The present invention uses a metal adhesive layer having a metal surface cleaning function and high insulation reliability, and an interlayer insulating material layer having high workability and reliability, thereby enabling reliable interlayer connection. It is possible to provide a multilayer wiring board with high interlayer insulation reliability other than the junction, a manufacturing method thereof, and a semiconductor device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 1).
FIG. 3 is a cross-sectional view showing the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 2).
FIG. 4 is a cross-sectional view showing a semiconductor device manufactured using a multilayer wiring board according to an embodiment of the present invention.
[Explanation of symbols]
101 metal layer
102 Plating resist
103 resist metal
104 Wiring pattern
105 Interlayer insulation material layer
106 Via
107 Conductor post
108 Metal material layer for bonding
109, 109 'metal bonding adhesive layer
110, 110a, 110b, 110c, 110d Connection layer
111, 111a Connected layer
112 Joined part
113, 112a multilayer wiring board
114a inner pad
114b outer pad
115 solder resist
116 Core substrate
201 Semiconductor device
202 Semiconductor chip
203 Bump
204 Underfill
205 Solder ball

Claims (17)

The wiring pattern formed embedded in the surface of the interlayer insulating material layer and the connected portion of the connected layer are joined to the conductor post formed in the interlayer insulating material layer by the metal bonding material layer, and the interlayer insulation In the multilayer wiring board in which the material layer and the connected layer are bonded with a metal bonding adhesive layer, the interlayer insulating material layer is 40% or less of the cyanate group of the cyanate compound represented by the general formula (2). It is obtained by laminating an interlayer insulating material layer containing 100 parts by weight of a trimerized cyanate compound, 5 parts by weight or more and 400 parts by weight or less of a soluble polyimide siloxane and having a melt viscosity of 500 Pa · s or more and 20,000 Pa · s or less. A multilayer wiring board characterized by that.
(In the formula (2), R ₁ to R ₃ each independently represents a hydrogen atom, a methyl group, a fluoroalkyl group, a halogen atom, n is an integer of 0-6.)   The multilayer wiring board according to claim 1, wherein the joining metal material layer is made of solder or solder formed by electrolytic plating.   The multilayer wiring board according to claim 1, wherein the conductor post is made of copper. The soluble polyimide siloxane (B) is 3,3 ', 4,4' biphenyltetracarboxylic dianhydride, 3,3,4,4' - benzophenone tetracarboxylic acid dianhydride, 4,4'-oxydiphthalic Aromatic tetracarboxylic acid component selected from acid dianhydride and 4,4′-diphenylsulfonetetracarboxylic dianhydride, and 10 mol% or more and 80 mol of diaminopolysiloxane represented by the general formula (3) The multilayer wiring board according to any one of claims 1 to 3, which is a soluble polyimide siloxane synthesized by reacting a diamine component consisting of 20% by mole or less and 20% by mole or more and 90% by mole or less of an aromatic diamine.
(In formula (3), R ₇ represents a divalent hydrocarbon group, R _{8 to} R ₁₁ represent a lower alkyl group or a phenyl group, and n represents an integer of 1 to 20.) The multilayer wiring board according to any one of claims 1 to 4 , wherein the interlayer insulating material further comprises 5 parts by weight or more and 400 parts by weight or less of silica filler (C). The multilayer wiring board according to claim 5 , wherein the silica filler (c) has an average particle diameter of 1 μm or less and a maximum particle diameter of 6 μm or less. The multilayer wiring board according to claim 5 or 6, wherein the silica filler (c) is dispersed in advance in a solvent (d) in which the polyimidesiloxane resin (b) is soluble. The multilayer wiring board according to claim 7 , wherein the solvent (d) is N-methyl-2-pyrrolidone. The multilayer wiring board according to any one of claims 1 to 8 , wherein the interlayer insulating material further comprises 0.0001 parts by weight or more and 0.1 parts by weight or less of metal acetylacetonate (e). Metal acetylacetonate (e) is selected from divalent copper, manganese, nickel, cobalt, lead, zinc and tin, trivalent aluminum, iron, cobalt and manganese, and tetravalent titanium The multilayer wiring board according to claim 9 , comprising a coordination metal. The multilayer according to any one of claims 1 to 10 , wherein the metal bonding adhesive comprises, as essential components, a resin (A) having at least one phenolic hydroxyl group and a resin (B) that acts as a curing agent thereof. Wiring board. The multilayer wiring board according to claim 11 , wherein the resin (A) having a phenolic hydroxyl group is selected from a phenol novolak resin, an alkylphenol novolak resin, a resole resin, a cresol novolac resin, and a polyvinyl phenol resin. The multilayer wiring board according to claim 11 or 12 , wherein the resin (A) having a phenolic hydroxyl group is contained in the metal bonding adhesive in an amount of 20 wt% to 80 wt%. Forming a wiring pattern by electrolytic plating using the metal layer as a lead for electrolytic plating;
A step of laminating an interlayer insulating sheet composed of an interlayer insulating material layer and at least one or more peelable protective film layers on the wiring pattern by a vacuum roll laminating device, and forming an interlayer insulating material layer;
Forming a via in the interlayer insulating material layer so that a part of the wiring pattern is exposed;
Forming a metal post as a lead for electrolytic plating and forming a conductor post by electrolytic plating;
Forming a bonding metal material layer on at least one of the surface of the conductor post or the surface of the bonded portion facing the conductor post;
Forming a metal bonding adhesive layer on at least one of the surface of the interlayer insulating material layer or the surface of the connected layer;
The conductor post and the part to be joined, which are opposed to each other through the metal bonding adhesive layer, are bonded by the bonding metal material layer, and the interlayer insulating material layer and the connection layer are bonded by the metal bonding adhesive layer. And the process of
Removing the metal layer by etching;
The method of manufacturing a multilayer wiring board comprising a melt viscosity of the interlayer insulating material layer in the step of forming an interlayer insulating material layer, 500 Pa · s or more, 20,000 Pa · s Ri der hereinafter and having the general formula (2 40% or less of the cyanate group of the cyanate compound represented by the formula (1) includes 100 parts by weight of a cyanate compound trimerized, and 5 parts by weight or more and 400 parts by weight or less of a soluble polyimide siloxane .
(In the formula (2), R ₁ to R ₃ each independently represents a hydrogen atom, a methyl group, a fluoroalkyl group, a halogen atom, n is an integer of 0-6.) 15. The method for producing a multilayer wiring board according to claim 14 , further comprising a step of forming a resist metal layer by electrolytic plating between the metal layer and the wiring pattern using the metal layer as an electrolytic plating lead. 16. The method for manufacturing a multilayer wiring board according to claim 14 , wherein the joining metal material layer is made of solder or solder formed by electrolytic plating. A semiconductor device using the multilayer wiring board according to any one of claims 1 to 13 or the multilayer wiring board obtained by the method for producing a multilayer wiring board according to any one of claims 14 to 16 .