JP2003282773A - Multilayer wiring board, its manufacturing method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board that is highly reliable, wherein a fine interlayer connection can be surely made, and a fine wiring pattern can be formed. <P>SOLUTION: In the multilayer wiring board, the diameter (R<SB>via</SB>) of a via, the average grain diameter (R<SB>ave</SB>) of an inorganic filler used for an interlayer insulating material, the 95% grain diameter (R<SB>95</SB>) of the filler indicating that a 95% filler is contained when the filler is integrated from the having a minimum grain diameter, and a maximum grain diameter (R<SB>max</SB>) are so set as to satisfy the following formulas; 0.002≤R<SB>ave</SB>/R<SB>via</SB>≤0.03, R<SB>95</SB>/R<SB>via</SB>≤0.06, and R<SB>max</SB>/ R<SB>via</SB>≤0.15. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, a method of manufacturing the same, and a semiconductor device.
More specifically, the present invention relates to a multilayer wiring board on which a semiconductor chip is mounted, a multilayer wiring board for simultaneously electrically connecting and bonding layers, a method for manufacturing the same, and a semiconductor device.

[0002]

2. Description of the Related Art With the recent demand for high functionality, lightness, thinness, shortness, and miniaturization of electronic devices, high-density integration and further high-density mounting of electronic parts have been advanced, and they are used in these electronic devices. Semiconductor packages are becoming smaller and more pins than ever before.

A conventional circuit board is called a printed wiring board, and is composed of a laminate of glass fiber woven cloth impregnated with epoxy resin. After patterning a copper foil attached to a glass epoxy board, a plurality of layers are stacked. The mainstream method is to use a wiring board in which layers are laminated and bonded, a through hole is drilled, copper is plated on the wall surface of the hole to form a via, and electrical connection is made between layers. However, the miniaturization and high densification of mounted components have advanced, and the wiring density is insufficient in the above-described wiring board, which causes a problem in mounting the components.

Under these circumstances, build-up multilayer wiring boards have been adopted in recent years. The build-up multilayer wiring board is formed by stacking an insulating layer composed only of resin and a conductor. As a method for forming vias, instead of conventional drilling, there are various methods such as laser method, plasma method, and photo method, and via holes of small diameter are freely arranged to achieve high density. As the interlayer connection portion, there are a blind via (Blind Via), a buried via (Buried Via: a structure in which a via is filled with a conductor), and the like, and a stacked via for forming a via on the via is possible. Has been done. Barry via holes are classified into a method of filling the via holes with plating and a method of filling the via holes with a conductive paste or the like. On the other hand, as a method for forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), etc. Is being started.

As the density and speed of multilayer wiring boards have increased, not only the density of wiring circuits and the diameter of vias have been reduced, but also thermal stress due to the difference in the coefficient of thermal expansion between the semiconductor and the semiconductor package substrate poses a problem. Becomes Therefore, it is important that the resin used for the semiconductor package substrate has a small thermal expansion coefficient. When the thickness of the insulating resin layer is 100 μm or more, the glass cloth is impregnated with the insulating resin to achieve low expansion. However, in a higher density semiconductor package substrate, the thickness of the insulating resin layer is 50 μm or less. And thin,
You cannot use glass cloth. Therefore, in order to reduce the expansion, a method of using a high heat resistant polyimide resin which originally has a low expansion coefficient or a method of filling an insulating resin with an inorganic filler has been adopted. When a high heat-resistant polyimide resin is used, a high temperature process is required at the time of ring closure from the polyamic acid to the polyimide, and since it is a resin with excellent heat resistance, it has very poor processability and high cost. is there. Further, the method of filling the insulating resin with the inorganic filler, the particle size of the inorganic filler in terms of via processability,
There is a problem that particle size distribution and packing rate are limited.

[0006]

SUMMARY OF THE INVENTION The present invention provides a reliable interlayer wiring in view of such problems of interlayer connection, wiring pattern formation and reliability in a multilayer wiring board mounting a semiconductor chip. It is an object of the present invention to provide a highly reliable multilayer wiring board capable of forming a fine wiring pattern.

[0007]

That is, according to the present invention, an interlayer insulating material layer having a film thickness of 10 μm or more and 50 μm or less and containing an inorganic filler is formed on a wiring pattern, and the interlayer insulating material layer is electrically connected to the wiring pattern. In a multilayer wiring board in which the conductor posts are formed in vias having an average diameter (R _via ) of 20 μm or more and 100 μm or less, the diameter of the via (R _via ) and the average particle diameter (R _ave ) of the inorganic filler used for the interlayer insulating material.
And 95% filler particle size (R _95% ) containing 95% of inorganic filler integrated from the smallest particle size inorganic filler,
The maximum particle size (R _max ) of the inorganic filler is 0.002 ≦
R _ave / R _via ≦ 0.03, and R _95% / R _via ≦ 0.0
It is a multilayer wiring board characterized by having a relationship of 6 and R _max / R _via ≦ 0.15.

In the multilayer wiring board of the present invention, preferably, the interlayer insulating material layer is made of an interlayer insulating material containing 40 wt% or more and 70 wt% or less of the inorganic filler, and the inorganic filler is
It is a silica filler.

According to the present invention, the film thickness is 10 μm or more and 50 μm or more on the wiring pattern or on the conductor to be the wiring pattern.
a step of forming an interlayer insulating material layer having an inorganic filler of not more than μm, and an average diameter (R _via ) of vias in the interlayer insulating material layer is 20 μm so that a part of the wiring pattern or a conductor to be the wiring pattern is exposed. In the method for manufacturing a multilayer wiring board, which includes the step of forming a via having a thickness of 100 μm or less and the step of forming a conductor post by electrolytic plating, the via has a diameter of the _via (R _via ) and an interlayer insulating material. The average particle size (R _ave ) of the inorganic filler used, the 95% filler particle size (R _95% ) containing 95% of the inorganic filler integrated from the minimum particle size of the inorganic filler, and the maximum particle size of the inorganic filler ( R _max ) is 0.002 ≦ R _ave / R
_A method of manufacturing a multilayer wiring board, characterized in that _via ≦ 0.03, R _95% / R _via ≦ 0.06, and R _max / R _via ≦ 0.15 are satisfied. Is.

The method for manufacturing a multilayer wiring board of the present invention is
Preferably, a step of forming a bonding metal material layer on at least one of the surface of the conductor post or the surface of the joined portion facing the conductor post, and at least one of the surface of the interlayer insulating material layer or the surface of the connected layer. A step of forming a metal bonding adhesive layer on the substrate, and a conductor post and a portion to be bonded which face each other via the metal bonding adhesive layer are bonded by a metal material layer for bonding, and an interlayer insulating material layer is formed. A step of adhering the layer to be connected with a metal bonding adhesive layer, and a step of removing the metal plate by etching, more preferably,
The wiring pattern and the conductor posts are formed by electrolytic plating using a metal plate as a lead for electrolytic plating, and more preferably, a resist is formed by electrolytic plating between the metal plate and the wiring pattern using the metal plate as a lead for electrolytic plating. The method includes the step of forming a metal layer.

The method for manufacturing a multilayer wiring board of the present invention is
Preferably, the joining metal material layer is made of solder or solder formed by electrolytic plating, and the conductor post is made of copper.

The method of manufacturing a multilayer wiring board according to the present invention is
Preferably, the metal-bonding adhesive layer comprises a metal-bonding adhesive containing, as essential components, a resin (A) having at least one or more phenolic hydroxyl groups and a resin (B) acting as a curing agent thereof, Preferably, the resin (A) having a phenolic hydroxyl group is a phenol novolac resin,
At least one selected from the group consisting of an alkylphenol novolac resin, a resole resin, a cresol novolac resin, and a polyvinylphenol resin, and more preferably a resin having a phenolic hydroxyl group (A).
Is contained in the metal bonding adhesive in an amount of 20 wt% or more and 80 wt% or less.

The method for manufacturing a multilayer wiring board according to the present invention is
Preferably, the interlayer insulating material layer contains 40 wt% of inorganic filler.
% Or more and 70 wt% or less, and more preferably, the inorganic filler is a silica filler.

The present invention is also a semiconductor device using any one of the above multilayer wiring boards or a multilayer wiring board obtained by the method for manufacturing any one of the above multilayer wiring boards.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The multilayer wiring board of the present invention has at least a wiring pattern, an interlayer insulating material layer, and a conductor post, and the interlayer insulating material layer contains an inorganic filler and has a film thickness of 10 μm or more and 50 μm or less. The conductor post formed on the wiring pattern and penetrating the interlayer insulating material layer to electrically connect the wiring pattern to another layer has an average diameter (R _via )
The via is formed to have a diameter of 20 μm or more and 100 μm or less. The via is composed of the diameter of the _via (R _via ), the average particle diameter (R _ave ) of the inorganic filler contained in the interlayer insulating material layer, and the inorganic filler having the minimum particle diameter. The 95% filler particle size (R _95% ) containing 95% of the inorganic filler and the maximum particle size (R _max ) of the inorganic filler are 0.002 ≦ R _ave / R _via ≦
0.03 and R _ave / R _via <R _95% / R _via ≦ 0.0
6 and R _95% / R _via <R _max / R _via ≤0.15. The inorganic filler is R _ave / R _via ≦ 0.03, and R _95% / R _via ≦
When 0.06 and R _max / R _via ≦ 0.15 are not satisfied, the shape of the side surface of the via becomes distorted, the current density during electrolytic plating is not stable, and the uppermost surface of the obtained conductor post is A bump-like protrusion is formed, and a stable conductor post shape cannot be obtained. The inorganic filler is 0.002 ≦ R _ave
If the relationship of / R _via is not satisfied, it becomes difficult to uniformly disperse the inorganic filler in the interlayer insulating material. Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto. 1 to 3 are views for explaining an example of a multilayer wiring board and a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, and FIG. 3 (n) is a cross-sectional view showing the structure of the obtained multilayer wiring board. It is a figure.

The method for manufacturing the multilayer wiring board of the present invention includes:
First, the patterned plating resist 102 is formed on the metal plate 101 (FIG. 1A). This plating resist 102 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal plate 101, selectively exposing it with a negative film or the like, and then developing it. The metal plate 101 may be made of any material as long as it is suitable for this manufacturing method.
It must be resistant to the chemical used and can be finally removed by etching. As a material of such a metal plate 101, for example,
Copper, a copper alloy, 42 alloy, nickel, etc. are mentioned.

Next, a resist metal 103 is formed by electrolytic plating using the metal plate 101 as an electrolytic plating lead (feeding electrode) (FIG. 1 (b)). By this electrolytic plating, a resist metal 103 is formed on a portion of the metal plate 101 where the plating resist 102 is not formed. The material of the resist metal 103 may be any material as long as it is suitable for this manufacturing method, but in particular, it may have resistance to a chemical solution used when finally removing the metal plate 101 by etching. is necessary. Examples of the material of the resist metal 103 include nickel, gold, tin,
Examples include silver, solder, palladium and the like. The purpose of forming the resist metal 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being corroded or corroded by the chemical solution used when etching the metal plate 101. Therefore, the wiring pattern 1 shown in FIG. 1C is used for the chemical solution used for etching the metal plate 101.
If 04 is resistant, this resist metal 10
3 is unnecessary. The resist metal 103 does not have to be the same pattern as the wiring pattern 104, and the resist metal 103 may be formed on the entire surface of the metal plate 101 before forming the plating resist 102 on the metal plate 101.

Next, the wiring pattern 104 is formed by electrolytic plating, using the metal plate 101 as an electrolytic plating lead (feeding electrode) (FIG. 1C). By this electrolytic plating, the wiring pattern 104 is formed on the portion of the metal plate 101 where the plating resist 102 is not formed. In addition to the wiring pattern formation, there is a method of forming a copper foil by pattern etching. Wiring pattern 1
As the material of 04, any material may be used as long as it is suitable for this manufacturing method, but in particular, it is necessary to have resistance to a chemical solution used when finally removing the resist metal 103 by etching. Is. In reality, since the wiring pattern 104 finally exists inside the multilayer wiring board 113, it is a good idea to select a resist metal 103 that can be etched with a chemical solution that does not corrode or corrode the wiring pattern 104. By using copper for the resist metal 103, an electrically stable wiring pattern 104 with low resistance can be obtained.

Next, the plating resist 102 is removed (FIG. 1D), and subsequently, the interlayer insulating material layer 105 having a film thickness of 10 μm or more and 50 μm or less is formed on the formed wiring pattern 104.
Are formed (FIG. 1E). The interlayer insulating material layer 105 is formed by printing resin varnish of the interlayer insulating material, curtain coating,
Examples thereof include a method of directly coating by a method such as bar coating and a method of laminating an inter-layer insulating material layer of a dry film with a supporting film prepared in advance by a method such as vacuum lamination and vacuum pressing. A protective film layer may be further formed on the dry film with a support film. Particularly, in the vacuum laminating method using a dry film with a supporting film, the wiring pattern 1 is obtained by temporarily heat-bonding the interlayer insulating material layer on the wiring pattern 104 in a vacuum and then heat-treating it in the atmosphere.
It is possible to embed the unevenness 04 and flatten it. Finally, when the support film is peeled off, the inter-layer insulating material layer 105 can obtain a very smooth surface without being affected by the unevenness of the wiring pattern 104. Moreover, by using a dry film having a known thickness in advance, the thickness of the interlayer insulating material layer can be reliably controlled.

Next, the formed film thickness is 10 μm or more and 50 μm.
The average diameter (R _via ) of the interlayer insulating material layer 105 of m or less is 2
A via 106 satisfying the relational expression is formed with a thickness of 0 μm or more and 100 μm or less (FIG. 1F). Here, the definition of the average diameter of the via is a value obtained by averaging the diameters from the top to the bottom of the via. The method of forming the via 106 may be any method as long as it is suitable for this manufacturing method, and more preferably a carbon dioxide gas laser, a UV-YAG laser, or an excimer laser method.

Next, the conductor post 107 is formed by electrolytic plating using the metal plate 101 as an electrolytic plating lead (feeding electrode) (FIG. 2 (g)). By this electrolytic plating, the conductor post 107 is formed in the portion of the interlayer insulating material layer 105 where the via 106 is formed. If the conductor post 107 is formed by electrolytic plating, the conductor post 107
The shape of the tip of the can be freely controlled. The material of the conductor post 107 may be any material as long as it is suitable for this manufacturing method, and examples thereof include copper, nickel, gold, tin, silver and palladium. Moreover,
By using copper, the conductor post 107 is stable with low resistance.
Is obtained.

Next, the surface (tip) of the conductor post 107.
The metal material layer for bonding 108 is formed on the surface (FIG. 2).
(H)). As the method of forming the bonding metal material layer 108, a method of forming by electroless plating, a method of forming the metal plate 101 as an electrolytic plating lead (feeding electrode) by electrolytic plating, and a paste containing a bonding metal material are used. There is a method of printing. In the printing method, it is necessary to accurately align the printing mask with the conductor post 107. However, in the electroless plating method or the electrolytic plating method, the bonding metal material layer 108 is formed on the surface other than the surface of the conductor post 107. Conductor post 1
It is easy to deal with 07 miniaturization and high density. In particular, the electrolytic plating method is very suitable because it has a wider variety of metals that can be plated and the chemical solution is easier to manage than the electroless plating method. As the material of the metal material for bonding, any metal can be used as long as it can be metal-bonded to the joined portion 112 shown in FIG.
For example, solder may be used. Among solders, Sn and I
n, or Sn, Ag, Cu, Zn, Bi, Pd, S
It is preferable to use a solder composed of at least two kinds of b, Pb, In and Au. More preferably, it is an environment-friendly Pb-free solder. Although FIG. 2H shows an example in which the bonding metal material layer 108 is formed on the surface of the conductor post 107, the purpose of forming the bonding metal material layer 108 is to form the conductor post 107 and the bonded portion 112. The metal material layer 108 for joining may be formed on the joined portion 112 because the joining is carried out. Of course, conductor post 1
07 and the joined portion 112 may be formed on both surfaces.

Next, the surface (tip) of the interlayer insulating material layer 105.
Then, a metal bonding adhesive layer 109 is formed (see FIG. 2).
(I)). The metal-bonding adhesive layer 109 may be formed by a method suitable for the resin to be used. The metal-bonding adhesive varnish may be directly applied by a method such as printing, curtain coating, bar coating, or a dry film with a supporting film. Examples thereof include a method of laminating the metal bonding adhesive layer 109 by a method such as vacuum laminating and vacuum pressing. In addition, in FIG. 2 (i),
Although the example in which the metal bonding adhesive layer 109 is formed on the surface of the interlayer insulating material layer 105 has been shown, the metal bonding adhesive layer 109 may be formed on the surface of the layer to be connected 111. Of course, the interlayer insulating material layer 105 may be formed on both surfaces of the layer 111 to be connected.

Next, the connection layer 1 obtained by the above steps
10 and the layer to be connected 111 are aligned (see FIG. 2).
(J)). For the alignment, a method of aligning a positioning mark previously formed on the connection layer 110 and the layer to be connected 111 with an image recognition device, alignment with a pin for alignment, or the like can be used. . Note that in FIG. 2 (j), as the layer to be connected 111,
Although an example of using a core substrate such as FR-4 used for giving a rigid property to the multilayer wiring board 113 shown in FIG. 3 (n) is shown, the wiring pattern 104 is provided on the metal plate 101 shown in FIG. 1 (d). It is also possible to use the one that is formed. Furthermore, it is also possible to use the one in the process of manufacturing the multilayer wiring board 113 shown in FIG.

Next, the connecting layer 110 and the connected layer 111.
And are stacked (FIG. 2 (k)). As a stacking method, for example, by using a vacuum press, the conductor post 107 excludes the metal bonding adhesive layer 109 and the bonding metal material layer 108.
By the above, heating and pressurization are performed until it is joined to the joined portion 112, and the conductor post 107 and the joined portion 112 are metal-joined.
Subsequently, the bonding layer 110 and the bonding target layer 11 are further heated by heating.
Glue 1 and. In addition, it is essential that the final heating temperature is equal to or higher than the melting point of the bonding metal material.

Next, the metal plate 101 is removed by etching (FIG. 3 (l)). Metal plate 101 and wiring pattern 1
04 and the resist metal 103 is formed between them, and the resist metal 103 has resistance to a chemical solution used for removing the metal plate 101 by etching, so that the metal plate 101 is etched. However, the resist metal 103 is not corroded or corroded, and as a result, the wiring pattern 104 is not corroded or corroded. Metal plate 1
When the material of 01 is copper and the material of the resist metal is nickel, tin, or solder, a commercially available ammonia-based etching solution can be used. When the material of the metal plate 101 is copper and the material of the resist metal is gold, most etching solutions including ferric chloride solution and cupric chloride solution can be used.

Next, the resist metal 103 is removed by etching (FIG. 3 (m)). The wiring pattern 104 is
Since the resist pattern 103 has resistance to a chemical solution used for removing the resist metal 103 by etching, the wiring pattern 1
04 is not corroded or corroded. Therefore, by removing the resist metal 103, the wiring pattern 1
04 is exposed. The resist metal 103 may be left without being removed, if necessary. When the material of the wiring pattern 104 is copper and the material of the resist metal is nickel, tin, or solder, a commercially available solder / nickel release agent (for example, Pewtax: trade name manufactured by Mitsubishi Gas Chemical Co., Inc.) can be used. The material of the wiring pattern 104 is copper, and the resist metal 1
When the material of 03 is gold, it is difficult to etch the resist metal 103 without eroding / corroding the wiring pattern 104. In this case, the resist metal 10
The step of etching 3 may be omitted.

Finally, the above process, that is, FIG.
The multilayer wiring board 113 is obtained by repeating the process of FIG. 3 (m) (FIG. 3 (n)). That is, the connection layer is formed on both sides of the core substrate by performing the laminating step shown in FIG. 2 (j) by using a layer in the process of manufacturing the multilayer wiring board 113 shown in FIG. 3 (m) as a layer to be connected, and further, The multilayer wiring board 113 can be obtained by carrying out the stacking step shown in FIG. 2 (j) using the thus obtained product as the layer to be connected, and further repeating these steps. FIG. 3 (n) shows a multilayer wiring board 113 in which two connecting layers are laminated on each side of the core substrate 116, and solder resists 115 are formed on both surfaces of the multilayer wiring board 113. In the solder resist 115, the inner pad 114a and the outer pad 114b are opened.

Through the above steps, the wiring pattern 1 of each layer
04 and the conductor post 107 are metal-bonded by the metal material layer for bonding 108 to manufacture a multilayer wiring board in which each layer is bonded.

The semiconductor chip 2 is formed on the inner pad 114a side of the multilayer wiring board 113 obtained by the above process.
02 is mounted, and solder balls are mounted on the outer pad 114b side, whereby the semiconductor device 201 can be obtained (FIG. 4).

The metal bonding adhesive used in the present invention is preferably an adhesive having a surface cleaning function and high insulation reliability. The surface cleaning function is, for example, a function of removing an oxide film existing on the surface of the bonding metal material layer or the surface of the metal to be connected, and a function of reducing the oxide film. The surface cleaning function of the metal bonding adhesive sufficiently enhances the wettability with the surface for connecting with the bonding metal material layer. for that reason,
In order to clean the metal surface, the metal bonding adhesive must be in contact with the bonding metal material layer and the surface for connection. By cleaning both surfaces, the bonding metal material layer has a force to spread and wet the surfaces to be bonded, and the wetting and spreading force of the bonding metal material layer causes the metal bonding at the metal bonding portion. The adhesive is eliminated.
As a result, in the metal bonding using the metal bonding adhesive, the resin residue is less likely to occur and the electrical connection reliability thereof is high.

The metal bonding adhesive used in the present invention is a resin (A) having at least one phenolic hydroxyl group.
And a resin (B) that acts as a curing agent thereof are preferably contained as essential components, and the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group has a surface cleaning function and thus has a metal material layer for bonding. It also removes stains such as oxides on the metal surface or reduces oxides and acts as a flux for metal bonding. Furthermore, since the resin (B) acting as the curing agent can obtain a good cured product, it is not necessary to wash and remove after metal bonding, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and the bonding strength, Enables highly reliable metal bonding.

Used in the present invention for a metal bonding adhesive,
The resin (A) having at least one or more phenolic hydroxyl groups is preferably selected from a phenol novolac resin, an alkylphenol novolac resin, a resole resin, a cresol novolac resin, and a polyvinylphenol resin, and at least one of them is used. be able to.

As the resin (A) having a phenolic hydroxyl group and used as a curing agent (B) used in the metal adhesive in the present invention, an epoxy resin, an isocyanate resin or the like is used. Specifically, both are based on bisphenol-based, phenol novolak-based, alkylphenol novolak-based, biphenol-based, phenol-based resins such as naphthol-based or resorcinol-based, and skeletons such as aliphatic, cycloaliphatic and unsaturated aliphatic. Examples thereof include modified epoxy compounds and isocyanate compounds.

Used in the present invention for a metal bonding adhesive,
The resin (A) having a phenolic hydroxyl group has a preferable lower limit of 20 wt% and a preferable upper limit of 80 wt% in the adhesive, and a more preferable upper limit is
It is 60 wt%. If it is less than the lower limit, the action of cleaning the metal surface may be reduced. On the other hand, if the amount exceeds the upper limit, there is a risk that a sufficient cured product may not be obtained, in which case the bonding strength and reliability will decrease. on the other hand,
The resin (B) acting as a curing agent is added to the adhesive in an amount of 20
It is preferable that the content is not less than wt% and not more than 80 wt%.
Further, a colorant, a curing catalyst, an inorganic filler, various coupling agents, a solvent, etc. may be added to the resin used for the metal bonding adhesive.

Examples of the interlayer insulating material used in the present invention include a resin composition obtained by mixing an inorganic filler as an essential component with a thermoplastic resin and / or a thermosetting resin. As the inorganic filler, the average diameter of vias (R
_via ), the average particle size (R _ave ) of the inorganic filler used for the interlayer insulating material, and the minimum particle size of the inorganic filler, and the result is 9
95% filler particle size (R
_95% ) and the maximum particle size (R _max ) of the inorganic filler can be used as long as they satisfy the above relationship, and specific examples thereof include spherical synthetic silica, aluminum borate, spherical synthetic alumina and the like. These may be used alone or in combination of two or more. More preferred is spherical synthetic silica having a low dielectric constant and a low dielectric loss tangent. The preferred content of the inorganic filler is 40 wt% or more and 70 wt
% Or less. If it is less than 40 wt%, it may not be possible to achieve low expansion, and if it is more than 70 wt%, the insulating properties may be deteriorated. As the thermoplastic resin, resins such as polyamide, polyimide, polyamideimide, polyetherimide, polyesterimide, polyetheretherketone, polyphenylene sulfide, polyquinoline, polynorbornene, polybenzoxazole and polybenzimidazole can be used.
As the thermosetting resin, resins such as epoxy, phenol, bismaleimide, bismaleimide triazine, triazole, cyanate, isocyanate, benzocyclobutene, etc. can be used. These resins may be used alone or in combination of two or more. Further, a leveling agent, a coupling agent, a defoaming agent, a curing catalyst, etc. may be added.

The maximum features of the multilayer wiring board and the method for manufacturing the multilayer wiring board according to the present invention are shown below. (1) It is possible to form fine vias of 20 μm or more and 100 μm or less, and it is possible to form an interlayer insulating material layer having a low expansion coefficient . (2) The wiring pattern 104 and the body post can be formed by electrolytic plating. (3) Since the metal plate 101 to be finally removed is used as an electrolytic plating lead, a special electrolytic plating lead is provided in the wiring pattern 104 or the wiring pattern 104 is provided.
It is not necessary to form a lead for electrolytic plating by electroless plating or sputtering after forming.

[0038]

EXAMPLES Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited thereto.

In order to confirm the effectiveness of the multilayer wiring board of the present invention, the multilayer wiring boards of Examples 1 to 13 shown below were produced,
The surface shape of the conductor post was observed, the cross section of the metal joint was observed, the temperature cycle test and the insulation reliability test were conducted, and the evaluation results are summarized in Table 1.

[Example 1] m, p-cresol novolac resin (PAS-1, manufactured by Nippon Kayaku Co., Ltd., OH equivalent 120) 1
00g and bisphenol F type epoxy resin (Nippon Kayaku
RE-404S, epoxy equivalent 165) 140g
Was dissolved in 60 g of cyclohexanone, and triphenylphosphine as a curing catalyst (manufactured by Kitako Chemical Co., Ltd.)
0.2 g was added to produce a metal bonding adhesive varnish.

Next, phenol novolac polycyanate resin (manufactured by Lonza Co., Ltd., trade name: Primaset)
PT-30, cyanate group trimerization rate 0%) 100 g, N
-Methylpyrrolidone 121 g, spherical synthetic silica filler SE2060 (manufactured by Admatechs Co., Ltd., average particle size R)
_ave 0.6 μm, 95% filler particle size R _95% 1.1 μm,
A silica filler solution in which 225 g of a maximum particle size R _{max of} 6.0 μm) is dispersed and mixed by ultrasonic waves, 50 g of a silicon-modified polyimide having a glass transition temperature Tg of 250 ° C., cobalt (III) acetylacetonate (Co (AA)) (sum) Koujunyaku Kogyo Co., Ltd. (0.02 g) and NMP (200 g) were mixed and stirred with a rotation / revolution mixer to dissolve to prepare an interlayer insulating material varnish.

Rolled copper plate (metal plate 101) having a surface of 150 μm and roughened (manufactured by Furukawa Electric Co., Ltd., EFTEC-6).
4T: product name), roll laminated with dry film resist (AQ-2058: product name, manufactured by Asahi Kasei),
Exposure and development were performed using a predetermined negative film to form a plating resist (plating resist 102) necessary for forming the wiring pattern 104. Next, using the rolled copper plate as a lead for electrolytic plating, nickel (resist metal 103) was formed by electrolytic plating, and further electrolytic copper plating was performed to form a wiring pattern (wiring pattern 104). Wiring pattern: line width / line spacing / thickness = 20 μm / 20 μm
/ 10 μm. The interlayer insulating material varnish obtained above is applied to a polyester (PET) film, and then at 80 ° C. for 10 minutes.
Min, and dried at 130 ° C. for 10 minutes to form an interlayer insulating material layer having a thickness of 25 μm. An interlayer insulating material layer with a PET film was formed by vacuum lamination while embedding irregularities in a wiring pattern, and the PET film was peeled off to form an interlayer insulating material layer (interlayer insulating material layer 105) having a thickness of 25 μm. After forming the interlayer insulating material layer, in a nitrogen atmosphere, at 150 ° C. for 30 minutes, 2
It was cured by heat treatment at 00 ° C. for 60 minutes and at 250 ° C. for 180 minutes.

Next, a via (via 106) having an average diameter of 45 μm was formed by a UV-YAG laser. Subsequently, the rolled copper plate was used as a lead for electrolytic plating, and the via was filled with copper by electrolytic copper plating to form a copper post (conductor post 107). The surface shape of the formed copper post was observed by an electron microscope (SEM) and is shown in Table 1. Next, using the rolled copper plate as a lead for electrolytic plating, Sn—Pb eutectic solder (bonding metal material layer 10
8) was formed by electrolytic plating. Next, the metal-bonding adhesive varnish obtained above was applied to the surface of the interlayer insulating material layer, that is, the surface on which the Sn-Pb eutectic solder was formed, by bar coating, and then dried at 80 ° C for 20 minutes to obtain 10 µm. A thick metal bonding adhesive layer (metal bonding adhesive layer 109) was formed. The connection layer (connection layer 110) could be obtained by the steps up to this point.

On the other hand, as the core substrate, a glass epoxy resin copper-clad laminate (made by Sumitomo Bakelite) corresponding to FR-5 on which a 12 μm thick copper foil is formed is used, and the copper foil is etched to form wiring patterns and pads (covered). The joined portion 112) was formed, and the connected layer (connected layer 111) could be obtained. Next, the connection layer obtained by the above-mentioned process and the positioning mark formed in advance on the layer to be connected were read by an image recognition device, both were aligned, and temporarily pressure-bonded at a temperature of 100 ° C. Furthermore, the above-mentioned alignment / temporary pressure bonding was performed again, and it was possible to obtain a product in which the connection layers were temporarily pressure bonded on both surfaces of the layer to be connected. This was heated and pressed at a temperature of 220 ° C. by a press, the copper post penetrated the metal bonding adhesive layer and was solder-bonded to the pad, and the connection layer was bonded to both surfaces of the layer to be connected. Next, post-curing was performed at 220 ° C. for 2 hours to cure the metal bonding adhesive layer. Next, the rolled copper plate is etched and removed using an ammonia-based etching solution, and solder / nickel release agent (Pheta manufactured by Mitsubishi Gas Chemical Co., Inc.
x: Nickel was used to remove the nickel by etching. Finally, solder resist (solder resist 1
15) was formed to obtain a multilayer wiring board (multilayer wiring board 113).

The obtained multilayer wiring board was designed for the temperature cycle test so that 60 metal joints were connected in series on both sides. Further, on the multilayer wiring board, a comb-shaped wiring pattern having a line width / line spacing = 20 μm / 20 μm is simultaneously formed for an insulation resistance test.

The cross section of the metal-bonded portion of the obtained multilayer wiring board was observed by an electron microscope (SEM) to evaluate the metal-bonded state.

After confirming the continuity of the obtained multilayer wiring board,
A temperature cycle test was conducted in which one cycle consisted of 10 minutes at −55 ° C. and 10 minutes at 125 ° C. The number of samples was 10. The results of the number of disconnection failures after 1000 cycles of the temperature cycle test are shown together in Table 1.

After measuring the initial insulation resistance of the obtained multilayer wiring board, a DC voltage of 5.5 V was applied in an atmosphere of 85 ° C./85% relative humidity, and the insulation resistance after 1000 hours was measured. The applied voltage at the time of measurement was 100 V for 1 minute, and the initial insulation resistance and the post-treatment insulation resistance are summarized in Table 1.

[Example 2] SE2 spherical synthetic silica filler SE2 used in the production of the interlayer insulating material varnish in Example 1
060 (manufactured by Admatechs Co., Ltd., average particle size R _ave 0.
6 μm, 95% filler particle size R _95% 1.1 μm, maximum particle size R _max 6.0 μm) Instead of 225 g, a multilayer wiring board was prepared in the same manner as in Example 1 of the multilayer wiring board. Was obtained and evaluated.

Example 3 The spherical synthetic silica filler SE2 used in the production of the interlayer insulating material varnish in Example 1
060 (manufactured by Admatechs Co., Ltd., average particle size R _ave 0.
6 μm, 95% filler particle size R _95% 1.1 μm, maximum particle size R _max 6.0 μm) Instead of 225 g, a multilayer wiring board was prepared in the same manner as in Example 1 of the multilayer wiring board. Was obtained and evaluated.

Example 4 A spherical synthetic silica filler SE2 used in the production of the interlayer insulating material varnish in Example 1
060 (manufactured by Admatechs Co., Ltd., average particle size R _ave 0.
6 [mu] m, 95% filler particle size R _95% 1.1 .mu.m, in place of the maximum particle diameter R _max 6.0 .mu.m) 225 g, a spherical synthetic silica filler SE3060 (Admatechs Co., Ltd., average particle diameter R _{av e} 0.9 .mu.m , 95% filler particle size R _95% 2.
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 of the multilayer wiring board, except that 100 g of 3 μm and maximum particle size R _{max of} 6.0 μm) was used.

[Example 5] In Example 1, 100 g of bisphenol A type novolak resin (LF4781, OH equivalent 120 manufactured by Dainippon Ink and Chemicals, Inc.) was used instead of 100 g of m, p-cresol novolak resin. A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 except for the above.

Example 6 In Example 1, instead of 100 g of m, p-cresol novolac resin, polyvinylphenol resin (Marukalinker manufactured by Maruzen Petrochemical Co., Ltd.) was used.
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 except that 100 g of M and OH equivalent 120) was used.

[Example 7] Phenol novolac resin (PR-51470 manufactured by Sumitomo Dures Co., OH equivalent 105)
100 g and diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., epoxy equivalent 22
0) 210 g of cyclohexanone was dissolved in 80 g of cyclohexanone, and 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-P manufactured by Shikoku Chemicals Co., Ltd.) was used as a curing catalyst.
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 except that 0.3 g of W) was added to produce a metal-bonding adhesive varnish.

[Example 8] m, p-cresol novolac resin (PAS-1, OH equivalent 120 manufactured by Nippon Kayaku Co., Ltd.) 1
00 g and 140 g of bisphenol F type epoxy resin (RE-404S manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent 165) as compound (B) were dissolved in 60 g of cyclohexanone to prepare a metal bonding adhesive varnish. A multilayer wiring board was obtained and evaluated in the same manner as in Example 1.

[Example 9] Phenol novolac resin (PR-HF-3, OH equivalent 106 manufactured by Sumitomo Durez Co., Ltd.) 1
06 g, diallyl bisphenol A type epoxy resin (RE-810NM manufactured by Nippon Kayaku Co., epoxy equivalent 22
0) 35 g and 210 g of dicyclopentadiene type novolak epoxy resin (Nippon Kayaku Co., Ltd. XD-1000L, epoxy equivalent 250) were added to methyl ethyl ketone 100.
except that it was dissolved in g to produce a metal bonding adhesive varnish.
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1.

[Example 10] Phenol novolak resin (PR-53647 manufactured by Sumitomo Dures Co., OH equivalent 10
6) 106 g, diallyl bisphenol A type epoxy resin (Nippon Kayaku Co., Ltd. RE-810NM, epoxy equivalent 220) 35 g and dicyclopentadiene type novolak epoxy resin (Nippon Kayaku Co., Ltd. XD-1000L, epoxy equivalent) 250) 210 g of methyl ethyl ketone 1
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 except that it was dissolved in 00 g to prepare a metal bonding adhesive varnish.

[Example 11] Bisphenol A type novolac resin (LF4871 manufactured by Sumitomo Durez Co., OH equivalent 1
20) 120 g, diallyl bisphenol A type epoxy resin (Nippon Kayaku Co., Ltd. RE-810NM, epoxy equivalent 220) 35 g and dicyclopentadiene type novolac epoxy resin (Nippon Kayaku Co., Ltd. XD-1000L,
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 except that 210 g of an epoxy equivalent of 250) was dissolved in 100 g of methyl ethyl ketone to prepare a metal bonding adhesive varnish.

[Example 12] In Example 10, a phenol novolac resin (PR-536 manufactured by Sumitomo Dures Co., Ltd.) was used.
47, OH equivalent 106), instead of 106 g, phenol novolac resin (PR-5364 manufactured by Sumitomo Dures Co., Ltd.)
Example 7, except that 62 g of OH equivalent 106) was used.
A multilayer wiring board was obtained and evaluated in the same manner as 0.

Example 13 In Example 10, a phenol novolac resin (PR-536 manufactured by Sumitomo Dures Co., Ltd.) was used.
47, OH equivalent 106), instead of 106 g, phenol novolac resin (PR-5364 manufactured by Sumitomo Dures Co., Ltd.)
7, multilayer OH was obtained and evaluated in the same manner as in Example 10 except that 200 g of OH equivalent 106) was used.

[Comparative Example 1] In Example 1, the interlayer insulating material
SE2 spherical synthetic silica filler used in the production of varnish
060 (Admatex Co., Ltd., average particle size R_ave0.
6 μm, 95% filler particle size R_95%1.1 μm, maximum grain
Diameter R_max6.0 μm) Instead of 225 g, spherical synthetic silicone
Kaffir SE5060 (manufactured by Admatechs Co., Ltd., flat
Uniform particle size R _ave1.6 μm, 95% filler particle size R_95%4.
4 μm, maximum particle size R_max6.0 g (6.0 μm) was used.
Except for the above, the multilayer wiring board is the same as in Example 1 of the multilayer wiring board.
Was obtained and evaluated.

[Comparative Example 2] The spherical synthetic silica filler SE2 used in the production of the interlayer insulating material varnish in Example 1
060 (manufactured by Admatechs Co., Ltd., average particle size R _ave 0.
6 [mu] m, 95% filler particle size R _95% 1.1 .mu.m, in place of the maximum particle diameter R _max 6.0 .mu.m) 225 g, a spherical synthetic silica filler SE6060 (Admatechs Co., Ltd., average particle diameter R _{av e} 2.1 .mu.m , 95% filler particle size R _95% 5.
A multilayer wiring board was obtained and evaluated in the same manner as in Example 1 of the multilayer wiring board, except that 225 g of 0 μm and maximum particle diameter R _{max of} 6.0 μm) was used.

[0063]

[Table 1]

As can be seen from the evaluation results shown in Table 1,
The multilayer wiring board of the present invention and the multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board of the present invention can be reliably metal-bonded, and in the temperature cycle test, no disconnection failure occurs, and the insulation resistance is also obtained in the insulation resistance test. Did not fall. In Comparative Examples 1 and 2, it was not possible to obtain a multilayer wiring board because the shape of the copper posts was distorted. Therefore, the effects of the multilayer wiring board and the manufacturing method thereof according to the present invention are obvious.

[0065]

According to the present invention, it is possible to provide a multilayer wiring board having stable conductor connection, reliable interlayer connection, and high interlayer insulation reliability other than the joint portion, a method for manufacturing the same, and a semiconductor device. be able to.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 1).

FIG. 3 is a cross-sectional view showing the method of manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 2).

FIG. 4 is a sectional view showing a semiconductor device manufactured by using the multilayer wiring board according to the embodiment of the present invention.

[Explanation of Codes] 101 Metal Plate 102 Plating Resist 103 Resist Metal 104 Wiring Pattern 105 Interlayer Insulating Material Layer 106 Via 107 Conductor Post 108 Bonding Metal Material Layer 109, 109 ′ Metal Bonding Adhesive Layers 110, 110a, 110b, 110c, 110d
Connection layers 111 and 111a Connected layers 112 Joined parts 113 and 112a Multilayer wiring board 114a Inner pad 114b Outer pad 115 Solder resist 116 Core substrate 201 Semiconductor device 202 Semiconductor chip 203 Bump 204 Underfill 205 Solder ball

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5E346 AA12 CC08 DD24 FF06 FF07                       FF14 HH07

Claims (15)

[Claims] 1. A film thickness of 10 μm or more on a wiring pattern 5
An interlayer insulating material layer having an inorganic filler of 0 μm or less is formed, and a conductor post electrically connected to the wiring pattern in the interlayer insulating material layer has an average diameter (R _via ) of 20 μm or more and 100 μm or less.
In a multilayer wiring board formed in a via having a diameter of m or less, the diameter of the via (R _via ), the average particle size (R _ave ) of the inorganic filler used for the interlayer insulating material, and the minimum particle size of the inorganic filler are integrated to be 95. % 95% filler particle size (R _95% ) containing 100% of the inorganic filler and the maximum particle size (R _max ) of the inorganic filler are 0.002 ≦ R _ave / R _via ≦ 0.03, and R
_95% / R _via ≤0.06 and R _max / R _via ≤0.1
A multilayer wiring board having a relationship of 5. 2. The interlayer insulating material layer is 40 wt% or more and 70 w
The multilayer wiring board according to claim 1, comprising an interlayer insulating material containing t% or less of an inorganic filler. 3. The multilayer wiring board according to claim 1, wherein the inorganic filler is a silica filler. 4. A step of forming an interlayer insulating material layer having an inorganic filler and having a film thickness of 10 μm or more and 50 μm or less on a wiring pattern or a conductor to be the wiring pattern, and the wiring pattern or the conductor to be the wiring pattern. The average diameter of the vias (R
a _{step Via)} to form the following via 100μm above 20 [mu] m, a step of forming by electrolytic plating conductor posts, the method for manufacturing a multilayer wiring board comprising, vias, a via having a diameter (R _Via), The average particle size (R _ave ) of the inorganic filler used for the interlayer insulating material and the inorganic filler having the minimum particle size are integrated to contain 95% of the inorganic filler 95.
% Filler particle size (R _95% ) and maximum particle size of inorganic filler (R _max ) are 0.002 ≦ R _ave / R _via ≦ 0.0
3, and R _95% / R _via ≤0.06, and R _max / R
_A method of manufacturing a multilayer wiring board, characterized in that it is formed so as to satisfy _via ≦ 0.15. 5. A step of forming a bonding metal material layer on at least one of a surface of a conductor post or a surface of a joined portion facing the conductor post, and a step of forming a surface of an interlayer insulating material layer or a surface of a connected layer. A step of forming a metal bonding adhesive layer on at least one side, and a conductor post and a bonded portion facing each other with the metal bonding adhesive layer interposed therebetween are bonded by a metal material layer for bonding, and an interlayer insulating material is also used. The method for manufacturing a multilayer wiring board according to claim 4, further comprising a step of adhering the layer and the layer to be connected with a metal bonding adhesive layer, and a step of removing the metal plate by etching. 6. The method for manufacturing a multilayer wiring board according to claim 4, wherein the wiring pattern and the conductor posts are formed by electrolytic plating using a metal plate as a lead for electrolytic plating. 7. The multilayer wiring board according to claim 5, further comprising the step of forming a resist metal layer by electrolytic plating between the metal plate and the wiring pattern using the metal plate as a lead for electrolytic plating. Manufacturing method. 8. The metal material layer for joining is made of solder or solder formed by electrolytic plating.
A method for manufacturing a multilayer wiring board according to any one of 1. 9. The method for manufacturing a multilayer wiring board according to claim 4, wherein the conductor post is made of copper. 10. The metal-bonding adhesive layer comprises a metal-bonding adhesive containing, as essential components, a resin (A) having at least one or more phenolic hydroxyl groups and a resin (B) acting as a curing agent for the resin (A). A method for manufacturing a multilayer wiring board according to any one of claims 5 to 9. 11. The resin (A) having a phenolic hydroxyl group is at least one selected from the group consisting of a phenol novolac resin, an alkylphenol novolac resin, a resole resin, a cresol novolac resin, and a polyvinyl phenol resin. A method for manufacturing the multilayer wiring board described. 12. The resin (A) having a phenolic hydroxyl group is contained in the metal bonding adhesive in an amount of 20 wt% or more and 80 w or more.
The method for manufacturing a multilayer wiring board according to claim 10, wherein the content is t% or less. 13. The interlayer insulating material layer comprises an inorganic filler of 40
The method for manufacturing a multilayer wiring board according to any one of claims 4 to 12, which comprises an interlayer insulating material which is contained in an amount of not less than wt% and not more than 70 wt%. 14. The method for producing a multilayer wiring board according to claim 4, wherein the inorganic filler is a silica filler. 15. A multilayer wiring board according to any one of claims 1 to 3 or a multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of claims 4 to 14 is used. A semiconductor device characterized in that