JP5106513B2 - Thin film magnetic memory device - Google Patents

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a thin film magnetic memory device including a memory cell having a magnetic tunnel junction (MTJ).

  In recent years, MRAM (Magnetic Random Access Memory) devices have attracted attention as a new generation of nonvolatile storage devices. An MRAM device is a non-volatile memory device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and can randomly access each of the thin film magnetic bodies. In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic body using a magnetic tunnel junction as a memory cell. (For example, refer nonpatent literature 1.).

  A memory cell having a magnetic tunnel junction (hereinafter also referred to as “MTJ memory cell”) can be configured with one MTJ element and one access element (for example, a transistor), which is advantageous for high integration. It is. The MTJ element has a magnetic layer that can be magnetized in the direction according to the applied magnetic field, and the MTJ memory cell has an electrical resistance (junction) in the MTJ element according to the magnetization direction of the magnetic layer. Data storage is executed by utilizing the characteristic that resistance changes.

  In order to read the storage data of the MTJ memory cell, it is necessary to detect an electric resistance difference corresponding to the storage data level. Specifically, data reading is executed based on the passing current of the MTJ memory cell that changes according to the electrical resistance (that is, stored data).

  Data writing to the MTJ memory cell is performed by supplying data write currents to two write lines for generating a data write magnetic field. A data write magnetic field is generated from each of the two write lines in directions along the easy axis and the hard axis of the MTJ memory cell. At the time of data writing, the MTJ memory cell is rotated by rotating the magnetization direction of the MTJ memory cell by applying the data write magnetic field in the hard axis direction and applying the data write magnetic field in the direction along the easy magnetization axis. Then, it is magnetized in the direction according to the write data (magnetization easy axis direction).

Roy Scheuerline and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129.

  However, the data write current in the MRAM device is generally on the order of several milliamperes to several tens of milliamperes in order to generate a magnetic field having a predetermined strength necessary for data writing. For this reason, it is necessary to sufficiently secure the current drive capability of the driver transistor that supplies the data write current. As a result, there is a possibility that a problem peculiar to the MRAM device as described below occurs.

  (1) When a driver transistor is enlarged to ensure current drive capability and does not fit within the write line arrangement pitch, the MTJ memory cell size increases and the chip area increases.

  (2) The current density of the write line is increased, and the operation reliability is impaired due to the occurrence of electromigration or the like.

  (3) The wiring resistance included in the data write current path, the contacts connecting the wiring layers, and the like increase the electrical resistance of the path, making it difficult to supply a sufficient data write current.

  In particular, in recent years, memory devices have been actively mounted on portable devices on the premise of battery driving, and low voltage operation is strongly demanded from the viewpoint of low power consumption. In particular, during such a low voltage operation, the problem (3) may become significant. That is, even under a low voltage operation, a configuration for ensuring a sufficient level of data write current necessary for data writing is required.

  The present invention has been made to solve such problems, and the object of the present invention is to supply a data write current stably and efficiently without increasing the memory cell size. Another object of the present invention is to provide a thin film magnetic memory device having such a structure.

  A thin film magnetic memory device according to the present invention includes a plurality of magnetic memory cells each having a magnetic layer that is magnetized in a direction according to stored data, and data writing that generates a data write magnetic field that magnetizes the magnetic layer. A current drive circuit for coupling a write line between a first voltage and a second voltage for supplying a data write current at the time of data writing; A field effect transistor including a field effect transistor electrically coupled between one of the first and second voltages and the write line has a gate length direction along the same direction as the write line Are arranged as follows.

  A thin film magnetic memory device according to another configuration of the present invention includes a plurality of magnetic memory cells each having a magnetic layer magnetized in a direction corresponding to stored data, a power supply wiring for supplying a predetermined voltage, and a magnetic layer And a write line for flowing a data write current for generating a data write magnetic field for magnetizing the data, and the write line is electrically coupled with the power supply wiring at least when the data write current is passed, The embedded wiring corresponds to a region where a plurality of memory cells are arranged, and is provided in at least a part of the first portion having the first cross-sectional area and the first portion and the power supply wiring. And a second portion having a second cross-sectional area larger than the cross-sectional area.

  A thin film magnetic memory device according to still another configuration of the present invention includes a plurality of magnetic memory cells each having a magnetic layer that is magnetized in a direction according to stored data, a power supply pad that receives a predetermined voltage, and a vertical A power supply wiring electrically coupled to the power supply pad through a contact provided in a direction, and a first write line formed in the same wiring layer as the power supply wiring along a direction intersecting the power supply wiring. The first write line is coupled with the power supply wiring in the same wiring layer, and is supplied with a first data write current for generating a data write magnetic field for magnetizing the magnetic layer.

  A thin film magnetic memory device according to still another configuration of the present invention includes a memory cell array in which a plurality of magnetic memory cells each having a magnetic layer magnetized in a direction according to stored data are arranged, and a plurality of magnetic memory cells And a plurality of bit lines provided corresponding to the predetermined sections, and at the time of data writing, a data write current for generating a data write magnetic field for magnetizing the magnetic layer is supplied to at least one of the plurality of bit lines. Therefore, a plurality of first and second bit line drivers provided corresponding to both ends of the plurality of bit lines, and a selected memory among the plurality of memory cells along a direction intersecting the plurality of bit lines A read data line provided for transmitting read data from the cell, one of a plurality of bit lines connected to the selected memory cell and a read data line at the time of data reading; A read select gate for connecting, read select gates, the memory cell array, one being disposed outside the plurality of first and second bit line driver.

  A thin film magnetic memory device according to still another configuration of the present invention includes a memory cell array in which a plurality of magnetic memory cells each having a magnetic layer magnetized in a direction according to stored data are arranged, and a plurality of magnetic memory cells And a plurality of data lines for supplying a data write current for generating a data write magnetic field for magnetizing the magnetic layer during data writing, and a plurality of data lines. A plurality of current drive circuits for supplying a data write current to a corresponding one of a plurality of data lines, and a predetermined voltage and a plurality of current drives. A power supply wiring provided along a direction intersecting with a plurality of data lines is provided between the circuit and a circuit element or a wiring is arranged in an intermediate region between the power supply wiring and the memory cell array. .

  A thin film magnetic memory device according to another configuration of the present invention includes a memory cell array in which a plurality of magnetic memory cells each having a magnetic material layer magnetized in a direction according to stored data are arranged, and a plurality of magnetic memory cells A plurality of bit lines provided corresponding to each predetermined section and a data write current for generating a data write magnetic field for magnetizing the magnetic layer at the time of data writing to at least one of the plurality of bit lines Provided to transmit read data along a direction intersecting with the plurality of bit lines, and a plurality of first and second bit line drivers provided corresponding to both ends of the plurality of bit lines. Read for connecting read data line to read data line and one of a plurality of bit lines connected to a selected memory cell and a read data line during data reading A-option gates, read select gate and the read data lines are disposed in a region corresponding to the central portion of the plurality of bit lines.

  A thin film magnetic memory device according to still another configuration of the present invention includes a plurality of magnetic memory cells each having a magnetic layer that is magnetized in a direction according to stored data. A plurality of bit lines, each of which is divided into a second memory block and provided corresponding to a predetermined section of a plurality of magnetic memory cells in each of the first and second memory blocks; In each of the two memory blocks, at the time of data writing, a data write current for generating a data write magnetic field for magnetizing the magnetic layer is supplied to the bit lines so as to correspond to both ends of the plurality of bit lines. A plurality of memory cells along a direction intersecting with the plurality of bit lines in common to the plurality of first and second bit line drivers and the first and second memory blocks. A read data line provided for transmitting read data from the selected memory cell and the first and second memory blocks are provided independently of each other and selected from a plurality of bit lines during data reading. One read cell connected to the memory cell and a read data line for connecting the read data line are provided, and the read select gate and the read data line are arranged in a region between the first and second memory blocks. .

  According to the present invention, in the thin film magnetic memory device, the field effect transistor (driver transistor) for supplying the data write current has the same gate length direction as the write line to which the data write current is supplied. By disposing the memory cells along the direction, it is possible to avoid hindering the integrated arrangement of the memory cells due to the arrangement pitch of the driver transistors.

  Further, in the thin film magnetic memory device, by providing a strengthened portion having a cross-sectional area larger than the steady portion between the write line and the power supply wire, the metal at the time of supplying the data write current at the end of the write line Even if the wiring width is reduced due to the movement of atoms, the current density is rapidly increased in this portion, and the risk of affecting the operation reliability can be suppressed.

  Further, in the thin film magnetic memory device, the power supply wiring and the write line are coupled by the same wiring layer, and the power supply pad and the power supply wiring are directly connected by the contact without extending over the plurality of wiring layers. The electrical resistance of the write current path can be reduced. As a result, a predetermined data write current can be easily secured even when the power supply voltage is set to a relatively low voltage.

  Alternatively, in the thin film magnetic memory device, the bit line driver and the read selection gate provided corresponding to the bit line are arranged outside the memory cell array so that the current of the data write current is increased. The electrical resistance can be reduced by shortening the path. As a result, it becomes easy to secure a predetermined level for the data write current flowing through the bit line.

  Further, in the thin film magnetic memory device, a power supply line at the time of data writing is provided by arranging a circuit element or a wiring group in an intermediate region between the power supply line for supplying a data write current to the data line and the memory cell array. Can reduce magnetic noise from the memory cell array to the memory cell array.

  Alternatively, in the thin film magnetic memory device, by providing the read selection gate corresponding to the intermediate node of the bit line, the data read current path can be shortened to reduce the electrical resistance. As a result, data reading speed can be increased.

  Further, in the thin film magnetic memory device, in an array configuration divided into a plurality of memory blocks, by arranging a read selection gate and a data read circuit shared between the memory blocks between adjacent memory blocks, a circuit area can be obtained. Thus, the chip size can be reduced.

It is a figure which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. It is a conceptual diagram explaining the structure and data storage principle of an MTJ memory cell. It is a conceptual diagram which shows the relationship between the data write current of an MTJ memory cell, and the magnetization direction of a tunnel magnetoresistive element. It is a conceptual diagram which shows the 1st structural example according to Embodiment 1 of the data write-current supply circuit system with respect to a write digit line. 6 is a conceptual diagram showing a design example of a write digit line according to the first embodiment. FIG. It is a conceptual diagram which shows the 2nd structural example according to Embodiment 1 of the data write-current supply circuit system with respect to a write digit line. FIG. 11 is a conceptual diagram showing a third configuration example according to the first embodiment of a data write current supply circuit system for a write digit line. FIG. 10 is a conceptual diagram showing a fourth configuration example according to the first embodiment of a data write current supply circuit system for a write digit line. FIG. 9 is a cross-sectional view showing an MTJ memory cell structure corresponding to FIG. 8. FIG. 11 is a conceptual diagram showing a first configuration example according to a modification of the first embodiment of the data write current supply circuit system for the bit line. FIG. 11 is a conceptual diagram showing a second configuration example according to the modification of the first embodiment of the data write current supply circuit system for the bit line. It is a figure which shows the 1st example of arrangement | positioning according to Embodiment 2 of a bit line driver. It is a figure which shows the 2nd example of arrangement | positioning according to Embodiment 2 of a bit line driver. It is a figure which shows the 3rd example of arrangement | positioning according to Embodiment 2 of a bit line driver. FIG. 15 is a first diagram showing a variation of the arrangement of the bit line drivers shown in FIG. 14. FIG. 15 is a second diagram showing a variation of the arrangement of the bit line drivers shown in FIG. 14. It is a figure which shows the 1st example of arrangement | positioning according to the modification 1 of Embodiment 2 of a write digit line drive circuit. FIG. 18 is a diagram showing a variation of the arrangement of the bit line drivers shown in FIG. 17. FIG. 11 is a conceptual diagram showing an arrangement of read selection gates according to a second modification of the second embodiment. FIG. 11 is a conceptual diagram showing an arrangement of read selection gates according to a third modification of the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

[Embodiment 1]
(Overall configuration and data read / write operations)
FIG. 1 is an overall configuration diagram of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 according to the first embodiment includes a control circuit 5 for receiving a command control signal CMD and controlling the overall operation of the MRAM device, and a memory cell array 10. The memory cell array 10 has a plurality of MTJ memory cells MC arranged in a matrix. Here, the configuration and data storage principle of the MTJ memory cell will be described.

FIG. 2 is a conceptual diagram illustrating the structure of the MTJ memory cell and the data storage principle.
Referring to FIG. 2, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and a magnetic field applied from the outside. And a ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that can be magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB, and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of tunneling magneto-resistance element TMR becomes the minimum value Rmin when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), and the magnetization directions of both are The maximum value Rmax is obtained in the opposite (antiparallel) direction.

  At the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current Ip in a predetermined direction for generating a data write magnetic field H (WDL) along the hard magnetic axis (HA) of free magnetic layer VL flows through write digit line WDL. On the other hand, a data write current + Iw or −Iw for generating a data write magnetic field H (BL) along the easy magnetic axis (EA) of the free magnetic layer VL flows through the bit line BL. That is, the data write current on the bit line BL is controlled to have a direction corresponding to the level of the write data. Hereinafter, data write currents + Iw and -Iw are collectively referred to as data write current ± Iw.

  FIG. 3 is a conceptual diagram showing the relationship between the data write current of the MTJ memory cell and the magnetization direction of the tunnel magnetoresistive element.

  Referring to FIG. 3, the horizontal axis H (EA) indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and write digit line WDL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy axis of the free magnetization layer VL, and the free magnetization layer VL extends in the easy axis direction according to the level of stored data. Along this direction, the magnetization is magnetized in a direction parallel or antiparallel (opposite) to the fixed magnetization layer FL. The MTJ memory cell can store 1-bit data corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to. As shown in FIG. 3, the operating point at the time of data writing is that the data stored in the MTJ memory cell, that is, the tunnel magnetic field when a predetermined data write current is supplied to both the write digit line WDL and the bit line BL. It is designed so that the magnetization direction of the resistance element TMR can be rewritten.

At the operating point illustrated in FIG. 3, the data write magnetic field in the easy axis direction is designed so that its strength is HWR in the MTJ memory cell to be written. That is, the value of the data write current flowing through bit line BL or write digit line WDL is designed so that this data write magnetic field HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

  Referring to FIG. 1 again, control circuit 5 generates various control signals for controlling the internal operation in MRAM device 1 in response to command control signal CMD. These control signals include, for example, a control signal RE that is activated to a high level (hereinafter referred to as “H level”) for a predetermined period during data reading, or a control that is activated to a H level for a predetermined period during data writing. A signal WE and the like are included.

  In memory cell array 10, read word line RWL and write digit line WDL are arranged corresponding to each row of MTJ memory cells MC, and bit line BL is arranged corresponding to each column of MTJ memory cells MC. Each MTJ memory cell MC has a tunnel magnetoresistive element TMR and an access transistor ATR connected in series between the corresponding bit line BL and source voltage line SL. Access transistor ATR is typically formed of an N-MOS transistor, and its gate is connected to corresponding read word line RWL. A source voltage line SL connected to the source of each access transistor ATR supplies a ground voltage GND. Hereinafter, in this specification, a MOS transistor is shown as a representative example of a field effect transistor.

Next, the configuration and operation of the data write circuit in the MRAM device 1 will be described.
The MRAM device 1 includes a row decoder 20, a write digit line drive circuit 30, bit line drivers 50 and 55 provided corresponding to each memory cell column, and a data write circuit 60.

  The row decoder 20 generates a row decode signal Rdw for each memory cell row based on the row address RA. The row decoder 20 activates the row decode signal Rdw of a selected memory cell row (hereinafter also referred to as “selected row”) to H level (power supply voltage Vcc2) during data writing, and other memory cell rows ( The row decode signal Rdw (hereinafter also referred to as “non-selected row”) is deactivated to a low level (hereinafter also referred to as “L level”). Except for the time of data writing, row decoder 20 inactivates each of row decode signal Rdw to L level (ground voltage GND).

  Write digit line drive circuit 30 has a driver transistor 35 connected between one end of each write digit line WDL and ground voltage GND. Driver transistor 35 is formed of an N-MOS transistor, and its gate receives row decode signal Rdw of the corresponding memory cell row. The other end of each write digit line WDL is connected to power supply voltage Vcc2 regardless of the row selection result.

  Therefore, in the selected row at the time of data writing, corresponding driver transistor 35 is turned on in response to activation (H level) of row decode signal Rdw. Thereby, data write current Ip flows through write digit line WDL of the selected row in the direction from power supply voltage Vcc2 to the write digit line drive circuit.

  Bit line driver 50 includes driver transistors 52 and 54 connected between one end side of corresponding bit line BL and power supply voltage Vcc2 and ground voltage GND, respectively. Similarly, bit line driver 55 has driver transistors 56 and 58 connected between the other end of corresponding bit line BL and power supply voltage Vcc2 and ground voltage GND, respectively. The bit line drivers 50 and 55 are constituted by C-MOS drivers. That is, the driver transistors 52 and 56 are P-MOS transistors, and the driver transistors 54 and 58 are N-MOS transistors.

  Write control signals / WTa1 and WTa0 are input to the gates of driver transistors 52 and 54, respectively, and write control signals / WTb0 and WTb1 are input to the gates of driver transistors 56 and 58, respectively.

  In each memory cell column, bit line driver 50 drives one end side of corresponding bit line BL with power supply voltage Vcc2 or ground voltage GND in accordance with write control signals / WTa1 and WTa0, or Floating without connecting to voltage. Similarly, the bit line driver 55 drives the other end side of the corresponding bit line BL with the power supply voltage Vcc2 or the ground voltage GND according to the write control signals / WTb0 and WTb1, or puts it in a floating state. Each bit line BL in the floating state is precharged to a fixed voltage by a precharge circuit (not shown) as necessary.

  Data write circuit 60 controls write control signals / WTa1, WTa0, / WTb0, WTb1 in each memory cell column in accordance with write data DIN and a column selection result. Write control signals / WTa0, WTa1, / WTb0, and WTb1 are set such that data write current ± Iw in a direction corresponding to write data DIN flows through bit line BL of the selected column.

  Data write circuit 60 sets write control signals / WTa1, / WTb0 to H level (power supply voltage Vcc2) and sets write control signals WTa0, WTb1 in each memory cell column except during data writing. Set to L level (ground voltage GND). As a result, each bit line BL is set in a floating state except during data writing.

  Data write circuit 60 sets each of write control signals / WTa1, WTa0, / WTb0, WTb1 corresponding to the non-selected memory cell columns at the time of data writing to H level. Thereby, the bit line BL of the non-selected column is connected to the ground voltage GND at both ends so that an unintended current does not flow during data writing.

  In contrast, data write circuit 60 sets write control signals / WTa1, WTa0, / WTb0, WTb1 corresponding to the selected memory cell column in accordance with write data DIN during data writing. Specifically, when write data DIN is at H level, write control signals / WTa1 and WTa0 are set to L level, and write control signals / WTb0 and WTb1 are set to H level. As a result, the data write current + Iw flows in the direction from the bit line driver 50 to 55 in the bit line BL of the selected column.

  In contrast, when write data DIN is at L level, write control signals / WTa1 and WTa0 are set to H level, and write control signals / WTb0 and WTb1 are set to L level. As a result, the data write current −Iw flows in the direction from the bit line driver 55 to 50 in the bit line BL of the selected column. Note that the drive voltages of the bit line drivers 50 and 55 can be independent voltages other than the ground voltage GND and the power supply voltage Vcc2.

  In addition, the driver transistors 52, 54, 56, and 58 can be composed of MOS transistors of the same conductivity type. In this case, for a driver transistor to which a MOS transistor having a conductivity type opposite to that in the configuration example of FIG. 1 is applied, if the inversion level of the corresponding write control signal in FIG. Can be executed.

  In MTJ memory cell MC (that is, selected memory cell) in which the data write current is supplied to both corresponding write digit line WDL and bit line BL, it corresponds to the direction of data write current ± Iw on bit line BL. Level data is magnetically written.

Next, the configuration and operation of the data read system circuit in the MRAM device 1 will be described.
The MRAM device 1 further includes a row decoder 21, a read selection gate 65, a current supply transistor 70, and a data read circuit 80.

  Row decoder 21 generates row decode signal Rdr for each memory cell row based on row address RA. Row decoder 21 activates row decode signal Rdr of the selected row to H level (power supply voltage Vcc1) and deactivates row decode signal Rdr of the unselected row to L level (ground voltage GND) during data reading.

  Therefore, at the time of data reading, read word line RWL of the selected row is activated to H level and read word line RWL of the non-selected row is deactivated to L level in accordance with row decode signal Rdr. On the other hand, each read word line RWL is inactivated to L level except during data reading. As a result, at the time of data reading, the access transistor ATR is turned on in the memory cell of the selected row, and each bit line BL is pulled down to the ground voltage GND via the tunnel magnetoresistive element TMR of the corresponding MTJ memory cell MC.

  Read select gate 65 is provided between each bit line BL and read data bus RDB, and is turned on or off in response to corresponding column select line CSL. Column selection line CSL is activated to H level in a column (hereinafter also referred to as “selected column”) selected at the time of data reading, and is set to L level in other columns (hereinafter also referred to as “non-selected column”). Deactivated. Except at the time of data reading, each column selection line CSL is inactivated to L level.

  As a result, at the time of data reading, read data bus RDB is pulled down to ground voltage GND via read selection gate 65 of the selected column, bit line BL of the selected column, and tunneling magneto-resistance element TMR in the selected memory cell. Yes. In this state, read data bus RDB is pulled up to power supply voltage Vcc1 by current supply transistor 70 which is turned on during data read.

  Current supply transistor 70 is formed of, for example, a P-MOS transistor connected between power supply voltage Vcc1 and read data bus RDB and receiving a control signal / RE at its gate. Control signal / RE is an inverted signal of control signal RE generated by control circuit 5, and is activated to L level in a predetermined period at the time of data reading. As a result, a voltage corresponding to the electric resistance (ie, stored data) of the selected memory cell is generated on read data bus RDB during data reading.

  Data read circuit 80 operates in response to supply of power supply voltage Vcc1 and ground voltage GND, amplifies the voltage difference between read data bus RDB and read reference voltage VRref, and reads the data stored in the selected memory cell. Data DOUT is generated. The read reference voltage VRref is the same as the voltage of the read data bus RDB when the selected memory cell corresponding to the electrical resistance Rmin is connected to the stored data and the selected memory cell corresponding to the electrical resistance Rmax when the stored data is connected. It is set to an intermediate level with the voltage of read data bus RDB. In this way, data reading from the selected memory cell is executed.

  In order to supply a sufficient data write current, power supply voltage Vcc2 is set to a voltage higher than power supply voltage Vcc1. On the other hand, power supply voltage Vcc1 corresponds to a voltage applied to tunnel film TB (FIG. 2) at the time of data reading, and cannot be a high voltage from the viewpoint of reliability. That is, by making the power supply voltage Vcc1 of the data read circuit system and the power supply voltage Vcc2 of the data write circuit system independent and satisfying Vcc2> Vcc1, both data reading and data writing can be executed stably. it can.

(Configuration for supplying data write current)
Next, the configuration of a data write current supply circuit system for supplying a data write current efficiently and stably with a small circuit area will be described.

  FIG. 4 is a conceptual diagram showing a first configuration example according to the first embodiment of the data write current supply circuit system for write digit line WDL. FIG. 4 shows a plan layout of a data write current supply configuration for write digit lines WDL (1) to WDL (4) corresponding to the first row to the fourth row, respectively. It is assumed that a similar configuration is provided for write digit line WDL.

  A driver transistor 35 formed of an N-MOS transistor is connected between one end side of each of write digit lines WDL (1) to WDL (4) and ground voltage GND. Driver transistor 35 is arranged such that the current passing direction, that is, the gate length direction (L direction) is along the same direction as write digit line WDL.

  The source of driver transistor 35 is coupled to ground voltage GND, and the drain of driver transistor 35 is electrically coupled to write digit line WDL via contact 36.

  Independent gate lines 37 are provided corresponding to the respective driver transistors 35. For example, row decode signal Rdw (1) is transmitted to gate wiring 37 of driver transistor 35 corresponding to write digit line WDL (1). Row decode signal Rdw (1) is selected at the time of data writing in the first memory cell row, then activated to H level, and otherwise deactivated to L level. In each driver transistor 35, the gate wiring 37 arranged along the gate width direction (W direction) is arranged in a direction intersecting the write digit line WDL.

  If the driver transistor 35 is arranged so that the gate width direction (W direction) thereof coincides with the arrangement direction of the write digit line WDL, the arrangement pitch in the vertical direction (pitch direction of the write digit line WDL) in FIG. May become large.

  In general, the arrangement pitch of the write digit lines WDL can be set to a minimum value corresponding to the minimum design rule of the MTJ memory cell, but the gate width direction of the driver transistor 35 and the arrangement direction of the write digit line WDL In such an arrangement, the gate length of the driver transistor 35, the contact region to the source and drain, and the isolation insulating film width between adjacent driver transistors need to be designed to fall within the arrangement pitch of the write digit line WDL described above. It is.

  In particular, in order to supply sufficient data write current Ip without significantly increasing the size of driver transistor 35, it is necessary to set the level of power supply voltage Vcc2 high. Particularly in such a case, since the transistor size in the gate length direction is increased in order to ensure a breakdown voltage, the arrangement pitch of the write digit lines WDL does not match the arrangement pitch according to the minimum design rule of the MTJ memory cell. This prevents high integration of MTJ memory cells.

  Therefore, as shown in FIG. 4, the driver transistor 35 is arranged so that the gate length direction (L direction) and the arrangement direction of the write digit line WDL coincide with each other. Thus, it is possible to prevent the MTJ memory cell from being prevented from being integrated.

  Further, on the write digit line WDL, between the steady portion 93 corresponding to the arrangement position of the MTT memory cell and the power supply wiring 90, an reinforced portion 95 whose cross-sectional area is designed larger than that of the steady portion 93 is provided. Yes.

FIG. 5 shows a design example of a write digit line according to the first embodiment.
FIG. 5A shows a problem when the write digit line WDL is designed with a uniform wiring width (that is, a wiring cross-sectional area).

  Referring to FIG. 5A, when a data write current is supplied, electrons flow from the write digit line WDL toward the power supply wiring 90. At this time, the electrons flowing in are near the end of the write digit line WDL. The material atoms (for example, Al and Cu) in the wiring are moved. By repeating this, as shown by the dotted line, the wiring width of the write digit line WDL becomes narrower and the cross-sectional area becomes smaller. As a result, the current density locally increases at this portion, and there is a risk of causing a disconnection due to electromigration or the like and hindering operation reliability.

  Therefore, as shown in FIG. 5B, the cross-sectional area is increased by gradually increasing the wiring width in the vicinity of the end of the write digit line WDL (on the side of the power supply wiring 90) compared to the steady portion 93. A reinforcing portion 95 is provided. As a result, even if the wiring width is reduced due to the movement of the metal atoms as described above, it is possible to suppress the risk that the current density rapidly increases in this portion and affects the operation reliability. Alternatively, as shown in FIG. 5C, the wiring width (cross-sectional area) of a part near the end of the write digit line WDL may be increased.

  On the other hand, the steady portion 93 of the write digit line WDL, that is, the portion with respect to the MTJ memory cell arrangement region is maintained at the steady wiring width Ws (cross-sectional area Ss) according to the minimum design rule of the MTJ memory cell. MTJ memory cells can be arranged highly integrated.

  FIG. 6 is a conceptual diagram showing a second configuration example according to the first embodiment of the data write current supply circuit system for write digit line WDL. FIG. 6 shows a plan layout of a data write current supply configuration for write digit lines WDL (1) and WDL (2) corresponding to the first row and the second row, respectively. It is assumed that a similar configuration is provided for write digit line WDL.

  Referring to FIG. 6, in the second configuration example, write digit line WDL is formed in each of the plurality of wiring layers in reinforcing portion 95 having a cross-sectional area larger than that of the steady portion, and is electrically connected via contact 100. And a plurality of wirings coupled to each other. As in the configuration example shown in FIG. 4, driver transistor 35 is arranged such that the gate length direction thereof coincides with the direction of write digit line WDL.

  Referring to the PQ cross-sectional view in FIG. 6, write digit line WDL is configured by wirings 101 and 102 formed in a plurality of wiring layers, respectively. The wiring 101 corresponds to the steady portion 93 of the write digit line WDL, and the wiring 102 is formed in a region corresponding to the strengthened portion 95 in a wiring layer different from the wiring 101. Wirings 101 and 102 are electrically coupled via contact 100 formed in the via hole.

  Wirings 101 and 102 are electrically directly coupled to wirings 91 and 92 constituting power supply wiring 90 in each wiring layer. That is, wirings 91 and 92 are supplied with power supply voltage Vcc2. The wirings 91 and 92 are also electrically coupled via a contact provided in the via hole.

  Driver transistor 35 includes impurity regions 110 and 120 and a gate 130. Impurity region 110 is supplied with ground voltage GND and acts as a source. The other impurity region 120 is electrically coupled to the wiring 101 through the contact 36 and functions as a drain. A gate wiring 37 is disposed on the gate 130. 4 does not show a cross-sectional view of the driver transistor 35, the cross-sectional views of the driver transistor 35 are the same in FIGS.

  With such a configuration, the data write current path on the write digit line WDL when the driver transistor 35 is turned on is formed to include both the wirings 101 and 102 in the reinforcing portion 95. As a result, in the strengthened portion 95 in the write digit line WDL, the wiring cross-sectional area increases equivalently as compared with the steady portion 93. Thereby, a local increase in current density can be avoided as in the layouts of FIGS.

  In particular, in the configuration example of FIG. 6, each of the wirings 101 and 102 can be designed in a uniform shape, so that the wiring can be easily manufactured as compared with FIGS. 5B and 5C. Further, since there is no spread in the plane direction, the present invention can be applied to a case where the wiring pitch corresponds to the minimum in the processing dimension.

  FIG. 7 is a conceptual diagram showing a third configuration example according to the first embodiment of the data write current supply circuit system for write digit line WDL. FIG. 7 shows a plan layout of a data write current supply configuration for write digit lines WDL (1) to WDL (4) corresponding to the first row to the fourth row, respectively. It is assumed that a similar configuration is provided for write digit line WDL.

  Referring to FIG. 7, in the third configuration example, driver transistors 35 are alternately arranged for each row with respect to one of the one end and the other end of write digit line WDL. Correspondingly, power supply lines 90 and 90 # are arranged corresponding to both ends of write digit line WDL, respectively.

  In other words, odd-numbered write digit lines WDL (1), WDL (3),... Are electrically coupled to power supply wiring 90, and even-numbered write digit lines WDL (2), WDL (4),. Electrically coupled to interconnection 90 #. Each of the write digit lines WDL is provided with a reinforcing portion 95 similar to that shown in FIG. 4 or FIGS. 5B and 5C between the corresponding power supply lines 90 and 90 # and the steady portion 93. It has been.

  Thus, by alternately arranging the driver transistors every other row, the arrangement pitch of the driver transistors 35 is relaxed, so that the driver transistors 35 can be arranged more efficiently. Such an alternate arrangement is effective when the power supply voltage Vcc2 is set higher than other power supply voltages.

  In particular, when the reinforced portion 95 is secured by the planar shape of the wiring as shown in FIGS. 5B and 5C, the degree of freedom in dimension in this region is increased, so that the driver transistor 35 is arranged more efficiently. can do.

  In FIG. 7, the configuration example in which the driver transistors 35 are alternately arranged for each row is shown. However, for example, the configuration in which the driver transistors 35 are alternately arranged for each of two or more write digit lines WDL. The same effect can be obtained.

  FIG. 8 is a conceptual diagram showing a fourth configuration example according to the first embodiment of the data write current supply circuit system for write digit line WDL. FIG. 8 shows a plan layout of a data write current supply configuration for write digit lines WDL (1) and WDL (2) corresponding to the first row and the second row, respectively. It is assumed that a similar configuration is provided for write digit line WDL.

  As understood from the PQ cross-sectional view in FIG. 8, in the fourth configuration example, the write digit line WDL is provided in the lowermost wiring layer in the MRAM device. Further, power supply wiring 90 is provided in the same wiring layer as write digit line WDL, and power supply wiring 90 and write digit line WDL are electrically coupled in the wiring layer.

  The power supply wiring 90 is electrically coupled to the power supply pad 150 to which the power supply voltage Vcc2 is supplied from the outside of the MRAM device through the contact 100. In particular, the electrical resistance between the power supply pad 150 and the power supply wiring 90 can be reduced by directly connecting the power supply pad 150 and the power supply wiring 90 with a contact without extending over a plurality of wiring layers. This is because such a design makes it easy to secure the cross-sectional area of contacts 100 or the number of parallel arrangements. Since the arrangement of driver transistor 35 is the same as that described with reference to FIG. 6, detailed description thereof will not be repeated.

  FIG. 9 is a cross-sectional view showing the MTJ memory cell structure when the write digit line WDL is provided in the lowermost layer wiring.

  Referring to FIG. 9, MTJ memory cell MC is formed of tunneling magneto-resistance element TMR and access transistor ATR, and access transistor ATR has impurity regions 110 # and 120 # and gate 130 #. Impurity region 110 # is electrically coupled to ground voltage GND by source voltage line SL shown in FIG. 1, and functions as a source. Impurity region 120 # is electrically coupled to tunneling magneto-resistance element TMR through a wiring provided in metal wiring layer M1 and a contact formed in a via hole. Tunneling magneto-resistance element TMR is further electrically coupled to bit line BL provided in metal interconnection layer M2.

  Further, in the metal wiring layer M1, a write digit line WDL is arranged in a region immediately below the tunnel magnetoresistive element TMR. The write digit line WDL and the bit line BL for causing the data write magnetic field to act on the tunnel magnetoresistive element in this way are adjacent to the metal wiring layers M1 and M2 sandwiching the tunnel magnetoresistive element TMR adjacent to the tunnel magnetoresistive element TMR Each is formed.

  In data reading, access transistor ATR is turned on in response to activation of read word line RWL arranged in gate region 130 #. Thereby, a current path of bit line to tunneling magneto-resistance element TMR, impurity region (drain) 120 # to impurity region (source) 110 # to ground voltage GND is formed, and the electric resistance of the tunneling magneto-resistance element is formed in the current path. That is, a current corresponding to the storage data of the MTJ memory cell can be passed.

  Referring to FIG. 8 again, in the fourth configuration example, by designing so that the path of data write current Ip does not straddle a plurality of wiring layers, it is possible to connect between power supply pad 150 and ground voltage GND. The electrical resistance of the path of the formed data write current Ip can be reduced. That is, the electrical resistance of the path is smaller than that in the case where the path of the data write current Ip is formed through the plurality of wirings formed in the plurality of wiring layers and the contact connecting these wiring layers. . Therefore, a predetermined data write current can be easily secured even when power supply voltage Vcc2 is set to a relatively low voltage.

  In particular, in the MRAM device, the wiring that needs to pass a relatively large amount of current is either the bit line BL or the write digit line WDL. Therefore, the bit line BL or the write digit line WDL is the lowermost layer wiring. It will be provided as a layer. In particular, which of the bit line BL and the write digit line WDL is formed in the lowermost layer may be determined based on the design value of the data write current flowing through each wiring.

  That is, the structure diagram of the MTJ memory cell shown in FIG. 9 corresponds to the case where the data write current Ip flowing through the write digit line WDL is larger than the data write current ± Iw flowing through the bit line.

[Modification of Embodiment 1]
In the first embodiment, the configuration for supplying data write current to write digit line WDL has been described. In the modification of the first embodiment, the configuration for supplying data write current to bit line BL is the same as that of the first embodiment. The case where it applies to is demonstrated.

  FIG. 10 is a conceptual diagram showing a first configuration example according to the modification of the first embodiment of the data write current supply circuit system for the bit lines. FIG. 10 shows a plane layout of the bit lines BL (1) and BL (2) in the first column and the second column and the data write current supply configuration for the bit lines BL (1) and BL (2). It is assumed that a similar configuration is provided for.

  Referring to FIG. 10, as described in FIG. 1, bit line drivers 50 and 55 are arranged corresponding to both ends of each bit line BL, respectively. In the following, the layout configuration of the bit line driver for the bit line BL (1) in the first column will be representatively described.

  Referring to FIG. 10, among the driver transistors constituting bit line driver 50, in driver transistor 52 which is a P-MOS transistor, the source is directly coupled to power supply voltage Vcc2, and the drain is connected to bit line BL via contact 135a. It is connected to one end (bit line driver 50 side) of (1). The gate of driver transistor 52 is connected to gate wiring 140a. A write control signal / WTa1 (1) corresponding to bit line BL (1) is transmitted to gate interconnection 140a.

  On the other hand, in driver transistor 54 which is an N-MOS transistor, the source is directly coupled to ground voltage GND, and the drain is connected to one end of bit line BL (1) via contact 135b. The gate of the driver transistor 54 is connected to the gate wiring 140b. Write control signal WTa0 (1) corresponding to bit line BL (1) is transmitted to gate interconnection 140b.

  Similarly, in the driver transistor 56 which is a P-MOS transistor among the driver transistors constituting the bit line driver 55, the source is directly coupled to the power supply voltage Vcc2, and the drain is connected to the bit line BL (1) via the contact 135d. Connected to the other end (bit line driver 55 side). The gate of driver transistor 56 is connected to gate line 140d. Write control signal / WTb0 (1) corresponding to bit line BL (1) is transmitted to gate interconnection 140d.

  On the other hand, in driver transistor 58 which is an N-MOS transistor, the source is directly coupled to ground voltage GND, and the drain is connected to the other end of bit line BL (1) via contact 135c. The gate of driver transistor 58 is connected to gate line 140c. Write control signal WTb1 (1) corresponding to bit line BL (1) is transmitted to gate interconnection 140c.

  Each of driver transistors 52, 54, 56, and 58 is arranged such that its gate length is the same as the arrangement direction of bit line BL (1), similarly to driver transistor 35 described in the first embodiment. .

  As a result, the arrangement pitch of the bit lines BL in the driver transistor group constituting the bit line drivers 50 and 55 is also compared with a layout arrangement in which the gate length direction and the bit line arrangement direction intersect (orthogonal). Can be arranged efficiently without affecting the operation.

Further, a reinforced portion whose wiring cross-sectional area is designed to be larger than that of the steady portion 143 between the steady portion 143 corresponding to the MTJ memory cell arrangement region in the bit line BL (1) and the contacts 135b and 135c. 145 is provided. Since the data write current flowing through the bit line BL changes according to the level of the write data, both the one end and the other end of the bit line BL may be coupled to the power supply voltage Vcc2. As already described, the reinforced portion 145 having a large wiring cross-sectional area needs to be provided on the side of the power supply voltage Vcc2 into which electrons flow when supplying the data write current. Thus, it is necessary to provide the reinforcing portion 145. Thus, it is necessary to provide the reinforcing portion 145.

  By adopting such a configuration, the bit line BL also enjoys the same effect as described in the first embodiment, prevents the occurrence of electromigration due to a local increase in current density, and operates reliably. Can be improved.

  FIG. 11 is a conceptual diagram showing a second configuration example according to the modification of the first embodiment of the data write current supply circuit system for the bit line.

  Referring to FIG. 11, in the second configuration example of the modification of the second embodiment, the arrangement of write digit line WDL shown in FIG. 6 is applied to bit line BL. The bit line BL is composed of wirings 151 and 152 formed in different wiring layers. The wiring 151 corresponds to, for example, the bit line BL in the stationary part shown in the structural diagram of FIG. 9, and is arranged close to the tunnel magnetoresistive element TMR.

  The wiring 152 is arranged on the upper layer of the wiring 151 and is electrically coupled to the wiring 151 by a contact 160 provided in the via hole.

  Driver transistor 52 has a gate connected to impurity regions 170a and 180a and gate wiring 140a. Impurity region 170a is electrically coupled to power supply voltage Vcc2 and functions as a source. Impurity region 180a is connected to wirings 151 and 152 by contact 135a and acts as a drain.

  Similarly, driver transistor 54 has a gate connected to impurity regions 170b and 180b and gate wiring 140b. Impurity region 170b is electrically coupled to ground voltage GND and acts as a source. Impurity region 180b is connected to wirings 151 and 152 by contact 135b and acts as a drain.

  Driver transistor 56 has a gate connected to impurity regions 170d and 180d and gate wiring 140d. Impurity region 170d is electrically coupled to power supply voltage Vcc2 and acts as a source. Impurity region 180d is connected to wirings 151 and 152 by contact 135d and acts as a drain.

  Driver transistor 58 has a gate connected to impurity regions 170c and 180c and gate wiring 140c. Impurity region 170c is electrically coupled to ground voltage GND and acts as a source. Impurity region 180c is connected to wirings 151 and 152 by contact 135c and functions as a drain.

  With such a configuration, similarly to the configuration shown in FIG. 10, the cross-sectional area (wiring cross-sectional area) through which the data write current passes is equivalently increased at both ends of the bit line BL. As a result, even if the wiring width decreases at both ends of the bit line, the occurrence of electromigration can be prevented without causing a local increase in current density.

  In particular, in the configuration example of FIG. 11, each of the wirings 151 and 152 can be designed in a uniform shape, so that the wiring can be easily manufactured as compared with the configuration example of FIG. 10. Further, since there is no spread in the plane direction, the present invention can be applied to a case where the wiring pitch corresponds to the minimum in the processing dimension.

[Embodiment 2]
In the second embodiment, a desirable arrangement of the bit line drivers described in the first embodiment will be described in more detail.

  FIG. 12 is a diagram showing a first arrangement example according to the second embodiment of the bit line driver. FIG. 12 representatively shows the bit lines BL (j) and BL (j + 1) of the j-th column and the (j + 1) -th row and the configuration corresponding thereto, but with respect to the other bit lines BL. However, it is assumed that the same configuration is provided. Note that the j-th column and the (j + 1) -th row are shown as representative examples of the odd-numbered column and the even-numbered column, respectively.

  Referring to FIG. 12, a pair of power supply wiring and ground wiring provided along the direction intersecting with bit line BL corresponding to both ends of each bit line BL is arranged in an adjacent region of memory cell array 10. Has been. Specifically, power supply wiring 190 for supplying power supply voltage Vcc2 is connected to driver transistor 52 in bit line driver 50, and ground wiring 195 for supplying ground voltage GND is connected to driver transistor 54 in bit line driver 50. Connected.

  Similarly, power supply wiring 190 # supplying power supply voltage Vcc2 is connected to driver transistor 56 in bit line driver 55, and ground wiring 195 # supplying ground voltage GND is connected to driver transistor 58 in bit line driver 55. Connected.

  As already described, read selection gate 65 for transmitting read data from the selected memory cell at the time of data reading is arranged corresponding to each bit line BL. Bit lines BL are connected to read data buses RDB1 and RDB2 every other row. For example, the bit line BL (j) in the odd column is connected to the read data bus RDB1 through the read selection gate 65, and the bit line BL (j + 1) in the even column is connected to the read data bus RDB2 through the read selection gate 65. Connected.

  Each gate of read selection gate 65 is connected to a column selection line CSL indicating a selection result at the time of data reading of the corresponding memory cell column. The activation and deactivation of the column selection line CSL is the same as described in FIG.

  Although not shown, read word line RWL shown in FIG. 1 is arranged corresponding to each memory cell row, and the selected memory cell is connected to bit line BL of the selected column at the time of data reading. .

  As a result, data read circuit 80 reads data from the selected memory cell based on a comparison between the voltage of read data bus RDB1 or RDB2 connected to the selected memory cell via read selection gate 65 and read reference voltage VRref. Data DOUT can be determined.

  Here, the read selection gate 65 is arranged outside the bit line driver 50 or 55 with respect to the memory cell array 10. With such a configuration, the current path of the data write current flowing through the bit line BL can be shortened, and the electrical resistance can be reduced. As a result, it becomes easy to secure a predetermined level of data write current ± Iw flowing through the bit line.

FIG. 13 is a diagram showing a second configuration example according to the second embodiment of the bit line driver.
Referring to FIG. 13, in the second configuration example, read selection gate 65 is connected between bit line driver 50 (or 55) and memory cell array 10 as compared with the first configuration example shown in FIG. It is different in that it is placed between them. Thereby, read selection gate 65 is arranged using region 200 # (or 200) between power supply line 190 # and ground line 195 # (or power supply line 190 and ground line 195) and memory cell array 10. Since the configuration and arrangement of the other parts are the same as in FIG. 12, detailed description will not be repeated.

  With such a configuration, power supply wiring 190 # and ground wiring 195 # included in the current path of data write current ± Iw can be kept away from memory cell array 10 during data writing. Therefore, the influence of magnetic noise generated by power supply wiring 190 # and ground wiring 195 # on memory cell array 10 can be reduced.

  Furthermore, by arranging read select gate 65 close to memory cell array 10, the electrical resistance of the data read current path during data read is reduced, so that the speed of the data read operation can be increased.

  In the configuration examples of FIGS. 12 and 13, the example in which the bit lines of the odd-numbered columns and the even-numbered columns are connected to the different read data buses RDB1 and RDB2 is shown. The bit line driver and the read selection gate can be similarly arranged in the connected configuration or the configuration in which three or more read data buses are connected to each part of the bit line BL.

FIG. 14 shows a third arrangement example according to the second embodiment of the bit line driver.
Referring to FIG. 14, in the third configuration example, read data buses RDB1 and RDB2 are arranged in regions on both sides of memory cell array 10 as compared with the second configuration example compared with FIG. Is different. Thus, data read circuit 80 is arranged corresponding to read data buses RDB1 and RDB2. Read selection gate 65 is arranged using power supply wiring 190 and ground wiring 195 and region 200 between memory cell arrays 10 in the odd columns, and power supply wiring 190 #, ground wiring 195 # and memory in the even columns. Arranged using region 200 # between cell array 10. Since other points are the same as those in FIG. 13, detailed description will not be repeated.

  With such a configuration, magnetic noise acting on memory cell array 10 from power supply lines 190 and 190 # and ground lines 195 and 195 # during data writing can be reduced. Thereby, the occurrence of erroneous data writing can be suppressed and more stable operation can be executed.

  15 and 16 show variations of the third configuration example shown in FIG.

  For example, in FIG. 15, a precharge transistor 66 for precharging bit line BL to a predetermined voltage is arranged using regions 200 and 200 # shown in FIG. Precharge transistor 66 is formed of, for example, an N-MOS transistor and corresponds to a predetermined bit line precharge voltage VBL in response to activation of control signal BLPR activated (H level) during the bit line precharge period. The bit line BL to be connected is connected.

  In FIG. 15, the arrangement of precharge transistors 66 corresponding to bit lines BL (j) and BL (j + 1) is representatively shown, but the same applies to other bit lines BL (not shown). A precharge transistor 66 is arranged.

  By adopting such a configuration, similarly to the third configuration example shown in FIG. 14, magnetic noise acting on the memory cell array 10 from the power supply wirings 190 and 190 # and the ground wirings 195 and 195 # can be reduced. Can do.

  Alternatively, as shown in FIG. 16, in a configuration in which data read circuit 80 is arranged corresponding to each bit line BL and parallel data read on a plurality of bit lines is realized, data read circuit 80 is arranged in region 200. , 200 # can also be used. FIG. 16 representatively shows a data read circuit 80 corresponding to each of bit lines BL (j) and BL (j + 1), but region 200 or 200 is also applied to other bit lines BL (not shown). Data read circuit 80 is arranged using #.

  Even in such a configuration, the power supply lines 190 and 190 # and the ground lines 195 and 195 # can be separated from the memory cell array 10, so that the power supply lines 190 and 190 # and the ground lines 195 and 195 are written at the time of data writing. Magnetic noise acting on the memory cell array 10 from # can be reduced.

  The configurations shown in FIGS. 13 to 15 can be similarly applied to the case where three or more read data buses are arranged separately on both sides of the memory cell array.

[Modification 1 of Embodiment 2]
In the first modification of the second embodiment, a configuration for reducing magnetic noise from the power supply wiring and the ground wiring for the write digit line drive circuit is shown.

  FIG. 17 is a diagram showing a first arrangement example according to the first modification of the second embodiment of the write digit line drive circuit. FIG. 17 typically shows a configuration corresponding to the i-th row (i: natural number) and (i + 2) -th row shown as representative examples of even-numbered rows and the (i + 1) -th row shown as representative examples of odd-numbered rows. Although shown, it is assumed that the same configuration is provided for the other memory cell rows.

  Referring to FIG. 17, driver transistors 35 constituting the write digit line drive circuit are alternately arranged every other row as shown in FIG. For example, the power supply wiring 191 and the ground wiring 196 are arranged in a direction intersecting the write digit line WDL using one of the regions adjacent to the memory cell array 10, and the power supply wiring 191 is used using the other of the regions adjacent to the memory cell array 10. # And ground wiring 196 # are arranged in a direction crossing write digit line WDL. Power supply lines 191 and 191 # transmit power supply voltage Vcc2, and ground lines 196 and 196 # transmit ground voltage GND. As already described, bit line drivers 50 and 55 are arranged corresponding to both ends of each bit line BL.

  One end side (upper side in FIG. 17) of write digit line WDL in even-numbered rows is connected to power supply wiring 191, and the other end side (lower side in FIG. 17) is connected to ground wiring 196 # through driver transistor 35. . Similarly, one end side of odd-digit write digit line WDL is connected to ground line 196 through driver transistor 35, and the other end side is connected to power supply line 191 #.

  Further, row decoders 20 and 20 # are arranged using regions 210 and 210 # between driver transistor 35 and memory cell array 10, respectively. Row decoder 20 outputs a row decode signal Rdw corresponding to an odd row, and row decoder 20 # outputs a row decode signal Rdw corresponding to an even row.

  With such a configuration, not only can driver transistor 35 and row decoders 20 and 20 # be efficiently arranged, but also power supply lines 191 and 191 # for supplying a data write current on write digit line WDL. Also, ground lines 196 and 196 # can be kept away from memory cell array 10. Thereby, magnetic noise from the power supply wiring and the ground wiring to the memory cell array, which is caused by the supply of the data write current Ip at the time of data writing, can be reduced.

  Alternatively, as shown in FIG. 18, wiring groups 230 and 230 # for transmitting address signals and other signals may be arranged using regions 210 and 210 #. In this case, row decoders 20 and 20 # may be arranged in regions outside driver transistor 35 with respect to memory cell array 10, respectively.

  Even in such a configuration, similarly to the configuration example shown in FIG. 17, magnetic noise acting on the memory cell array 10 from the power supply wiring and the ground wiring when supplying the data write current on the write digit line WDL is reduced. Can do.

[Modification 2 of Embodiment 2]
FIG. 19 is a conceptual diagram showing an arrangement of read selection gates according to the second modification of the second embodiment.

  Referring to FIG. 19, in the second modification 2 of the second embodiment, read data buses RDB1, RDB2 provided in the direction intersecting with each bit line BL are compared with the arrangement example shown in FIG. Is differently arranged corresponding to the middle portion of the bit line BL. As a result, read selection gate 65 is arranged between the intermediate node of each bit line BL and read data bus RDB1 or RDB2. Data read circuit 80 is provided in the peripheral region of memory cell array 10 corresponding to read data buses RDB1 and RDB2. Since the configuration of other parts is the same as that of FIG. 13, detailed description will not be repeated.

  With such a configuration, the bit line BL is divided into two parts with an intermediate node connected to the read selection gate 65 as a boundary, and is coupled to the selected memory cells of the two parts at the time of data reading. Only the data read current flows.

  As a result, the data read current path during data read can be shortened and the electrical resistance can be reduced. As a result, the data reading operation can be speeded up.

[Modification 3 of Embodiment 2]
FIG. 20 is a conceptual diagram showing the arrangement of read selection gates according to the third modification of the second embodiment.

  Referring to FIG. 20, in modification 3 of the second embodiment, memory cell array 10 in which a plurality of MTJ memory cells are arranged is divided into two memory blocks 10a and 10b.

  Bit line BL is divided into memory blocks 10a and 10b in each memory cell column. For example, the bit line BL in the j-th column is divided into a bit line BLa (j) arranged in the memory block 10a and a bit line BLb (j) arranged in the memory block 10b. In each of memory blocks 10a and 10b, bit line drivers 50 and 55 are arranged corresponding to both ends of each bit line, respectively. In the following, the bit lines arranged in the memory block 10a are collectively referred to as the bit line BLa, and the bit lines arranged in the memory block 10b are collectively referred to as the bit line BLb. And

  Although not shown, in each of the memory blocks 10a and 10b, a read word line RWL and a write digit line WDL are arranged for each memory cell row. Therefore, the designation of the selected memory cell to be the data read target and the data write target is executed by a combination of the selection of the memory blocks 10a and 10b and the row and column selection in each memory block.

  Read data buses RDB1, RDB2 and data read circuit 80 are arranged at the boundary between memory blocks 10a and 10b, and are shared by both memory blocks. In the odd columns, read selection gates 65 are provided between read data bus RDB1 and corresponding bit lines BLa and BLb, respectively. Similarly, in even columns, read selection gates 65 are provided between read data bus RDB2 and bit lines BLa and BLb, respectively.

  On / off of each read selection gate 65 is controlled by a column selection line CSLa or CSLb reflecting the selection result of the corresponding memory cell column and memory block. For example, in the j-th column, column selection line CSLa (j) is connected to the gate of read selection gate 65 corresponding to memory block 10a, and column selection line is connected to the gate of read selection gate 65 corresponding to memory block 10b. CSLb (j) is connected.

  Column select line CSLa (j) is selected when memory block 10a is selected and the jth memory cell column is selected in data reading, that is, the selected memory cell is connected to bit line BLa (j). When activated, it is activated to H level, otherwise it is deactivated to L level. Similarly, column select line CSLb (j) is selected when memory block 10b is selected and the jth memory cell column is selected at the time of data reading, that is, bit line BLb (j) is selected memory cell. Is activated to H level when is connected, otherwise it is deactivated to L level.

  With such a configuration, in an array configuration divided into a plurality of memory blocks, it is possible to reduce the chip size by sharing a data read system circuit group between adjacent memory blocks 10a and 10b. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 MRAM device, 10 memory cell array, 10a, 10b memory block, 20, 20 #, 21 row decoder, 30 write digit line drive circuit, 35 driver transistor (for write digit line), 36, 135a to 135d, 100, 160 wiring Contact, 37, 140a to 140d, gate wiring, 50, 55 bit line driver, 52, 54, 56, 58 driver transistor (for bit line), 60 data write circuit, 65 read selection gate, 66 precharge transistor, 80 Data readout circuit, 90, 190, 190 #, 191, 191 # power supply wiring, 91, 101, 102, 151, 152 wiring, 93, 143 steady portion, 95, 145 strengthened portion, 110, 110 #, 120, 120 # , 170a-1 0d, 180a to 180d Impurity region, 130, 130 # gate, 150 power supply pad, 195, 195 #, 196, 196 # ground wiring, 200, 200 #, 210, 210 # region, 230, 230 # wiring group, ATR access Transistor, BL, BLa, BLb Bit line, CSL, CSLa, CSLb Column selection line, FL pinned magnetization layer, GND ground voltage, Ip, ± Iw Data write current, MC MTJ memory cell, RDB, RDB1, RDB2 Read data bus , RWL Read word line, TB tunnel barrier, TMR tunnel magnetoresistive element, VL free magnetic layer, Vcc1, Vcc2 power supply voltage, WDL write digit line.

Claims (2)

A memory cell array in which a plurality of magnetic memory cells each having a magnetic layer magnetized in a direction according to stored data are disposed;
A plurality of bit lines provided respectively corresponding to predetermined sections of the plurality of magnetic memory cells;
In order to flow a data write current for generating a data write magnetic field for magnetizing the magnetic layer to at least one of the plurality of bit lines at the time of data writing, respectively corresponding to both ends of the plurality of bit lines A plurality of first and second bit line drivers provided;
A read data line provided for transmitting read data from a selected memory cell of the plurality of magnetic memory cells along a direction intersecting the plurality of bit lines;
A read selection gate for connecting one of the plurality of bit lines connected to the selected memory cell and the read data line during data reading;
The thin film magnetic memory device, wherein the read selection gate is arranged outside one of the plurality of first and second bit line drivers with respect to the memory cell array. A memory cell array in which a plurality of magnetic memory cells each having a magnetic layer magnetized in a direction according to stored data are disposed;
A plurality of bit lines provided respectively corresponding to predetermined sections of the plurality of magnetic memory cells;
Corresponding to both ends of the plurality of bit lines in order to flow a data write current for generating a data write magnetic field for magnetizing the magnetic layer to at least one of the plurality of bit lines during data writing A plurality of first and second bit line drivers provided,
A read data line provided for transmitting read data along a direction intersecting the plurality of bit lines;
A read selection gate for connecting one of the plurality of bit lines connected to a selected memory cell of the plurality of magnetic memory cells and the read data line during data reading;
The thin film magnetic memory device, wherein the read selection gate and the read data line are arranged in a region corresponding to a central portion of the plurality of bit lines.

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