JP3936005B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to lower power consumption, higher speed, and smaller area of a DRAM (Dynamic Random Access Memory).
[0002]
[Prior art]
In recent years, DRAM has been highly integrated, and 1Gb DRAM prototype chips have already been announced. The biggest problem in realizing such a large-capacity DRAM is an increase in power consumption. The power consumption of DRAM can be divided into that due to memory arrays and those due to peripheral circuits, but the former usually occupies a large proportion. The power consumed by the memory array is due to charging / discharging of the parasitic capacitance Cd of the data line. However, as the capacity increases, the number of data lines simultaneously charged / discharged increases, so that the power consumption of the memory array increases.
[0003]
In order to reduce the charge / discharge power of Cd or increase the read signal of the memory cell, a method of hierarchizing the data line and dividing it into multiple layers has attracted attention. BMGB (Bidirectional Matched Global Bit Line) is a method that does not increase the chip area when the number of data line divisions is increased. Page).
[0004]
Figure 16 shows the BMGB memory array described in Fig. 1 of the above document. In this example, four pairs of data lines (D0-D0B, D1-D1B, etc.) are arranged between the sense amplifiers (SA), four pairs in the data line direction and two pairs in the word line direction. A memory cell (MC) is connected to the intersection of the word line (W) and the data line (D). A folded data line cell arrangement is used. Each D is provided with a data line connection switch (QT). Wire a global data line pair (GD-GDB) in parallel with D. Three GDs are arranged in the data line direction (GD0 to GD2) and connected to each other by a global data line separation switch (QM). Sense amplifiers (SA0, SA1) are connected to the GD pairs at both ends.
[0005]
The connection relationship between D and GD is as follows. D0-D0B and D1-D1B have QT0 and QT1 connected to the right ends, respectively. QT0 and QT1 are connected to GD0-GD0B and GD1-GD1B, respectively. D2-D2B and D3-D3B have QT2 and QT3 connected to the left end, respectively. QT2 and QT3 are connected to GD1-GD1B and GD0-GD0B, respectively. That is, in this example, QT and QM are concentrated on the switch block SWB. The other Ds are connected to GD in the same way.
[0006]
FIG. 16 shows switch control when data is read from the MC at the intersection of W0, D0, and D1. Only QT0 and QT1 are turned on, and other QTs are turned off. Turn off QM0-QM0B and turn on QM1-QM1B. Accordingly, D0-D0B is connected to SA0 via GD0-GD0B, and D1-D1B is connected to SA1 via GD1-GD1B and GD2-GD2B.
[0007]
In this method, the length of D connected to the sense amplifier becomes 1/4 compared to a normal array configuration, and Cd is reduced to 1/4. The extra parasitic capacitance of GD is connected accordingly, but D is connected to many memory cell transistors and the parasitic capacitance is large, whereas GD is a simple circuit using a wiring layer above D. Since it is a wiring, the parasitic capacitance is relatively small. Accordingly, the total parasitic capacitance connected to the sense amplifier is smaller than that of the conventional Cd. As a result, the charge / discharge power of the array can be reduced and the S / N ratio can be increased.
[0008]
FIG. 23 shows the conventional twist global data line shown in FIG. 2 of the above document. This is an example in which the GD line is twisted to reduce the coupling noise between GD. In the figure, the length of GD is 1024 word lines, and the length of D is 128 word lines. Here, the sense amplifier block SB includes a CMOS sense amplifier and the like. Also, D and QT are omitted.
[0009]
As shown in the figure, GD connected to SB0 and SB1 is twisted in the areas of QM0 and QM1, and GD connected to SB2 and SB3 is shifted by one line and twisted in the areas of QM6 and QM8. Other GDs are arranged so as to be repeated in the word line direction with the unit shown in FIG. 23 as a unit.
[0010]
[Problems to be solved by the invention]
(1) Problem of switch area
FIG. 17 shows an example of a plan view (layout) for realizing the BMGB type switch block SWB of FIG. 16 on a specific integrated circuit. It was assumed that the switches QT and QM can each be realized by one MOS transistor. Here, ACT is an active region for forming a MOS transistor, FG is a gate electrode, CONT is a conductive layer for forming D and a connection region for ACT, TC1 is a connection between a conductive layer for forming D and a conductive layer for forming GD It is an area. The layout shown in FIG. 17 assumes an ideal layout rule where the minimum processing dimension is F and the alignment margin between layers is 0. The layout can be done with 8F in the word line direction and 13F in the data line direction. The total length of the switch part in the array shown in 16 is 26F. However, in this layout, there are many wiring intersections, and there is a problem that the layout is difficult and the area becomes large. Furthermore, it is necessary to perform wiring by using a long and narrow diffusion layer at the intersection, and there is a problem that the resistance at the switch portion increases.
[0011]
(2) Problem of signal delay and power consumption when GD becomes long
In the array of FIG. 16, when the capacity of the chip is increased and the array size is increased, GD becomes longer, and there is a problem that signal delay and power consumption at GD increase.
[0012]
(3) S / N problem when GD becomes longer
There is a problem that the unbalance of the length of the global data line GD connected to SA0 and SA1 lowers the S / N. For example, when word line W0 is selected in FIG. 16, data pair lines D0-D0B are connected to SA0 via pair lines GD0-GD0B, while pair lines D1-D1B are paired lines GD1-GD1B and GD2- Connected to SA1 through GD2B. This method has inherent S / N problems as follows.
[0013]
Now, let Cd be the parasitic capacitance per D, Cgd is the parasitic capacitance of the same length as D of GD, and Cs is the memory cell capacitance. The parasitic capacitance connected to the input GD0 of SA0 is Csa0 (t) = Cs + Cd + Cgd because the memory cell is connected, and the parasitic capacitance connected to the input GD0B is Csa0 ( b) = Cd + Cgd. Similarly, the parasitic capacitance connected to the input GD1 of SA1 is Csa1 (t) = Cs + Cd + 3Cgd, and the parasitic capacitance connected to the input GD1B is Csa1 (b) = Cd + 3Cgd. Here, in SA0 and SA1, noise vn (0) and vn (1) caused by imbalance between input pair lines for the memory cell capacity is "VLSI LSI" (Ito Kiyoo, Baifukan, 1994 issue) , Page 205).
[0014]
vn (0) = A Cs {K0 / (Cd + Cgd)} ^ (1/2)
vn (1) = A Cs {K1 / (Cd + 3Cgd)} ^ (1/2)
Here, A is a proportionality constant, and K0 and K1 are the amplification rates of SA0 and SA1, respectively. If the parasitic capacitance of GD cannot be ignored, vn (0) may increase significantly compared to vn (1). That is, Cd + Cgd <Cd + 3Cgd, and when SA0 and SA1 are driven with the same driving force, SA0 having a small parasitic capacitance is quickly amplified and K0> K1.
[0015]
Further, as another noise, there is a possibility that coupling noise from D0-D0B to D1-D1B increases. As mentioned above, if there is a difference in the amplification speed between SA0 and SA1, D0-D0B is amplified to a large amplitude quickly, so it is amplified slowly, so D1 is still in a small signal state. This is because the capacitive coupling noise to -D1B cannot be ignored.
[0016]
(4) GD coupling noise problem
In the GD twist method shown in FIG. 23, the coupling is unbalanced in the worst case, and noise cannot be completely canceled.
[0017]
Consider the worst case where the read signal amount is the smallest, in FIG. 23, where QM0 and QM5 are turned off and other QMs are turned on. Assume that the SA in SB1 is activated from the state where all GDs are precharged to 1V and are floating, and the sense amplifier node I1 is amplified to 2V and I1B is amplified to 0V. At this time, consider the coupling noise received by GD connected to I3 and I3B. First, for I3, GD9 receives a negative coupling from GD4B and GD6 receives a positive coupling from GD1. However, since the length of GD9 is 128W and the length of GD6 is 256W, the positive coupling becomes twice as large and the positive noise of 128W remains without being canceled. Next, for I3B, GD8B receives a negative coupling from GD3B, and GD7B receives a positive coupling from GD2. In this case, the length of both GD8B and GD7B is 256 W, and the positive and negative couplings are cancelled. Accordingly, since the noise received by I3 and I3B is different, the operating margin of SA in SB3 is reduced.
[0018]
Conversely, consider the coupling noise received by GD connected to I1 and I1B when SA in SB3 is activated to amplify sense amplifier node I3 to 2V and I3B to 0V. First, for I1, GD2 receives a negative coupling from GD7B and GD1 receives a positive coupling from GD6. In this case, the length of both GD2 and GD1 is 256W, and the positive / negative coupling is canceled. Next, for I1B, GD4B receives a positive coupling from GD9 and GD3B receives a negative coupling from GD8B. However, since the length of GD4B is 128 W and the length of GD3B is 256 W, the negative coupling is twice as large, and the negative noise of 128 W remains without being canceled. Therefore, in this case as well, the noise received by I1 and I1B is different, so the operating margin of the SA in SB1 decreases.
[0019]
An object of the present invention is to provide a hierarchical data line DRAM.
(1) To provide a circuit system that does not increase the chip area when the number of data line hierarchies is reduced and the number of data line divisions is increased.
[0020]
(2) Further, it is to suppress an increase in signal delay and power consumption in the global data line.
[0021]
(3) It is another object of the present invention to provide an operation method that does not lower the S / N even if the parasitic capacitance of the global data line is unbalanced.
[0022]
(4) Another object is to reduce coupling noise between global data lines.
[0023]
[Means for Solving the Problems]
  The following is a brief description of an outline of typical inventions disclosed in the present application.
[0024]
  [1] A plurality of memory arrays, and each of the plurality of memory arrays includes a first sense amplifier, a first switch block, a first memory block disposed adjacent to the first switch block, and the first A second switch block disposed adjacent to one memory block; a second memory block disposed adjacent to the second switch block; and a third switch block disposed adjacent to the second memory block. And a second sense amplifier.
[0025]
  At this time, each of the first and second memory blocks includes a first data line extending in a first direction, a second data line arranged in parallel to the first data line, and the first data line. Main data lines arranged in parallel to each other, a plurality of word lines extending in the second direction and intersecting the first and second data lines, the plurality of word lines and the first and second data lines And a plurality of memory cells provided at predetermined intersections.
[0026]
  The first sense amplifier is connected to a main data line of the first memory block, and the second sense amplifier is connected to a main data line of the second memory block.
[0027]
  The first switch block includes a first switch connected to the first data line of the first memory block and a main data line of the first memory block.
[0028]
  The second switch block includes a second switch that connects the second data line of the first memory block and a main data line of the second memory block, and the main data line of the first memory block and the second data block. A third switch that connects the main data lines of the two memory blocks; and a fourth switch that connects the first data line of the second memory block and the main data lines of the first memory block.
[0029]
  The third switch block includes a fifth switch that connects the main data line of the second memory block and the second data line of the second memory block.
[0030]
  [2] In the above [1], each of the first and second data lines has a folded data line structure, and the main data line is a complementary main data line pair.
[0031]
  [3] In the above [1] or [2], one end of the first switch block is adjacent to one end of the first memory block, and the other end of the first memory block is connected to the second switch block. Adjacent to one end, the other end of the second switch block is adjacent to one end of the second memory block, and the other end of the second memory block is adjacent to one end of the third switch block.
[0032]
  [4] In any one of [1] to [3], in the first memory block, one of the plurality of word lines is a first memory provided at an intersection with the first data line. The second memory cell provided at the intersection of the cell and the second data line is selected, and the third switch is turned off and the first and second switches are turned on. The data of the first memory cell is amplified by the first sense amplifier, and the data of the second memory cell is amplified by the second sense amplifier.
[0033]
  [5] In the above [4], from one period in which one of the plurality of word lines selects the first and second memory cells to a second period in which the first and second sense amplifiers are activated. In the meantime, the first switch is turned off for a predetermined period.
[0034]
  [6] In any one of the above [1] to [4], each of the first and second sense amplifiers includes a cross-coupled P-type MOSFET pair, and the first and second data lines Are connected to third and fourth sense amplifiers having cross-coupled N-type MOSFET pairs.
[0035]
  [7] In any one of the above [1] to [4], each of the first and second data lines has a voltage - The current conversion type third and fourth sense amplifiers are connected.
[0036]
  [8] In any one of the above [1] to [7] 7, each of the plurality of memory cells includes one MOS transistor and one capacitor.
[0037]
  [9] In any one of [1] to [8], the semiconductor memory device further includes a plurality of column selection lines extending in the first direction, and the first data line The first data line has an inverted first data line, the second data line has a non-inverted second data line and an inverted second data line, and the main data line has non-inverted main data. And four data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer, and the non-inverted main data line is formed. The inverted main data line and the column selection line are formed in a second wiring layer on the first wiring layer, and the non-inverted and inverted main data lines are adjacent to each other among the four data lines. Two data lines are wired at one pitch.
[0038]
  [10] In any one of [1] to [8], the semiconductor memory device further includes a plurality of column selection lines extending in the first direction, and the first data line The first data line has an inverted first data line, the second data line has a non-inverted second data line and an inverted second data line, and the main data line has non-inverted main data. And four data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer, and the non-inverted main data line is formed. And the inverted main data line is formed in a second wiring layer on the first wiring layer, and the plurality of column selection lines are formed on a second wiring layer on the second wiring layer. Three The non-inverted and inverted main data lines are formed in a wiring layer, and are arranged at a pitch of two adjacent data lines of the four data lines, respectively, and the column selection lines are the data lines. Wiring is performed at a pitch of 4 or more.
[0039]
  [11] In any one of [1] to [8], the semiconductor memory device further includes a plurality of column selection lines extending in the first direction, and the first data line The first data line has an inverted first data line, the second data line has a non-inverted second data line and an inverted second data line, and the main data line is a non-inverted main data line And four main data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer, and The inverted main data line and the column selection line are formed in a second wiring layer on the first wiring layer, and the pitches of the non-inverted and inverted main data lines are adjacent to each other among the four data lines. It can be wider than two pitches.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). The MOS transistor circuit symbol without an arrow represents an N-type MOS transistor (NMOS), and is distinguished from a P-type MOS transistor (PMOS) with an arrow.
[0041]
(Reference example)
  Figure 1To1 shows a memory array (1) of a switch-separated hierarchical data line system DRAM. This example shows an example in which eight pairs (D0-D0B, D1-D1B, etc.) of data lines are arranged between the sense amplifiers (SA) in four pairs in the data line direction and two pairs in the word line direction. A memory cell (MC) is connected to the intersection of the word line (W) and the data line (D). The cell arrangement (1) of the folded data line method is used, and there is MC at the intersection of W0 and D0, but there is no MC at the intersection of W0 and D0B, and every other data line D0-D0B , D1-D1B are paired. The cells are repeatedly arranged in the data line direction with the cell block UCB1 shown in the figure as a unit. Each D is provided with a data line connection switch (QT). If attention is paid to the data line related to D0, it can be seen that the original one long data line is divided into four sections (D0, D3,...).
[0042]
Wire a global data line pair (GD-GDB) in parallel with D. Three GDs are arranged in the data line direction (GD0 to GD2) and connected by a global data line separation switch (QM) connected in series with each other. Focusing on the global data line related to GD0, the first and second global data lines, which were originally one long global data line, are divided into three sections (GD0, GD1, GD2). It can also be seen that the second switch (a pair of QM0T and QM1T and a pair of QM2T and QM3T) is connected. Sense amplifiers (SA0, SA1) are connected to the GD pairs at both ends.
[0043]
The data line and the global data line may be called a sub data line and a main data line, respectively, in order to make the hierarchical structure clearer. Also, the main and sub data lines are provided in a complementary manner for differential amplification. As an example, the non-inverted sub-data line D0 and the inverted sub-data line D0B form a sub-data line pair (referred to simply as a sub-data line), and the non-inverted main data line GD0 and the inverted complementary data line GD0B are main data. A line pair (for convenience, called a main data line) is formed.
[0044]
QT0T and QT0B are connected to D0 and D0B at the right end, QT0T is connected to the connection point of GD0 and QM0T, and QT0B is connected to the connection point of GD0B and QM0B. On the other hand, QT1T and QT1B are connected to D1 and D1B at the right end, QT1T is connected to the connection point between QM0T and QM1T, and QT1B is connected to the connection point between QM0B and QM1B. Further, QT2T and QT2B are connected to D2 and D2B at the left end, QT2T is connected to a connection point between QM0T and QM1T, and QT2B is connected to a connection point between QM0B and QM1B. On the other hand, QT3T and QT3B are connected to D3 and D3B at the left end, QT3T is connected to the connection point of GD1 and QM1T, and QT3B is connected to the connection point of GD1B and QM1B. In FIG. 1, when data is read from the MC at the intersection of W0, D0, and D1, T0 is activated, QT0T-QT0B and QT1T-QT1B are turned on, and the other QTs are turned off. QM0T-QM0B is turned off and other QMs are turned on. Accordingly, D0-D0B is connected to SA0 via GD0-GD0B, and D1-D1B is connected to SA1 via GD1-GD1B and GD2-GD2B.
[0045]
The array of the present invention connects two global data line separation switches in series and uses them independently on both data lines, that is, the left switch is used for the left data line separation and the right switch Is used for right data line separation.
[0046]
The advantage of the present invention is that when connecting a data line connection switch, a global data line, and a global data line separation switch, the circuit layout becomes easier to reduce the number of wiring crossings, and the conventional BMGB method The area can be made smaller than the array. FIG. 2 (a) shows a layout of the switch block SWB1 of the array (1). Here, ACT is an active region for forming a MOS transistor, CONT is a connection region between the conductive layer forming D and the ACT, and TC1 is a connection region between the conductive layer forming D and the conductive layer forming GD. This layout assumes an ideal layout rule where the minimum processing dimension is F and the alignment margin between layers is zero. The layout can be 8F in the word line direction and 9F in the data line direction, and the total switch overhead between the sense amplifiers is 18F. This is smaller than the value 26F of the conventional example. The area reduction effect of the entire chip is as follows. As the chip capacity increases, the number of data line divisions, that is, the number of switches increases. In 1Gb DRAM, the number of word lines is 32K, and if the number of cells connected to a pair of data lines is 128 and four data lines are arranged in the data line direction between the sense amplifiers, the entire chip has 32K / ( 128x4) = 64 switches are required. Therefore, compared with the conventional example, the length of the chip can be shortened by L = (26F-18F) × 64 = 512F in the data line direction. If F = 0.15 μm, then L = 76.8 μm.
[0047]
In Fig. 1, four data lines are arranged between SA0 and SA1 in the data line direction. However, if there are two data lines, SA1 is connected to GD1 and QM is not required. What is necessary is just to isolate GD1. Therefore, in this case, the chip area can be reduced by QM. Further, the number of data lines arranged between SA0 and SA1 can be increased in units of GRN shown in FIG.
[0048]
(Reference example)
  In the memory array (2) shown in FIG. 3, the memory cell arrangement is the folded data line type cell arrangement (2) in the switch separation type hierarchical data line type shown above. The cells are repeatedly arranged in the data line direction with the cell block UCB2 shown in the figure as a unit. However, the connection between the sense amplifier and the data line is different from the normal folded data line system. Out of the four lines aligned in the word line direction, the outer two D0-D0B and the inner two D1-D1B are paired respectively. Become.
[0049]
When the sense amplifier and the data line are connected in this way, there is an advantage that even if a folded data line type cell arrangement is used, there is no crossing of wiring in the switch portion, and the area can be reduced.
[0050]
(Reference example)
  In the memory array (3) shown in FIG. 4, the arrangement of memory cells is the folded data line type cell arrangement (2) in the switch separation type hierarchical data line type shown above. The cells are repeatedly arranged in the data line direction with the cell block UCB2 shown in the figure as a unit. The connection between the sense amplifier and the data line is also a normal folded data line system, and two adjacent lines in the word line direction are paired.
[0051]
By connecting the sense amplifier and the data line in this way, there is an advantage that the coupling noise between the data lines can be minimized.
[0052]
(ImplementationExample )
  FIG. 5 shows a memory array (4) of the switch alternate arrangement type hierarchical data line type DRAM of the present invention. This example shows an example in which eight pairs (D0-D0B, D1-D1B, etc.) of data lines are arranged between the sense amplifiers (SA) in four pairs in the data line direction and two pairs in the word line direction. A memory cell (MC) is connected to the intersection of the word line (W) and the data line (D). The cell arrangement (UCB2) of the folded data line system is used, and the connection between the sense amplifier and the data line is a normal folded data line system in which two adjacent lines in the word line direction are paired. Each D is provided with a data line connection switch (QT). Wire a global data line pair (GD-GDB) in parallel with D. Three GDs are arranged in the data line direction (GD0 to GD2) and connected to each other by one global data line separation switch (QM0, QM1, etc.). Sense amplifiers (SA0, SA1) are connected to the GD pairs at both ends.
[0053]
D0-D0B has QT0 connected to the left end, and D1-D1B has QT1 connected to the right end. QT0 and QT1 are connected to GD0-GD0B and GD1-GD1B, respectively. D2-D2B has QT2 connected to the left end, and D3-D3B has QT3 connected to the right end. QT2 and QT3 are connected to GD0-GD0B and GD1-GD1B, respectively.
[0054]
The memory array of this embodiment is characterized in that data line connection switches of adjacent data line pairs are alternately arranged, that is, arranged on opposite sides to the data lines. The other Ds are connected to GD in the same way.
[0055]
The layout of switch blocks SWB4 to SWB6 is shown in Figure 18, but the pitch of the data line connection switches (QT0T-QT0B, etc.) in the word line direction is relaxed to twice the pitch of the data lines in the word line direction. Is to be easier.
[0056]
(Reference example)
  Fig. 6To2 shows a memory array (5) of a switch alternate arrangement type hierarchical data line system DRAM.This exampleThis array is characterized in that the data line connection switches (QT0, QT1, etc.) of adjacent data line pairs are on the same side with respect to the data lines and are shifted in the data line direction.
[0057]
The advantage of this embodiment is that the pitch of the data line connection switches in the word line direction is relaxed to twice the pitch of the data lines in the word line direction, and the circuit layout becomes easy.
[0058]
(Reference example)
  FIG.ToA chip configuration when a column decoder is shared by a plurality of column switches in the data line direction (YS control method) in the switch separation type hierarchical data line method or the switch alternate arrangement type hierarchical data line method is shown. This chip is roughly divided into a memory mat (MAT0) and peripheral circuits. Although not shown in the figure, a plurality of memory mats can be provided in the chip. The memory mat has a hierarchical structure such as a sub memory array (SMA0, SMA1,...) And a unit memory array (UA0, UA1,...) In order from a large part to a small part. In UA, an element unit memory array (PUA) in which memory cells, data line connection switches, and global data line separation switches are arranged, and sense amplifier blocks (SB) consisting of sense amplifiers, precharge circuits, and column switches are alternately arranged. Be placed. Here, the word lines (W) are wired in the vertical direction, and the data lines are wired in the horizontal direction.
[0059]
The peripheral circuit will be described. For the address terminal (A), an address multi system in which a row address (XAD) and a column address (YAD) are inputted in a time-division manner is usually used. XAD is stored in the row address latch (XLTC) by lowering the row address strobe signal (RASB), and YAD is stored in the column address latch (YLTC) by lowering the column address strobe signal CASB. If there is a margin in the address terminals, a full address system in which XAD and YAD are input simultaneously may be used. XAD is input to the row control circuit (XC), and control signals PC, M, and T described later are generated. XAD is decoded by a row decoder (Xdec), and the corresponding W is selected. When data is read from the memory cell connected to W, the data is amplified by the sense amplifier control signals SN and SP generated from XC. YAD is decoded by the column decoder (Ydec), and the column selection line (YS) is selected. Ydec is shared by column switches in a plurality of SBs, and YS is commonly input to the plurality of SBs. In the case of reading, the data of the column selected by YS is read to the common input / output line pair (I / O) via the column switch, and input / output by the read / write circuit (RWC) and output buffer (DOB) Read out of the chip from the pin (DQ). In the case of writing, data from outside the chip is written to the memory cells in the column selected by YAD via the input buffer (DINB), RWC, and I / O.
[0060]
In the following description, details of the portion of UA0 in FIG. 7 will be described. FIG. 8 (a) shows an array (6) in which the YS control method is applied to the switch-separated hierarchical data line array (1) of the present invention shown in FIG. 1 (Embodiment 1). Similarly, the YS method can be applied to the array shown in FIG. QT is connected to global data lines (GD0-GD0B to GD2-GD2B) in which 2 pairs in the word line direction and 4 pairs in the data line direction (D0-D0B, D1-D1B, etc.) are wired in parallel with the data lines. To form a single element unit memory array (PUA0). Global data line pairs GD0-GD0B and GD1-GD1B are connected to each other via QM0T-QM0B and QM1T-QM1B, and GD1-GD1B and GD2-GD2B are connected to each other via QM2T-QM2B and QM3T-QM3B. A sense amplifier block (SB) is connected to the GD pair at both ends. As shown in FIG. 7, another element unit memory array PUA1 is connected to the right side of SB1. SB includes a CMOS sense amplifier (SA), a precharge circuit (PB), and a column switch (YG). YG and a read / write circuit (RWC) are connected to the main input / output line pair (I / O-I / OB). Specific circuit diagrams of MC, SA, PB, and YG are shown in FIGS. 8 (b), (c), (d), and (e). The CMOS sense amplifier SA is composed of a pair of P-type MOS transistors and a pair of N-type MOS transistors whose sources are commonly connected and whose gates and drains are cross-coupled. A column selection line (YS) is connected to the output of Ydec, and YGs with the same YAD are commonly controlled by one YS0.
[0061]
In this embodiment, one unit memory array (UA) is divided into a plurality of PUAs and SBs. This has the effect of suppressing signal delay and power consumption on the global data line when the degree of integration of the memory increases and UA becomes longer. In addition, since a plurality of column switches in the data line direction are commonly controlled by YS, even if the number of UA divisions is increased, only one Ydec is required, so that an increase in chip area can be prevented. The same effect can be obtained even if the number of MCs connected to one data line pair, the number of GD pairs in the PUA, and the number of PUAs in one UA are different from those shown in this example. can get.
[0062]
FIG. 2 (b) shows a switch layout in the memory array (6). FIG. 9 shows a cross-sectional structure taken along line BB ′ of FIG. 2 (b).
[0063]
As shown in the circuit diagram of FIG. 8, in this embodiment, one global data line may be wired for two data lines. Usually, in the wiring process, the upper layer becomes difficult to be miniaturized, so the pitch of the upper layer needs to be large. In the array of this embodiment, even if the global data line and YS are wired using the same wiring layer above the data line as shown in FIG. 9, the wiring pitch of this layer is larger than the pitch of the data line layer. This condition is satisfied by increasing. Therefore, if the global data line and YS are wired using the same wiring layer, there is an advantage that the number of wiring layers does not increase.
[0064]
On the other hand, YS can be wired using a wiring layer that is further higher than the global data line. In this case, since the pitch of the YS wiring layer can be widened, there is an advantage that the coupling capacitance between the wirings is reduced and the signal transmission speed is increased.
[0065]
In the cross-sectional view of FIG. 9, if a refractory metal such as polysilicon, a compound of polysilicon and metal, or tungsten is used as the wiring material for the gate (T1 etc.) and data line (D1 etc.) of the MOS transistor, the memory is used thereafter. There is an advantage that the cell is not affected by the high temperature process. In addition, when GD and YS are made of a low resistance material such as aluminum or copper, there is an advantage that signal delay can be suppressed.
[0066]
The memory access, that is, the read and write operations from the memory cell by the circuit shown in FIG. 8 will be described below with reference to FIGS.
[0067]
FIG. 10 is a timing chart showing the read operation of the circuit of FIG. . Here, data is read from the MC at the intersection of W0 and D0. In the initial state where RASB is 2V, precharge signals PC0 and PC1 are 2V, global data line separation switch control lines M0 to M3 and data line connection switch control lines T0 to T3 are 2.5V, and all D is GD Is precharged to 1V. From this state, RASB is lowered to 0V to determine the row address, and then PC0, PC1, M0, and T1 to T3 are lowered to 0V. M1 to M3 and T0 remain at 2.5V. As a result, D0-D0B is connected to SA0 via GD0-GD0B, and D1-D1B is connected to SA1 via GD1-GD1B and GD2-GD2B, and enters a floating state. The other D is disconnected from the GD. Here, raise W0 to 2.5V. Then, a signal of about 0.1 V is output from MC on D0, and a potential difference is generated between D0 and D0B. Therefore, the potential difference is amplified by SA0 by changing the sense amplifier NMOS drive line SN0 to 0V and the sense amplifier PMOS drive line SP0 to 2V. At the same time, a signal is also output to D1, which is amplified by SA1. Since GD0 and GD1 are separated by QM0T, data does not collide. After the potential difference of D0-D0B is sufficiently amplified, CASB is lowered to 0V to determine the column address, YS0 is raised to 2V, YG is opened, and GD0-GD0B and I / O0-I / O0B are connected. I / O0-I / O0B is precharged to 1V in the initial state, but by opening YG0, complementary data on GD0-GD0B appears in I / O0-I / O0B. In order to increase the speed, a bias circuit is provided in RWC0 to reduce the signal on I / O0-I / O0B to a small amplitude of 0.5V. RWC0 amplifies the complementary data on the I / O line pair and transmits it to the output buffer, and the output buffer outputs the data outside the chip. After CASB returns to 2V again, return YS0 to 0V and close YG. After RASB returns to 2V, WL0 is lowered to 0V, and data is again written to MC from D0 and D1. After that, return SN0, SP0, SN1, SP1 to 1V, raise PC0, PC1, M0, T1 to T3 to 2.5V, and precharge D0-D0B, D1-D1B to 1V again to finish.
[0068]
FIG. 11 shows the write operation. Data is written to MC at the intersection of W0 and D0 in the same way as reading. First, control similar to the above read operation is performed, and old information is read from the MC. After the potential difference between D0 and D0B is sufficiently amplified by SA0, CASB is lowered to 0V to determine the column address. As a result, I / O0-I / O0B are driven complementarily by the RWC corresponding to the write data. At the same time, YS0 is raised to 2V, YG0 is opened, and data on I / O0-I / O0B is written to D0-D0B through GD0-GD0B. After CASB returns to 2V again, return YS0 to 0V and close YG0. After RASB returns to 2V again, an end operation similar to that of the read cycle is performed to complete the write cycle.
[0069]
(Reference example)
  FIG.To2 shows a sense amplifier drive circuit SAD in the switch alternate arrangement type hierarchical data line system. This circuit is included in XC. The feature of this sense amplifier drive circuit is that the drive capability of the sense amplifier can be made variable according to the change in the load to be driven by the sense amplifier according to the open / close state of the global word line isolation switch. . SAD0 includes NMOS transistors DNL0 and DNS0 for driving SN0, and PMOS transistors DPL0 and DPS0 for driving SP0. Here, the current drive capability of DNL0 is made larger than that of DNS0. Therefore, for example, the gate lengths of DNL0 and DNS0 are made equal, and the gate width of DNL0 is increased. Similarly, the current driving force of DPL0 is made larger than that of DPS0. SAD1 has a similar configuration.
[0070]
When word line W0 is selected in FIG. 12, data pair line D0-D0B is connected to SA0 through pair line GD0-GD0B, and pair line D1-D1B is connected through pair lines GD1-GD1B and GD2-GD2B. Connected to SA1. Here, GD0 and GD2 have almost the same length as D, but GD1 has a length corresponding to two of D. Therefore, the length of GD connected to SA0 is the same as D, but the length of GD connected to SA1 is three times that of D, and the parasitic capacitance connected to the sense amplifier is greater for SA1 than for SA0. Is also big.
[0071]
FIG. 10 shows a timing chart at the time of reading. At this time, SAD0 raises STS0 to 2V, turns on DNS0 and DPS0, SAD1 raises STL1 to 2V, and turns on DNL1 and DPL1. In other words, for SA0 with a small load capacity, SN0 and SP0 are driven by DNS0 and DPS0 with a small driving capacity, and for SA1 with a large load capacity, SN1 and SP1 are driven by DNL1 and DPL1 with a large driving capacity. Thus, the amplification rates of SA0 and SA1 are set to be approximately equal. Here, when the word line crossing GD2 is selected, the load on SA1 is smaller than that on SA0, so STS1 and STL0 are raised to 2V, and SN0 and SP0 have greater driving power DNL0 and DPL0 Drive with.
[0072]
Therefore, according to this method, even if there is an imbalance in the length of the global data line, there is an advantage that the S / N is not lowered because there is no fear that SA0 having a small load is amplified at an excessively high speed.
[0073]
In order to eliminate the influence of the load imbalance between the sense amplifier input pair lines due to the cell capacity, the driving method shown in FIG. 13 can be adopted. After raising W0 to 2.5V and reading signals to D0 and GD0, T0 is momentarily lowered to 0V, and the sense amplifier is activated while increasing the resistance of QT. Amplification is performed in a state where SA0, D0, and D0B are separated by high resistance, and the cell capacity is almost invisible to the sense amplifier, so the load on the input pair line becomes equal and the S / N increases.
[0074]
The above shows that when four data lines are arranged in the data line direction between the sense amplifiers, the unbalance of the length of GD connected to the sense amplifiers on both sides is 3: 1. However, when the capacity of the memory chip increases, it is necessary to arrange eight data lines in the data line direction between the sense amplifiers in order to reduce the number of sense amplifiers. In this case, the GD length imbalance increases to 7: 1, and the above control method becomes more important.
[0075]
(Reference example)
  FIG.ToThe Mori array (7) is shown. A modification of PUA0 in FIG. This embodiment is a modification of the array (4) in FIG. When an N-channel MOS transistor is used as the MC transfer gate, a sense amplifier NSA made of NMOS is provided on D instead of the CMOS sense amplifier SA in the array (4) in FIG. A sense amplifier PSA is provided. Other data line pairs have the same configuration as D0-D0B and D1-D1B. When NSA is arranged on D in this way, since N-channel MOS transistors are used for both MC and NSA, it is not necessary to provide an N / P isolation region for each data line. Only the part of the PSA on the GD needs the N / P separation region. Therefore, even if NSA is provided on D, the area increase is small. When a PMOS is used as the MC transfer gate, a PMOS sense amplifier PSA is provided on D instead of the CMOS sense amplifier SA in the array (4) of FIG. 5, and an NMOS sense amplifier NSA is provided in the SB on GD. Is provided.
[0076]
At the time of reading, after precharging is stopped, all of T0 to T7 are closed, W0 is activated, and a signal is read on D0 and D1. Thereafter, SN0 and SN1 are lowered to 0V to amplify the signal. At this time, the data line pair is amplified to approximately 0V and 1V. Then, T0 and T1 are opened and signals are read on GD0 and GD1, then SP0 and SP1 are raised to 2V, and the data lines are amplified to 0V and 2V.
[0077]
Thus, by initially performing the initial amplification in the data line, the influence of the parasitic capacitance of the global data line on the S / N can be eliminated. Therefore, this embodiment is effective in increasing the S / N when the chip has a large capacity and the PUA becomes long.
[0078]
In addition, since the data line connection switches (QT) are alternately arranged in this array, the length of the NSA in the word line direction can be obtained for two pairs of data lines, and there is an advantage that the layout becomes easy.
[0079]
(Reference example)
  Figure 15ToThe Mori array (8) is shown. PUA0 etc. in Fig. 8Modified exampleAre omitted. This embodiment is a modification of the array (4) in FIG. When an N-channel MOS transistor is used as the MC transfer gate, a sense amplifier DSA made of NMOS is provided on D, and a CMOS sense amplifier SA is provided in SB on GD. Here, DSA is a voltage / current conversion circuit (or a voltage / current conversion type sense circuit). Other data line pairs have the same configuration as D0-D0B and D1-D1B. When DSA is arranged on D in this way, since N-channel MOS transistors are used for both MC and DSA, it is not necessary to provide an N / P isolation region for each data line. Only the SA portion on the GD needs an N / P isolation region. Therefore, even if DSA is provided on D, the area increase is small. When a PMOS is used as the MC transfer gate, a DSA comprising a PMOS sense amplifier is provided on D.
[0080]
At precharge, all TW are 2.5V, all TR are 0V, M0 and M1 are 2.5V. When reading data from the MC at the intersection of W0, D0, and D1, after stopping precharge, all TW are lowered to 0V, TR0 and TR1 are raised to 2.5V, and M1 is lowered to 0V. Raise W0 to 2.5V, read the signal on D0, and convert the voltage difference between D0 and D0B to a current difference with DSA0. The current difference between GD0 and GD0B is transmitted to RWC0 via the YG and IO pairs in SB0 by raising YS to 2V. At the same time, SP0 of SA0 is driven to 2V and SN0 is driven to 0V to amplify GD0-GD0B to 0V and 2V. The signal on D1 is similarly processed by SB1. At the time of rewriting, TR0 and TR1 are lowered to 0V, TW0 and TW1 are raised to 2.5V, and a voltage of 0V or 2V is written to the memory cell.
[0081]
Thus, by performing voltage / current conversion in the data line, the influence of the parasitic capacitance of the global data line on the S / N can be eliminated. Therefore, this embodiment is effective in increasing the S / N when the chip has a large capacity and the PUA becomes long. Also, even if TR and YS are raised before W is raised to 2.5 V, information is not read out by mistake, so there is no timing margin in this part, and high-speed reading is possible.
[0082]
In addition, since the data line connection switches (QT) are alternately arranged in this array, the length of the DSA in the word line direction can be obtained for two pairs of data lines, and there is an advantage that the layout becomes easy.
[0083]
(Reference example)
  the aboveExampleWhen YS is wired for each pair of GDs as shown in, coupling noise from other GD pairs is shielded. However, when the minimum pitch allowed for the GD and YS wiring layers is large and YS can be wired only for each of a plurality of GD pairs, coupling noise from other GD pairs becomes a problem.
[0084]
FIG. 19 shows a twisted global data line (1) of the present invention. This is an example in which the GD line is twisted to reduce the coupling noise between GD. In the figure, the length of GD is 1024 word lines, and the length of D is 128 word lines. Here, the sense amplifier block SB includes the CMOS sense amplifier, precharge circuit, and column switch shown in FIG. Also, D and QT are omitted.
[0085]
As shown in the figure, the memory array is configured as follows. Two sets of GD and two sets of QM form a global data line group GDG. A global data line unit GDU is formed by two sets of GDGs. The memory array is configured by repeatedly arranging GDUs in the data line direction and the word line direction. At least two sense amplifier blocks SB are connected to each global data line row in which GDGs are arranged in the data line direction.
[0086]
In GDG1, GD twists in the QM2 region, and in GDG2, twists in the QM6 region. In the case of the switch separation type, for example, SWB1 in FIG. 1 is twisted, and in the case of the switch alternate arrangement type, twisting is performed at SWB4 in FIG.
[0087]
This embodiment can also be considered for the following. First, there is a first main data line pair, which is divided into a plurality of parts (divided into five parts, GD0, GD1, GD2, GD3, and GD4) having substantially the same length. Then, the division points are connected by main data line separation switches (QL0, QM0, QM1, QM2, QM3, QMR0). The same is true for the second main data line pair adjacent to the first main data line pair. Finally, for the first main data line pair, if the main data line separation switch is numbered starting from 1 from the left (note that it does not coincide with the reference symbol, an even-numbered main data line separation switch ( Twist the main data line pair in the vicinity of QM0, QM2, QMR0). Conversely, the second data line pair twists the main data line pair in the vicinity of the odd-numbered main data line separation switches (QML1, QM5, QM8). In this way, the coupling noise can be effectively canceled by making the lengths of the divided divisions of the main data line pairs to be divided and shifting the twist positions of the adjacent main data line pairs by a half cycle.
[0088]
The difference from the conventional example is that, for example, GD0 is extended to the opposite array without being separated at SB0, and both GDs share SB and are separated by the QM of the opposite array. Therefore, all the GDs have almost the same length and intersect with almost the same number of word lines. In addition, the SB connection position should be approximately the middle of GD.
[0089]
In the GD twist method of the present invention, there is no unbalanced coupling in the worst case, and noise can be completely canceled. When redundant circuits are used, the number of intersecting word lines may differ depending on the number of GD, or the SB connection position may deviate by several from the center. , Coupling noise can be tolerated.
[0090]
Consider the worst case in which the read signal amount is the smallest, in FIG. 19, where QM0 and QM5 are turned off and other QMs are turned on. The GD of the adjacent mat is separated by QML0, QMR0, etc. Therefore, all GD is 256W in length. Assume that SA in SB1 is activated from the state where GD is precharged to 1V and is floating, and the sense amplifier node I1 is amplified to 2V and I1B is amplified to 0V. At this time, consider the coupling noise received by GD connected to I3 and I3B. First, for I3, GD9 receives a negative coupling from GD4B and GD6 receives a positive coupling from GD1. However, the length of both GD9 and GD6 is 256W, and the positive and negative couplings are cancelled. Next, for I3B, GD8B receives a negative coupling from GD3B, and GD7B receives a positive coupling from GD2. However, the length of both GD8B and GD7B is 256W, and the positive / negative coupling is canceled. Accordingly, the noise received by I3 and I3B is canceled, so the SA operating margin in SB3 does not decrease.
[0091]
Conversely, consider the coupling noise received by GD connected to I1 and I1B when SA in SB3 is activated to amplify sense amplifier node I3 to 2V and I3B to 0V. First, for I1, GD2 receives a negative coupling from GD7B and GD1 receives a positive coupling from GD6. However, the length of both GD2 and GD1 is 256W, and the positive and negative couplings are cancelled. Next, for I1B, GD4B receives a positive coupling from GD9 and GD3B receives a negative coupling from GD8B. However, the length of both GD4B and GD3B is 256W, and the positive and negative couplings are cancelled. Accordingly, in this case as well, the noise received by I1 and I1B is canceled, so the SA operating margin in SB3 does not decrease.
[0092]
Therefore, the twisted global data line of the present invention has an advantage that there is no imbalance in coupling in the worst case, and noise can be completely canceled.
[0093]
FIG. 21 shows a switch layout when the GD is twisted at the SWB4 portion of FIG. 5 in the case of the switch alternate arrangement type. The data line direction can be laid out with a length of 9F, and a data line twist can be realized with a small overhead compared to 7F in FIG.
[0094]
(Reference example)
  Figure 20, TsuThe ist global data line (2) is shown. Similar to the above example, the length of GD is 1024 word lines, and the length of D is 128 word lines. Here, the sense amplifier block SB includes the CMOS sense amplifier, precharge circuit, and column switch shown in FIG. Also, D and QT are omitted.
[0095]
As shown in the figure, the memory array is configured as follows. Two sets of GD and two sets of QM form a global data line group GDG. A global data line unit GDU is formed by two sets of GDGs. The memory array is configured by repeatedly arranging GDUs in the data line direction and the word line direction. At least two sense amplifier blocks SB are connected to each global data line row in which GDGs are arranged in the data line direction.
[0096]
In this embodiment, GDG1 is twisted at the center of GD2, and GDG2 is twisted at the center of GD6. The twist region is the SB region and, for the switch separation type, for example, the middle point portion of GD1 in FIG. 1, and the switch alternate arrangement type is a portion of SWB5 in FIG. As can be seen from a comparison with FIG. 19, the main data line is divided into substantially the same length as in the previous embodiment. In FIG. 19, the twist position is placed in the vicinity of the global data line separation switch, which is the division position of the main data line, whereas in this embodiment, the twist position is placed in the middle of the division position.
[0097]
Also in this embodiment, GD0 is extended to the opposite array without being separated at SB0 as in the previous embodiment, and both GDs share SB and are separated by the QM of the opposite array. Therefore, all the GDs have almost the same length and intersect with almost the same number of word lines. In addition, the SB connection position should be approximately the middle of GD. When a redundant circuit is used, the number of intersecting word lines may differ by several GD depending on the GD, but if this degree of imbalance is present, coupling noise can be allowed.
[0098]
In this embodiment, by performing twisting at the center of GD, adjacent GDs in units of GD, such as GD1-GD1B and GD6-GD6B, can cancel noise. Therefore, not only the worst case, but also when reading a signal from any data line, there is a feature that there is no imbalance in coupling and noise can be completely canceled.
[0099]
As an example, consider the worst case in which the read signal amount is the smallest, in which QM0 and QM5 are turned off and other QMs are turned on in FIG. The GD of the adjacent mat is separated by QML0, QMR0, etc. Therefore, all GD is 256W in length. Assume that SA in SB1 is activated from the state where GD is precharged to 1V and is floating, and the sense amplifier node I1 is amplified to 2V and I1B is amplified to 0V. At this time, consider the coupling noise received by GD connected to I3 and I3B. First, GD6 and GD6B both receive negative coupling from GD1B, but the length of the portion of GD that receives the coupling is the same, and I3 and I3B generate noise of the same phase and the same magnitude. The margin does not decrease. The same applies when both GD8 and GD8B receive positive coupling from GD3. For GD7 and GD7B, only GD7B receives coupling noise, but receives positive coupling from GD2 and negative coupling from GD2B, and cancels because these magnitudes are equal. The same applies to GD9. Accordingly, the noise received by I3 and I3B is canceled, so the SA operating margin in SB3 does not decrease.
[0100]
Conversely, consider the coupling noise received by GD connected to I1 and I1B when SA in SB3 is activated to amplify sense amplifier node I3 to 2V and I3B to 0V. First, GD2 and GD2B both receive negative coupling from GD7B, but the length of the GD part that receives the coupling is the same, and I1 and I1B generate noise of the same phase and the same magnitude. The margin does not decrease. The same applies when both GD4 and GD4B receive positive coupling from GD9. As for GD1 and GD1B, only GD1B receives coupling noise, but receives positive coupling from GD6 and negative coupling from GD6B. The same applies to GD3. Accordingly, the noise received by I1 and I1B is canceled, so the SA operating margin in SB1 does not decrease.
[0101]
As can be easily guessed, since the noise is canceled in units of GD, it can be seen that the noise is canceled even when separated by different QMs.
[0102]
Therefore, the twisted global data line of the present invention has an advantage that there is no imbalance in coupling and noise can be completely canceled when a signal is read from any data line.
[0103]
FIG. 22 shows a switch layout when the GD is twisted at the SWB5 portion in FIG. 5 in the case of the switch alternate arrangement type. The data line direction can be laid out with a length of 7F, and a twist of the data line can be realized with a small overhead compared to 5F in FIG.
[0104]
【The invention's effect】
  Using the above array configuration and operation method, a DRAM with a small chip area and low power consumption can be realized. That is, in this configuration, the data line can be divided into multiple parts with almost no increase in area, and low power consumption is possible.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a memory array (1) of a reference example.
FIG. 2 is a layout of a switch of the memory array (1).
FIG. 3 is a circuit diagram of a memory array (2) of a reference example.
FIG. 4 is a circuit diagram of a memory array (3) of a reference example.
FIG. 5 is a circuit diagram of a memory array (4) of the present invention.
FIG. 6 is a circuit diagram of a memory array (5) of a reference example.
FIG. 7 is a chip configuration diagram.
FIG. 8 is a circuit diagram of a memory array (6) of a reference example.
FIG. 9 is a cross-sectional structure of a switch portion.
FIG. 10 is a read waveform of the memory array (6).
FIG. 11 is a write waveform of the memory array (6).
FIG. 12 is a circuit diagram of a sense amplifier driving circuit.
FIG. 13 is a lead waveform with improved S / N.
FIG. 14 is a circuit diagram of a memory array (7) of a reference example.
FIG. 15 is a circuit diagram of a memory array (8) of a reference example.
FIG. 16 is a circuit diagram of a conventional memory array.
FIG. 17 is a layout of a conventional memory array switch.
FIG. 18 is a layout of switches of a memory array (4) of a reference example.
FIG. 19 is a twist global data line (1) of a reference example;
FIG. 20 is a twist global data line (2) of a reference example.
FIG. 21 is a layout of a switch of a twisted global data line (1) of a reference example.
FIG. 22 is a layout of a switch of a twisted global data line (2) of a reference example.
FIG. 23 shows a conventional twist global data line.
[Explanation of symbols]
MC ... memory cell, D ... data line, W ... word line, SA ... sense amplifier, GD ... global data line, QT ... data line connection switch, QM ... global data line separation switch, T ... data line connection switch Control line, M ... Global data line separation switch control line, PB ... Precharge circuit, YG ... Column switch, I / O ... Main input / output line, YS ... Column selection line, Ydec ... Column decoder, MAT ... Memory mat, SMA ... Sub memory array, UA ... Unit memory array, PUA ... Element unit memory array, SB ... Sense amplifier block, GDG ... Global data line group, GDU ... Global data line unit.

Claims (11)

A semiconductor memory device having a plurality of memory arrays,
Each of the plurality of memory arrays is disposed adjacent to the first sense amplifier, the first switch block, the first memory block disposed adjacent to the first switch block, and the first memory block. A second switch block; a second memory block disposed adjacent to the second switch block; a third switch block disposed adjacent to the second memory block; and a second sense amplifier. And
Each of the first and second memory blocks includes a first data line extending in a first direction, a second data line disposed in parallel with the first data line, and in parallel with the first data line. A main data line disposed; a plurality of word lines extending in a second direction and intersecting the first and second data lines; and a predetermined intersection of the plurality of word lines and the first and second data lines A plurality of memory cells provided in the
The first sense amplifier is connected to a main data line of the first memory block;
The second sense amplifier is connected to a main data line of the second memory block,
The first switch block includes a first switch connected to the first data line of the first memory block and a main data line of the first memory block;
The second switch block includes a second switch that connects the second data line of the first memory block and a main data line of the second memory block, and the main data line of the first memory block and the second data block. A third switch for connecting the main data line of two memory blocks; and a fourth switch for connecting the first data line of the second memory block and the main data line of the first memory block;
The semiconductor memory device, wherein the third switch block includes a fifth switch that connects the main data line of the second memory block and the second data line of the second memory block. In claim 1,
Each of the first and second data lines has a folded data line structure;
The semiconductor memory device , wherein the main data line is a complementary main data line pair. In claim 1 or 2,
One end of the first switch block is adjacent to one end of the first memory block;
The other end of the first memory block is adjacent to one end of the second switch block,
The other end of the second switch block is adjacent to one end of the second memory block,
The other end of the second memory block is adjacent to one end of the third switch block. In any one of Claim 1 to 3,
In the first memory block, one of the plurality of word lines is a first memory cell provided at an intersection with the first data line and a second memory cell provided at an intersection with the second data line. And the third switch is turned off and the first and second switches are turned on, whereby the data of the first memory cell is amplified in the first sense amplifier and the first switch is turned on. 2. A semiconductor memory device, wherein data of a second memory cell is amplified by the second sense amplifier. In claim 4,
The first switch is between a first period in which one of the plurality of word lines selects the first and second memory cells and a second period in which the first and second sense amplifiers are activated. A semiconductor memory device which is turned off for a predetermined period. In any one of Claims 1-4,
Each of the first and second sense amplifiers includes a cross-coupled P-type MOSFET pair;
Each of the first and second data lines is connected to a third and fourth sense amplifier having a cross-coupled N-type MOSFET pair. In any one of Claims 1-4,
Each of the first and second data lines is connected to voltage-current conversion type third and fourth sense amplifiers. In any one of Claims 1-7,
Each of the plurality of memory cells includes one MOS transistor and one capacitor. In any one of Claims 1-8,
The semiconductor memory device further includes a plurality of column selection lines extending in the first direction,
The first data line includes a non-inverted first data line and an inverted first data line, and the second data line includes a non-inverted second data line and an inverted second data line, The data line has a non-inverted main data line and an inverted main data line,
Four data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer,
The non-inverted and inverted main data lines and the column selection line are formed in a second wiring layer on the first wiring layer,
The non-inverted and inverted main data lines are wired at a pitch of two adjacent data lines among the four data lines, respectively. In any one of Claims 1-8,
The semiconductor memory device further includes a plurality of column selection lines extending in the first direction,
The first data line includes a non-inverted first data line and an inverted first data line, and the second data line includes a non-inverted second data line and an inverted second data line, The data line has a non-inverted main data line and an inverted main data line,
Four data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer,
The non-inverted and inverted main data lines are formed in a second wiring layer on the first wiring layer,
The plurality of column selection lines are formed in a third wiring layer on the second wiring layer,
The non-inverted and inverted main data lines are wired at a pitch of two adjacent data lines among the four data lines, respectively.
The column select line is wired at a pitch of four or more data lines. In any one of Claims 1-8,
The semiconductor memory device further includes a plurality of column selection lines extending in the first direction,
The first data line includes a non-inverted first data line and an inverted first data line, and the second data line includes a non-inverted second data line and an inverted second data line, and the main data The line has a non-inverted main data line and an inverted main data line,
Four data lines of the non-inverted and inverted first data line and the non-inverted and inverted second data line are formed in a first wiring layer,
The non-inverted and inverted main data lines and the column selection line are formed in a second wiring layer on the first wiring layer,
The non-inverted and inverted main data line pitch is wider than the adjacent two pitches of the four data lines.

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