JP4264633B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, a normal memory cell (first cell) and a so-called dummy cell (second cell) that has the same transistor arrangement structure as the first cell but is not used for data storage are arranged in the cell array. The present invention relates to a semiconductor memory device.
[0002]
[Prior art]
FIG. 8 is a block diagram showing an example of a conventional semiconductor memory having a precharge circuit. In FIG. 8, reference numerals are given to each block of the semiconductor memory and signals between the blocks, but the reference numerals for the word lines and the bit lines indicate both signals and signal wirings.
8 includes a memory cell array (MCA) 10, a row decoder 2, a column control circuit 3, a column operation circuit 4, a column switch circuit (C.SW) 5, and a local precharge circuit (L.PCHG). ) 6. The column control circuit 3 includes a column decoder (C.DEC) and a clock generator (CLK.GEN). The column operation circuit 4 includes a global precharge circuit (G.PCHG), a write circuit (W), and a read circuit (R) such as a sense amplifier.
[0003]
Although not particularly shown, a large number of memory cells are arranged in a matrix in the memory cell array 10. Memory cells in the same row are commonly connected to any of a plurality of word lines WL, and memory cells in the same column are commonly connected to any of bit line pairs (BIT0, BITX0), (BIT1, BITX1),. Has been.
An address signal AA, a clock CK, an operation enable signal OE, and the like are input to the column control circuit 3. The column control circuit 3 generates a precharge signal PRE, a column selection signal COL, a sense amplifier enable signal SAE, and a write enable signal WRE based on these signals. The precharge signal PRE is supplied to the local precharge circuit 6 and the global precharge circuit (G.PCHG) in the column operation circuit 4, the column selection signal COL is supplied to the column switch circuit 5, and the sense amplifier enable signal SAE. The write enable signal WRE is supplied to the column operation circuit 4.
[0004]
Hereinafter, the operation of the semiconductor memory will be described by taking data writing as an example.
At the start of the data write cycle, the local precharge circuit 6 and the global precharge circuit in the column operation circuit 4 perform local bit line pairs (BITi, BITXi: i = 0, 1,... In response to the precharge signal PRE. ) And the global bit line pair (GBIT, GBITX) to the power supply voltage V_ddAlternatively, it is precharged to a high level voltage close to the power supply voltage. At this time, all the column switches of the column switch circuit 5 are off.
[0005]
When the data write cycle starts, first, the address signal AA, the input data signal I and the like change and are determined. Further, the operation enable signal OE input to the column control circuit 3 changes to a “write permission” state.
As a result, the column control circuit 3 decodes the address signal AA and outputs the decoded column selection signal COL to the column switch circuit 5. The column switch circuit 5 connects the local bit line pair specified based on the input column selection signal COL to the global bit line pair (GBIT, GBITX).
[0006]
The row decoder 2 operates in accordance with the row clock ROWCK generated by the clock generator in the column control circuit 3 and selects any of the plurality of word lines WL according to the row address signal RA input from the column control circuit 3. A voltage necessary for writing is applied to the selected word line.
[0007]
The write circuit in the column operation circuit 4 operates in response to the write enable signal WRE output from the column control circuit 3, and the write data that takes the high level or the low level in accordance with the input data signal I is forcibly changed to the global The bit line pair is set to a predetermined bit line pair connected to the global bit line pair via the column switch in the ON state. As a result, write data is input to the memory cell located at the intersection of the predetermined bit line pair and the activated word line. Thereafter, when the word line is deactivated, the storage data of the memory cell is determined by the bit line pair potential at that time.
[0008]
FIG. 9 is an equivalent circuit diagram of a conventional local precharge circuit.
The local precharge circuit 6 shown in FIG. 9 includes three P-channel transistors for each bit line pair, that is, an equalizing transistor Te connected between the bit line pair (BITi, BITXi), the first bit line BITi, Power supply voltage V_ddPrecharging transistor Tc1 connected between the first and second supply lines, second bit line (bit complementary line) BITXi, and power supply voltage V_ddAnd a precharging transistor Tc2 connected between the first and second supply lines.
A common precharge signal line PCL is connected to these three transistors Te, Tc1 and Tc2, and the precharge signal PRE inverted by the inverter 61 during operation is applied. For this reason, when the inverted signal of the precharge signal PRE is at a low level, the three transistors Te, Tc1 and Tc2 are turned on in the precharge circuits corresponding to all the bit line pairs. The potential of the bit line pair after precharging is the power supply voltage V_ddIt becomes.
[0009]
The global precharge circuit has a circuit configuration equivalent to that shown in FIG. 9, and one global precharge circuit is provided for each of a plurality of bit line pairs.
[0010]
[Problems to be solved by the invention]
In a semiconductor memory having a large number of rows in a cell array, bit lines and bit complementary lines are long, and a large number of memory cells are connected to these. Therefore, the load capacity of the bit line and the bit complementary line is large, and P-channel transistors Te, Tc1 and Tc2 used in the local precharge circuit 6 and the global precharge circuit are used to quickly charge the load capacity. It is necessary to increase the size. As a result, there is a disadvantage that the area occupied by the precharge circuit is increased, and further, an area penalty is incurred, such as increasing the interval between the bit line pairs.
[0011]
In particular, since the global precharge circuit is located near the sense amplifier circuit portion (read circuit R) that consumes a large amount of current, if the local precharge circuit has low capability, the load on the global precharge circuit increases. At the start of charging, the current supply is concentrated on the sense amplifier circuit portion. As a result, the power supply voltage V by IR (Internal Resistance) -drop in this sense amplifier circuit portion._{d d}Or a problem of reduced reliability of the power supply voltage supply line due to electromigration or the like. In order to eliminate these influences, it is necessary to increase the width of the power supply wiring supply line, which disadvantageously increases the area for wiring. In addition, when there is not enough space to increase the width of the power supply voltage supply line, the operation cycle time is prolonged or malfunction is likely to occur by delaying the operation timing so as not to be affected by the above-described IR-drop. It suffers from various disadvantages that reliability due to electromigration is reduced.
[0012]
The present invention provides a semiconductor memory device having a so-called dummy cell that has the same transistor configuration as that of a memory cell but is not used for data storage. Thus, the precharge circuit increases the area, operation speed, and reliability decreases. It is to prevent.
[0013]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention relates toHalfA conductor memory device has a plurality of cells arranged in a matrix.And a cell array in which cells are interconnected by bit lines and word lines. In the cell array,Used for data storagememoryCell and, DeNot used for data storagedummyWith cellTo do.
The memory cellAre connected in series between a power supply voltage supply line and a reference voltage supply line.TransistorAnd a second transistor;AboveFirstTransistorAnd a third transistor connected between the connection midpoint of the second transistor and the bit line and having a gate connected to the word line.To do.
  SaiddummycellIncludes a first precharge transistor connected between a power supply voltage supply line and the bit line and having a gate connected to the precharge signal line, and a first dummy transistor and a second dummy transistor.
Two transistors forming each pair of three pairs of the first transistor and the first precharge transistor, the second transistor and the first dummy transistor, the third transistor and the second dummy transistor, The memory cell and the dummy cell have the same transistor size and are arranged at the same in-cell position.
Both the first dummy transistor and the second dummy transistor are not connected to the first precharge transistor, and the second dummy transistor is not connected to the word line and the bit line.
[0015]
  Semiconductor memory of the present inventionapparatusIs used for data storageMemory cellAnd not used for data storageDummy cellAnd have the same transistor structure, that is, the same number and arrangement of transistors. However,dummyA part of the cell transistor is used for precharging.
  Specifically,Semiconductor memory device of the present inventionThendummyIn the cell, one of the source and drain is connected to the supply line for the power supply voltageIn the memory cellCorresponding to the first transistorAs the first precharge transistor, for example, a memory cellThird transistorTransistor corresponding toConnect directly to the bit line without going throughing.FirstPrechargeA precharge signal line is connected to the gate of the transistor.
  Also,dummyIn the cellMemory cellThird transistorSecond dummy transistor corresponding toIs not connected to the bit line and the word line. further,memorycellIn the dummy cell, the first dummy transistor corresponding to the second transistor and the second dummy transistor areFirstPrechargeThe transistor is not connected.
[0016]
  When the precharge signal line is activated,dummyThe first of the cellPrechargeThe transistor is turned on and the bit line is charged by the power supply voltage.dummyFor example, the cells are often distributed and arranged in the cell array in order to secure a portion where the bit line pair is twisted, or provided in the outermost periphery of the cell array. For this reason,dummyWhen the cell is used for precharging, the power supply voltage for charging the bit line is supplied without concentration of current at a specific location.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking an SRAM having a cell having a 6-transistor structure as an example.
[0018]
FIG. 1 is a block diagram of an SRAM according to an embodiment of the present invention. In FIG. 1, symbols are assigned to each block of the SRAM and signals between the blocks, but the symbols for the word lines and the bit lines indicate both the signals and the signal wirings.
1 includes a memory cell array (MCA) 1, a row decoder 2, a column control circuit 3, a column operation circuit 4, a column switch circuit (C.SW) 5, and a bit line equalize circuit (BL.EQ) 7. Have The column control circuit 3 includes a column decoder (C.DEC) and a clock generator (CLK.GEN). The column operation circuit 4 includes a global precharge circuit (G.PCHG), a write circuit (W), and a read circuit (R) such as a sense amplifier.
[0019]
As in the case shown in FIG. 8, the address signal AA, the clock CK, the operation enable signal OE, and the like are input to the column control circuit 3. The column control circuit 3 generates a precharge signal PRE, a column selection signal COL, a sense amplifier enable signal SAE, and a write enable signal WRE based on these signals. The precharge signal PRE is supplied to the bit line equalize circuit 7, the global precharge circuit (G.PCHG) in the column operation circuit 4, and the memory cell array 1. The column selection signal COL is supplied to the column switch circuit 5, and the sense amplifier enable signal SAE and the write enable signal WRE are supplied to the column operation circuit 4.
[0020]
A large number of cells are arranged in a matrix in the memory cell array 1. Cells in the same row are commonly connected to any of a plurality of word lines WL, and cells in the same column are commonly connected to any of bit line pairs (BIT0, BITX0), (BIT1, BITX1),. Yes.
The cells in the memory cell array 1 are composed of memory cells as “first cells” occupying the majority and relatively few dummy cells as “second cells”.
[0021]
2A to 2C show several modes of cell arrangement.
In FIG. 2A, dummy cells DC are provided around the arrangement area of the memory cells MC. The dummy cells DC arranged in this way are provided for the purpose of preventing variations in cell characteristics due to the difference in the accuracy of repeated pattern formation in the semiconductor process between the outer peripheral portion and the inside of the cell array. Therefore, depending on the degree of variation in the cell characteristics, the dummy cells DC may be provided in double, triple or more around the area where the memory cells MC are arranged.
[0022]
In FIG. 2B and FIG. 2C, dummy cells are provided in order to secure a region for twisting the bit line in the twisted bit line structure. The twisted bit line structure means that the relative positional relationship between the bit line and the bit complementary line in the row direction is determined for each predetermined number of cells in the column direction in order to cancel noise between the bit lines or reduce the so-called mirror effect. The wiring structure of the bit line to be replaced with. The mirror effect is a phenomenon that apparently doubles the load capacity of each bit line when the potential of one line of the bit line pair rises and at the same time the potential of the other line decreases. The mirror effect causes a malfunction, and the timing design based on the mirror effect increases the operation cycle time and hinders high-speed operation. In FIG. 2B, dummy cells DC are provided continuously in the row direction. In FIG. 2C, the dummy cells DC are provided every other column.
When the dummy cells DC are continuously arranged in the row, the word line of the dummy cell row can be used as a precharge signal line. For example, the first row ROW1 or the last row ROW2 of the cell array shown in FIG. 2A or the middle rows ROW3 and ROW4 of the cell array shown in FIG. Can be used as a precharge signal line. Hereinafter, a more detailed configuration will be described using the case of FIG. 2B as an example.
[0023]
FIG. 3 shows a detailed configuration example of the memory cell array 1, the column operation circuit 4, the column switch circuit 5, and the bit line equalize circuit 7. FIG. 4 shows a circuit diagram of the memory cell, and FIG. 5 shows a circuit diagram of the dummy cell.
Each of memory cell MC and dummy cell DC includes MOS transistors M1 and M4 having two P-type channels and MOS transistors M2, M3, M5 and M6 having four N-type channels. These transistors M1 to M6 constitute the “first to sixth transistors” of the present invention, respectively.
[0024]
In the memory cell MC shown in FIG. 4, the first transistor M1 and the second transistor M2 are connected to the power supply voltage V_ddAre connected in series with a supply line of a reference voltage, for example, a ground voltage GND. Similarly, the fourth transistor M4 and the fifth transistor M5 are connected to the power supply voltage V_ddAnd a ground voltage GND supply line are connected in series. A connection midpoint (first storage node ND1) between the first transistor M1 and the second transistor M2 is connected to the gate of the fourth transistor and the gate of the fifth transistor. Similarly, a connection midpoint (second storage node ND2) between the fourth transistor M4 and the fifth transistor M5 is connected to the gate of the first transistor and the gate of the second transistor. A third transistor M3 is connected between the first storage node ND1 and the bit line BITi (i = 0, 1,...). Similarly, a sixth transistor M6 is connected between the second storage node ND2 and the bit complement line BITXi. The gates of the third and sixth transistors M3 and M6 are connected to the word line WLj (j = 0, 1,..., N).
Transistors M1 and M4 function as load transistors, transistors M2 and M5 function as driver transistors, and transistors M3 and M6 function as access transistors, respectively.
[0025]
The dummy cell DC shown in FIG. 5 has a transistor arrangement structure, that is, the number and position of the transistors in common with the memory cell MC.
The difference between the dummy cell DC and the memory cell MC is that, first, the drain of the first transistor M1 is disconnected from the connection midpoint of the second and third transistors and directly connected to the bit line BLi. Similarly, the drain of the fourth transistor M4 is disconnected from the midpoint of connection of the fifth and sixth transistors and directly connected to the bit complement line BLXi.
Second, the drain of the third transistor M3 is disconnected from the bit line BLi and is in an open state. Similarly, the drain of the sixth transistor M6 is disconnected from the bit complement line BLXi and is in an open state.
Third, the gate connection of the first, second, fourth and fifth transistors is different from that of the memory cell MC. That is, in the memory cell MC, the gates of the two transistors (M1 and M2 or M4 and M5) constituting the inverter are interconnected with the storage node which is another inverter output, but in the dummy cell DC, the first transistor Both the gate of M1 and the gate of the fourth transistor M4 are connected to the precharge signal line PCL, and the gates of the second and fifth transistors are open. Precharge signal line PCL is formed of the same wiring layer as word line WLj in memory cell MC.
[0026]
On the other hand, as shown in FIG. 3, the bit line equalize circuit 7 is provided with a plurality of P-type equalize transistors provided for each column and connected between bit line pairs (BIT0 and BITX0, BIT1 and BITX1,...). It consists of Te. The precharge signal PRE output from the column control circuit 3 is inverted through the inverter 71 and applied to the gates of the plurality of equalizing transistors Te and the precharge signal line PCL.
[0027]
The bit line pairs (BIT0 and BITX0, BIT1 and BITX1,...) Cross (twist) in a dummy manner at the dummy cell DC portion. The bit lines BIT0, BIT1,... Correspond to the “first bit line” in the present invention, and the bit complementary lines BITX0, BITX1,.
[0028]
As shown in FIG. 3, the column switch circuit 5 includes a plurality of transfer gates TG and TGX connected to the bit line and the bit complementary line, respectively. Each of the transfer gates TG and TGX has a configuration in which the sources and drains of the P-type MOS transistor and the N-type MOS transistor are interconnected. In each column, the PMOS gates and NMOS gates of the transfer gate TG connected to the bit line and the transfer gate TGX connected to the bit complement line are connected. A column selection signal COLi (i = 0, 1,...) Is applied to the NMOS gate. A column selection signal inverted through the inverter 51 is applied to the PMOS gate.
[0029]
On the counter cell array side of the column switch circuit 5, bit lines and bit complementary lines are grouped in units of a predetermined number of columns, thereby forming a global bit line pair (GBIT, GBITX). The global bit line pair (GBIT, GBITX) is connected to the column control circuit 4.
In the column control circuit 4, a global precharge circuit 41 and a write / read circuit (W / R) 42 are connected to the global bit line pair (GBIT, GBITX). The global precharge circuit 41 has three P-type transistor configurations similar to those in FIG. 9, and is controlled by an inverted signal of the precharge signal PRE.
[0030]
FIG. 6 shows a configuration example of the writing circuit.
The write circuit W includes four N-type transistors M7 to M10, two NAND gates 43 and 44, and an inverter 45. Transistors M7 and M8 are connected to the power supply voltage V_ddAre connected in series between the supply line of the ground voltage GND and the supply line of the ground voltage GND, and the transistors M9 and M10 are connected to the power supply voltage V_ddAnd a ground voltage GND supply line are connected in series. The midpoint of connection between the transistors M7 and M8 is connected to the global bit line GBIT, and the midpoint of connection between the transistors M9 and M10 is connected to the global bit complementary line GBITX. The gates of the transistors M7 and M10 are connected to each other, and the midpoint of connection is connected to the output of the NAND gate 44. Similarly, the gates of the transistors M8 and M9 are connected to each other, and the connection midpoint is connected to the output of the NAND gate 43. A write enable signal WRE is input to one input of the two NAND gates 43 and 44. The input data signal I is input to the other input of the NAND gate 44, and the input data signal IX inverted through the inverter 45 is input to the other input of the NAND gate 43.
[0031]
In the write circuit W having such a configuration, the larger threshold voltage of the transistors M7 and M9 is set to Vth. When the input data signal I whose logic is “low level (L)” is input when the write enable signal WRE is “high level (H)”, the global bit line GBIT has (V_dd-Vth) high level voltage is precharged, and the global bit complementary line GBITX is grounded. On the contrary, when the input data signal I having the logic “H” is input when the write enable signal WRE is “high level (H)”, the global bit line GBIT is grounded and the global bit complement line GBITX is set to (V_dd-Vth) is precharged with a high level voltage.
[0032]
Hereinafter, the operation of the SRAM will be described by taking as an example a case where data is written in the first cycle and data is read in the next cycle.
7A to 7H are timing charts showing waveforms of various signals.
[0033]
As shown in FIG. 7H, since the precharge signal PRE is “H” at the start of the data write cycle C1, the first and fourth transistors M1, M4 for precharging the dummy cell DC, and The bit line equalizing transistor Te is on. As a result, the power supply voltage V while the bit line pair (BITi, BITXi) is short-circuited._ddHas been precharged. On the other hand, the global bit line pair (GBIT, GBITX) is short-circuited by the global precharge circuit 41 while the power supply voltage V_ddHas been precharged. At this time, the transfer gate pair (TG, TGX) is off.
[0034]
When the data write cycle C1 starts, first, as shown in FIG. 7B, the address signal AA, the input data signal I, etc. are changed and determined, and as shown in FIG. The operation enable signal OE input to the circuit 3 changes to “H”.
Thereby, the column control circuit 3 decodes the address signal AA and outputs the decoded column selection signal COLi to the column switch circuit 5. The column switch circuit 5 selects a local bit line pair connected to the global bit line pair (GBIT, GBITX) based on the input column selection signal COLi.
[0035]
Thereafter, as shown in FIG. 7H, at time T0, the precharge signal PRE changes to “L”, and the bit line pair (BITi, BITXi) enters a floating state.
[0036]
The row decoder 2 operates according to a row clock signal ROWCK (FIG. 7A) generated by a clock generator in the column control circuit 3 and a plurality of word lines in accordance with a row address signal RA input from the column control circuit 3. And a pulse Pgw having a voltage necessary for writing shown in FIG. 7F is applied to the selected word line WLj. As a result, the select transistors (first and fourth transistors M1, M4) of the memory cells MC in the selected row are turned on.
[0037]
In synchronization with the rise of the row clock ROWCK (FIG. 7A), the write enable signal WRE output from the column control circuit 3 changes to “H”. As a result, the write circuit W shown in FIG. 6 operates, and the high level (V_dd−Vth) or low level (GND), the write data is forcibly passed through the global bit line pair (GBIT, GBITX) and the on-state transfer gate pair (TG, TGX). Set to pair (BITi, BITXi). As a result, write data is turned on at the first and second storage nodes ND1 and ND2 for the memory cell MC located at the intersection of the bit line pair of the selected column and the word line of the selected row. It is input via the state select transistors M1 and M4. When the word line WL and the write enable signal WRE are deactivated, the data stored in the memory cell MC is determined by the bit line pair potential at that time. Thereafter, when the column switch circuit 5 turns off all the transfer gates and the precharge signal becomes “H” at time T1 to return to the precharge state again, the data write cycle C1 ends.
[0038]
In the data read cycle C2, the write enable signal WRE remains “L” during the period of the cycle C2. Instead, when the enable signal SAE of the sense amplifier as the read circuit (R) passes a sufficient time after the read gate pulse Pgr rises on the selected word line as shown in FIG. It rises from “L” to “H”.
In the data read operation, the write enable signal WRE is “L” until the sense amplifier is driven, so that the bit line pair is not forcibly changed to a predetermined voltage and remains in the floating state. Therefore, when the read gate pulse Pgr rises and the select transistors M1 and M4 are turned on in the memory cell MC of the selected row, the bit line pair is set according to the amount of charge stored in the first and second storage nodes ND1 and ND2. A potential change occurs. This potential change is caused by the power supply voltage V being driven by the sense amplifier._ddThe signal is amplified to an amplitude signal and output as an output data signal O to an I / O bus (not shown). When the read gate pulse Pgr and the sense amplifier enable signal SAE are deactivated and the precharge signal becomes “H” to return to the precharge state again, the data read cycle C2 is completed.
In the read operation, the operation timing in the first half of the cycle such as the row clock ROWCK, the operation enable signal OE, the determination operation of the address signal AA, the column switching, and the precharge operation is almost the same as that in the above-described write. However, there is no input data signal I input and its determination operation.
[0039]
The embodiment of the present invention has the following effects.
First, a reduction in memory area and cost can be achieved.
In the present embodiment, the dummy cells DC are used as local precharge circuits by changing the connection relationship between the transistors of the dummy cells DC and between the transistors and the wirings, which have not been used for the operation in the past, with those of the memory cells MC. Since the transistor size and arrangement of the precharge circuit can be the same as those of the memory cell MC, the size of the dummy cell DC does not differ from the memory cell size. Further, the precharge line PCL is composed of the same layer as the word line WL. That is, in the cell-based layout design, the function of the local precharge circuit is realized in the dummy cell DC only by changing the pattern shape of several layers of the dummy cell DC and the presence or absence of contacts. As a result, in the semiconductor wafer process, there is no additional photomask and process, and process cost does not increase.
On the other hand, the local precharge circuit 6 which is conventionally provided for each column and has a three-transistor configuration is replaced with a bit line equalize circuit 7 formed of one transistor. In the conventional local precharge circuit 6, in order to discharge a large bit line load capacity, two large precharge transistors and one bit line equalizing transistor are indispensable. On the other hand, in the present embodiment, a precharge transistor is not required, and the area is reduced correspondingly, and the cost can be reduced. Further, in the case where a relatively large number of dummy cells DC are arranged and the unit load capacity to be precharged by one dummy cell DC is small, it is possible to omit even the bit line equalizing transistors.
[0040]
Secondly, since the precharge circuits are distributed in the cell array 1, a long operation cycle time is obtained by delaying the operation timing so that there is no malfunction due to IR-drop that occurs immediately after the start of precharge and the influence of IR-drop. Various disadvantages such as reduction of wiring reliability due to electrical migration or electromigration are eliminated.
[0041]
Third, there are various disadvantages described in the above-mentioned second effect in a product with different memory capacity, or a semiconductor memory based on a so-called parametric cell design in which the memory capacity can be changed according to the customer's request. There is a benefit that can be easily resolved.
In other words, conventionally, as the memory capacity increases, the bit line load capacity also increases, and it is necessary to increase the capacity of the precharge circuit accordingly. In order to minimize the area penalty under these circumstances, it was necessary to prepare several precharge circuits with different capacities in the design. By installing it, there was an overhead of precharge capability, and there was a case where the area penalty was large accordingly.
On the other hand, in the present embodiment, an upper limit is determined for the unit load capacity of the bit line borne by one dummy cell in order to exert the second effect, and if the mirror effect and noise reduction are added to this, 1 The cell interval at which the dummy cells are to be arranged in the column can be easily obtained. Therefore, even if the memory capacity changes, as long as this condition is observed, the effects of IR-drop and electromigration can be easily prevented without incurring a large area penalty, and the advantage that the design is easy can be obtained. .
[0042]
【The invention's effect】
According to the present invention, in a semiconductor memory device having a so-called dummy cell that has the same transistor configuration as a memory cell but is not used for data storage, the area is increased by the precharge circuit, the operation is slowed down, and the reliability is lowered. Etc. can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram of an SRAM according to an embodiment of the present invention.
FIGS. 2A to 2C are diagrams showing several modes of cell arrangement of a cell array to which the present invention can be applied.
FIG. 3 is a circuit block diagram showing a detailed configuration example of a memory cell array, a column operation circuit, a column switch circuit, and a bit line equalize circuit.
FIG. 4 is a circuit diagram of a memory cell.
FIG. 5 is a circuit diagram of a dummy cell.
FIG. 6 is a circuit diagram of a write circuit.
7A to 7H are timing charts showing waveforms of various signals.
FIG. 8 is a block diagram showing an example of a conventional semiconductor memory having a precharge circuit.
FIG. 9 is a circuit diagram of a conventional local precharge circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Cell array, MC ... Memory cell as 1st cell, DC ... Dummy cell as 2nd cell, M1-M6 ... 1st-6th transistor, BIT ... Bit line as 1st bit line, BITX ... 2nd bit Bit complementary lines as lines, WL0 to WLn, WLi, word lines, PCL, precharge signal lines, PRE, precharge signals

Claims (3)

A cell array in which a plurality of cells are arranged in a matrix and the cells are interconnected by bit lines and word lines,
In the cell array having a memory cell for use in data storage, and a dummy cell that is not used in data storage,
The memory cell is
A first transistor and a second transistor connected in series between a power supply voltage supply line and a reference voltage supply line;
A third transistor connected between a connection midpoint of the first transistor and the second transistor and a bit line and having a gate connected to a word line;
Have
The dummy cell,
A first precharge transistor connected between a power supply voltage supply line and the bit line and having a gate connected to a precharge signal line;
A first dummy transistor and a second dummy transistor;
Have
Two transistors forming each pair of three pairs of the first transistor and the first precharge transistor, the second transistor and the first dummy transistor, the third transistor and the second dummy transistor, The memory cell and the dummy cell have the same transistor size and are disposed in the same cell position,
Both the first dummy transistor and the second dummy transistor are not connected to the first precharge transistor, and the second dummy transistor is not connected to the word line and the bit line . The memory cell is
Fourth and fifth transistors connected in series between a power supply voltage supply line and a reference voltage supply line;
A sixth transistor connected gate between a connection point and bit complement lines of said fourth and fifth transistors are connected to said word line,
Further comprising
The dummy cell,
A second precharge transistor connected between a power supply voltage supply line and the bit complement line and having a gate connected to the precharge signal line;
A third dummy transistor and a fourth dummy transistor;
Further comprising
Two transistors forming each pair of three pairs of the fourth transistor and the second precharge transistor, the fifth transistor and the third dummy transistor, the sixth transistor and the fourth dummy transistor, The memory cell and the dummy cell have the same transistor size and are disposed in the same cell position,
The third dummy transistor and the fourth dummy transistor are both disconnected from the second precharge transistor, and the fourth dummy transistor is disconnected from the word line and the bit complement line,
The bit line and the bit complementary line are composed of a twist bit line pair twisted in the middle of the column direction,
The dummy cells are arranged in a twisted portion of the twisted bit line pair,
The bit line for each of the third transistor and the sixth transistor is a memory cell arranged on one side in the column direction across the dummy cell and another memory cell arranged on the other side in the column direction. 2. The semiconductor memory device according to claim 1, wherein a connection relationship between the bit line and the bit complementary line is reversed . A cell row in the cell array in which all cells in the row are the dummy cells ;
The cell line in which all the cells in the row are the dummy cells, and the precharge signal line is formed of the same layer as a word line connected to the memory cell in another cell row . Semiconductor memory device.

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