JP5105415B2 - Semiconductor device, power supply system including the same, and startup control method for semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, a power supply system including the semiconductor device, and a startup control method for the semiconductor device, and more particularly to a semiconductor device supplied with power from a plurality of power supplies, a power supply system including the semiconductor device, and a startup control method for the semiconductor device. .

  As a power control method for an LSI (Large Scale Integration) having a plurality of power systems, for example, Patent Literature 1 discloses the following power-on control method. That is, the power supply monitoring circuit checks whether or not a plurality of power supplies are turned on, and only when all the power supplies are turned on, the logic circuit is connected to each MOS (Metal Oxide Semiconductor) -FET (Field Effect Transistor) via the smoothing circuit. ) At the same time. As a result, power from each power source is supplied to the elements of the LSI internal circuit via each MOS-FET in the on state.

With such a configuration, power from a plurality of power supplies is simultaneously supplied to the internal circuit of the LSI. Therefore, when the power is turned on, even if the turn-on sequence of each power supply is indefinite, it is possible to prevent an inrush current from flowing through the elements of the internal circuit, so that the elements of the internal circuit can be prevented from being destroyed. it can. In addition, since each MOS-FET is gradually turned on by the smoothing circuit, it is possible to reliably prevent destruction of the elements of the internal circuit.
JP 2002-10488 A

  However, the power-on control method described in Patent Document 1 has the following problems. That is, firstly, since it is only possible to control whether all the power supplies are turned on or off at the same time, for example, in a power supply system in which only a part of a plurality of power supplies needs to be turned off during standby of the LSI. Not applicable.

  Second, even if the logic circuit outputs a control signal for simultaneously turning on each MOS-FET to each MOS-FET, a plurality of power supplies are supplied to the LSI due to variations in the time when each MOS-FET is turned on. May not be able to supply power simultaneously. In this case, until the power from all the power supplies is supplied to the LSI, the state (level) of the signal received by the LSI from the outside in the LSI internal circuit and the state of the signal output from the LSI to the external terminal are indefinite. turn into.

  Thirdly, since each MOS-FET is gradually turned on by the smoothing circuit, it takes time for each MOS-FET to be turned on, so that the startup time of the LSI becomes long.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device, a power supply system including the semiconductor device capable of stabilizing circuit operations and shortening the startup time, and the startup of the semiconductor device, corresponding to various power supply startup sequences. It is to provide a control method.

In order to solve the above problems, a semiconductor device according to one aspect of the present invention is a semiconductor device in which a plurality of power supply or et power is supplied, are respectively provided corresponding to the plurality of power supply, each corresponding a control terminal for receiving a plurality of power supply terminals for receiving power from a power source, a control signal which varies the output voltage of the plurality of power supplies respectively reach the plurality of voltage thresholds from a first logic level to a second logic level When the control signal is at the second logic level, the first signal is passed, and when the control signal is at the first logic level, the first signal is received from outside the semiconductor device. A first control circuit that prohibits the passage of the signal, an internal circuit that receives the first signal that has passed through the first control circuit and outputs a second signal, a second signal from the internal circuit, When the control signal is at the second logic level Passed through a second signal to the outside of the semiconductor device, when the control signal is at a first logic level and a second control circuit for inhibiting the passage of the second signal. The first and second control circuits operate with electric power supplied from a plurality of power supplies via a plurality of power supply terminals. The internal circuit is operated by power supplied from at least one power source of the plurality of power sources through at least one power source terminal of the plurality of power source terminals.

In order to solve the above problems, a power supply system according to one aspect of the present invention includes a plurality of power supply, monitors the output voltage of each of the plurality of power supply, the output voltages of the power source reaches to the plurality of voltage thresholds Then a power supply monitoring unit for generating a control signal from a first logic level changes to a second logic level, Ru and a semiconductor device. The semiconductor device is provided corresponding to each of a plurality of power supplies, each of which has a plurality of power supply terminals for receiving power from the corresponding power supply, a control terminal for receiving a control signal, and a first externally connected to the semiconductor device. The first signal is passed when the control signal is at the second logic level, and the first signal is inhibited from passing when the control signal is at the first logic level. 1 control circuit, an internal circuit that receives the first signal that has passed through the first control circuit and outputs a second signal, and receives a second signal from the internal circuit, and the control signal is at the second logic level. And a second control circuit that passes the second signal to the outside of the semiconductor device and prohibits the passage of the second signal when the control signal is at the first logic level. The first and second control circuits operate with electric power supplied from a plurality of power supplies via a plurality of power supply terminals. The internal circuit is operated by power supplied from at least one power source of the plurality of power sources through at least one power source terminal of the plurality of power source terminals.

In order to solve the above problems, the start control method of the semiconductor device according to one aspect of the present invention is the activation control method of a semiconductor device in which a plurality of power supply or et power is supplied, a plurality of the output voltage of the power supply When the condition that each of the plurality of voltage thresholds has reached a plurality of voltage thresholds is not satisfied, a control signal of the first logic level is output to the semiconductor device, and the output voltages of the plurality of power supplies respectively reach the plurality of voltage thresholds. A step of outputting a control signal of the second logic level to the semiconductor device if the condition is satisfied, and an input signal received from the outside of the semiconductor device if the control signal is of the second logic level; If the control signal is at the first logic level and passing the signal to the internal circuit of the device, and prohibiting the passage of the input signal; and if the control signal is at the second logic level, the output of the internal circuit Trust It is passed through to the outside of the semiconductor device, when the control signal is at a first logic level, and a step of prohibiting the passage of the output signal.

  According to the present invention, it is possible to cope with various power supply startup sequences, stabilize the circuit operation, and shorten the startup time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Configuration and basic operation]
FIG. 1 is a diagram showing a configuration of a power supply system according to an embodiment of the present invention.

  With reference to FIG. 1, a power supply system 301 includes semiconductor devices 101 and 201, power supplies PS <b> 1 to PS <b> 3, and a power supply monitoring unit 61. The semiconductor device 201 is controlled by the semiconductor device 101.

  The semiconductor device 101 includes control circuits CKTA, CKTB, and CKTC, an internal circuit 51, input terminals TIN1 and TIN2, output terminals TOUT1 and TOUT2, a control terminal TCONT1, and power supply terminals TPS1 to TPS3. Control circuit CKTA includes AND circuits 5 and 6. Control circuit CKTB includes AND circuits 7 and 8. Control circuit CKTC includes AND circuits 9 and 10. The power monitoring unit 61 includes power monitoring circuits 1 to 3 and an AND circuit 4.

  The power supplies PS1 to PS3 generate power and supply the generated power to the semiconductor device 101. The power supply terminals TPS1 to TPS3 in the semiconductor device 101 receive power from the power supplies PS1 to PS3, respectively.

  The control circuits CKTA, CKTB, and CKTC are operated by power from the power supplies PS1 to PS3 supplied via the power supply terminals TPS1 to TPS3, respectively.

  The internal circuit 51 operates with at least one of power from the power supplies PS1 to PS3 supplied via the power supply terminals TPS1 to TPS3.

  The power monitoring unit 61 monitors whether or not the power supplies PS1 to PS3 are normally supplying power to the semiconductor device 101.

  More specifically, the power supply monitoring circuits 1 to 3 monitor the output voltages of the power supplies PS1 to PS3, respectively, and when the output voltages of the power supplies PS1 to PS3 reach the first voltage threshold value to the third voltage threshold value, respectively. Outputs a logic high level detection signal, and outputs a logic low level detection signal when the output voltages of the power supplies PS1 to PS3 are lower than the first voltage threshold value to the third voltage threshold value, respectively.

  AND circuit 4 outputs a logical product of detection signals received from power supply monitoring circuits 1 to 3, respectively. That is, the AND circuit 4 outputs a logic low level signal when any one of the output voltages of the power supplies PS1 to PS3 is less than the voltage threshold, and the output voltages of the power supplies PS1 to PS3 are the first voltages, respectively. When the voltage threshold value to the third voltage threshold value are reached, a logic high level control signal CONT3 is output.

  A control terminal TCONT 1 in the semiconductor device 101 receives a control signal CONT 3 from the AND circuit 4.

  The control circuits CKTA, CKTB, and CKTC output signals received from the outside of the semiconductor device 101 to the internal circuit 51 via the input terminals TIN1 and TIN2. In addition, the control circuits CKTA, CKTB, and CKTC output the signal generated by the internal circuit 51 to the outside of the semiconductor device 101 through the output terminals TOUT1 and TOUT2. The control circuits CKTA, CKTB, and CKTC switch whether or not to output a signal received from the outside of the semiconductor device 101 to the internal circuit 51 based on the monitoring result of the power supply monitoring unit 61, and generate the internal circuit 51. Whether or not to output the signal to the outside of the semiconductor device 101 is switched.

[Operation]
Next, an operation when the power supply system according to the embodiment of the present invention supplies power to the semiconductor device will be described.

  When the power supplies PS1 to PS3 are turned on, power is normally supplied to the semiconductor device 101 from all of the power supplies PS1 to PS3. That is, since power is supplied to the power supply terminals TPS1 to TPS3 of the semiconductor device 101, power is supplied to the control circuits CKTA, CKTB, CKTC and the internal circuit 51 in the semiconductor device 101.

  Further, the power supply monitoring circuits 1 to 3 each output a logic high level detection signal because the output voltages of the power supplies PS1 to PS3 have reached the first voltage threshold value to the third voltage threshold value, respectively.

  The AND circuit 4 receives a logic high level detection signal from all of the power supply monitoring circuits 1 to 3 and outputs a logic high level control signal CONT 3 to the control terminal TCONT 1 of the semiconductor device 101.

  The AND circuit 5 receives the logic high level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and transmits the logic level of the signal received from the outside via the input terminal TIN1 to the control circuit CKTC.

  The AND circuit 6 receives the logic high level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and sends the logic level of the signal received from the internal circuit 51 to the semiconductor device 201 as the control signal CONT1 via the output terminal TOUT1. introduce.

  AND circuit 9 receives logic high level control signal CONT 3 from AND circuit 4 and transmits the logic level of the signal received from AND circuit 5 to internal circuit 51.

  The AND circuit 7 receives a logic high level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and transmits the logic level of the signal received from the outside via the input terminal TIN2 to the control circuit CKTC.

  The AND circuit 8 receives the logic high level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and converts the logic level of the signal received from the internal circuit 51 to the semiconductor device 201 as the control signal CONT2 via the output terminal TOUT2. introduce.

  The AND circuit 10 receives a logic high level control signal CONT 3 from the AND circuit 4 via the control terminal TCONT 1 and transmits the logic level of the signal received from the AND circuit 7 to the internal circuit 51.

  On the other hand, until power is normally supplied from all of the power supplies PS1 to PS3 to the semiconductor device 101, at least one of the power supply monitoring circuits 1 to 3 has an output voltage of the corresponding power supply that is less than the voltage threshold value. Therefore, a logic low level detection signal is output.

  The AND circuit 4 receives a logic low level detection signal from at least one of the power supply monitoring circuits 1 to 3, and outputs a logic low level control signal CONT 3 to the semiconductor device 101.

  The AND circuit 5 receives a logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops outputting the signal received from the outside via the input terminal TIN1 to the control circuit CKTC. That is, the AND circuit 5 outputs a logic low level signal to the control circuit CKTC regardless of the logic level of the signal received from the outside via the input terminal TIN1.

  The AND circuit 6 receives a logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops outputting the signal received from the internal circuit 51 to the semiconductor device 201. That is, the AND circuit 6 outputs a logic low level signal to the semiconductor device 201 as the control signal CONT1 regardless of the logic level of the signal received from the internal circuit 51.

  The AND circuit 9 receives the logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops outputting the signal received from the AND circuit 5 to the internal circuit 51. That is, AND circuit 9 outputs a logic low level signal to internal circuit 51 regardless of the logic level of the signal received from AND circuit 5.

  The AND circuit 7 receives the logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops the output of the signal received from the outside via the input terminal TIN2 to the control circuit CKTC. That is, AND circuit 7 outputs a logic low level signal to control circuit CKTC regardless of the logic level of the signal received from the outside via input terminal TIN2.

  The AND circuit 8 receives the logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops outputting the signal received from the internal circuit 51 to the semiconductor device 201. That is, the AND circuit 6 outputs a logic low level signal to the semiconductor device 201 as the control signal CONT2 regardless of the logic level of the signal received from the internal circuit 51.

  The AND circuit 10 receives the logic low level control signal CONT3 from the AND circuit 4 via the control terminal TCONT1, and stops outputting the signal received from the AND circuit 7 to the internal circuit 51. That is, AND circuit 10 outputs a logic low level signal to internal circuit 51 regardless of the logic level of the signal received from AND circuit 7.

  FIG. 2 is a diagram showing an example of the state of each terminal and internal circuit of the semiconductor device 101 when the power supply system according to the embodiment of the present invention is started.

  Referring to FIG. 2, power supplies PS1, PS2, and PS3 are turned on in this order. That is, power is supplied from the power supplies PS1 to PS3 to the power supply terminal TPS1, the power supply terminal TPS2, and the power supply terminal TPS3 in this order.

  At time T0, power is not supplied from the power sources PS1 to PS3 to the control circuits CKTA, CKTB, and CKTC, respectively, so that the control circuits CKTA, CKTB, and CKTC are not operating. At this time, the AND circuit 4 outputs a control signal CONT3 having a logic low level.

  At time T1, power supply from the power supply PS1 is started via the power supply terminal TPS1. Then, the control circuit CKTA starts operating. However, since power supply is not started from the power supplies PS2 and PS3, the AND circuit 4 outputs a control signal CONT3 having a logic low level. Therefore, the control circuit CKTA outputs a logic low level signal as the control signal CONT1 to the semiconductor device 201, and outputs a logic low level signal to the control circuit CKTC.

  At time T2, power supply from the power supply PS2 is started via the power supply terminal TPS2. Then, the control circuit CKTB starts its operation. However, since the power supply from the power source PS3 has not started, the AND circuit 4 outputs the control signal CONT3 having a logic low level. Therefore, the control circuits CKTA and CKTB output logic low level signals to the semiconductor device 201 as control signals CONT1 and CONT2, respectively, and output logic low level signals to the control circuit CKTC.

  At time T3, power supply from the power supply PS3 is started via the power supply terminal TPS3. Then, the control circuit CKTC starts operation. However, since the output voltage of the power supply PS3 does not reach the third voltage threshold, the AND circuit 4 still outputs the control signal CONT3 having a logic low level. Therefore, the control circuits CKTA and CKTB output logic low level signals to the semiconductor device 201 as control signals CONT1 and CONT2, respectively, and output logic low level signals to the control circuit CKTC. Further, since the control circuit CKTC receives the logic low level control signal CONT 3 from the AND circuit 4, it outputs a logic low level signal to the internal circuit 51.

  At time T4, since the output voltages of the power supplies PS1 to PS3 have reached the first voltage threshold value to the third voltage threshold value, the AND circuit 4 outputs the control signal CONT3 having a logic high level. Then, control circuits CKTA and CKTB output signals received from internal circuit 51 to semiconductor device 201 and output signals received from outside of semiconductor device 101 to control circuit CKTC. Control circuit CKTC outputs signals received from control circuits CKTA and CKTB to internal circuit 51.

  FIG. 3 is a diagram showing an example of the state of each terminal and internal circuit of the semiconductor device 101 at the time of starting the power supply system according to the embodiment of the present invention.

  Referring to FIG. 3, power supplies PS2, PS1, and PS3 are turned on in this order. That is, power is supplied from the power supplies PS1 to PS3 to the power supply terminal TPS2, the power supply terminal TPS1, and the power supply terminal TPS3 in this order.

  At time T0, power is not supplied from the power sources PS1 to PS3 to the control circuits CKTA, CKTB, and CKTC, respectively, so that the control circuits CKTA, CKTB, and CKTC are not operating. At this time, the AND circuit 4 outputs a control signal CONT3 having a logic low level.

  At time T1, power supply from the power supply PS2 is started via the power supply terminal TPS2. Then, the control circuit CKTB starts its operation. However, since power supply from the power sources PS1 and PS3 has not started, the AND circuit 4 outputs a control signal CONT3 having a logic low level. Therefore, the control circuit CKTB outputs a logic low level signal to the semiconductor device 201 as the control signal CONT2, and outputs a logic low level signal to the control circuit CKTC.

  At time T2, power supply from the power supply PS1 is started via the power supply terminal TPS1. Then, the control circuit CKTA starts operating. However, since the power supply from the power source PS3 has not started, the AND circuit 4 outputs the control signal CONT3 having a logic low level. Therefore, the control circuits CKTA and CKTB output logic low level signals to the semiconductor device 201 as control signals CONT1 and CONT2, respectively, and output logic low level signals to the control circuit CKTC.

  At time T3, power supply from the power supply PS3 is started via the power supply terminal TPS3. Then, the control circuit CKTC starts operation. However, since the output voltage of the power supply PS3 does not reach the third voltage threshold, the AND circuit 4 still outputs the control signal CONT3 having a logic low level. Therefore, the control circuits CKTA and CKTB output logic low level signals to the semiconductor device 201 as control signals CONT1 and CONT2, respectively, and output logic low level signals to the control circuit CKTC. Further, since the control circuit CKTC receives the logic low level control signal CONT 3 from the AND circuit 4, it outputs a logic low level signal to the internal circuit 51.

  At time T4, since the output voltages of the power supplies PS1 to PS3 have reached the first voltage threshold value to the third voltage threshold value, the AND circuit 4 outputs the control signal CONT3 having a logic high level. Then, control circuits CKTA and CKTB output signals received from internal circuit 51 to semiconductor device 201 and output signals received from outside of semiconductor device 101 to control circuit CKTC. Control circuit CKTC outputs signals received from control circuits CKTA and CKTB to internal circuit 51.

  FIG. 4 is a diagram showing an example of the state of each terminal and internal circuit of the semiconductor device 101 at the time of starting the power supply system according to the embodiment of the present invention.

  Referring to FIG. 4, power supplies PS3, PS1, and PS2 are turned on in this order. That is, power is supplied from the power supplies PS1 to PS3 to the power supply terminal TPS3, the power supply terminal TPS1, and the power supply terminal TPS2 in this order.

  At time T0, power is not supplied from the power sources PS1 to PS3 to the control circuits CKTA, CKTB, and CKTC, respectively, so that the control circuits CKTA, CKTB, and CKTC are not operating. At this time, the AND circuit 4 outputs a control signal CONT3 having a logic low level.

  At time T1, power supply from the power supply PS3 is started via the power supply terminal TPS3. Then, the control circuit CKTC starts operation. However, since power supply from the power sources PS1 and PS2 has not been started, the AND circuit 4 outputs a control signal CONT3 having a logic low level. Therefore, the control circuit CKTC outputs a logic low level signal to the internal circuit 51.

  At time T2, power supply from the power supply PS1 is started via the power supply terminal TPS1. Then, the control circuit CKTA starts operating. However, since the power supply from the power source PS3 has not started, the AND circuit 4 outputs the control signal CONT3 having a logic low level. Therefore, the control circuit CKTA outputs a logic low level signal as the control signal CONT1 to the semiconductor device 201, and outputs a logic low level signal to the control circuit CKTC. The control circuit CKTC outputs a logic low level signal to the internal circuit 51.

  At time T3, power supply from the power supply PS2 is started via the power supply terminal TPS2. Then, the control circuit CKTB starts its operation. However, since the output voltage of the power supply PS2 does not reach the second voltage threshold, the AND circuit 4 still outputs the control signal CONT3 having a logic low level. Therefore, the control circuits CKTA and CKTB output logic low level signals to the semiconductor device 201 as control signals CONT1 and CONT2, respectively, and output logic low level signals to the control circuit CKTC. Further, since the control circuit CKTC receives the logic low level control signal CONT 3 from the AND circuit 4, it outputs a logic low level signal to the internal circuit 51.

  At time T4, since the output voltages of the power supplies PS1 to PS3 have reached the first voltage threshold value to the third voltage threshold value, the AND circuit 4 outputs the control signal CONT3 having a logic high level. Then, control circuits CKTA and CKTB output signals received from internal circuit 51 to semiconductor device 201 and output signals received from outside of semiconductor device 101 to control circuit CKTC. Control circuit CKTC outputs signals received from control circuits CKTA and CKTB to internal circuit 51.

  By the way, the power-on control method described in Patent Document 1 cannot be applied first to a power supply system in which only a part of a plurality of power supplies needs to be turned off at the time of standby of an LSI, for example. Second, the state (level) of the signal received from the outside in the LSI and the state of the signal output from the LSI to the external terminal are indefinite until power from all the power supplies is supplied to the LSI. End up. Third, the startup time of the LSI becomes long.

  However, in the semiconductor device 101 according to the embodiment of the present invention, when all of the power supplies PS1 to PS3 are turned on and then a part of the power supplies PS1 to PS3 is turned off to enter a standby state, the power supply that is turned off is supported. The power supply monitoring circuit that outputs the detection signal at the logic low level outputs the control signal CONT3 at the logic low level. Therefore, even in such a case, since the signal to the internal circuit 51 of the semiconductor device 101 and the control signals CONT1 and CONT2 to the semiconductor device 201 are fixed to the logic low level, the through current in the semiconductor devices 101 and 201 and Malfunctions can be prevented.

  Further, in the semiconductor device 101 according to the embodiment of the present invention, the signal to the internal circuit 51 of the semiconductor device 101 is logic low until all the power supplies PS1 to PS3 are normally supplied to the semiconductor device 101. Fixed to level. Thereby, it is possible to prevent the state (level) of the signal received from the outside by the semiconductor device 101 in the LSI internal circuit from becoming indefinite. In addition, the logic low level control signals CONT1 and CONT2 are always output from the semiconductor device 101 until power is normally supplied to the semiconductor device 101 from all of the power supplies PS1 to PS3. Thereby, it is possible to prevent the state of a signal output from the semiconductor device 101 to the external terminal from becoming indefinite.

  That is, even if the power-on sequence of the power supplies PS1 to PS3 is uncertain, the signals to the internal circuit 51 of the semiconductor device 101 and the control signal CONT1 to the semiconductor device 201 until all of the power sources PS1 to PS3 are turned on. , CONT2 are fixed at a logic low level, so that through current and malfunction in the semiconductor devices 101 and 201 can be prevented. Further, even when the power supplies PS1 to PS3 are started in an incorrect order due to some trouble, it is possible to prevent the semiconductor devices 101 and 201 from being destroyed.

  In addition, the semiconductor device 101 according to the embodiment of the present invention is configured to directly receive power from the power supplies PS1 to PS3 at the power supply terminals TPS1 to TPS3 without going through a circuit such as a MOS-FET. Can be prevented from being prolonged due to the circuit between the power supply PS1 and PS3.

  Therefore, in the semiconductor device 101 and the power supply system 301 according to the embodiment of the present invention, it is possible to cope with various power supply startup sequences, stabilize the circuit operation, and shorten the startup time.

  Further, in the semiconductor device 101 and the power supply system 301 according to the embodiment of the present invention, the semiconductor device is determined depending on whether power is normally supplied to the semiconductor device 101 from all of the power supplies PS1 to PS3 only by hardware. 101, switching between enabling and disabling a signal from the outside, and switching between enabling and disabling a signal generated by the internal circuit 51 of the semiconductor device 101 and output to the semiconductor device 201. . With such a configuration, it is possible to safely turn on the power without using software or the like or without complicating the software procedure.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the power supply system which concerns on embodiment of this invention. It is a figure which shows an example of the state of each terminal of the semiconductor device 101 at the time of starting of the power supply system which concerns on embodiment of this invention, and an internal circuit. It is a figure which shows an example of the state of each terminal of the semiconductor device 101 at the time of starting of the power supply system which concerns on embodiment of this invention, and an internal circuit. It is a figure which shows an example of the state of each terminal of the semiconductor device 101 at the time of starting of the power supply system which concerns on embodiment of this invention, and an internal circuit.

Explanation of symbols

  51 internal circuit, 61 power supply monitoring unit, 101, 201 semiconductor device, 301 power supply system, PS1 to PS3 power supply, CKTA, CKTB, CKTC control circuit, TIN1, TIN2 input terminal, TOUT1, TOUT2 output terminal, TCONT1 control terminal, TPS1 TPS3 power supply terminal, 1-3 power supply monitoring circuit, 4-10 AND circuit.

Claims (3)

A semiconductor device in which a plurality of power supply or et power is supplied,
A plurality of power supply terminals each provided corresponding to the plurality of power supplies, each receiving power from a corresponding power supply;
A control terminal for receiving a control signal that changes from a first logic level to a second logic level when output voltages of the plurality of power sources respectively reach a plurality of voltage thresholds ;
When a first signal is received from the outside of the semiconductor device, the first signal is passed when the control signal is at the second logic level, and the control signal is at the first logic level Includes a first control circuit that prohibits passage of the first signal;
An internal circuit for receiving the first signal passing through the first control circuit and outputting a second signal ;
When the second signal is received from the internal circuit and the control signal is at the second logic level, the second signal is allowed to pass outside the semiconductor device, and the control signal is transmitted to the first circuit. A second control circuit for prohibiting the passage of the second signal when it is at a logic level ;
The first and second control circuits are operated by electric power supplied from the plurality of power supplies via the plurality of power supply terminals,
The internal circuit is a semiconductor device that operates by electric power supplied via at least one power supply terminal of the plurality of power supply terminals from at least one power source of the plurality of power supply. Multiple power supplies,
Monitoring the output voltage of each of the plurality of power supply, the power supply monitoring unit the output voltages of the power supply for generating a control signal respectively vary from reaching the plurality of voltage thresholds first logic level to a second logic level When,
A semiconductor device,
The semiconductor device includes:
A plurality of power supply terminals each provided corresponding to the plurality of power supplies, each receiving power from a corresponding power supply;
A control terminal for receiving the control signal;
When a first signal is received from the outside of the semiconductor device, the first signal is passed when the control signal is at the second logic level, and the control signal is at the first logic level Includes a first control circuit that prohibits passage of the first signal;
An internal circuit for receiving the first signal passing through the first control circuit and outputting a second signal ;
When the second signal is received from the internal circuit and the control signal is at the second logic level, the second signal is allowed to pass outside the semiconductor device, and the control signal is transmitted to the first circuit. If the logic level seen including a second control circuit for prohibiting the passing of said second signal,
The first and second control circuits are operated by electric power supplied from the plurality of power supplies via the plurality of power supply terminals,
The internal circuit is operated by power supplied from at least one of the plurality of power supplies through at least one power terminal of the plurality of power terminals . A startup control method of a semiconductor device in which a plurality of power supply or et power is supplied,
When the condition that the output voltages of the plurality of power supplies have reached a plurality of voltage thresholds is not satisfied, a control signal of a first logic level is output to the semiconductor device, and the output voltages of the plurality of power supplies Outputting a control signal of a second logic level to the semiconductor device when the condition that each of the plurality of voltage thresholds has been satisfied is satisfied ;
When the control signal is at the second logic level, an input signal received from outside the semiconductor device is passed to an internal circuit of the semiconductor device, and the control signal is at the first logic level. The step of prohibiting the passage of the input signal ;
When the control signal is at the second logic level, the output signal of the internal circuit is passed to the outside of the semiconductor device, and when the control signal is at the first logic level, the output And a step of inhibiting the passage of signals .

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