JP2007049786A - Rush current suppressing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a connection target which makes a power feeder recognize connection without fail and prevents the malfunction due to a rush current. <P>SOLUTION: This rush current limiting circuit 10 suppresses a rush current supplied from a PC2 and makes the PC2 recognize that a device 3 is connected, by being provided with: a current limiting circuit 13 which limits the current from the PC2 so as to suppress the rush current; a time adjusting circuit 12 which cancels the limitation of the current by the current limiting circuit 13 when a specified time has passed after start of the supply of the current; and a recognition current generating circuit 11 which is provided at the previous stage of the current limiting circuit 13 and the time adjusting circuit 12, and generates a recognition current for making the PC2 recognize that a device 3 is connected to the PC2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inrush current suppression circuit, and is suitable for application to, for example, a USB (Universal Serial Bus) device.

  Conventionally, a USB device is connected to a personal computer (hereinafter referred to as a PC) and operates by receiving power supply from the connected PC. As shown in FIG. 5, it is known that a large current, a so-called inrush current UC, flows instantaneously from the PC to the device immediately after being connected to the PC in order to charge the starting power. .

On the other hand, in many cases, PCs on the power supply side are provided with a protection circuit in order to prevent malfunction due to the loss of their own power balance due to the supply of the inrush current UC. In such a PC, when a large inrush current flows from the PC to the device, the protection circuit is operated to stop the power supply to the device. As a result, no power is supplied to the device, so that the device cannot operate normally, resulting in malfunction. Therefore, by combining three transistors in the device and providing a rush current suppression circuit that suppresses the rush current by switching according to the magnitude of the current and flowing a constant current, such a malfunction can be prevented. There is an inrush current suppression circuit designed to prevent this. (For example, refer to Patent Document 1).
JP-A-8-154338

  By the way, the PC measures the value of the current flowing to the connection port, and recognizes that the device has been connected when detecting that the current value has exceeded a predetermined threshold value. Therefore, when a device is connected to the PC, if the maximum value of the current flowing to the connection port is smaller than a predetermined threshold for recognizing the device, the PC Unable to recognize that the device is connected.

  On the other hand, in the device provided with the inrush current suppression circuit described above, when the supply of current is started, the current supplied for a predetermined time is limited and the current is constant, so that the peak of the inrush current hardly occurs. The maximum value of current will be small. For this reason, even when this device is connected to a PC, it is not possible to cause the PC to supply a current exceeding a predetermined threshold value for recognizing the device. As a result, a steady current cannot be supplied to the device, resulting in a malfunction of the device.

  The present invention has been made in consideration of the above points, and intends to propose an inrush current suppressing circuit capable of preventing malfunction of a device.

  In order to solve this problem, the inrush current suppression circuit of the present invention is an inrush current suppression circuit that suppresses an inrush current supplied from a power supply device, and the current from the power supply device is suppressed in order to suppress the inrush current. Current limiting means for limiting, restriction releasing means for releasing the current restriction by the current limiting means when a predetermined delay time has elapsed since the start of the supply of current, and a stage preceding the current limiting means and the restriction releasing means And a recognition current generating means for generating a recognition current for causing the power supply apparatus to recognize that a device is connected to the power supply apparatus.

  As a result, regardless of the configuration of the device operation circuit, the current limiting unit, and the current limit canceling unit, a recognition current is generated to ensure that the device is connected to the power supply unit. Since it can be recognized, since it is not recognized that the device is connected, inrush current can be suppressed while preventing power from being supplied from the power supply device.

  According to the present invention, the current supplied from the power supply device is limited, and when the predetermined delay time elapses, the current limitation is canceled, and the current limiting unit and the current limit canceling unit are provided in a preceding stage. The recognition current is generated by the recognized current generation means, so that the recognition current is generated and the device is connected to the power supply apparatus regardless of the configuration of the device operation circuit, the current limiting means, and the current limit releasing means. The power supply device can be surely recognized that the power supply device has been connected, so that the inrush current can be suppressed while preventing the power supply device from not supplying power because the device is not recognized to be connected. Thus, an inrush current suppressing circuit that can prevent malfunction of the device can be realized.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Overall Configuration of Power Supply System In FIG. 1, reference numeral 1 denotes a power supply system as a whole, which includes a PC 2 and a device 3.

  The device 3 and the PC 2 are connected by inserting a USB connector 3A into a USB (Universal Serial Bus) port 2A of the PC 2. When the device 3 is connected, the PC 2 supplies power to the device 3, while the device 3 is operated by the power supplied from the PC 2.

  Here, when the PC 2 monitors the value of the current flowing to the USB port 2A and detects that a current exceeding a predetermined threshold (hereinafter referred to as a recognition threshold) for recognizing the device 3 is detected, 3 is connected, and a steady current is supplied to the recognized device 3 for normal operation after activation.

  The PC 2 is provided with a protection circuit (not shown), and when it detects that a current exceeding a predetermined threshold (hereinafter referred to as a protection threshold) for protecting the PC 2 flows to the USB port 2A, the protection circuit By temporarily operating, the current supply to the device 3 is temporarily stopped to prevent malfunction caused by insufficient power in the PC 2 itself.

  On the other hand, the device 3 is provided with an inrush current suppression circuit so as to prevent malfunction of the device 3 caused when the device 3 is connected to the PC 2.

(2) Inrush Current Suppression Circuit Next, the inrush current suppression circuit will be described in detail with reference to FIG. As shown in FIG. 2, the inrush current suppression circuit 10 is disposed between the USB connector 3A of the device 3 and the internal circuit IK, and current supplied from the PC 2 to the internal circuit IK via the USB connector 3A. It is made to send out.

  The inrush current suppression circuit 10 includes a time adjustment unit 12 and a current limiting unit 13, and a recognition current generation unit 11 provided in front of the time adjustment unit 12 and the current limiting unit 13. When the device 3 is connected to the PC 2 by inserting the USB connector 3A into the USB port 3 (FIG. 1), the inrush current suppression circuit 10 receives supply of current from the PC 2 and inputs this current to each part. It is made to do.

  Here, FIG. 3 shows a current value supplied from the PC 2 to the inrush current suppression circuit 10 via the USB connector 12A after the device 3 is connected to the PC 2 at the time T0 until the steady current DC flows after the time T3. I is shown.

  The recognition current generator 11 generates an instantaneously large current (hereinafter referred to as a recognition current) IR1 from the time T0 to the time T1 immediately after the device 3 is connected to the PC 2 at the time T0. As a result, the recognition current generation unit 11 instantaneously supplies a current equal to or greater than the recognition threshold, which is a current value for the PC 2 to recognize the device 3, from the PC 2 and reliably recognizes that the device 3 is connected to the PC 2. It is possible to prevent the current from being supplied because it is not recognized by the PC 2. Further, after the device 3 is recognized, the recognition current generation unit 11 can supply a stable current from the PC 2 as a steady current to the recognized device 3 instead of suddenly or accidentally. Has been made.

  This recognition current IR1 is set so as to be larger than the recognition threshold value by which the PC 2 recognizes the device 3 and smaller than the protection threshold value for operating the protection circuit. Thereby, the inrush current suppression circuit 10 can supply the current exceeding the recognition threshold value from the PC 2 without operating the protection circuit of the PC 2, and can make the PC 2 surely recognize that the device 3 is connected. .

  On the other hand, the time adjustment unit 12 waits for a predetermined delay time LT to elapse after the device 3 is connected to the PC 2 from the time T0 to the time T2, and supplies from the PC 2 at the time T2 when the delay time LT has elapsed. The generated current is sent to the current limiting unit 13.

  On the other hand, the current limiter 13 limits the current supplied from the PC 2 from time T0 to time T2 (hereinafter referred to as the limit current), and sends the limit current to the internal circuit IK. The starting power of IK is gradually charged.

  Then, when the delay time LT has passed and the current is supplied from the time adjustment unit 12 at the time point T2, the current limiting unit 13 releases the limitation on the current supplied to the internal circuit IK described above using the current supply as a trigger. The current is supplied from the PC 2 according to the power required by the internal circuit IK and is sent to the internal circuit IK.

  Here, when the starting power of the internal circuit IK is not completely charged by the limiting current supplied to the internal circuit IK from the time T0 to the time T2, the remaining starting power is immediately stored in the internal circuit IK at the time T2. Is charged, a charging current IR2 is generated.

  As a result, the inrush current suppression circuit 10 can supply start-up power to the internal circuit IK immediately after the end of the delay time LT, and supply the limiting current to the internal circuit IK over the delay time LT as described above. Therefore, the charging current IR2 can be made smaller than the protection threshold value at which the protection circuit of the PC2 operates, and the malfunction of the device 3 due to the operation of the protection circuit being stopped and the supply of the current to the device 3 being stopped. It has been made to be able to prevent.

  Then, when the charging of the starting power is completed at time T3, the current limiting unit 13 supplies the PC 2 with a steady current DC for normal operation of the device 3 according to the power required by the internal circuit IK. Send to IK.

  On the other hand, when the starting power required by the internal circuit IK is completely charged by the limiting current supplied to the internal circuit IK from the time point T0 to the time point T2, the charging current IR2 as described above is generated. Absent. Even in this case, the inrush current suppression circuit 10 can reliably cause the PC 2 to recognize that the device 3 is connected by the recognition current IR1, so that the current can be supplied from the PC 2 to the device 3. It is designed to prevent malfunctions.

  Further, since the current limiting unit 13 sends the current supplied from the PC 2 to the internal circuit IK in accordance with the power required by the internal circuit IK after the time T2 when the delay time LT has elapsed, The power required by the internal circuit IK can be sent to the internal circuit IK at a timing that requires the internal circuit IK without any time lag or current limitation. As a result, the device 3 can perform a stable operation.

  Incidentally, the inrush current suppression circuit 10 adjusts the delay time LT and the magnitude of the limit current according to the startup power of the internal circuit IK, and according to the magnitude of the startup power of the internal circuit IK and the protection threshold value of the PC 2. Thus, the magnitude of the charging current IR2 can be freely set.

  In this way, the current limiting unit 13 gradually sends the starting power to the internal circuit IK by sending the current to the internal circuit IK from the time T0 while limiting the current, and sets the starting power to be charged to the internal circuit IK. The charging current IR2 generated for charging the internal circuit IK with the remaining starting current at the time T2 when the delay time LT has elapsed can be made smaller than the protection threshold at which the protection circuit of the PC2 operates. In addition, since the current supply to the device 3 can be prevented from being stopped due to the operation of the protection circuit of the PC 2, the current is normally supplied from the PC 2 to the device 3 to prevent malfunction of the device 3. Has been made to get.

  Next, a specific inrush current suppression circuit 10 will be described with reference to FIG. The current supply line 32 is connected to the power input end 21 and the power output end 22, and the ground line 31 is connected to the ground end 23 and the ground end 24, respectively.

  The recognition current generator 11 is configured by disposing a capacitor C1 between the current supply line 32 and the ground line 31.

  The time adjustment unit 12 is configured by connecting a resistor R2 and a capacitor C2 forming a time constant circuit in parallel with the capacitor C1, and connecting the gate terminal of the field effect transistor Q1 between the resistor R2 and the capacitor C2. Has been.

  In the current limiting unit 13, the gate terminal of the field effect transistor Q2 is connected to the drain terminal of the field effect transistor Q1, and the resistor R3 is connected between the drain terminal of the field effect transistor Q1 and the source terminal of the field effect transistor Q2. Further, a resistor R1 is arranged in parallel with the field effect transistor Q2 between the source terminal and the drain terminal of the field effect transistor Q2.

  First, in a state where no voltage is applied from the power input terminal 20, the field effect transistor Q1 and the field effect transistor Q2 are off.

  When the device 3 is connected to the PC 2 at the time T0, the inrush current suppression circuit 10 applies a voltage to the current supply line 32, and the capacitor C1 of the recognition current generation unit 11 is charged. As a result, a charging current for the capacitor C1 is generated as the recognition current IR1 (FIG. 3), and a momentary large current flows into the inrush current suppression circuit 10. The current value of the adjustment inrush current IR can be freely adjusted by the capacity of the capacitor C1 used.

  On the other hand, in the current limiting unit 13, the limiting current is constantly supplied to the internal circuit IK through the resistor R1. Note that the magnitude of the limiting current can be freely adjusted by the magnitude of the resistor R1.

  On the other hand, in the time adjustment unit 12, the capacitor C2 is gradually charged through the resistor R2. At this time, the potential is adjusted by the resistor R3, and the field effect transistor Q1 is surely turned off. When charging of the capacitor C2 is completed at the time point 2 (FIG. 3) when the delay time LT has elapsed, a voltage is applied to the gate of the field effect transistor Q1, and the field effect transistor Q1 is turned on. The delay time LT can be freely adjusted by a time constant “resistance R2 × capacitor C2”.

  When the field effect transistor Q1 is turned on at time T2, the current limiting unit 13 applies a negative voltage to the gate of the field effect transistor Q2, and the field effect transistor Q2 is turned on. As a result, a drain current flows through the field effect transistor Q2, and the current is sent to the internal circuit IK via the field effect transistor Q2.

(3) Operation and Effect In the above configuration, in the inrush current suppression circuit 10 of the present invention, the recognition current generation unit 11 is provided before the time adjustment unit 12 and the current limiting unit 13, and immediately after the device 3 is connected to the PC 2. When the device 3 having the internal circuit IK that is the operation circuit of the device 3 is connected to the PC 2, the current limiting unit 13 limits the current supplied from the PC 2 to the internal circuit IK. Send it out. The inrush current suppression circuit 10 releases the current limitation at the timing when the delay time LT has elapsed, and sends the current supplied from the PC 2 to the internal circuit IK according to the power required by the internal circuit IK.

  Thus, the inrush current suppression circuit 10 generates the recognition current IR1 at the timing when the device 3 is connected to the PC2, regardless of the configuration and settings of the internal circuit IK, the time adjustment unit 12, and the current limiting unit 13, and the PC2 Can reliably detect that the device 3 is connected to the PC 2 and allow the PC 2 to supply a steady current, thereby ensuring that the subsequent power is supplied from the PC 2 and operating the device 3 normally. Can do.

  In the inrush current suppression circuit 10, the recognition current generator 11 is provided in front of the time adjustment unit 12 and the current limiting unit 13, so that the recognition current IR 1 can be generated quickly immediately after the PC 2 and the device 3 are connected. Therefore, as compared with the conventional method of simply limiting the current to the internal circuit IK for a predetermined time and then releasing the limitation after charging the internal circuit IK, the device 3 is quickly connected to the PC 2 Therefore, the PC 2 can promptly send an operation instruction to the device 3, and the device 3 can be operated quickly.

  Further, the inrush current suppression circuit 10 sends out the current supplied from the PC 2 to the internal circuit IK while limiting the current supplied thereto, and cancels the current limitation at the timing when the delay time LT has passed, so that the delay time LT is applied. The startup power can be charged to the internal circuit IK little by little, the charging current IR2 generated to charge the startup power of the internal circuit IK at once can be reduced, and the inrush current can be suppressed. Thus, the power supply to the device 3 can be prevented from being stopped, and the device 3 can be operated normally.

  Further, in the inrush current suppression circuit 10, since the recognition current IR1 and the charging current IR2 can be reduced, the maximum current value of the device 3 can be reduced and the difference between the steady current and the maximum current value can be reduced. Compared with the device 3 that does not have a conventional inrush current suppression circuit, it is possible to prevent a current exceeding the rated current from flowing, and failure of the internal circuit IK due to a current exceeding the rated current flowing or excessive Since the load can be prevented, the durability of the device 3 can be improved, and the maximum current value can be reduced. Therefore, the rated current value can be reduced according to the maximum current value, and a simple configuration can be achieved.

  The inrush current suppression circuit 10 is provided between the current supply line 32 and the ground line 31 connected to the VBUS conforming to the USB standard, and includes a capacitor C1 as a recognition current generation unit 11 that generates the recognition current IR1, and a limit. A resistor R2, a capacitor C2, and a field effect transistor Q1 as a time adjustment unit 12 that generates a trigger for release; a resistor R1, a resistor R3 as a current limiter 13 that sends out the current to the internal circuit IK while limiting the current; Since it is configured by the field effect transistor Q2, the number of components can be significantly reduced as compared with the conventional method in which three transistors are combined to flow a constant current, and thus a simple configuration can be achieved.

  According to the above configuration, the inrush current suppression circuit 10 adjusts the inrush current supplied from the PC 2 at the timing when the device 3 is connected to the PC 2, and first the recognition current generator 11 supplies the recognition current IR 1 from the PC 2. As a result, it is possible to reliably recognize that the device 3 is connected to the PC 2 without being affected by other circuit configurations, to supply the subsequent power, and over the delay time LT adjusted by the time adjustment unit 12. Thus, the current limiting unit 13 can limit the current and send the current to the internal circuit IK to gradually charge the starting power, so that the charging current IR2 can be made smaller than the protection threshold value at which the protection circuit operates. Since the protection circuit can be prevented from operating, power can be normally supplied to the PC 2, thus preventing malfunction of the device 3. That.

(4) Other Embodiments In the above-described embodiment, when the PC 2 supplies a current exceeding a predetermined protection threshold, the protection circuit operates and stops supplying the current to the device 3. However, the present invention is not limited to this, and when the PC 2 does not have a protection circuit, a large inrush current is supplied to the device 3 so that the PC 2 and other devices connected to the PC 2 are connected. The power is instantaneously insufficient, and the PC 2 and other devices malfunction.

  Even in this case, the inrush current suppression circuit 10 of the present invention can reduce the charging current IR2 by sending power to the internal circuit IK by the current limiting unit 13 and gradually charging it, so that the PC2 And malfunction due to momentary shortage of power of other devices can be prevented.

  In the above-described embodiment, the PC 2 has described the case in which the device 3 recognizes that the device 3 is connected when a current exceeding a predetermined recognition threshold is supplied and supplies a steady current. The invention is not limited to this, and the PC 2 may automatically supply a steady current to the connected device 3 regardless of whether or not the connected device 3 is recognized.

  Even in this case, the inrush current suppression circuit 10 can reliably cause the PC 2 to recognize that the device 3 is connected by the recognition current IR1. Thereby, the inrush current suppression circuit 10 can prevent malfunction of the device 3 due to the fact that the PC 2 cannot recognize the device 3 and is not given an operation instruction to the device 3.

  In the above-described embodiment, the case where the PC 2 monitors the current flowing to the USB port 3A and detects that the current is equal to or higher than the recognition threshold value is to recognize that the device 3 is connected. The present invention is not limited to this. When the charge amount or voltage per predetermined time to the USB port 3A is monitored and a charge amount higher than the recognition threshold is supplied, or when a voltage higher than the recognition threshold is applied. A steady current may be automatically supplied to the connected device 3. Even in this case, similarly, the inrush current suppression circuit 10 can cause the PC 2 to recognize that the device 3 is connected by the recognition current IR1, so that it can promptly receive an operation instruction from the PC 2 and operate the device 3. Can be made.

  Further, in the above-described embodiment, the case where the inrush current suppression circuit 10 is provided inside the device 3 has been described. However, the present invention is not limited to this, and for example, the inside of various cables such as a USB cable. You may make it provide in. Thus, even when the device 3 not having the inrush current suppression circuit 10 and the PC 2 are connected, by connecting the device 3 and the PC 2 using the USB cable having the inrush current suppression circuit 10 As described above, malfunctions in the device 3 and the PC 2 can be prevented.

  Further, in the above-described embodiment, the case where the inrush current generation unit 11 generates the recognition current IR1 by charging the capacitor C1 with electric power has been described. However, the present invention is not limited to this. By forming a circuit combining effect transistors and the like, the power charged in the capacitor C1 may be sent to the internal circuit IK. As a result, the inrush current suppression circuit 10 can send the power supplied from the PC 2 to the internal circuit IK without waste, and the power charged in the capacitor C1 until the delay time LT elapses. When the power is sent to the circuit IK, the power can be charged to the internal circuit IK as the starting power, so that the charging inrush current IR2 can be further reduced.

  Further, in the above-described embodiment, the time adjustment unit 12 has described the case where the current is sent to the current limiting unit 13 as a trigger for releasing the current limitation when the delay time LT has elapsed. The invention is not limited to this. For example, a switch signal may be sent to the current limiting unit 13 as a trigger, and the current limiting unit 13 may release the current limitation in accordance with the switch signal.

  Further, in the above-described embodiment, the recognition current generation unit 11 as the recognition current generation unit, the time adjustment unit 12 as the limit release unit, and the current limit unit 13 as the current limit unit serve as an inrush current suppression circuit. Although the case where the inrush current suppressing circuit 10 is configured has been described, the present invention is not limited to this, and the inrush current is suppressed by a recognition current generating unit, a limit releasing unit, and a current limiting unit having various other configurations. A circuit may be configured.

  The inrush current suppression circuit of the present invention is connected to various power supply devices such as a personal computer, and is applied to various electronic devices such as a digital camera, a memory card reader / semiconductor memory, and a semiconductor memory which operate by receiving power from the power supply device. Can be applied.

It is a basic diagram which shows the whole structure of a power supply system. It is a basic diagram which shows the functional block of an inrush current suppression circuit. It is an approximate line figure showing current supply to an inrush current control circuit. It is a basic diagram which shows the structure of an inrush current limiting circuit. It is a basic diagram which shows the electric current supply to the conventional circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Power supply system, 2 ... Device 3A ... USB connector, 3 ... PC2A ... USB port, 10 ... Inrush current suppression circuit, 11 ... Inrush current generation part, 12 ... Time adjustment part, 13 ...... Current sending part.

Claims (3)

An inrush current suppressing circuit for suppressing an inrush current supplied from a power supply device,
Current limiting means for limiting the current from the power supply device to suppress inrush current;
Restriction release means for releasing the restriction of the current by the current restriction means when a predetermined delay time has elapsed since the start of the supply of the current;
Recognizing current generating means provided in a preceding stage of the current limiting means and the restriction releasing means for generating a recognition current for recognizing the power supply apparatus that a device is connected to the power supply apparatus. An inrush current suppression circuit characterized by that. The restriction release means is
A time constant circuit interposed between the ground line and the current supply line, and a first transistor having a gate terminal connected between the time constant circuits,
The current limiting means is
The gate terminal of the second transistor is connected to the drain terminal of the first transistor, and a resistor is interposed between the drain terminal and the source terminal of the second transistor.
The recognition current generating means includes
The inrush current suppressing circuit according to claim 1, comprising a capacitor interposed between the ground line and the current supply line. The inrush current suppression circuit according to claim 1, wherein the current supply line is a VBUS conforming to a USB standard.

Images