JP2007324843A - Rush current suppression circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rush current suppression circuit capable of supplying current necessary for quick starting of a load circuit while suppressing current rating of a power source. <P>SOLUTION: The rush current suppression circuit suppresses rush current to the load circuit when power source is turned on. The rush current suppression circuit comprises a load connection switch for switching off a part between a power source and a load circuit in an initial state, a capacitor provided closer to the power source side than the load connection switch and charged by the supplied current from the power source at starting, a first voltage monitoring circuit for monitoring voltage at both ends of the capacitor and turning on the load connection switch when reaching a prescribed voltage, a limiting resistor for limiting the current to be supplied to a load circuit by turning on the load connection switch, a second voltage monitoring circuit for monitoring voltage at both ends of the load circuit and detecting the end of standup of the load circuit, and a resistor short circuit switch for short-circuiting the limiting resistor when the starting of the load circuit ends. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an inrush current suppression circuit, for example, an attempt to prevent delay of start-up of a load circuit by an inrush current suppression function to a load circuit when a power source is turned on.

  Conventionally, an inrush current suppression circuit has been provided to suppress a large inrush current to the load circuit when power supply is started by turning on the power switch or inserting an electronic circuit card having a load circuit ( Patent Document 1).

The conventional inrush current suppression circuit is generally configured as shown in FIG. That is, a resistor 3 for preventing overcurrent is provided on the power supply line of the DC power supply 1 and the load circuit 2 such as an on-board power supply (OBP), and the voltage monitoring circuit 4 for monitoring the supply voltage to the load circuit 2 is provided. By detecting that the supply voltage has reached the desired voltage, the semiconductor switch 5 is turned on to short-circuit the resistor 3, and the power supply is started up while suppressing the inrush current immediately after the power supply is started Met.
Japanese Patent Laid-Open No. 10-327057

  By the way, the load circuit 2 often includes many IC chips, and the operating voltage of the IC chip is considerably low, such as 3.3V, 2.5V, 1.8V, 1.2V, and the like. At times, resistance power consumption is being planned. On the other hand, the load circuit 2 (IC chip group) has a large current capacity when the power supply is turned on, and a sharp power supply startup is required.

  However, an inrush current suppression circuit configured as shown in FIG. 4 is provided for stable power supply, and a regulator including a bypass capacitor is provided in the load circuit 2 for power supply stabilization. If the inrush current is suppressed, the current required for starting up the load circuit 2 (for example, an IC chip) cannot be supplied, which may cause a start-up failure.

  In order to avoid this, it is conceivable to use a DC power supply with high power and speed up the startup, but considering the capacity required during steady operation, use a DC power supply with excessive capacity. Will be.

  Therefore, there is a demand for an inrush current suppression circuit that can supply a current necessary for prompt start-up of the load circuit while suppressing the rated current of the power source.

  In order to solve such a problem, the present invention provides an inrush current suppression circuit that suppresses an inrush current to a load circuit when the power is turned on. (1) The power supply and the load circuit are disconnected in an initial state. A load connection switch for connecting the power supply and the load circuit when an ON control signal is given; and (2) provided on the power supply side from the load connection switch, and by a supply current at the time of rising from the power supply A capacitor to be charged; (3) a voltage monitoring circuit for controlling load connection that monitors an end-to-end voltage of the capacitor and gives an ON control signal to the load connection switch when a predetermined voltage is reached; and (4) the load A limiting resistor that limits the current supplied to the load circuit when the connection switch is turned on, and (5) monitors the voltage across the load circuit and detects the end of the rise of the load circuit. That the rising end detecting voltage monitoring circuit (6) when the rise of the load circuit termination is detected; and a resistor short-circuiting switch for short-circuiting the limiting resistor.

  According to the inrush current suppression circuit of the present invention, the capacitor is charged by the output current from the power source, and when the capacitor is in a predetermined charging state, the load circuit outputs the output current from the power source and the discharge current of the capacitor. Since the combined circuit is supplied to start up the load circuit, it is possible to supply the current necessary for the rapid startup of the load circuit while suppressing the rated current of the power supply.

(A) First Embodiment Hereinafter, a first embodiment of an inrush current suppression circuit according to the present invention will be described in detail with reference to the drawings.

(A-1) Configuration of First Embodiment FIG. 1 is a block diagram illustrating a configuration of an inrush current suppression circuit according to the first embodiment. In FIG. 1, the inrush current suppression circuit 10 of the first embodiment is also interposed between the DC power supply 1 and the load circuit 2. The inrush current suppression circuit 10, the DC power source 1, and the load circuit 2 of the first embodiment are mounted on the same printed wiring board, for example.

  The DC power source 1 is a so-called on-board power source (OBP), and may be an AC / DC converter, a DC / DC converter, or a device using various batteries. The DC power supply 1 may be turned on by turning on a power switch, or may be caused by the start of power supply to the printed wiring board on which the DC power supply 1 is mounted under the control of the upper board. The printed wiring board on which the DC power source 1 is mounted may be inserted into the upper board.

  The load circuit 2 is supplied with power from the DC power source 1 and includes, for example, a low power consumption IC chip.

  The inrush current suppression circuit 10 of the first embodiment includes a first inrush current suppression circuit unit 11, a large-capacitance capacitor 12, a load connection control circuit unit 13, and a second inrush current suppression circuit unit in order from the DC power supply 1 side. 14 and a start-up end detection voltage monitoring circuit unit 15.

  The first inrush current suppression circuit unit 11 includes a resistor 11a inserted in series with the high-potential-side power supply line LH, and a semiconductor switch composed of an FET switch or the like connected in parallel to the resistor 11a (other than the semiconductor switch) 11b may be applied; the same applies to semiconductor switches in other positions). The semiconductor switch 11b is normally off, and after the start-up detection voltage monitoring circuit unit 15 detects that the supply voltage to the load circuit 2 has sufficiently risen, the semiconductor switch 11b is on-controlled to short-circuit the resistor 11a. It is.

  As the large-capacitance capacitor 12, for example, a capacitor provided for emergency backup when the power is cut off is used. In general, a large-capacity capacitor for emergency backup when the power is turned off is connected so as to perform a positive discharge operation so as to supply power instead of the power when the power is turned off. In the case of the first embodiment, it is provided between the first inrush current suppression circuit unit 11 and the load connection control circuit unit 13. The large-capacitance capacitor 12 is charged by a power source from the DC power source 1 when a semiconductor switch 13a of a load connection control circuit unit 13 described later is off. In the case of the first embodiment, the large-capacitance capacitor 12 contributes to stabilization of the power supply voltage to the load circuit 2 during steady operation.

  The load connection control circuit unit 13 monitors the voltage across the semiconductor switch 13a, such as an FET switch inserted in series with the high-potential-side power supply line LH, and the large-capacitance capacitor 12 (charging voltage), thereby monitoring the semiconductor switch 13a. And a voltage monitoring circuit 13b for controlling on / off of the circuit. The semiconductor switch 13a disconnects the DC power supply 1 and the load circuit 2 when turned off, and connects the DC power supply 1 and the load circuit 2 when turned on. The voltage monitoring circuit 13b turns off the semiconductor switch 13a when the voltage across the large-capacitance capacitor 12 is lower than the threshold voltage, and turns on the semiconductor switch 13a when the voltage across the large-capacitance capacitor 12 is equal to or higher than the threshold voltage. .

  The second inrush current suppression circuit unit 14 includes a resistor 14a inserted in series with the high-potential-side power supply line LH, and a semiconductor switch 14b made of an FET switch or the like connected in parallel to the resistor 14a. The semiconductor switch 14b is normally off, and after the start-up detection voltage monitoring circuit unit 15 detects that the supply voltage to the load circuit 2 has sufficiently risen, the semiconductor switch 14b is on-controlled to short-circuit the resistor 14a. It is.

  The resistor 14a of the second inrush current suppression circuit unit 14 has a function of protecting the semiconductor switch 13a of the load connection control circuit unit 13 in addition to the function of suppressing the inrush current. The resistor 11a may mainly have a function of suppressing the inrush current, and the resistor 14a may have a resistance value small enough to fulfill the protective function of the semiconductor switch 13a. For example, the resistance value of the resistor 14a is determined in consideration of the startup request time required for the load circuit 2, and the specific type of the semiconductor switch 13a is determined based on the maximum current value determined from the value.

  The start-up detection voltage monitoring circuit unit 15 monitors the supply voltage to the load circuit 2 and controls to turn on the semiconductor switches 11b and 14b when it detects that the supply voltage to the load circuit 2 has risen sufficiently. A signal is output.

(A-2) Operation of the First Embodiment Next, the operation of the inrush current suppression circuit 10 of the first embodiment having the above configuration will be described.

  In the initial state before the power supply from the DC power supply 1 is started, all the semiconductor switches 11b, 13a and 14b in the inrush current suppression circuit 10 are in an off (open) state.

  In this initial state, when the DC power source 1 is turned on (when power supply is started), a charging current flows to the large-capacitance capacitor 12 via the first inrush current suppression circuit unit 11, and the large-capacity capacitor 12 is charged. Thus, the voltage across the large-capacitance capacitor 12 gradually increases. During such charging, since the semiconductor switch 13a is off, no power is supplied to the load circuit 2.

  The voltage monitoring circuit 13b of the load connection control circuit unit 13 monitors the voltage (charged state) across the large-capacitance capacitor 12. When the voltage across the capacitor 12 can ensure a stable voltage, the semiconductor switch 13a is turned on (closed). Let When the semiconductor switch 13a is turned on, rapid power supply is performed to the load circuit 2 via the second inrush current suppression circuit unit 14. In the power supply at the time of rising to the load circuit 2, the limiting resistors 11a and 14a function to suppress the inrush current, and the function of the limiting resistor 14a can prevent the semiconductor switch 13a from being destroyed.

  In the power supply state at the time of start-up to the load circuit 2, the start-up end detection voltage monitoring circuit unit 15 monitors (voltage monitoring) that the power supply state to the load circuit 2 is sufficient. When it is detected that the power supply state has been entered, the semiconductor switches 11b and 14b are turned on, the limiting resistors 11a and 14a are short-circuited, the restriction of the inrush current is released, and the steady state is entered.

(A-3) Effects of the First Embodiment According to the inrush current suppression circuit of the first embodiment, when viewed from the load circuit 2, the power supply start time is the time when the DC power supply 1 starts power supply. Rather, it is when the semiconductor switch 13a is turned on, and the supply current at that time is approximately the combined current of the output current of the DC power supply 1 and the discharge current of the large-capacitance capacitor 12, and therefore the output current of the DC power supply 1 A sufficient startup current can be supplied to the load circuit 2 without increasing the (rated current), and the load circuit 2 can be started up quickly.

  FIG. 2 is an explanatory diagram of this effect. Now, let the output current (rated current) of the DC power source 1 flowing through the limiting resistor 11a be i1 and the discharge current i2 of the large-capacitance capacitor 12. In the case of the conventional circuit as shown in FIG. 4, at the time of start-up, only the current (rated current) i1 is supplied to the load circuit, and therefore, toward the predetermined voltage VREF as shown by the straight line L1 in FIG. Stand up slowly. On the other hand, in the case of the first embodiment, at the time of start-up, the sum of the output current (rated current) of the DC power source 1 and the discharge current i2 of the large-capacitance capacitor 12 becomes the supply current, as shown by the straight line L2 in FIG. Then, it quickly rises toward the predetermined voltage VREF.

  Thereby, it is possible to prevent the load circuit 2 from causing a start-up failure.

(B) Second Embodiment Next, a second embodiment of the inrush current suppression circuit according to the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a block diagram showing the configuration of the inrush current suppression circuit 10A of the second embodiment. The same and corresponding parts as those in FIG. 1 according to the first embodiment are indicated by the same reference numerals. ing.

  The inrush current suppression circuit 10A of the second embodiment is for a case where the DC power supply 1 supplies power to a plurality of load circuits 2-1 and 2-2 (two examples in FIG. 3). Corresponding to each load circuit 2-1, 2-2, large-capacitance capacitors 12-1, 12-2, load connection control circuit units 13-1, 13-2, second inrush current suppression circuit unit 14-1. 14-2 and start-up end detection voltage monitoring circuit units 15-1 and 15-2. The first inrush current suppression circuit unit 11 is connected to both load circuits 2-1 and 2-2. It is common.

  The semiconductor switch 11b of the first inrush current suppression circuit section 11 is controlled to be turned on by the output of the rising end detection voltage monitoring circuit sections 15-1 and 15-2 that is detected later. Yes.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained, and the effect that it is possible to cope with a plurality of load circuits to which the DC power supply is supplied can also be achieved.

(C) Other Embodiments In the description of each of the above embodiments, various modified embodiments have been referred to, but further modified embodiments as exemplified below can be given.

  In each of the above embodiments, the second inrush current suppression circuit units 14, 14-1 and 14-2 are provided. However, the semiconductor switches 13 a, 13 a-1 and 13 a-2 in the load connection control circuit unit are shown. Depending on the tolerance, the second inrush current suppression circuit unit may be omitted. Further, the second inrush current suppression circuit unit 14, 14-1, and 14-2 may be left and the first inrush current suppression circuit unit 11 may be omitted. In this case, the values of the limiting resistors of the second inrush current suppression circuit units 14, 14-1, and 14-2 can be increased in consideration of suppression of the inrush current.

  Further, in each of the above embodiments, the large capacitors 12, 12-1, and 12-2 are shown to function even in the steady state. May be cut off.

  Further, in each of the above embodiments, the charging current to the large-capacitance capacitors 12, 12-1, and 12-2 passes through the first inrush current suppression circuit unit 11, but the first inrush current suppression is performed. Large capacitors 12, 12-1, and 12-2 may be provided on the power supply 1 side of the circuit unit 11.

  Further, in each of the above embodiments, the semiconductor switch for disconnecting the load circuit in the initial state is provided in the high potential side power supply line LH. However, it may be provided in the low potential side power supply line LL. Alternatively, both lines LH and LL may be provided. A similar modification can be given for the limiting resistance.

It is a block diagram which shows the structure of the inrush current suppression circuit of 1st Embodiment. It is explanatory drawing of the effect of 1st Embodiment. It is a block diagram which shows the structure of the inrush current suppression circuit of 2nd Embodiment. It is a block diagram which shows the structure of the conventional inrush current suppression circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2, 2-1, 2-2 ... Load circuit 10, 10A ... Inrush current suppression circuit, 11 ... 1st inrush current suppression circuit part, 12, 12-1, 12-2 ... Large capacity Capacitors 13, 13-1, 13-2 ... Load connection control circuit unit, 14, 14-1, 14-2 ... Second inrush current suppression circuit unit, 15, 15-1, 15-2 ... End of start-up Detection voltage monitoring circuit section.

Claims (2)

In the inrush current suppression circuit that suppresses the inrush current to the load circuit when the power is turned on,
A load connection switch that disconnects the power supply and the load circuit in an initial state and connects the power supply and the load circuit when an ON control signal is given;
A capacitor provided on the power supply side from the load connection switch and charged by a supply current at the time of rising from the power supply;
A voltage monitoring circuit for load connection control that monitors the voltage across the capacitor and gives an on control signal to the load connection switch when a predetermined voltage is reached;
A limiting resistor that limits the current supplied to the load circuit by turning on the load connection switch;
A voltage monitoring circuit for detecting the end of rising, which monitors the voltage across the load circuit and detects the end of rising of the load circuit;
And a resistance short-circuit switch for short-circuiting the limiting resistor when the end of rising of the load circuit is detected. Two sets of the limiting resistor and the resistance short-circuit switch are provided, one set is provided on the power supply side from the load connection switch, and the other set is provided on the load circuit side from the load connection switch. The inrush current suppression circuit according to claim 1, wherein:

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