JP5105083B2 - Broadband power amplifier and bias control circuit - Google Patents

Description

  The present invention relates to a broadband power amplifier and a bias control circuit, and more particularly to a broadband power amplifier and a bias control circuit that apply a burst voltage as a bias voltage.

  A VHF (very high frequency) or UHF (ultra high frequency) band radio communication system (for example, a mobile broadband radio communication system) is known (for example, see Patent Document 1).

  In this wireless communication system, the modulation schemes are diversified, so that the required signal-to-noise ratio (C / N) is also increased, and the power amplifier has a higher output in order to ensure the communication reachability. Required.

  However, since the power source of the moving body is limited, it is necessary to reduce power consumption.

  FIG. 6 is a circuit diagram of an example of a broadband power amplifier related to the present invention.

  Referring to the figure, an example of a broadband power amplifier related to the present invention includes a gate bias circuit 5, a power amplifier 1, a negative feedback circuit 2, an inductor 6, and a power source 7.

  The gate bias circuit 5 includes a gate bias unit 51 and a resistor 52. The gate bias unit 51 generates a predetermined gate bias voltage. The resistor 52 is a voltage dividing resistor.

  The power amplifier 1 includes an input terminal 8, a capacitive element (hereinafter referred to as a capacitor) 11, a transistor 12, a capacitor 13, and an output terminal 9.

  A high frequency signal is input to the input terminal 8. Capacitors 11 and 13 are for DC blocking and are set to values that are sufficiently lower in impedance than high-frequency signals.

  For example, the transistor 12 is a DMOSFET (double diffusion metal oxide semiconductor field effect transistor) suitable for amplification of VHF and UHF.

  A high frequency signal amplified by the transistor 12 is output from the output terminal 9.

  The negative feedback circuit 2 includes a resistor 21 and a capacitor 22.

  The inductor 6 is for high frequency blocking.

  The power source 7 supplies power to the power amplifier 1 and is, for example, a direct current power source such as a battery or a battery of a moving body.

  The gate bias circuit 5 constantly supplies a predetermined gate bias voltage to the gate of the transistor 12 of the power amplifier 1.

  The negative feedback circuit 2 has a transistor (for example, DMOSFET) 12 of the power amplifier 1 that has a large gain in the low frequency region and a low gain in the high frequency region, so that the frequency characteristic is flattened. Negative feedback is applied from the drain to the gate of the transistor 12.

  The inductor 6 always supplies a bias voltage to the drain of the power amplifier 1.

  However, in the related broadband power amplifier shown in FIG. 6, since a bias voltage is always supplied to the power amplifier 1, there is a problem that standby current flows even during transmission and power saving is difficult.

  An example of an invention for solving this problem is disclosed in Patent Document 1. The invention described in this document is to operate the power supply in a burst manner to reduce power consumption.

  In the present invention, a negative feedback circuit is connected between the gate and drain of the FET of the power amplifier in order to expand the frequency band of the power amplifier.

  However, when the power supply is operated in a burst mode, a surge voltage due to the burst operation of the power supply is input to the gate of the FET via negative feedback connected between the gate and drain of the FET of the power amplifier, and the characteristics of the FET are deteriorated. There is a problem.

  In order to solve this problem, in the invention described in Patent Document 1, a Zener diode is further provided in the negative feedback to suppress a surge voltage due to a burst operation of the power supply.

  That is, the peak of the surge voltage at the rise and fall of the power supply voltage is suppressed to a predetermined voltage by the Zener diode.

  Another example of the related invention is disclosed in Patent Document 2.

  The present invention relates to a gate control device for a voltage-controlled switching element such as a MOSFET, and is characterized by suppressing a surge voltage generated when the switching element is turned off during inverter operation.

JP 2005-236679 A JP 05-090928 A

  However, in the invention disclosed in Patent Document 1, since the surge voltage is suppressed by a Zener diode, the Zener voltage is added to the gate bias voltage, and the gate bias potential rises to the Zener potential. It cannot be said that it can be suppressed.

  On the other hand, the invention disclosed in Patent Document 2 is intended to prevent the switching element from being damaged, and aims to reduce the power consumption of the broadband power amplifier of the present invention and to suppress the deterioration of transistor characteristics. Are completely different, and therefore the configuration and effects for achieving the objective are also completely different.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wideband power amplifying device and a bias control circuit that can save power and can suppress deterioration of transistor characteristics as compared with related art.

Broadband power amplifier according to the present invention for solving the above problem is a wideband power amplifier for VHF and UHF, a negative feedback circuit provided between the input and the output of the wideband power amplifier, the input side of the wideband power amplifier or a burst control circuit for applying a burst voltage as a bias voltage to the output side, the wideband power input to the bias control for reducing a surge voltage generated by the amplifier when the burst voltage is applied to the wideband power amplifier The bias control circuit includes a surge voltage short-circuit unit that short-circuits the surge voltage using a transistor .

The bias control circuit according to the invention, VHF and a broadband power amplifier for UHF, wherein the negative feedback circuit provided between the input and output of the wideband power amplifier, the bias voltage to the input or output side of said wide-band power amplifier A broadband control circuit that applies a burst voltage and a bias control circuit that reduces a surge voltage generated on the input side of the broadband power amplifier when the burst voltage is applied to the broadband power amplifier. The bias control circuit in an amplifying device includes a surge voltage short-circuit unit that short-circuits the surge voltage using a transistor .

  According to the present invention, power saving can be achieved, and deterioration of transistor characteristics can be suppressed more than in the related art.

  First, before entering the description of the embodiment of the present invention, the operation principle of the present invention will be described.

  FIG. 1 is a diagram showing an operation principle of an example of a wideband power amplifying apparatus according to the present invention. In addition, the same number is attached | subjected about the same component as an example (refer FIG. 6) of a related broadband power amplifier, and the description is abbreviate | omitted.

  Referring to the figure, an example of a wideband power amplifier according to the present invention includes a power amplifier 1, a negative feedback circuit 2 provided between the input and output of the power amplifier 1, and the input side or output side of the power amplifier 1. And a burst control circuit 3 for applying a burst voltage as a bias voltage.

  Furthermore, an example of the broadband power amplifying device according to the present invention includes a bias control circuit 4 that reduces a surge voltage generated on the input side of the power amplifier 1, and the bias control circuit 4 includes a surge voltage short-circuit unit 41 that short-circuits the surge voltage. Contains.

  A burst voltage is applied as a bias voltage by the burst control circuit 3 to the input side or the output side of the power amplifier 1. Further, a negative feedback circuit 2 for flattening frequency characteristics is connected between the input and output of the power amplifier 1.

  If the bias control circuit 4 does not exist, a surge voltage is generated on the input side of the power amplifier 1 when a burst voltage is applied to the power amplifier 1.

  However, in the present invention, when the bias control circuit 4 is present and a burst voltage is applied to the power amplifier 1 and a surge voltage is generated on the input side of the power amplifier 1, the surge voltage short-circuit unit 41 in the bias control circuit 4 is While the surge voltage is generated, the input side of the power amplifier 1 is forcibly short-circuited.

  As described above, according to the present invention, since a burst voltage is supplied to the power amplifier 1 as a bias voltage, it is possible to save power compared to the case where the bias voltage is always supplied.

  Moreover, since the surge voltage short-circuit unit 41 in the bias control circuit 4 short-circuits the surge voltage generated on the input side of the power amplifier 1 when the power supply is operated in a burst mode, the surge voltage is suppressed more than in the related art. It becomes possible.

  Hereinafter, embodiments of the present invention will be described. First, the first embodiment will be described. FIG. 2 is a circuit diagram of the first embodiment of the broadband power amplifier according to the present invention. Components similar to those in FIGS. 1 and 6 are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 2, the first embodiment of the broadband power amplifying device according to the present invention includes a power amplifier 1 and a negative feedback circuit 2 connected between a gate and a drain of a transistor 12 described later in the power amplifier 1. Consists of including.

  Furthermore, the first embodiment of the broadband power amplifier according to the present invention includes a burst control circuit 3 that applies a burst voltage as a bias voltage to the drain of the transistor 12.

  Furthermore, the first embodiment of the broadband power amplifying device according to the present invention includes a gate bias control circuit 4 for reducing a surge voltage generated at the gate of the power amplifier 1 and a gate bias circuit 5 for generating a predetermined bias voltage. Consists of.

  Furthermore, the first embodiment of the broadband power amplifying apparatus according to the present invention includes an inductor 6 and a power source 7 that generates a constant voltage.

  The power amplifier 1 includes an input terminal 8, a capacitor 11, a transistor 12, a capacitor 13, and an output terminal 9.

  A high frequency signal is input to the input terminal 8. Capacitors 11 and 13 are for DC blocking and are set to values that are sufficiently lower in impedance than high-frequency signals.

  For example, the transistor 12 is a DMOSFET suitable for amplification of VHF and UHF.

  A high frequency signal amplified by the transistor 12 is output from the output terminal 9.

  The negative feedback circuit 2 includes a resistor 21 and a capacitor 22. One end of the resistor 21 and one end of the capacitor 22 are connected in series. The other end of the resistor 21 is connected to the gate of the transistor 12 in the power amplifier 1 and the other end of the capacitor 22 is connected to the drain.

  That is, the transistor 12 has a relatively large gain in the low frequency region and tends to have a relatively low gain in the high frequency region. Therefore, the negative feedback circuit 2 is used to flatten the frequency characteristics from the drain of the transistor 12. Apply negative feedback to the gate.

  The negative feedback circuit 2 flattens the frequency characteristics and contributes to the stable operation of the amplifier. However, since the negative feedback circuit 2 is connected in series with the resistor 21 and the capacitor 22, it is differentiated when a bursty steep voltage is input to the drain of the transistor 12. The surge voltage waveform is applied to the gate of the transistor 12.

  The burst control circuit 3 includes a transistor 31 and a burst control unit 32 that is connected to the gate of the transistor 31 and controls on / off of the transistor 31. The power source 7 is connected to the source of the transistor 31.

  The burst control unit 32 controls the transistor 31 so that the output voltage of the power source 7 is supplied to the drain of the transistor 12 in the power amplifier 1 via the inductor 6 only at the time of transmission.

  Therefore, it is preferable to use an FET that can handle a large current with high speed switching and low loss as the transistor 31.

  The gate bias control circuit 4 includes a transistor 42 constituting a surge voltage short circuit 41, a capacitor 43 connected between the base of the transistor 42 and the drain of the transistor 31 in the burst control circuit 3, a collector of the transistor 42, and a negative feedback circuit. And an inductor 44 connected between the other ends of the two resistors 21. The emitter of the transistor 42 is grounded.

  The transistor 42 is a bipolar type. This is because the FET has a relatively high cut-off voltage, and thus the gate bias may not be short-circuited.

  The transistor 42 shorts a surge voltage generated at the gate of the transistor 12 in the power amplifier 1.

  The capacitor 43 sets the time for short-circuiting the surge voltage. The inductor 44 prevents the transistor 12 from becoming unloaded in high frequency when the surge voltage is short-circuited.

  The gate bias circuit 5 includes a gate bias unit 51 and a resistor 52, and supplies a predetermined gate bias voltage to the gate of the transistor 12 of the power amplifier 1 at all times.

  The resistor 52 is a voltage dividing resistor and has a sufficiently large value as compared with the gate impedance of the transistor 12.

  The inductor 6 supplies a bias to the drain of the transistor 12 in the power amplifier 1. Since a large current flows, the inductor 6 has a low impedance and prevents high frequency leakage to the power source 7. Must be impedance.

  The power source 7 supplies power to the power amplifier 1 and is, for example, a direct current power source such as a battery or a battery of a moving body.

  In this embodiment, the transistor 12 of the power amplifier 1 has a single configuration. However, the present invention is not limited to this, and the present invention can also be applied to a push-pull configuration.

  The present invention can be applied to the arrangement of the resistor 21 and the capacitor 22 of the negative feedback circuit 2 and vice versa.

  When the power supply 7 is turned on only during transmission by the burst control circuit 3, a surge voltage due to a burst operation is generated through the negative feedback circuit 2 connected between the gate and drain of the transistor 12 in the power amplifier 1, and this voltage Is input to the gate of the transistor 12. Therefore, the surge voltage is superimposed on the gate bias voltage supplied by the gate bias circuit 5 at the gate of the transistor 12.

  In contrast, the gate bias control circuit 4 shorts this surge voltage.

  Hereinafter, the operation of the first embodiment will be described in detail.

  Referring to FIG. 2, when the power supply 7 is turned on during transmission by the burst control circuit 3, the voltage from the power supply 7 is applied to the drain of the transistor 12 in the power amplifier 1 via the transistor 31 and the inductor 6. As a result, a surge voltage is superimposed on the gate of the transistor 12 via the negative feedback circuit 2.

  On the other hand, when the power supply 7 is turned on during transmission by the burst control circuit 3, the voltage from the power supply 7 is input to the base of the transistor 42 via the capacitor 43 of the gate bias control circuit 4.

  Thereby, the transistor 42 is turned on, and the surge voltage superimposed on the gate of the transistor 12 is grounded, that is, short-circuited via the inductor 44 and the transistor 42.

  In addition, since the capacitor 43 is connected to the base of the transistor 42, it is possible to appropriately set the time for short-circuiting the surge voltage by changing the capacitance of the capacitor 43.

  In addition, since the inductor 44 is connected between the collector of the transistor 42 and the gate of the transistor 12, it is possible to prevent the transistor 12 from becoming unloaded in high frequency when the surge voltage is short-circuited.

  Next, a specific example of the operation of the first embodiment will be described with reference to FIG. FIG. 3 is a timing chart showing a specific example of the operation of the first embodiment.

  A voltage Vbst in FIG. 5A indicates a burst control voltage that is an output of the burst control unit 32 in the burst control circuit 3. The burst control unit 32 generates a burst control voltage V4 during transmission (time t1).

  When this voltage V4 is applied to the gate of the transistor 31 in the burst control circuit 3, the transistor 31 is turned on, and the output voltage V5 of the power supply 7 is applied to the drain of the transistor 12 in the power amplifier 1. FIG. 2B shows the drain voltage Vd applied to the drain of the transistor 12.

  FIG. 3C shows the gate voltage of the transistor 12 in the power amplifier 1. The gate bias voltage Vg (voltage V1) from the gate bias circuit 5 is always applied to the gate of the transistor 12 in the power amplifier 1. However, the gate bias voltage Vg is short-circuited by the gate bias control circuit 4 during the time t1 to t2 when the surge voltage is generated by the negative feedback circuit 2, and as a result, the gate bias voltage Vg is changed from V1 to V3 (0 <V3 < V1).

  FIG. 5E shows the drain current Ad of the transistor 12. A current A1 indicates a standby current when a normal gate bias voltage and drain voltage are applied. This figure shows that the inrush current generated at the drain of the transistor 12 when the output voltage V5 of the power supply 7 rises is suppressed to the current A1 or less.

  FIG. 4D shows the gate voltage Vg of the transistor in the power amplifier in the related art, and the surge voltage V2 (V2> V1) exceeding the normal gate bias voltage V1 is between time t1 and time t2. It shows a state where the signal is input to the gate of the transistor inside.

  In the related art, since the surge voltage V2 is input to the gate of the transistor in the power amplifier, an inrush current A2 (A2> A1) far exceeding the normal standby current A1 flows to the drain of the transistor (FIG. F)), which contributed to the deterioration of transistor characteristics.

  As described above, according to the first embodiment of the present invention, since the surge voltage generated by the burst operation of the power supply is short-circuited, it is possible to appropriately suppress the deterioration of the transistor characteristics of the power amplifier. It becomes.

  In addition, since the power supply of the power amplifier is operated in a burst, significant power saving can be achieved.

  In addition, since the gate bias voltage is short-circuited while the surge voltage is generated, inrush current during burst operation can also be suppressed, thereby preventing malfunction of peripheral circuits due to instantaneous voltage drop. Is possible.

  Next, a second embodiment will be described. FIG. 4 is a circuit diagram of a second embodiment of the broadband power amplifier according to the present invention. In addition, the same number is attached | subjected to the component similar to FIG. 2, and the description is abbreviate | omitted.

  Referring to this figure, the difference from the first embodiment (see FIG. 2) is that a burst voltage is applied to the gate of the power amplifier 1 and that the capacitor 43 is connected to the base of the transistor 42 of the gate bias control circuit 4. Instead, a timer circuit 48 is connected. Other configurations are the same as those of the first embodiment.

  Some types of power amplifier transistors do not recommend drain bias burst operation. For this reason, in the second embodiment, the burst control is further devised.

  In the present embodiment, the power source 7 is always supplied to the 12 drains of the transistors of the power amplifier 1.

  The burst control circuit 3 applies the gate bias voltage from the gate bias circuit 5 to the gate of the transistor 12 of the power amplifier 1.

  When a gate bias voltage is applied to the 12 gates of the transistors of the power amplifier 1, the gate bias control circuit 4 shorts the 12 gates of the transistors of the power amplifier 1 for the time set by the timer circuit 48.

  That is, the burst control unit 32 of the burst control circuit 3 controls the transistor 31 and also controls the timer circuit 48.

  Next, a specific example of the operation will be described with reference to FIG. FIG. 5 is a timing chart showing a specific example of the operation of the second embodiment.

  First, at time t1, when the burst control unit 32 applies the burst control voltage Vbc to the gate of the transistor 31 (see burst control Vbc in FIG. 3A), the gate voltage Vg is applied from the gate bias circuit 5 to the gate of the transistor 12. Applied.

  At time t1, the burst control unit 32 controls the timer circuit 48 to turn on the transistor 42 for a time preset in the timer circuit 48 (between time t1 and time t2) (in FIG. Gate bias control Vgc).

  While the gate bias control voltage Vgc is input from the timer circuit 48 (between time t1 and time t2), the transistor 42 of the gate bias control circuit 4 shorts the gate of the transistor 12.

  FIG. 5B shows that the drain bias voltage Vd of the transistor 12 is always the voltage V5. The gate bias voltage Vg of the transistor 12 is shortened from time t1 to time t2 by the gate being short-circuited to V3. It shows that it falls. The voltage V1 is a normal gate bias voltage.

FIG. 3C shows the change of the drain current Ad of the transistor 12 of the power amplifier 1. The drain current Ad is the standby current before the power is turned on and from the time t1 to t2 after the power is turned on. It is smaller than A1 and shows that it becomes standby current A1 after time t2. As shown in the figure, the inrush current from time t1 to t2 is also suppressed.

  As described above, according to the second embodiment of the present invention, since the drain bias is always applied and the gate bias is controlled by the burst control, the first embodiment is performed even in the transistor that does not recommend the drain bias burst operation. The same effect as the form can be obtained.

It is a figure which shows the operation principle of an example of the wideband power amplifier which concerns on this invention. 1 is a circuit diagram of a first embodiment of a wideband power amplifier according to the present invention. It is a timing chart which shows the specific example of operation | movement of 1st Embodiment. FIG. 3 is a circuit diagram of a second embodiment of a wideband power amplifier according to the present invention. It is a timing chart which shows the specific example of operation | movement of 2nd Embodiment. 1 is a circuit diagram of an example of a broadband power amplifier related to the present invention.

Explanation of symbols

1 Power amplifier
2 Negative feedback circuit
3 Burst control circuit
4 Bias control circuit
5 Gate bias circuit 6,44 Inductor
7 Power supply
8 Input terminal
9 Output terminal 10
DESCRIPTION OF SYMBOLS 11, 13 Capacitor 22, 43 Capacitor 12, 31 Transistor 42 Transistor 21, 52 Resistance 32 Burst control part 41 Surge voltage short-circuit part 48 Timer circuit 51 Gate bias part

Claims (18)

A broadband power amplifier for VHF and UHF ;
A negative feedback circuit provided between the input and output of the broadband power amplifier;
A burst control circuit for applying a burst voltage as a bias voltage to the input side or output side of the broadband power amplifier;
And a bias control circuit for reducing a surge voltage which the burst voltage is generated at the input side of the wideband power amplifier when it is applied to the wideband power amplifier,
The wideband power amplifying apparatus according to claim 1, wherein the bias control circuit includes a surge voltage short-circuit unit that short-circuits the surge voltage using a transistor .   2. The broadband power amplifier according to claim 1, wherein the bias control circuit includes a short-circuit time setting unit that sets a time for short-circuiting the surge voltage. The broadband power amplifier is bursty voltage to an output side of the applied, the broadband power constant voltage to the input side of the amplifier, characterized in that it is applied claim 1 or 2 broadband power amplifier described by the burst control circuit apparatus. The burst-like voltage to the input side of the wideband power amplifier is applied, the broadband power constant voltage to the output side of the amplifier, characterized in that it is applied claim 1 or 2 broadband power amplifier described by the burst control circuit apparatus.   4. The broadband power amplifying apparatus according to claim 1, wherein the surge voltage short-circuit portion included in the bias control circuit is a switching transistor.   The broadband power amplifier according to claim 1, wherein the surge voltage short-circuit portion included in the bias control circuit is a switching transistor.   6. The broadband power amplifying apparatus according to claim 2, wherein the short-circuit time setting unit included in the bias control circuit is a capacitive element connected to an input side of the switching transistor.   7. The broadband power amplifier according to claim 2, wherein the short-circuit time setting unit included in the bias control circuit is a timer circuit connected to an input side of the switching transistor. 9. The broadband power according to claim 1, wherein the bias control circuit includes an inductor that prevents the broadband power amplifier from becoming no load at a high frequency when the surge voltage is short-circuited. 10. Amplification equipment. A broadband power amplifier for VHF and UHF ;
A negative feedback circuit provided between the input and output of the broadband power amplifier;
A burst control circuit for applying a burst voltage as a bias voltage to the input side or output side of the broadband power amplifier;
A said bias control circuit in a broadband power amplifier comprising a bias control circuit for reducing a surge voltage generated at the input side of the wideband power amplifier when the burst voltage is applied to the wideband power amplifier,
A bias control circuit comprising a surge voltage short-circuit portion that short-circuits the surge voltage using a transistor .   The bias control circuit according to claim 10, further comprising a short-circuit time setting unit that sets a time for short-circuiting the surge voltage. 12. The bias control circuit according to claim 10, wherein a burst voltage is applied to the output side of the broadband power amplifier by the burst control circuit, and a constant voltage is applied to the input side of the broadband power amplifier. . 12. The bias control circuit according to claim 10, wherein a burst voltage is applied to the input side of the broadband power amplifier by the burst control circuit, and a constant voltage is applied to the output side of the broadband power amplifier. .   The bias control circuit according to claim 10, wherein the surge voltage short-circuit portion is a switching transistor.   The bias control circuit according to claim 10, wherein the surge voltage short-circuit portion is a switching transistor.   The bias control circuit according to claim 11, wherein the short-circuit time setting unit included in the bias control circuit is a capacitive element connected to an input side of the switching transistor.   16. The bias control circuit according to claim 11, wherein the short-circuit time setting unit included in the bias control circuit is a timer circuit connected to an input side of the switching transistor. 18. The bias control according to claim 10, wherein the bias control circuit includes an inductor that prevents the broadband power amplifier from becoming no-load at a high frequency when the surge voltage is short-circuited. 18. circuit.

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