JP5104057B2 - Manufacturing method of semiconductor device - Google Patents

Description

This invention relates to a manufacturing method of a semiconductor equipment.

Conventionally, as a semiconductor device constituted by a plurality of organic field effect transistors (hereinafter referred to as organic FETs), for example, a device constituted by a switching organic FET and a driving FET and incorporated in an active matrix organic EL display or the like is known. It has been. Also, a device provided with a CMOS inverter circuit or the like is known. As such a semiconductor device, an apparatus in which an n-type semiconductor and a p-type semiconductor are deposited by ink jet printing to manufacture a complementary logic circuit is disclosed (for example, see Patent Document 1).
JP-T-2005-531134

However, in the above conventional semiconductor device, since organic FETs having different characteristics are used in combination, there is a problem that symmetry in output characteristics of the semiconductor device is lost.
For example, a CMOS inverter circuit is composed of two types of FETs, a p-type FET and an n-type FET. The p-type organic FET operates in a region where the gate voltage and the drain voltage are negative with respect to the source voltage. On the other hand, in the n-type organic FET, the gate voltage and the drain voltage operate in a positive region with respect to the source voltage. It is desirable that the characteristics of the p-type organic FET and the output characteristics of the n-type organic FET match as much as possible by comparing the absolute values of the voltages. In particular, drain current symmetry is required.

However, the field effect mobility of the organic semiconductor film of the p-type organic FET is greatly different from that of the n-type organic FET. For this reason, the characteristics of the p-type organic FET and the output characteristics of the n-type organic FET are greatly different from each other in absolute value of voltage. This degrades the symmetry of the output characteristics of the CMOS inverter circuit. When the symmetry of the output characteristics of the CMOS inverter circuit deteriorates, there is a problem that one of the ON region and the OFF region of the input voltage signal becomes narrow.
The drain current is proportional to the channel width. Therefore, conventionally, the characteristics of each organic FET have been adjusted by the channel width of the organic FET. However, this method requires a wide channel width to obtain a large drain current, and miniaturization and integration become difficult.

Even if the channel length is changed, the characteristics of the organic FET change. However, the shorter the channel length, the better the characteristics, and it is designed to be the shortest channel length that can be manufactured in the process at the circuit design stage. Therefore, if the channel length is increased to adjust the characteristics, the characteristics of the organic FET are deteriorated.
Also, the characteristics of the organic FET can be adjusted by changing the organic semiconductor material and the source and drain electrode materials. However, using several different materials complicates the process and is not rational.

  Therefore, the present invention has been made to solve at least a part of the above-described problems, and can be realized as the following forms or application examples.

In order to solve the above problems, one of the methods for manufacturing a semiconductor device according to the present invention includes a first gate electrode, a first gate insulating film, a first semiconductor film, a first source electrode, and a first drain electrode. A semiconductor device comprising: a first transistor including: a second gate electrode; a second gate insulating film; a second semiconductor film; a second transistor including a second source electrode and a second drain electrode; Forming the first gate electrode and the second gate electrode on the surface, oxidizing the surface of the second gate electrode by an anodic oxidation method to form a second gate insulating film; and Oxidizing a surface of one gate electrode to form a first gate insulating film having a thickness larger than that of the second gate insulating film; and forming a p-type organic semiconductor material on the first gate insulating film. Including first semiconductor film Forming a second semiconductor film including an n-type organic semiconductor material on the second gate insulating film, and forming the first source electrode on the first semiconductor film and the second semiconductor film on the second semiconductor film. A second source electrode is formed, and a first drain electrode is formed on the first semiconductor film so that the first drain electrode and the second drain electrode are electrically connected to each other. a second drain electrode on the steps of forming each of the the first gate electrode and said second gate electrode possess a step of electrically connecting the said first and second gate insulating film formed The first and second gate electrodes are immersed in an electrolyte solution, except for a portion for electrically connecting the first and second gate electrodes, and the first and second gate electrodes are In the electrolyte solution In the step of forming the first and second gate insulating films by oxidation by a polar oxidation method and electrically connecting the first and second gate electrodes, the first and second gate electrodes are formed on the surfaces of the first and second gate electrodes. A wiring for electrically connecting the first and second gate electrodes is formed in a portion where the first and second gate insulating films are not formed .
Another embodiment of the method of manufacturing a semiconductor device according to the present invention includes a first transistor including a first gate electrode, a first gate insulating film, a first semiconductor film, a first source electrode, and a first drain electrode. And a second transistor including a second gate electrode, a second gate insulating film, a second semiconductor film, a second source electrode, and a second drain electrode, wherein the first transistor is formed on a substrate. Forming a gate electrode and the second gate electrode; and oxidizing the surface of the second gate electrode by an anodic oxidation method to form a second gate insulating film; and the surface of the first gate electrode Forming a first gate insulating film having a thickness larger than that of the second gate insulating film, and a first semiconductor film containing a p-type organic semiconductor material on the first gate insulating film And forming Forming a second semiconductor film containing an n-type organic semiconductor material on the second gate insulating film, the first source electrode on the first semiconductor film, and the second source electrode on the second semiconductor film. And forming a first drain electrode on the first semiconductor film and a second drain on the second semiconductor film so that the first drain electrode and the second drain electrode are electrically connected to each other. A step of forming a drain electrode, and a step of electrically connecting the first gate electrode and the second gate electrode, and forming the first and second gate insulating films, Masks are respectively formed on portions of the surfaces of the first and second gate electrodes for electrically connecting the first and second gate electrodes, and the first and second gate electrodes are immersed in the electrolytic solution. And the electrolyte The first and second gate insulating films are formed by oxidizing the non-formation portions of the mask on the surfaces of the first and second gate electrodes in the electrolytic solution by the anodic oxidation method. In the step of electrically connecting the gate electrodes, the mask is removed to expose the surfaces of the first and second gate electrodes, and the first and second gate electrodes are exposed on the surfaces of the first and second gate electrodes. It is characterized in that a wiring for electrically connecting each other is formed.

By manufacturing in this way, gate insulating films having different thicknesses can be formed in the first transistor and the second transistor by controlling the anodizing voltage, the anodizing time, and the like. Then, a CMOS inverter circuit is formed in which the thickness of the gate insulating film of the first transistor including the p-type semiconductor film is larger than the thickness of the gate insulating film of the second transistor including the n-type semiconductor film. Can do.
Moreover, by manufacturing in this way, the part for electrically connecting the gate electrodes of the first transistor and the second transistor is not oxidized and becomes a non-formation part of the gate insulating film. Therefore, when the gate electrodes are electrically connected to each other, the portions where the gate insulating film is not formed can be connected. Therefore, it is not necessary to remove the gate insulating film, the manufacturing process can be simplified, and productivity can be improved.

In another aspect of the method for manufacturing a semiconductor device according to the present invention, in the step of forming the first and second gate insulating films, the first gate electrode has an anode larger than the second gate electrode. An oxidation voltage is applied.
By manufacturing in this way, the film thickness of the first gate insulating film of the first transistor can be made larger than the film thickness of the second gate insulating film of the second transistor.

In another embodiment of the method for manufacturing a semiconductor device according to the present invention, in the step of forming the first and second gate insulating films, the first gate electrode has a longer time than the second gate electrode. An anodizing voltage is applied.
By manufacturing in this way, the film thickness of the first gate insulating film of the first transistor can be made larger than the film thickness of the second gate insulating film of the second transistor.

In another aspect of the method for manufacturing a semiconductor device according to the present invention, in the step of electrically connecting the first and second gate electrodes, a part of the first and second gate insulating films is etched. And a wiring for electrically connecting the first and second gate electrodes to each other is formed on the surfaces of the first and second gate electrodes exposed by the etching.
By manufacturing in this way, the first and second gate insulating films formed on the surfaces of the first and second gate electrodes can be removed, and the first and second gate electrodes can be exposed. Then, by forming a wiring in a portion where the first and second gate electrodes are exposed, the gate electrodes of the first transistor and the second transistor can be electrically connected.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scale is appropriately changed for each layer and each member so that each layer and each member can be recognized on the drawing.

(Semiconductor device)
As shown in FIGS. 1 and 2, a semiconductor device 100 includes a CMOS inverter circuit 30 including a first transistor (hereinafter referred to as a p-type organic FET 10) and a second transistor (hereinafter referred to as an n-type organic FET 20) on a substrate 1. It has. The substrate 1 is made of an electrically insulating material such as glass, for example. Each of the p-type organic FET 10 and the n-type organic FET 20 includes a p-type gate electrode 11 and an n-type gate electrode 21 formed on the substrate 1. Each of the gate electrodes 11 and 21 is made of, for example, tantalum.

A p-type gate insulating film 12 and an n-type gate insulating film 22 are formed on the gate electrodes 11 and 21 so as to cover the gate electrodes 11 and 21 except for the connecting portions 11a and 21a shown in FIG. Has been.
As shown in FIG. 2, the thickness T1 of the p-type gate insulating film 12 is formed to be larger than the thickness T2 of the n-type gate insulating film 22. Each of the gate insulating films 12 and 22 is made of, for example, tantalum oxide. Here, the film thickness T1 of the p-type gate insulating film 12 is, for example, about 400 nm, and the film thickness T2 of the n-type gate insulating film 22 is, for example, about 133 nm.
The connecting portions 11 a and 21 a are electrically connected by a wiring 31 formed across the p-type gate electrode 11 and the n-type gate electrode 21, and constitute the input electrode 101 of the semiconductor device 100. The wiring 31 is formed by sequentially laminating aluminum and gold.

  A p-type semiconductor film 13 and an n-type semiconductor film 23 are formed on each gate insulating film 12 and 22 so as to cover a part of each gate insulating film 12 and 22. Each of the semiconductor films 13 and 23 is formed of (thiophene / phenylene) co-oligomer, and the p-type semiconductor film 13 is formed including BP3T which is a p-type organic semiconductor material represented by the following formula (1). . The n-type semiconductor film 23 is formed including AC5F6pm which is an n-type organic semiconductor material represented by the following formula (2).

A p-type source electrode 14, a p-type drain electrode 15, an n-type source electrode 24, and an n-type drain electrode 25 are formed on the p-type semiconductor film 13 and the n-type semiconductor film 23, respectively. The p-type drain electrode 15 and the n-type drain electrode 25 are stacked so as to partially overlap each other and are electrically connected to each other, and constitute the output electrode 102 of the semiconductor device 100.
Here, the p-type source electrode 14 and the p-type drain electrode 15 are made of, for example, gold. The n-type source electrode 24 and the n-type drain electrode 25 are made of, for example, aluminum.

  As shown in FIG. 1, the channel width W1 of the p-type organic FET 10 is formed to be smaller than the channel width W2 of the n-type organic FET 20. The channel width W1 of the p-type organic FET 10 is, for example, about 1 mm, and the channel width W2 of the n-type organic FET 20 is about 3 mm. Further, the channel lengths L1 and L2 of the p-type organic FET 10 and the n-type organic FET 20 are formed to be substantially equal to each other, for example, about 20 μm.

Next, the operation of this embodiment will be described.
As shown in FIGS. 1 and 2, in the CMOS inverter circuit 30 including the p-type organic FET 10 and the n-type organic FET 20, the n-type source electrode 24 is grounded, and the p-type source electrode 14 has a positive power supply voltage V. _{Apply DD} . The power supply voltage _{V DD} of about 10V, the input voltage _{V in} about 0~10V applied to the input electrode 101, by measuring the output voltage _{V out} from the output electrode 102, to obtain an output characteristic shown in FIG. 3 .

The input electrode 101, as shown in FIG. 3, when a voltage of about 0 (V) ~10 (V) as the input voltage _{V in,} the output electrode 102 and the inverting input voltage _{V in,} about 10 ( An output voltage _{Vout of} V) to 0 (V) is output. Further, defined as the input voltage _{V in} the output voltage _{V out} of the inverted voltage _{V R} becomes a half of the supply voltage _{V DD} (5V).
Here, the field-effect mobility of AC5F6pm used for the n-type semiconductor film 23 is about 10 ⁻³ cm ² / Vs, which is approximately from the field-effect mobility of BP3T used for the p-type semiconductor film. It is smaller on the order of one digit.

Therefore, in the semiconductor device 100 of the present embodiment, the film thickness T1 of the p-type gate insulating film 12 is formed to be larger than the film thickness T2 of the n-type gate insulating film 22 in order to prevent deterioration of output characteristics. Yes. As a result, the gate capacitance of the p-type organic FET 10 is reduced, and the field-effect mobility of the p-type organic FET 10 is reduced.
The p-type gate insulating film 12 and the n-type gate insulating film 22 are each formed of tantalum oxide, and the film thicknesses T1 and T2 are formed to be about 400 nm and about 133 nm, respectively.

Thus, by setting the film thickness T2 of the n-type gate insulating film 22 to about 1/3 of the film thickness of the p-type gate insulating film, the field effect of the n-type organic FET 20 is relatively increased, and p The field effect mobility of the n-type organic FET 10 can be made substantially equal to the field effect mobility of the n-type organic FET 20. Thus, as shown in FIG. 3, it may be approximately 5.1V is substantially intermediate value of the minimum values 0V and a maximum value of 10V input voltage _{V in} the inversion voltage _{V R.}
Therefore, according to this embodiment, a substantially intermediate value between the minimum and maximum values of the input voltage V _in the inversion voltage V _R of the CMOS inverter circuit 30, that the symmetry of the output characteristic to obtain a good semiconductor device 100 it can. Thereby, the ON / OFF margin can be expanded and the degree of freedom in designing the semiconductor device 100 can be improved.

Further, since there is no need to adjust the channel widths W1 and W2 and the channel lengths L1 and L2, the semiconductor device 100 can be reduced in size, and the semiconductor device 100 can be miniaturized and integrated. Further, since a part of the p-type drain electrode 15 and a part of the n-type drain electrode 25 are laminated, the area of the output electrode 102 is reduced as compared with the case where they are formed side by side on the substrate 1. Therefore, miniaturization and high integration of the semiconductor device 100 can be realized.
Further, since the channel width W1 of the p-type organic FET 10 is smaller than the channel width W2 of the n-type organic FET 20, the field effect of the p-type organic FET 10 can be reduced and the balance of the output characteristics of the CMOS inverter circuit 30 can be improved. .

  Further, since the gate electrodes 11 and 21 are made of tantalum and the gate insulating films 12 and 22 are made of tantalum oxide, the surfaces of the gate electrodes 11 and 21 are oxidized to form the gate insulating films 12 and 22. Can be formed. Therefore, the gate insulating films 12 and 22 can be easily formed, there are few defects, and the manufacturing equipment can be simplified. Further, since the gate insulating films 12 and 22 are made of tantalum oxide, the gate insulating films 12 and 22 are dense and have high quality.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, a tantalum film is formed on the surface of the substrate 1 by, for example, sputtering. Next, the formed tantalum film is patterned by, for example, a photolithography method, a dry etching method, or the like to form a p-type gate electrode 11 and an n-type gate electrode 21 as shown in FIG. As a result, the p-type gate electrode 11 and the n-type gate electrode 21 are electrically independent.

  Next, as shown in FIG. 4B, the surface of the n-type gate electrode 21 is oxidized to form the n-type gate insulating film 22, and the surface of the p-type gate electrode 11 is oxidized. A p-type gate insulating film 12 having a thickness T1 larger than the film thickness T2 of the n-type gate insulating film 22 is formed. The p-type gate insulating film 12 and the n-type gate insulating film 22 are formed by an anodic oxidation method.

  When forming the p-type gate insulating film 12 and the n-type gate insulating film 22 by the anodic oxidation method, first, as shown in FIG. 5, the anodic oxidation electrolytic solution 52 filled in the anodic oxidation bath 51 is formed. Then, the substrate 1 on which the p-type gate electrode 11 and the n-type gate electrode 21 are formed is immersed. At this time, the connecting portions 11a and 21a are from the liquid surface 52s of the anodizing electrolyte 52 so that the connecting portions 11a and 21a of the p-type gate electrode 11 and the n-type gate electrode 22 do not contact the anodizing electrolyte 52. Also, the substrate 1 is fixed so as to be positioned on the upper side.

Next, the n-type gate electrode 21 is connected to the anode 53 p of the anodizing power source 53. Next, the p-type gate electrode 11 and the cathode electrode 54 are connected to the cathode 53 n of the anodizing power source 53. The cathode electrode 54 is immersed in the anodic oxidation electrolyte 52 together with the substrate 1. Then, an anodizing voltage V of about 70 V is applied by the anodizing power source 53. The film thickness of the tantalum oxide film by the anodic oxidation method is proportional to the anodic oxidation voltage V, and the proportionality factor is about 1.9 nm / V.
Therefore, by applying an anodic oxidation voltage V of about 70 V, an n-type gate insulating film 22 having a thickness T2 of about 133 nm is formed on the surface of the n-type gate electrode 21. At this time, the surface of the p-type gate electrode 11 connected to the cathode 53n of the anodic oxidation power supply 53 and the connection portion 21a exposed on the liquid surface 52s of the anodic oxidation electrolyte 52 are not oxidized.

Next, the p-type gate electrode 11 and the n-type gate electrode 21 are removed from the cathode 53 n of the anodizing power source 53 and the anode 53 p of the anodizing power source 53. Then, the wiring is switched, and the p-type gate electrode 11 is connected to the anode 53p of the anodizing power supply 53, and the n-type gate electrode 21 is connected to the cathode 53n of the anodizing power supply 53. Next, an anodizing voltage V of about 210 V is applied by the anodizing power source 53.
As a result, a p-type gate insulating film 12 of about 400 nm is formed on the surface of the p-type gate electrode 11 excluding the connection portion 11a.

  Thus, by forming the p-type gate insulating film 12 and the n-type gate insulating film 22 by the anodic oxidation method, the anodic oxidation voltage V is controlled, and the film thicknesses T1 and n of the p-type gate insulating film 11 are controlled. The film thickness T2 of the mold gate insulating film 21 can be independently and freely controlled. Then, by making the anodic oxidation voltage V for the p-type gate electrode 11 larger than the anodic oxidation voltage V for the n-type gate electrode 21, as shown in FIG. 4B, the p-type gate insulating film 12. The film thickness T1 can be made larger than the film thickness T2 of the n-type gate insulating film 22.

Next, as shown in FIG. 4C, the p-type semiconductor film 13 is formed on the p-type gate insulating film 12 by, for example, vapor deposition, and the n-type is formed on the n-type gate insulating film 22. A semiconductor film 23 is formed.
Next, as shown in FIG. 4D, the n-type source electrode 24 and the n-type drain electrode 25 are formed on the n-type semiconductor film 23 by, for example, mask vapor deposition or the like. At the same time, as shown in FIG. 1, the lower layer side of the wiring 31 is formed so as to straddle the connection portion 11a of the p-type gate electrode 11 and the connection portion 21a of the n-type gate electrode 21.

At this time, since no insulating film is formed on the connection portions 11a and 21a, the connection portion 11a of the p-type gate electrode 11 and the connection portion 21a of the n-type gate electrode 21 are electrically connected by the wiring 31. .
That is, as described above, the connection portions 11a and 21a are not immersed in the anodic oxidation electrolytic solution 52 during anodic oxidation, so that the conductivity of the surfaces of the connection portions 11a and 21a is maintained, and the p-type gate electrode 11 and The n-type gate electrode 21 can be electrically connected. Therefore, a manufacturing process can be simplified and productivity can be improved.

  Next, as shown in FIGS. 1 and 2, the p-type source electrode 14 and the p-type drain electrode 15 are formed on the p-type semiconductor film 11 by, for example, a mask vapor deposition method or the like. At the same time, the upper layer side of the wiring 31 is formed so as to straddle the connection portion 11 a of the p-type gate electrode 11 and the connection portion 21 a of the n-type gate electrode 21. Further, the p-type drain electrode 15 is formed so as to partially overlap the n-type drain electrode 25. Thereby, the p-type drain electrode 15 and the n-type drain electrode 25 are electrically connected. As described above, the semiconductor device 100 shown in FIGS. 1 and 2 is manufactured.

(Comparative example)
Next, a comparative example for the semiconductor device 100 of the above-described embodiment will be described with reference to FIGS. 6 and 7 with reference to FIG. In this comparative example, the semiconductor device 100 described in the above embodiment and the p-type gate insulating film 12 ′ and the n-type gate insulating film 22 ′ are formed to have equal thicknesses T1 ′ and T2 ′. Is different in that it is. Since the other points are the same as those of the above-described embodiment, the same parts are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 6, the film thicknesses T1 ′ and T2 ′ of the p-type gate insulating film 12 ′ and the n-type gate insulating film 22 ′ are about 266 nm, which are substantially equal to the film thicknesses T1 ′ and T2 ′. ing. The film thicknesses T1 ′ and T2 ′ are substantially intermediate values of the film thicknesses T1 and T2 of the p-type gate insulating film 12 and the n-type gate insulating film 22 in the above-described embodiment.
Similarly to the above-described embodiment, the n-type source electrode 24 is grounded, and the positive power supply voltage V _DD is applied to the p-type source electrode 14. The power supply voltage _{V DD} of about 10V, the input voltage _{V in} about 0~10V applied to the input electrode 101, by measuring the output voltage _{V out} from the output electrode 102, to obtain an output characteristic shown in FIG. 7 .

As described above, the field effect mobility of the n-type semiconductor film 23 is smaller than that of the p-type semiconductor film 13 on the order of about one digit. Therefore, when the film thicknesses T1 ′ and T2 ′ of the p-type semiconductor film 13 and the n-type semiconductor film 23 are equal, the ON current of the n-type organic FET 10 ′ is smaller than the ON current of the p-type organic FET 20 ′.
In order to make both the ON currents equal, the absolute value of the gate voltage of the n-type organic FET 10 ′ must be larger than the absolute value of the gate voltage of the p-type organic FET 20 ′.
Therefore, as shown in FIG. 7, the inverted voltage V _R is compared from the intermediate value between the minimum and maximum values of the input voltage V _in, next to 7.2V largely deviated to the maximum value side, and the above-described embodiment As a result, the symmetry of the output characteristics deteriorates.

  The channel width W2 of the n-type organic FET 20 'is about three times the channel width W1 of the p-type organic FET 10' as in the above embodiment. However, this alone cannot sufficiently improve the output characteristics. In order to obtain output characteristics having sufficient symmetry only by adjusting the channel widths W1 and W2, it is necessary to further increase the channel width W2 of the n-type organic FET 20 'by several times. However, in this method, the area of the CMOS inverter circuit 30 'is enlarged, and it is difficult to miniaturize and integrate the semiconductor device 100' as compared with the above-described embodiment.

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the semiconductor device manufacturing method described in the above embodiment, the thickness of the gate insulating film is controlled by the magnitude of the applied anodizing voltage. The film thickness may be controlled by controlling. In this case, the application time of the anodic oxidation voltage of the p-type gate electrode is made longer than the application time of the anodic oxidation voltage of the n-type gate electrode, whereby the film thickness of the p-type gate insulating film is made to be n-type gate insulation. It can be larger than the film thickness.

Further, in the above-described embodiment, in order not to form an insulating film in the connection portion, the connection portion is not immersed in the anodic oxidation electrolyte. Each gate insulating film may be formed by dipping in an electrolytic solution and oxidizing a non-forming portion of the mask on the surface of each gate electrode in an anodic electrolytic solution. As a result, the gate insulating film is not formed in the mask forming portion, and the gate insulating film is formed only in the non-mask forming portion.
Therefore, according to this method, in the step of electrically connecting the gate electrodes, the case where a plurality of p-type organic FETs and n-type organic FETs are formed on the substrate has been described in the above embodiment. Compared with the method, the oxidation of each connection portion can be more reliably prevented.

  In addition, as in the above-described embodiment, the formation of an oxide film on the connection portion is not prevented, and each gate electrode is completely immersed in an anodic oxidation electrolyte, and a gate insulating film is formed on the entire surface of each gate electrode. Also good. In this case, in the step of electrically connecting the gate electrodes, a part of each gate insulating film corresponding to the connecting portion is removed by etching, and the gate electrodes are electrically connected to the surface of each gate electrode exposed by the etching. A wiring to be connected to is formed. Thereby, similarly to the above-described embodiment, the gate electrodes can be electrically connected to each other.

  The gate electrode may be formed of a metal material having conductivity other than tantalum. The material of the semiconductor film is not limited to the material described in the above embodiment as long as it is a light-emitting organic semiconductor material. As the p-type organic semiconductor material, in addition to the above-described BP3T, for example, AC5 represented by the following formula (3), pentacene, or the like can be used.

  As the n organic semiconductor material, for example, (thiophene / phenylene) co-oligomer-based AC5CF3 represented by the following formula (4), PTCDI represented by the formula (5), or the like can be used.

  Further, as the n-type semiconductor film, a p-type semiconductor material AC5 or AC5F6pm subjected to fluorine substitution treatment may be used. Further, as other materials, C60 fullerene or the like may be used.

  In the above-described embodiment, the film thickness ratio of the n-type gate insulating film and the p-type gate insulating film is 1: 3. However, the film thickness ratio is not limited to this value. What is necessary is just to set according to material characteristics, such as a field effect mobility of a type organic semiconductor, and the dimension of each part of n-type FET and p-type FET.

  In addition, the present invention is not limited to the CMOS inverter circuit described in the above-described embodiment. For example, characteristics different for each group of organic FETs such as a circuit composed of a switching organic FET and a driving organic FET in an organic FET active matrix display. Can be applied to required circuits. In addition, the present invention can be applied to circuits that require the characteristics of individual organic FETs to match the same characteristics or desired characteristics.

1 is a plan view of a semiconductor device according to an embodiment of the present invention. It is sectional drawing which follows the A-A 'line of FIG. It is a figure which shows the output characteristic of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is explanatory drawing of the manufacturing process of a semiconductor device similarly. It is explanatory drawing of the anodic oxidation method in embodiment of this invention. It is sectional drawing corresponding to FIG. 2 of the semiconductor device in a comparative example. It is a figure which shows the output characteristic of the semiconductor device in a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, 10 p-type organic FET (first transistor), 11 p-type gate electrode (first gate electrode), 11a connection part (non-formation part of gate insulating film), 12 p-type gate insulating film (first Gate insulating film), 13 p-type semiconductor film (first semiconductor film), 14 p-type source electrode (first source electrode), 15 p-type drain electrode (first drain electrode), 20 n-type organic FET (first 2 transistors), 21 n-type gate electrode (second gate electrode), 21a connection part (non-formation part of gate insulating film), 22 n-type gate insulating film (second gate insulating film), 23 n-type semiconductor film (Second semiconductor film), 24 n-type source electrode (second source electrode), 25 n-type drain electrode (second drain electrode), 100 semiconductor device, T1 film thickness, T2 film thickness, W1 channel width, W2 Channel width , V Anodizing voltage

Claims (5)

A first transistor including a first gate electrode, a first gate insulating film, a first semiconductor film, a first source electrode and a first drain electrode; a second gate electrode; a second gate insulating film; a second semiconductor film; A second transistor including a source electrode and a second drain electrode, and a manufacturing method of a semiconductor device comprising:
Forming the first gate electrode and the second gate electrode on a substrate;
The surface of the second gate electrode is oxidized by anodic oxidation to form a second gate insulating film, and the surface of the first gate electrode is oxidized to form a film that is thicker than the film thickness of the second gate insulating film. Forming a thick first gate insulating film;
Forming a first semiconductor film including a p-type organic semiconductor material on the first gate insulating film and forming a second semiconductor film including an n-type organic semiconductor material on the second gate insulating film;
The first source electrode is formed on the first semiconductor film, the second source electrode is formed on the second semiconductor film, and the first drain electrode and the second drain electrode are electrically connected. Forming a first drain electrode on the first semiconductor film and a second drain electrode on the second semiconductor film, and
Electrically connecting the first gate electrode and the second gate electrode;
I have a,
In the step of forming the first and second gate insulating films, the first and second gate electrodes are immersed in an electrolytic solution except for a portion for electrically connecting the first and second gate electrodes. And oxidizing the first and second gate electrodes in the electrolytic solution by the anodic oxidation method to form the first and second gate insulating films,
In the step of electrically connecting the first and second gate electrodes, the first and second gate electrodes are not formed on the first and second gate insulating film non-forming portions on the surfaces of the first and second gate electrodes. A method of manufacturing a semiconductor device, comprising forming a wiring for electrically connecting each other . A first transistor including a first gate electrode, a first gate insulating film, a first semiconductor film, a first source electrode and a first drain electrode; a second gate electrode; a second gate insulating film; a second semiconductor film; A second transistor including a source electrode and a second drain electrode, and a manufacturing method of a semiconductor device comprising:
Forming the first gate electrode and the second gate electrode on a substrate;
The surface of the second gate electrode is oxidized by anodic oxidation to form a second gate insulating film, and the surface of the first gate electrode is oxidized to form a film that is thicker than the film thickness of the second gate insulating film. Forming a thick first gate insulating film;
Forming a first semiconductor film including a p-type organic semiconductor material on the first gate insulating film and forming a second semiconductor film including an n-type organic semiconductor material on the second gate insulating film;
The first source electrode is formed on the first semiconductor film, the second source electrode is formed on the second semiconductor film, and the first drain electrode and the second drain electrode are electrically connected. Forming a first drain electrode on the first semiconductor film and a second drain electrode on the second semiconductor film, and
Electrically connecting the first gate electrode and the second gate electrode;
I have a,
In the step of forming the first and second gate insulating films, masks are respectively formed on portions of the surfaces of the first and second gate electrodes for electrically connecting the first and second gate electrodes to each other. The first and second gate electrodes are immersed in the electrolytic solution, and the non-forming portion of the mask on the surface of the first and second gate electrodes is oxidized in the electrolytic solution by the anodic oxidation method in the electrolytic solution. Forming the first and second gate insulating films,
In the step of electrically connecting the first and second gate electrodes, the mask is removed to expose the surfaces of the first and second gate electrodes, and the first and second gate electrodes are exposed on the surfaces of the first and second gate electrodes. A method of manufacturing a semiconductor device, comprising forming a wiring for electrically connecting the first and second gate electrodes . 3. The semiconductor device according to claim 1, wherein in the step of forming the first and second gate insulating films, an anodic oxidation voltage larger than that of the second gate electrode is applied to the first gate electrode. Manufacturing method. In the step of forming the first and second gate insulating film, the first gate electrode, longer than the second gate electrode, according to claim 1, wherein applying the anodization voltage A method for manufacturing a semiconductor device. In the step of electrically connecting the first and second gate electrodes, a part of the first and second gate insulating films is removed by etching, and the surfaces of the first and second gate electrodes exposed by the etching the method of manufacturing a semiconductor device according to any one of claims 1 to 4 and forming a wiring for electrically connecting the first and second gate electrodes are to.

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