JP5091017B2 - Thin film transistor manufacturing method - Google Patents

Description

The present invention relates to a thin film transistor, a method of manufacturing the same, and an organic light emitting display device including the same. Between values Ioff / W (A / mm), Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant, c is 2.5 × 10 ^-13 to 6.8 × 10 ⁻¹³ )), a manufacturing method thereof, and an organic light emitting display device including the same.

  Thin film transistors are mainly used for active elements of active matrix liquid crystal display devices (AMLCD) and switching elements and driving elements of organic electroluminescent elements (OLEDs), but it is necessary to control the characteristics of the thin film transistors according to the characteristics of each element. . One of the important factors in determining the characteristics of the thin film transistor is the leakage current value.

  Generally, in a thin film transistor that uses a polycrystalline silicon layer crystallized by a crystallization method that does not use metal as a semiconductor layer, the leakage current value increases as the channel region width increases, and the channel region length increases. If it becomes, it has the tendency to become small. However, even if the length of the channel region is increased in order to reduce the leakage current value, the effect is insignificant. In the display device, if the length of the channel region is increased, the size of the device is increased, and the aperture ratio is increased. Therefore, the length of the channel region is restricted.

  On the other hand, the current method of crystallizing an amorphous silicon layer using a metal has the advantage that it can be crystallized in a rapid time at a lower temperature than the solid phase crystallization method or the excimer laser crystallization method. Many studies have been made. However, in a thin film transistor that uses a polycrystalline silicon layer crystallized using the metal as a semiconductor layer, the leakage current value of the thin film transistor due to a change in the length or width of the channel region changes without a certain tendency, It does not have the tendency of general thin film transistors.

Therefore, there is a problem that a leakage current value due to the size of the channel region of the semiconductor layer cannot be predicted, particularly in a thin film transistor using a semiconductor layer crystallized using a crystallization-inducing metal, and the leakage current value to be controlled There is a problem that the size of the channel region of the semiconductor layer for obtaining the above cannot be determined.
JP 2003-100653 A

  The present invention is for solving the above-described problems of the prior art, and in a thin film transistor using a semiconductor layer crystallized using a crystallization-inducing metal, the crystallization present in the channel region of the semiconductor layer. The leakage current value can be reduced by removing the inductive metal, predicting the leakage current value due to the width and length of the channel region of the semiconductor layer, or considering the leakage current value to be controlled in reverse. An object of the present invention is to provide a thin film transistor capable of determining the width and length of the channel region of the semiconductor layer, a method for manufacturing the same, and an organic light emitting display.

To achieve the above object, the present invention provides a substrate; a semiconductor layer located on the substrate, including a channel region and source / drain regions, and crystallized using a crystallization-inducing metal; and the semiconductor layer A gate electrode positioned so as to correspond to a certain region of the gate electrode; a gate insulating film positioned between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode; and a source / drain region of the semiconductor layer The semiconductor layer includes source / drain electrodes that are electrically connected, and the crystallization-inducing metal and another metal or the metal are disposed in the semiconductor layer at a position spaced apart from the channel region from the surface of the semiconductor layer to a certain depth. the metal silicide is present, the semiconductor layer between the length of the channel region and the width and the leakage current Ioff / W (L) = 3.4 × 10 -15 L 2 +2. × ¹⁰ -12 L + c (Ioff is the leakage current value of the semiconductor layer (A), W is the width of the channel region (mm), L is the length of the channel region ([mu] m), and c are constants, c is 2. 5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ )) is provided.

According to the present invention, a method of manufacturing a thin film transistor includes providing a substrate; forming an amorphous silicon layer on the substrate; converting the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal. Crystallized; Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (Ioff is the leakage current value of the semiconductor layer (A), W is the width of the channel region (mm)) , L is the length (μm) of the channel region, and c is a constant, and c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ ). Determining the length and width of the channel region of the semiconductor layer according to the leakage current value; and patterning the polycrystalline silicon layer to form a semiconductor layer having the channel region having the length and width; Located a certain distance from Forming a metal layer pattern or a metal silicide layer pattern in contact with the semiconductor layer on a region other than the channel region; heat treating the substrate to convert the crystallization-inducing metal present in the channel region of the semiconductor layer into the metal layer; Gettering a region in the semiconductor layer corresponding to a region where the pattern or metal silicide layer pattern is formed; removing the metal layer pattern or metal silicide layer pattern; corresponding to a certain region of the semiconductor layer Forming a gate electrode on the semiconductor layer; forming a gate insulating film positioned between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode; electrically forming a source / drain region of the semiconductor layer; Forming coupled source / drain electrodes.

The present invention also relates to a substrate; a semiconductor layer located on the substrate and including a channel region and source / drain regions and crystallized using a crystallization-inducing metal; and corresponding to a certain region of the semiconductor layer A gate electrode located between the semiconductor layer and the gate insulating film located between the semiconductor layers to insulate the semiconductor layer from the gate electrode; a source electrically connected to a source / drain region of the semiconductor layer A first electrode electrically connected to the source / drain electrode; an organic film layer including a light emitting layer located on the first electrode; and a second electrode located on the organic film layer In the semiconductor layer, the crystallization-inducing metal and another metal or a metal silicide of the metal is provided at a position spaced apart from the channel region from the surface of the semiconductor layer to a certain depth. Mashimashi, length and width and the inter-leakage current Ioff / W (L) = 3.4 × 10 -15 L 2 + 2.4 × 10 -12 L + c (Ioff of the channel region of the semiconductor layer is a semiconductor layer Leakage current value (A), W is the width (mm) of the channel region, L is the length (μm) of the channel region, and c is a constant, and c is 2.5 × 10 ⁻¹³ to 6.8 × ^10-13 .) An organic light emitting display device characterized by satisfying the mathematical formula 1 is provided.

  As described above, according to the present invention, in a thin film transistor using a semiconductor layer crystallized using a crystallization-inducing metal, the leakage current value is reduced by removing the crystallization-inducing metal present in the channel region of the semiconductor layer. The leakage current value due to the width and length of the channel region of the semiconductor layer can be predicted, or conversely, the leakage current value can be predicted. A thin film transistor capable of determining the width and length, a manufacturing method thereof, and an organic light emitting display device can be provided.

  Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and can be embodied in other forms.

  FIG. 1 is a cross-sectional view illustrating a thin film transistor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining a semiconductor layer in the thin film transistor according to the first embodiment of the present invention.

  Referring to FIG. 1, first, a substrate 100 is prepared. The substrate 100 may be a glass substrate or a plastic substrate. A buffer layer 105 is located on the substrate 100. The buffer layer 105 can sufficiently crystallize the amorphous silicon layer by preventing diffusion of moisture or impurities generated in the substrate 100 or adjusting the heat transfer rate during crystallization. . The substrate 100 may be formed of a single layer or a plurality of layers using an insulating film such as a silicon oxide film or a silicon nitride film.

  A patterned semiconductor layer 135 is located on the buffer layer 105. The semiconductor layer 135 is a semiconductor layer crystallized by a crystallization method using a crystallization-inducing metal such as a MIC (Metal Induced Crystallization) method, a MILC (Metal Induced Lateral Crystallization) method, or an SGS (Super Grain Silicon) method. A channel region 136 and source / drain regions 137 and 138. The semiconductor layer 135 is preferably crystallized by the SGS method in which the concentration of the crystallization-inducing metal diffusing into the amorphous silicon layer can be controlled at a low concentration as compared with the MIC method or MILC method.

  Referring to FIG. 2, the channel region 136 of the semiconductor layer 135 has a length L and a width W. Here, the length L of the channel region 136 means a horizontal distance from a line connecting the source / drain regions 137 and 138 of the semiconductor layer 135, and the width W of the channel region 136 is the source / drain region 137, 138. Means the distance in the vertical direction from the line connecting

Between the length L (μm) of the channel region 136 of the semiconductor layer 135 and the leakage current value Ioff (A / mm) per width W1 mm of the channel region 136 of the semiconductor layer 135, Ioff / W (L) = 3.4 The mathematical formula 1 of × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant and c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ ) is satisfied. Therefore, since it is possible to predict the leakage current value depending on the size of the channel region 136 of the semiconductor layer 135, the leakage current value is controlled by controlling the width W and length L of the channel region 136 of the semiconductor layer 135. Can be controlled. On the other hand, since the leakage current value can be predicted, the length L and the width W of the channel region 136 of the semiconductor layer 135 can be controlled in consideration of the leakage current value to be controlled.

Here, referring to FIG. 9, when the width of the channel region of the semiconductor layer 135 is the same, the shorter the length L of the channel region, the more the metal different from the crystallization-inducing metal described later or the metal silicide of the metal is formed. It can be seen that the efficiency of removing the crystallization-inducing metal existing in the channel region by using the region that has been increased increases, and the leakage current value per 1 mm width W of the channel region decreases. Especially when the length of the channel region is larger than 0 and 15 μm or less, the gettering effect is remarkable, and Ioff / W has a value of 1.0 × 10 ⁻¹² A / mm or less, which is good when used for a display. It can have the characteristic.

In the semiconductor layer 135, a metal different from the crystallization-inducing metal or a metal silicide of the metal is formed from the surface of the semiconductor layer 135 to a certain depth in the semiconductor layer 135 at a position separated from the channel region 136. The region 145a that is being positioned is located. At this time, the metal or the metal silicide is a metal or metal silicide for gettering. In the present invention, by performing a gettering process using the region 145a where the metal or the metal silicide is formed, the crystallization-inducing metal present in the channel region 136 of the semiconductor layer 135 is removed, thereby causing a leakage current. Between the length L (μm) of the channel region 136 of the semiconductor layer 135 and the leakage current value Ioff / W (A / mm) per width W1 mm of the channel region 136 of the semiconductor layer 135. Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant, c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ )) To satisfy the mathematical formula 1.

  Here, the distance that the region 145a where the metal different from the crystallization-inducing metal or the silicide of the metal is formed is separated from the channel region 136 with respect to the change in the length L of the channel region 136. Has a numerical value. That is, only the length L of the channel region changes, and the distance that the region 145a is separated from the channel region 136 has a constant value with respect to the changing L.

  The metal or the metal silicide for gettering is preferably a metal having a diffusion coefficient smaller than the crystallization-inducing metal in the semiconductor layer 135 or a metal silicide of the metal. The diffusion coefficient of the metal or the metal silicide in the semiconductor layer 135 is preferably 1/100 or less of the diffusion coefficient of the crystallization-inducing metal. When the diffusion coefficient of the metal or the metal silicide is 1/100 or less of the diffusion coefficient of the crystallization-inducing metal, the gettering metal or the metal silicide is separated from the region 145a in the semiconductor layer 135 and the semiconductor. Diffusion to other regions in the layer 135 can be prevented.

Nickel is widely used as a crystallization-inducing metal used for crystallization of the semiconductor layer. In the case of nickel, the diffusion coefficient in the semiconductor layer is about 10 ⁻⁵ cm ² / s or less. Therefore, when nickel is used as the crystallization-inducing metal, the diffusion coefficient of the gettering metal or metal silicide in the semiconductor layer 135 is not more than 1/100 times that of nickel, that is, greater than 0 and 10 ⁻ It is desirable to have a value of ⁷ cm ² / s or less. At this time, the metal or the metal silicide is Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, Ta, One selected from the group consisting of La, Ce, Pr, Nd, Dy, Ho, TiN, and TaN, an alloy thereof, or a metal silicide thereof can be used.

  A gate insulating layer 150 is located over the entire surface of the substrate including the semiconductor layer 135. The gate insulating layer 150 may be a silicon oxide layer, a silicon nitride layer, or a double layer thereof. A gate electrode 155 is located on the gate insulating layer 150 in a region corresponding to the channel region 136 of the semiconductor layer 135. The gate electrode 155 is a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd), or a multilayer in which an aluminum alloy is stacked on a chromium (Cr) or molybdenum (Mo) alloy. be able to.

  An interlayer insulating layer 160 is located on the entire surface of the substrate 100 including the gate electrode 155. The interlayer insulating film 160 may be a silicon nitride film, a silicon oxide film, or a multilayer of these.

  Source / drain electrodes 167 and 168 electrically connected to the source / drain regions 137 and 138 of the semiconductor layer 135 are located on the interlayer insulating layer 160. Thus, the thin film transistor according to the first embodiment of the present invention is completed.

  3A to 3G are cross-sectional views illustrating a process of manufacturing a thin film transistor according to the first embodiment of the present invention.

  First, referring to FIG. 3A, a buffer layer 105 is formed on a substrate 100 made of glass, stainless steel, plastic, or the like. The buffer layer 105 may be a single layer using an insulating film such as a silicon oxide film or a silicon nitride film using a chemical vapor deposition method or a physical vapor deposition method. Alternatively, these layers are formed. At this time, the buffer layer 105 may sufficiently crystallize the amorphous silicon layer by preventing diffusion of moisture or impurities generated in the substrate 100 or adjusting a heat transfer rate during crystallization. Can do.

  Subsequently, an amorphous silicon layer 110 is formed on the buffer layer 105. At this time, the amorphous silicon layer 110 may be formed using a chemical vapor deposition method or a physical vapor deposition method. In addition, when the amorphous silicon layer 110 is formed or after the amorphous silicon layer 110 is formed, a dehydrogenation process can be performed to reduce the hydrogen concentration.

  Next, the amorphous silicon layer 110 is crystallized into a polycrystalline silicon layer. In the present invention, the amorphous silicon is obtained by using a crystallization method using a crystallization-inducing metal such as a MIC (Metal Induced Crystallization) method, a MILC (Metal Induced Lateral Crystallization) method, or an SGS (Super Grain Silicon) method. Crystallize the layer into a polycrystalline silicon layer.

  In the MIC method, a crystallization-inducing metal such as nickel (Ni), palladium (Pd), or aluminum (Al) is brought into contact with or injected into an amorphous silicon layer, and the crystallization-inducing metal causes many amorphous silicon layers. The MILC method uses a phenomenon in which a phase change is induced in a crystalline silicon layer, and the MILC method sequentially forms a crystal of silicon while a silicide formed by a reaction between a crystallization-inducing metal and silicon is continuously propagated to a side surface. This is a method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer using a method for inducing crystallization.

  In the SGS method, the concentration of the crystallization-inducing metal diffusing into the amorphous silicon layer is adjusted to be lower than that in the MIC method or MILC method, and the crystal grain size is adjusted to several μm to several hundred μm. It is a crystallization method capable of As one embodiment for adjusting the concentration of the crystallization-inducing metal diffused in the amorphous silicon layer to a low concentration, a capping layer is formed on the amorphous silicon layer, and the crystallization induction is formed on the capping layer. After forming the metal layer, the crystallization-inducing metal can be diffused by heat treatment. Depending on the process, the crystallization-inducing metal diffuses by forming the crystallization-inducing metal layer at a low concentration without forming a capping layer. The metal concentration can be adjusted to a low concentration.

  In the embodiment of the present invention, it is desirable to form a polycrystalline silicon layer by the SGS crystallization method, which will be described below.

  FIG. 3B is a cross-sectional view of a process of forming a capping layer and a crystallization-inducing metal layer on the amorphous silicon layer.

  Referring to FIG. 3B, a capping layer 115 is formed on the amorphous silicon 110. At this time, the capping layer 115 is preferably formed of a silicon nitride film that can easily control the diffusion of the crystallization-inducing metal formed in a future process through the heat treatment process. Multiple layers of membranes can be used. The capping layer 115 is formed by a method such as chemical vapor deposition or physical vapor deposition. At this time, the capping layer 115 has a thickness of 1 to 2000 mm. When the thickness of the capping layer 115 is less than 1 mm, it is difficult to prevent the amount of crystallization-inducing metal diffused by the capping layer 115, and when the thickness is greater than 2000 mm, it diffuses into the amorphous silicon layer 110. The amount of the crystallization-inducing metal is reduced and it is difficult to crystallize into the polycrystalline silicon layer.

Subsequently, a crystallization induction metal is deposited on the capping layer 115 to form a crystallization induction metal layer 120. At this time, the crystallization-inducing metal may be any one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr, and Cd. Uses nickel (Ni). At this time, the crystallization-inducing metal layer 120 is formed on the capping layer 115 at a surface density of 10 ¹¹ to 10 ¹⁵ atoms / cm ² , but the crystallization-inducing metal has a surface density of 10 ¹¹ atoms / cm ^2. If it is formed in a small amount, the amount of seeds that are crystallization nuclei is small, so that the amorphous silicon layer is difficult to crystallize into a polycrystalline silicon layer, and the crystallization-inducing metal has a surface of 10 ¹⁵ atoms / cm ² . If the density is higher than the density, the amount of crystallization-inducing metal diffusing into the amorphous silicon layer is large, so that the crystal grains of the polycrystalline silicon layer are small and the amount of residual crystallization-inducing metal is large. Become. As a result, the characteristics of the semiconductor layer formed by patterning the polycrystalline silicon layer may deteriorate.

  FIG. 3C is a cross-sectional view of the step of heat-treating the substrate to diffuse the crystallization-inducing metal through the capping layer and move it to the interface of the amorphous silicon layer.

  Referring to FIG. 3C, the substrate 100 on which the buffer layer 105, the amorphous silicon layer 110, the capping layer 115, and the crystallization-inducing metal layer 120 are formed is heat-treated to induce crystallization of the crystallization-inducing metal layer 120. Part of the metal is moved to the surface of the amorphous silicon layer 110. That is, only a small amount of the crystallization-inducing metal 120b among the crystallization-inducing metals 120a and 120b diffused through the capping layer 115 by the heat treatment is diffused to the surface of the amorphous silicon layer 110. Most of the crystallization-inducing metal 120 a cannot reach the amorphous silicon layer 110 or pass through the capping layer 115.

  Therefore, the amount of crystallization-inducing metal reaching the surface of the amorphous silicon layer 110 is determined by the diffusion preventing ability of the capping layer 115, and the diffusion preventing ability of the capping layer 115 is the thickness of the capping layer 115. There is a close relationship with density or density. That is, as the thickness of the capping layer 115 increases or the density increases, the amount of diffusion decreases, and the size of crystal grains increases accordingly. Conversely, the smaller the thickness or the lower the density, the greater the amount of diffusion and the smaller the crystal grain size.

  The deformation of the substrate due to an excessive heat treatment process can be prevented, and the heat treatment process is performed in a temperature range of 200 to 900 ° C. for several seconds to several hours in consideration of manufacturing cost and yield. Diffuse chemical-inducing metal. The heat treatment process may use any one of a furnace process, an RTA (Rapid Thermal Annealing) process, a UV process, and a laser process.

  FIG. 3D is a cross-sectional view of a process in which an amorphous silicon layer is crystallized into a polycrystalline silicon layer by a diffused crystallization-inducing metal.

  Referring to FIG. 3D, the amorphous silicon layer 110 is crystallized into the polycrystalline silicon layer 130 by the crystallization-inducing metal 120 b that has passed through the capping layer 115 and diffused to the surface of the amorphous silicon layer 110. That is, the diffused crystallization-inducing metal 120b is combined with silicon in the amorphous silicon layer 110 to form a metal silicide, and the metal silicide forms a seed that is a nucleus of crystallization. As a result, the amorphous silicon layer is crystallized into a polycrystalline silicon layer.

  On the other hand, in FIG. 3D, the heat treatment process is performed without removing the capping layer 115 and the crystallization-inducing metal layer 120. However, the crystallization-inducing metal is diffused on the amorphous silicon layer 110 to cause crystallization nuclei. After forming a certain metal silicide, the capping layer 115 and the crystallization-inducing metal layer 120 may be removed and heat-treated to form a polycrystalline silicon layer.

  Subsequently, referring to FIG. 3E, the capping layer 115 and the crystallization-inducing metal layer 120 are removed, and the polycrystalline silicon layer is patterned to form a semiconductor layer 135. Patterning the polycrystalline silicon layer may be a subsequent process separate from the present embodiment.

Here, the size of the semiconductor layer 135 is Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant, and c is 2.5 × 10 ^−13. To 6.8 × 10 ⁻¹³ )). That is, the length L and the width W of the channel region of the semiconductor layer 135 are determined according to the leakage current value to be controlled, and the length of the semiconductor layer 135 is considered in consideration of the length L and the width W of the channel region. And also determine the width.

At this time, referring to FIG. 9, when the width of the channel region of the semiconductor layer 135 is equal, the shorter the channel region length L, the subsequent gettering metal layer or metal silicide layer is present in the channel region. It can be seen that the efficiency of removing the crystallization-inducing metal is increased, and the leakage current value is decreased per 1 mm width W of the channel region. Especially when the length of the channel region is larger than 0 and 15 μm or less, the gettering effect is remarkable, and Ioff / W has a value of 1.0 × 10 ⁻¹² A / mm or less, which is good when used for a display. It can have the characteristic.

  Subsequently, a photoresist pattern 140 is formed on the semiconductor layer 135 so as to correspond to a region defined as a channel region of the semiconductor layer 135. Subsequently, a certain amount of conductive impurity ions are implanted using the photoresist pattern 140 as a mask to form a source region 137, a drain region 138, and a channel region 136 having a length L and a width W. At this time, a p-type impurity or an n-type impurity can be used as the impurity ion, and the p-type impurity includes boron (B), aluminum (Al), gallium (Ga), and indium (In). The n-type impurity may be selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), and the like.

  Next, referring to FIG. 3F, the photoresist pattern 140 is removed, and a metal layer pattern located at a certain distance from the channel region 136 and in contact with the semiconductor layer 135 on a region other than the channel region 136. Alternatively, a metal silicide layer pattern 145 is formed. In the present invention, after the metal layer pattern or the metal silicide layer pattern 145 is deposited, a gettering process is performed using a region 145a in the semiconductor layer 135 formed by performing a subsequent heat treatment process. The leakage current value can be reduced by removing the crystallization-inducing metal present in the channel region 136 of the semiconductor layer 135, and the length L of the channel region 136 of the semiconductor layer 135 and the channel region 136 of the semiconductor layer 135 can be reduced. It can be formed so as to satisfy the mathematical formula 1 between the leakage current values Ioff / W (A / mm) per 1 mm width.

  Here, the position where the metal layer pattern or the metal silicide layer pattern 145 is formed has a constant value with respect to the change in the length L of the channel region 136. That is, only the length L of the channel region 136 changes, and the position where the metal layer pattern or the metal silicide layer pattern 145 is formed from the channel region 136 has a constant value with respect to the changing length L. Form to have.

  The metal layer pattern or the metal silicide layer pattern 145 for gettering is a metal layer pattern including a metal having a diffusion coefficient smaller than the crystallization-inducing metal for crystallization or an alloy of these metals in the semiconductor layer 135, or A metal silicide layer pattern of these metals is desirable.

  The diffusion coefficient of the metal or metal silicide of the metal layer pattern or metal silicide layer pattern 145 in the semiconductor layer 135 is preferably 1/100 or less of the diffusion coefficient of the crystallization-inducing metal. When the diffusion coefficient of the metal or metal silicide is 1/100 or less of the diffusion coefficient of the crystallization-inducing metal, the gettering metal or metal silicide is the metal layer pattern or metal silicide layer pattern in the semiconductor layer 135. Accordingly, it is possible to prevent the semiconductor layer 135 from being diffused out of the region 145 a in contact with the region 145.

Nickel is widely used as a crystallization-inducing metal used for crystallization of the semiconductor layer. In the case of nickel, the diffusion coefficient in the semiconductor layer is about 10 ⁻⁵ cm ² / s or less. Therefore, when nickel is used as the crystallization-inducing metal, the diffusion coefficient of the metal or metal silicide of the metal layer pattern or metal silicide layer pattern 145 used for the gettering in the semiconductor layer 135 is 1 of nickel. It is desirable to have a value less than / 100 times, that is, a value greater than 0 and less than 10 ⁻⁷ cm ² / s. At this time, the metal or metal silicide is Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, Ta, La. , Ce, Pr, Nd, Dy, Ho, TiN, and TaN, one of these alloys, or a silicide of these metals.

  The metal layer pattern or the metal silicide layer pattern 145 is preferably formed to a thickness of 30 to 10,000 mm. When the thickness is less than 30 mm, the efficiency of gettering the crystallization-inducing metal in the region 145a in the semiconductor layer 135 in contact with the metal layer pattern or the metal silicide layer pattern 145 is reduced, and exceeds 10,000 mm. When the metal layer pattern or the metal silicide layer pattern 145 is thick, there is a possibility that peeling of the layer may occur due to subsequent stress during heat treatment.

  Subsequently, a heat treatment process is performed to remove the crystallization-inducing metal remaining in the semiconductor layer 135, particularly in the channel region 136 of the semiconductor layer. When the heat treatment step is performed, the metal of the metal layer pattern diffuses from the surface of the semiconductor layer 135 in contact with the metal layer pattern or the metal silicide layer pattern 145 to a region in the semiconductor layer 135, or the semiconductor layer 135 The metal silicide is bonded to form a metal silicide or the metal silicide of the metal silicide layer pattern diffuses into a region in the semiconductor layer 135. As a result, in a region in contact with the metal layer pattern or the metal silicide layer pattern 145, a region 145a where a metal different from the crystallization-inducing metal or the metal silicide of the metal exists from the surface of the semiconductor layer 135 to a certain depth is formed.

  The crystallization-inducing metal for crystallization remaining in the channel region 136 of the semiconductor layer 135 diffuses into the region 145a in the semiconductor layer 135 in contact with the metal layer pattern or the metal silicide layer pattern 145 by the heat treatment step. The crystallization-inducing metal is precipitated in the region 145a and does not diffuse any further. This is because the crystallization-inducing metal is more thermodynamically stable in the region 145a where another metal or metal silicide exists than in the silicon. Therefore, the crystallization-inducing metal remaining in the channel region 136 of the semiconductor layer 135 can be removed based on this principle.

  At this time, the heat treatment is performed in a temperature range of 500 to 993 ° C. and heated for 10 seconds to 10 hours. When the heat treatment temperature is less than 500 ° C., diffusion of the crystallization-inducing metal does not occur in the semiconductor layer 135, and the crystallization-inducing metal cannot move to the region 145 a in the semiconductor layer 135. When the heat treatment temperature exceeds 993 ° C., the eutectic point of nickel used for the crystallization-inducing metal is 993 ° C., so that nickel liquefies and the substrate may be deformed due to the high temperature.

  Further, when the heat treatment time is less than 10 seconds, the crystallization-inducing metal remaining in the channel region 136 of the semiconductor layer 135 is not sufficiently removed, and when the heat treatment time exceeds 10 hours, a long time is required. Problems of substrate deformation due to heat treatment and production cost and yield of thin film transistors may occur. On the other hand, when it is carried out at a higher temperature, the crystallization-inducing metal can be removed by heating in a short time.

  Subsequently, referring to FIG. 3G, the metal layer pattern or the metal silicide layer pattern 145 is removed, and a gate insulating layer 150 is formed over the entire surface of the substrate 100 on which the semiconductor layer 135 is formed. The gate insulating layer 150 may be a silicon oxide layer, a silicon nitride layer, or a double layer thereof.

  Subsequently, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) is laminated on the gate insulating film 150, or an aluminum alloy is laminated on a chromium (Cr) or molybdenum (Mo) alloy. A gate electrode metal layer (not shown) is formed on the multi-layer, and the gate electrode metal layer is etched by a photoetching process to form a gate electrode 155 at a portion corresponding to the channel region 136 of the semiconductor layer 135. Form.

  Subsequently, an interlayer insulating layer 160 is formed over the entire surface of the substrate 100 including the gate electrode 155. Here, the interlayer insulating film 160 may be a silicon nitride film, a silicon oxide film, or a multilayer of these.

  Subsequently, the interlayer insulating layer 160 and the gate insulating layer 150 are etched to form contact holes that expose the source / drain regions 137 and 138 of the semiconductor layer 135. Source / drain electrodes 167 and 168 connected to the source / drain regions 137 and 138 through the contact holes are formed. Here, the source / drain electrodes 167 and 168 include molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum tungsten (MoW), aluminum (Al), aluminum-neodymium (Al-Nd), and titanium (Ti ), Titanium nitride (TiN), copper (Cu), molybdenum alloy (Mo alloy), aluminum alloy (Al alloy), and copper alloy (Cu alloy). . Thus, a thin film transistor including the semiconductor layer 135, the gate electrode 155, and the source / drain electrodes 167 and 168 is completed.

  FIG. 4 is a cross-sectional view illustrating a thin film transistor according to a second embodiment of the present invention. Reference is made to what was referred to in FIGS. 1 and 2 above, except as otherwise noted below.

  Referring to FIG. 4, a substrate 400 is first prepared. A buffer layer 410 is located on the substrate 400. A gate electrode 420 is positioned on the buffer layer 410. A gate insulating layer 430 is located on the gate electrode 420.

  A patterned semiconductor layer 440 is located on the gate insulating layer 430. The semiconductor layer 440 is a semiconductor layer crystallized by a crystallization method using a crystallization-inducing metal such as a MIC (Metal Induced Crystallization) method, a MILC (Metal Induced Lateral Crystallization) method, or an SGS (Super Grain Silicon) method. A channel region 441 and source / drain regions 442 and 443. The semiconductor layer 440 is preferably crystallized by an SGS method in which the concentration of the crystallization-inducing metal diffused in the amorphous silicon layer can be controlled at a low concentration as compared with the MIC method or MILC method.

Between the length L (μm) of the channel region 441 of the semiconductor layer 440 and the leakage current value Ioff (A / mm) per width W1 mm of the channel region 441 of the semiconductor layer 440, Ioff / W (L) = 3.4. The mathematical formula 1 of × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant and c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ ) is satisfied. Therefore, since it is possible to predict the leakage current value depending on the size of the channel region 441 of the semiconductor layer 440, the leakage current value is controlled by controlling the width W and the length L of the channel region 441 of the semiconductor layer 440. Can be controlled. In contrast, since the leakage current value can be predicted, the length L and the width W of the channel region 441 of the semiconductor layer 440 can be controlled in consideration of the leakage current value to be controlled.

Here, referring to FIG. 9, when the width of the channel region of the semiconductor layer 440 is equal, a metal different from the crystallization-inducing metal described later or a metal silicide of the metal is formed as the length L of the channel region is shorter. It can be seen that the efficiency of removing the crystallization-inducing metal existing in the channel region using the region that has been increased increases, and the leakage current value per 1 mm width W of the channel region decreases. In particular, when the length of the channel region is greater than 0 and 15 μm or less, the gettering effect is remarkable, and Ioff / W can have a value of 1.0 × 10 ⁻¹² A / mm or less. Can have good properties when used.

In the semiconductor layer 440 spaced apart from the channel region 441, a metal different from the crystallization-inducing metal or a metal silicide of the metal is formed from the surface of the semiconductor layer 440 to a certain depth in the semiconductor layer 440. A region 460a is located. At this time, the metal or the metal silicide is a metal or metal silicide for gettering. In the present invention, a gettering process is performed using the region 460a in which the metal or the metal silicide is formed, thereby removing the crystallization-inducing metal present in the channel region 441 of the semiconductor layer 440, thereby causing leakage current. Between the length L (μm) of the channel region 441 of the semiconductor layer 440 and the leakage current value Ioff / W (A / mm) per width W1 mm of the channel region 441 of the semiconductor layer 440. Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant, c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ )) To satisfy the mathematical formula 1.

  Here, the distance from the channel region 441 to the region 460a in which the metal different from the crystallization-inducing metal or the metal silicide of the metal is formed is relative to the change in the length L of the channel region 441. Has a constant value.

  Source / drain electrodes 472 and 473 electrically connected to the source / drain regions 442 and 443 are located on the semiconductor layer 440. Thus, the thin film transistor according to the second embodiment of the present invention is completed.

  5A to 5D are cross-sectional views illustrating a process of manufacturing a thin film transistor according to the second embodiment of the present invention. Except as otherwise noted below, reference is made to what has been said in the above embodiments.

  Referring to FIG. 5A, a buffer layer 410 is formed on the substrate 400. A gate electrode metal layer (not shown) is formed on the buffer layer 410, and the gate electrode metal layer is etched by a photoetching process to form the gate electrode 420. Subsequently, a gate insulating layer 430 is formed on the substrate 400 on which the gate electrode 420 is formed.

  5B, after an amorphous silicon layer is formed on the gate insulating film 430, the amorphous silicon layer is crystallized using a crystallization-inducing metal as in the first embodiment. To form a polycrystalline silicon layer. The polycrystalline silicon layer is patterned to form the semiconductor layer 440. Patterning the polycrystalline silicon layer may be a subsequent process separate from the present embodiment.

Here, the size of the semiconductor layer 440 is Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c (c is a constant, and c is 2.5 × 10 ^{−13. Or} 6.8 × 10 ⁻¹³ )). That is, the length L and the width W of the channel region of the semiconductor layer 440 are determined according to the leakage current value to be controlled, and the length of the semiconductor layer 440 is taken into consideration in consideration of the length L and the width W of the channel region. And also determine the width. The semiconductor layer 440 is formed by patterning the polycrystalline silicon layer according to the determined length and width.

Referring to FIG. 9, when the width of the channel region of the semiconductor layer 440 is equal, the channel region is obtained by using the subsequent gettering metal layer pattern or metal silicide layer pattern as the length L of the channel region is shorter. It can be seen that the efficiency of removing the crystallization-inducing metal present in is increased, and the leakage current value is reduced per 1 mm width W of the channel region. In particular, when the length of the channel region is greater than 0 and 15 μm or less, the gettering effect is remarkable, and Ioff / W can have a value of 1.0 × 10 ⁻¹² A / mm or less. Can have good properties when used.

  Subsequently, a photoresist pattern 450 is formed on the semiconductor layer 440 so as to correspond to a region defined as a channel region of the semiconductor layer 440. Subsequently, a certain amount of conductive impurity ions are implanted using the photoresist pattern 450 as a mask to form a source region 442, a drain region 443, and a channel region 441 having a length L and a width W.

  Subsequently, referring to FIG. 5C, the photoresist pattern 450 is removed, and the metal layer pattern is located at a certain distance from the channel region 441 and is in contact with the semiconductor layer 440 on a region other than the channel region 441. Alternatively, a metal silicide layer pattern 460 is formed.

  In the present invention, after the metal layer pattern or the metal silicide layer pattern 460 is deposited, a gettering process is performed using a region 460a in the semiconductor layer 440 formed by performing a subsequent heat treatment process. The leakage current value can be reduced by removing the crystallization-inducing metal present in the channel region 441 of the semiconductor layer 440, and the length L of the channel region 441 of the semiconductor layer 440 and the channel region of the semiconductor layer 440 can be reduced. It can be formed so as to satisfy the mathematical formula 1 between the leakage current value Ioff / W (A / mm) of 441 in width of 1mm.

  Here, the position where the metal layer pattern or the metal silicide layer pattern 460 is formed has a constant value with respect to the change in the length L of the channel region 441. That is, only the length L of the channel region changes, and the position where the metal layer pattern or the metal silicide layer pattern 460 is formed from the channel region 441 is formed to have a constant value with respect to the changing L. To do.

  Subsequently, a heat treatment process is performed to remove the crystallization-inducing metal remaining in the semiconductor layer 440, particularly in the channel region 441 of the semiconductor layer. When the heat treatment step is performed, a region different from the crystallization-inducing metal or a metal silicide of the metal exists in a region in contact with the metal layer pattern or the metal silicide layer pattern 460 from the surface of the semiconductor layer 440 to a certain depth. 460a is formed. The crystallization-inducing metal present in the channel region 441 of the semiconductor layer 440 is diffused into the region 460a to getter the crystallization-inducing metal. The heat treatment is the same as that described in the embodiment.

  Subsequently, referring to FIG. 5D, the metal layer pattern or the metal silicide layer pattern 460 is removed, and a source / drain conductive film is formed on the semiconductor layer 440 and patterned to form source / drain electrodes 472 and 473. Form. Thus, a bottom gate thin film transistor including the gate electrode 420, the semiconductor layer 440, and the source / drain electrodes 472 and 473 is completed.

  FIG. 6 shows a leakage current according to a channel ratio (channel region width W (mm) / channel region length L (μm)) of a thin film transistor using a semiconductor layer crystallized using a conventional crystallization-inducing metal. It is the graph which measured the value. Here, the horizontal axis indicates the channel ratio (channel region width W (mm) / channel region length L (μm)), and the vertical axis indicates the leakage current value Ioff (A).

Referring to FIG. 6, the leakage current value of a thin film transistor using a semiconductor layer crystallized using a conventional crystallization-inducing metal increases the width of a channel region to 4, 10, 50 mm, or a length of 3 to 20 μm. It can be seen that increasing within the range increases or decreases irregularly without having a certain tendency. It can also be seen that even if the channel ratio changes, the leakage current value is in the range of 2.0 × 10 ⁻¹² to 4.0 × 10 ⁻¹² A, and changes within a range that does not have a significant difference. Therefore, it can be seen that the effect is small when the leakage current value is controlled by changing the channel ratio. Therefore, in a thin film transistor that uses a semiconductor layer that has been crystallized using a conventional crystallization-inducing metal, a change in leakage current value due to a change in the channel ratio of the semiconductor layer cannot be predicted separately from the embodiment of the present invention. The leakage current value cannot be clearly controlled by changing the channel ratio, and the size of the channel region cannot be determined in consideration of the leakage current value to be controlled.

  On the other hand, FIG. 7 is a graph obtained by measuring the leakage current value according to the channel ratio of a thin film transistor that has been heat-treated after forming a gettering metal layer pattern or a metal silicide layer pattern according to an embodiment of the present invention. Here, the horizontal axis indicates the channel ratio (channel region width W (mm) / channel region length L (μm)), and the vertical axis indicates the leakage current value Ioff (A).

  FIG. 8 is a graph showing a leakage current value Ioff (A / mm) per 1 mm width of the channel region of the semiconductor layer according to the length L (μm) of the channel region of the thin film transistor according to the embodiment of the present invention. Here, the horizontal axis indicates the length L (μm) of the channel region, and the vertical axis indicates the leakage current value Ioff / W (A / mm) per width W1 mm of the channel region. FIG. 9 is a functional relational expression of the leakage current value Ioff / W (A / mm) per width W1 mm of the channel region of the semiconductor layer with respect to the length L (μm) of the channel region through regression analysis of the data of FIG. It is a graph of the result of having derived | led-out. Here, the horizontal axis indicates the length L (μm) of the channel region, and the vertical axis indicates the leakage current value Ioff / W (A / mm) per width W1 mm of the channel region.

Referring to FIG. 7, the thin film transistor according to the embodiment of the present invention has the same channel ratio as the thin film transistor of FIG. 6, but the leakage current value is significantly reduced to a value close to 5.0 × 10 ⁻¹³ A. I understand that. That is, when the heat treatment is performed after forming the gettering metal layer pattern or the metal silicide layer pattern, it can be confirmed that the crystallization-inducing metal in the channel region has been gettered.

  Referring to FIG. 8, in order to grasp the correlation between the length L of the channel region and the leakage current value in the thin film transistor according to the embodiment of the present invention, the leakage current value Ioff is divided by the width W of the channel region in FIG. If the Ioff / W value according to the length L of the channel region is made to correspond, the value of Ioff / W may change to a quadratic function curve form as the length L of the channel region increases as shown in FIG. I understand. That is, when the widths of the channel regions are equal, the leakage current increases in a quadratic function curve as the length L of the channel region increases.

Referring to FIG. 9, if a function relational expression is derived from the data of FIG. 8 by regression analysis using the value of Ioff / W, Loff / W (L) = 3.4 × 10 ⁻¹⁵ L ² +2 4 × 10 ⁻¹² L + 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ of the functional relational expression. Here, the unit of Ioff is A, W is mm, and L is μm.

  Therefore, the thin film transistor according to the embodiment of the present invention can reduce the leakage current value by removing the crystallization-inducing metal present in the channel region of the semiconductor layer, and predict the leakage current value due to the size of the channel region of the semiconductor layer. Therefore, the leakage current value can be controlled by controlling the width W or length L of the channel region of the semiconductor layer. In contrast, since the leakage current value can be predicted, the length L and the width W of the channel region of the semiconductor layer can be controlled in consideration of the leakage current value to be controlled.

Referring to FIG. 9, the thin film transistor according to the embodiment of the present invention uses the gettering metal layer pattern or the metal silicide layer pattern as the length L of the channel region is shorter when the width of the channel region of the semiconductor layer is equal. As a result, the efficiency of removing the crystallization-inducing metal existing in the channel region is increased, so that the leakage current value per 1 mm width W of the channel region has a value that decreases in a quadratic function as in the above functional relational expression. I understand. In particular, the thin film transistor according to the embodiment of the present invention may have a value of Ioff / W of 1.0 × 10 ⁻¹² A / mm when the length L of the channel region has a value of 15 μm or less. In addition, when the thin film transistor is used in a display, the thin film transistor can have good characteristics.

  FIG. 10 is a cross-sectional view of an organic light emitting display including the thin film transistor according to the first embodiment of the present invention.

  Referring to FIG. 10, an insulating layer 170 is formed on the entire surface of the substrate 100 including the thin film transistor according to the embodiment of FIG. 3G of the present invention. The insulating film 170 may be any one selected from a silicon oxide film, a silicon nitride film, or a spin-on-glass film, which is an inorganic film, or a polyimide, an organic film, or a benzocyclobutene resin. It can be formed of any one selected from (benzocyclobutene series resin) or acrylate. Further, it may be formed of a laminated structure of the inorganic film and the organic film.

  The insulating layer 170 is etched to form via holes that expose the source or drain electrodes 167 and 168. A first electrode 175 connected to any one of the source or drain electrodes 167 and 168 through the via hole is formed. The first electrode 175 may be an anode or a cathode. When the first electrode 175 is an anode, the anode may be formed of a transparent conductive film made of any one of ITO, IZO, and ITZO. When the first electrode 175 is a cathode, the cathode is Mg, Ca. , Al, Ag, Ba, or an alloy thereof can be used.

  Subsequently, a pixel definition film 180 having an opening exposing a part of the surface of the first electrode 175 is formed on the first electrode 175, and an organic film including a light emitting layer is formed on the exposed first electrode 175. Layer 185 is formed. The organic film layer 185 further includes one or more layers selected from the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, an electron suppression layer, an electron injection layer, and an electron transport layer. Can be included. Subsequently, a second electrode 190 is formed on the organic layer 185. Accordingly, an organic light emitting display according to an embodiment of the present invention is completed.

  Therefore, in the thin film transistor according to the embodiment of the present invention, the crystallization-inducing metal and the semiconductor layer are separated from the channel region in a position separated from the channel region in the semiconductor layer crystallized using the crystallization-inducing metal. Forming a region where a different metal or metal silicide of the metal is present and performing a gettering process using the region, thereby removing a crystallization-inducing metal present in the channel region and reducing a leakage current value. Since it is possible to predict the leakage current value due to the size of the channel region of the semiconductor layer, the leakage current value can be controlled by controlling the width W and length L of the channel region of the semiconductor layer. Can be controlled. In contrast, since the leakage current value can be predicted, the length L and the width W of the channel region of the semiconductor layer can be controlled in consideration of the leakage current value to be controlled.

1 is a cross-sectional view illustrating a thin film transistor according to a first embodiment of the present invention. It is sectional drawing for demonstrating the semiconductor layer of the thin-film transistor by 1st Embodiment of this invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view sequentially illustrating steps of manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view for explaining a thin film transistor according to a second embodiment of the present invention. It is sectional drawing which shows in order the process of manufacturing the thin-film transistor by 2nd Embodiment of this invention. It is sectional drawing which shows in order the process of manufacturing the thin-film transistor by 2nd Embodiment of this invention. It is sectional drawing which shows in order the process of manufacturing the thin-film transistor by 2nd Embodiment of this invention. It is sectional drawing which shows in order the process of manufacturing the thin-film transistor by 2nd Embodiment of this invention. A graph of leakage current measured by channel ratio (channel region width W (mm) / channel region length L (μm)) of a thin film transistor using a semiconductor layer crystallized using a conventional crystallization-inducing metal. is there. 6 is a graph showing a measured leakage current value according to a channel ratio of a thin film transistor according to an embodiment of the present invention. 5 is a graph showing a leakage current value Ioff (A / mm) per 1 mm width of the channel region of the semiconductor layer according to the length L (μm) of the channel region of the thin film transistor according to the embodiment of the present invention. FIG. 8 is a graph showing the result of deriving a functional relational expression for the leakage current value Ioff / W (A / mm) per channel width W1 mm of the semiconductor layer and the length L (μm) of the channel region through regression analysis of the data of FIG. It is. 1 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to a first embodiment of the present invention.

Explanation of symbols

100, 400: Substrate 105, 410: Buffer layer 135, 440: Semiconductor layer 150, 430: Gate insulating film 145, 460: Metal layer pattern or metal silicide layer pattern 155, 420: Gate electrode 160, 760: Interlayer insulating film 167 168, 472, 473: source / drain electrodes 170: insulating film 175: first electrode 180: pixel defining film 185: organic film layer 190: second electrode

Claims (8)

Providing the substrate,
Forming an amorphous silicon layer on the substrate;
Crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal;
The length and width of the channel region of the semiconductor layer are determined by the leakage current value to be controlled using the following mathematical formula 1,
Patterning the polycrystalline silicon layer to form a semiconductor layer having a channel region having the length and width;
Forming a metal layer pattern or a metal silicide layer pattern in contact with the semiconductor layer on a region other than the channel region, spaced apart from the channel region by a certain distance;
Heat-treating the substrate to getter the crystallization-inducing metal present in the channel region of the semiconductor layer to a region in the semiconductor layer corresponding to a region where the metal layer pattern or metal silicide layer pattern is formed;
Removing the metal layer pattern or metal silicide layer pattern;
Forming a gate electrode to correspond to a certain region of the semiconductor layer;
Forming a gate insulating film located between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode;
A method of manufacturing a thin film transistor, comprising forming a source / drain electrode electrically connected to a source / drain region of the semiconductor layer.
[Equation 1]
Ioff / W (L) = 3.4 × 10 ⁻¹⁵ L ² + 2.4 × 10 ⁻¹² L + c, where Ioff is the leakage current value (A) of the semiconductor layer and W is the width of the channel region (mm) , L is the length (μm) of the channel region, and c is a constant, and c is 2.5 × 10 ⁻¹³ to 6.8 × 10 ⁻¹³ . The metal layer pattern or the metal silicide layer pattern is a metal layer pattern including a metal or an alloy thereof having a diffusion coefficient smaller than that of the crystallization-inducing metal in the semiconductor layer, or a metal silicide layer pattern including a silicide of these metals. The method for producing a thin film transistor according to claim 1 , wherein: 3. The method of manufacturing a thin film transistor according to claim 2 , wherein a diffusion coefficient of the metal layer pattern or the metal silicide layer pattern is 1/100 or less of a diffusion coefficient of the crystallization-inducing metal. The metal layer pattern or the metal silicide layer pattern is Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, Ta, la, Ce, Pr, Nd, Dy, Ho, claim 3, wherein TiN, and or include one or an alloy selected from the group consisting of TaN, or to include a silicide of these metals A method for producing the thin film transistor according to 1. The method of claim 1 , wherein the heat treatment is performed in a temperature range of 500 ° C to 993 ° C for 10 seconds to 10 hours. 2. The method of manufacturing a thin film transistor according to claim 1 , wherein the amorphous silicon layer is formed on the polycrystalline silicon layer by SGS crystallization. 2. The method of claim 1 , wherein the metal layer pattern or the metal silicide layer pattern is formed to a thickness of 30 to 10,000. 2. The method of manufacturing a thin film transistor according to claim 1 , wherein the length of the channel region of the semiconductor layer is greater than 0 and 15 μm or less.

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