JP5058841B2 - Inverter power supply and arc machining power supply - Google Patents

Description

  The present invention relates to an inverter power supply device and an arc machining power supply device that are provided in parallel and are provided with a plurality of inverter circuits built in the power supply device in parallel.

  In the arc machining power supply device, in order to increase the output current, a plurality of inverter circuits are provided in parallel to perform parallel operation.

  FIG. 4 shows a conventional arc machining power supply apparatus in which, for example, two main circuits formed of an inverter circuit, a main transformer, a secondary rectifier circuit, and a DC reactor are provided in parallel. In the figure, a DC power supply circuit is formed by a primary rectifier circuit DR1 that rectifies a commercial AC power supply AC and outputs a DC voltage, and a smoothing capacitor C1 that smoothes the DC voltage.

  The bridge-connected first inverter circuit IN1 shown in FIG. 4 is formed by the first switching element TR1 to the fourth switching element TR4, and the first switching element TR1 and the fourth switching element TR4 facing each other. The second switching element TR2 and the third switching element TR3 form a pair, and the pair alternately turns on and off alternately to convert the DC voltage into a high-frequency AC voltage and output it. The second inverter circuit IN2 is formed by the fifth switching element TR5 to the eighth switching element TR8, and is provided in parallel with the first inverter circuit IN1.

  The first main transformer INT1 converts the high-frequency AC voltage converted by the first inverter circuit IN1 into a high-frequency AC voltage suitable for arc machining, and the first secondary rectifier circuit DR2 The output power of the vessel INT1 is rectified and supplied between the torch TH and the workpiece M via the first DC reactor DCL1.

  The second main transformer INT2 converts the high-frequency AC voltage converted by the second inverter circuit IN2 into a high-frequency AC voltage suitable for arc machining, and the second secondary rectifier circuit DR3 The output power of the container INT2 is rectified and supplied between the torch TH and the workpiece M via the second DC reactor DCL2.

  The first output current detection circuit ID1 detects the rectified output current on the secondary side of the first main transformer INT1 and outputs it as the first output current detection signal Id1, and the second output current detection circuit ID2 detects the rectified output current on the secondary side of the second main transformer INT2 and outputs it as a second output current detection signal Id2.

  The current-corresponding pulse width modulation circuit PWI performs PWM control for modulating the pulse width with a constant pulse frequency, and performs first pulse width modulation Pw1 based on the deviation between the first output current detection signal Id1 and the output current setting signal. And the second pulse width modulation signal Pw2 and the third pulse width modulation Pw3 and the fourth pulse width modulation based on the deviation between the second output current detection signal Id2 and the output current setting signal. Modulates the pulse width of Pw4.

  The first inverter drive circuit SD1 outputs a first switching element drive signal Tr1 and a fourth switching element drive signal Tr4 according to the first pulse width modulation Pw1, and according to the second pulse width modulation signal Pw2. The second switching element drive signal Tr2 and the third switching element drive signal Tr3 are output. The second inverter drive circuit SD2 outputs a fifth switching element drive signal Tr5 and an eighth switching element drive signal Tr8 in response to the third pulse width modulation signal Pw3, and a fourth pulse width modulation signal Pw4. Accordingly, the sixth switching element drive signal Tr6 and the seventh switching element drive signal Tr7 are output.

Next, the operation will be described.
The current-corresponding pulse width modulation circuit PWI compares the first output current detection signal Id1 detected by the first output current detection circuit ID1 with a predetermined output current setting signal Ir, and the first pulse width modulation signal The Pw1 and the second pulse width modulation signal Pw2 are generated, the second output current detection signal Id2 detected by the second output current detection circuit ID2 is compared with the output current setting signal Ir, and the third pulse A width modulation signal Pw3 and a fourth pulse width modulation signal Pw4 are generated and output.

  At this time, the current corresponding pulse width modulation circuit PWI uses the first pulse width modulation signal Pw1 and the second pulse width modulation so that the value of the first output current detection signal Id1 and the output current setting signal Ir become substantially the same. While modulating the pulse width of the signal Pw2, the third pulse width modulation signal Pw3 and the fourth pulse width modulation signal Pw4 so that the value of the second output current detection signal Id2 and the output current setting signal Ir become substantially the same. Since the output currents of the first inverter circuit IN1 and the second inverter circuit IN2 can be balanced, the inverter circuits can be operated in parallel. (For example, Patent Document 1)

  However, in order to operate a plurality of main circuits in parallel, a plurality of expensive output current detection circuits are required according to the number of main circuits.

Japanese Utility Model Publication No. 6-34873

  In the prior art, in an arc machining power supply device in which N main circuits each including an inverter circuit, a main transformer, a secondary rectifier circuit, and a DC reactor are provided in parallel, the output current from each main circuit is detected, and each of these outputs is detected. When the pulse width modulation signal is controlled so that each output current becomes substantially the same as the output current setting value by comparing the current with a predetermined output current setting value, and each inverter circuit is driven by each pulse width modulation signal, The output currents of the N main circuits provided are substantially balanced, and parallel operation is possible.

  However, in order to operate N main circuits in parallel, a plurality of output current detection circuits are required according to the number of units. This output current detection circuit is formed by an expensive hall device and electronic components attached thereto. Therefore, it was a major factor that hindered price increases and product prices.

  Therefore, it is an object of the present invention to provide an arc machining power supply device that can solve the above-described problems.

In the case of operating a plurality of main circuits in parallel, it is necessary to balance the current flowing through each main circuit, and the biggest factor that causes the current balance to be lost is the components that form the inverter drive circuit and each of the inverter circuits. It has been elucidated that this is a difference in ON and OFF timing due to variations in switching elements.
In order to solve the above-mentioned problem, a first invention is a primary rectifier circuit that rectifies a commercial AC power supply and outputs a DC voltage, and a smoothing capacitor that is provided in parallel to the primary rectifier circuit and smoothes the DC voltage. A first inverter circuit for converting the DC voltage into a high-frequency AC voltage, a first main transformer for converting the output of the first inverter circuit into a high-frequency AC voltage suitable for a predetermined load, and the first A first secondary rectifier circuit for rectifying the output power of the main transformer, a first DC reactor for smoothing the rectified output power and outputting it to an output terminal, and between the smoothing capacitor and the output terminal (N-1) main circuits formed by connecting an inverter circuit, a main transformer, a secondary rectifier circuit and a DC reactor in series, and detecting the total output current of the main circuit by detecting the total output current Total output as a signal A current detection circuit; an output current setting circuit for setting a predetermined output current setting signal; and a first pulse width modulation signal and a second pulse width modulation signal based on a deviation between the total output current detection signal and the output current setting signal. A pulse width modulation circuit that modulates a pulse width of a pulse width modulation signal, and a first output voltage detection circuit that detects an output voltage of the first main transformer to an output voltage of the Nth main transformer. An Nth output voltage detection circuit, a first output voltage rectifier circuit that rectifies the first output voltage and outputs it as a first DC voltage, or rectifies and outputs the Nth output voltage as an Nth DC voltage. An Nth output voltage rectifier circuit, an average reference voltage circuit for calculating an average of the first DC voltage to the Nth DC voltage and outputting the average reference voltage, and the first DC voltage and the average reference voltage So that the values of and The first pulse width correction circuit through the Nth pulse width correction signal for correcting the pulse widths of the first pulse width modulation signal and the second pulse width modulation signal and outputting them as the first pulse width correction signal and the second pulse width correction signal. The pulse widths of the first pulse width modulation signal and the second pulse width modulation signal are corrected so that the values of the DC voltage and the average reference voltage are substantially the same, and the (2N-1) th pulse width correction signal and An Nth pulse width correction circuit that outputs as a (2N) pulse width correction signal, and a first inverter that drives the first inverter circuit in response to the first pulse width correction signal and the second pulse width correction signal. Inverter driving circuit to Nth inverter driving circuit for driving the Nth inverter circuit in response to the (2N-1) th pulse width correction signal and the (2N) th pulse width correction signal. It is characterized by A converter power supply.

  According to a second aspect of the present invention, the correction of the pulse width of the pulse width modulation signal is performed by calculating a deviation between the average reference voltage and the DC voltage, and when the deviation value is positive, the pulse width is calculated based on the positive value. The inverter power supply device according to claim 1, wherein when the deviation value is negative, the pulse width is lengthened based on the negative value.

  According to a third aspect of the present invention, the first output voltage detection circuit through the Nth output voltage detection circuit are formed by providing an auxiliary winding on the secondary side of the first main transformer through the Nth main transformer. The inverter power supply device according to claim 1 or 2, wherein

  4th invention converts the output voltage of the inverter power supply device of any one of said Claim 1 thru | or 3 into the voltage for arc machining suitable for arc load, The arc machining characterized by the above-mentioned Power supply device.

According to the first and second inventions, N main circuits formed by connecting an inverter circuit, a main transformer, a secondary rectifier circuit, and a DC reactor in series are provided in parallel, and the total output current of the main circuit is one. In an arc machining power supply device that detects the output current detection circuit of the inverter and controls the pulse width of the pulse width modulation signal of each inverter circuit based on the detected total output current, it is formed with low-priced parts such as resistors and photocouplers The output voltage detection circuit is provided on the secondary side of each main transformer to detect the output voltage, and each output voltage is rectified into a DC voltage, and the average reference voltage is obtained by averaging the plurality of DC voltages. When the pulse width of the pulse width modulation signal that controls the inverter circuit is corrected based on the deviation value between the average reference voltage and the DC voltage of each main transformer, each DC voltage becomes substantially the same as the average reference voltage, and in parallel. Provided in The output current of the pieces of the main circuit is substantially balanced.
As described above, one expensive output current detection circuit and N low-value output voltage detection circuits can be operated in parallel, and the number of expensive output current detection circuits can be reduced.

  According to the third invention, the output voltage detection circuit is formed by providing the auxiliary winding on the secondary side of each main transformer, the circuit configuration is greatly simplified, and the price is further reduced.

  According to the fourth aspect of the invention, it can be applied to a power supply device for arc machining, and the welding current can be easily increased at a low price.

  In the case where a plurality of main circuits are operated in parallel, the major factor of the current variation in the parallel operation is a variation in the ON period of each inverter circuit, thereby balancing the output currents of the N main circuits provided in parallel. Can not be removed. Therefore, in the present invention, the output voltage on the secondary side of each main transformer is detected, the average output voltage is obtained by averaging the plurality of output voltages, and the average output voltage and the output voltage of each main transformer are When the pulse width of the pulse width modulation signal for controlling each inverter circuit is corrected so as to be substantially the same, variation in the ON period of each inverter circuit is suppressed, and the output currents of the N main circuits provided in parallel are substantially reduced. It becomes equilibrium.

  FIG. 1 is a power supply device for arc processing according to an embodiment of the present invention that suppresses variations in ON periods of a plurality of inverter circuits (for example, two main circuits are provided in parallel). In the figure, the components having the same reference numerals as those in the electrical connection diagram of the arc machining power supply device of the prior art shown in FIG. 4 perform the same operations, so the description thereof will be omitted, and only the components having different reference numerals will be described.

  The first output voltage detection circuit VD1 is formed by a resistor and a photocoupler (not shown), and is provided on the secondary side of the first main transformer INT1, thereby detecting an AC output voltage and generating a first output voltage detection signal Vd1. The second output voltage detection circuit VD2 is formed by a resistor and a photocoupler (not shown) and provided on the secondary side of the second main transformer INT2, thereby detecting the AC output voltage and detecting the second output voltage. Output as signal Vd2.

  The first output voltage rectifier circuit AR1 rectifies the first output voltage detection signal Vd1 and outputs it as the first DC voltage Ar1, and the second output voltage rectifier circuit AR2 receives the second output voltage detection signal Vd2. Rectified and output as a second DC voltage Ar2, and the first DC voltage Ar1 and the second DC voltage Ar2 are proportional to the ON time of the switching element.

  The average reference voltage circuit EA calculates an average value of two DC voltages of the first DC voltage Ar1 and the second DC voltage Ar2 and outputs it as an average reference voltage Ea.

  The pulse width modulation circuit PW performs PWM control that modulates the pulse width with a constant pulse frequency, and based on the deviation between the total output current detection signal Id and the output current setting signal Ir, the first pulse width modulation signal Pw1 and the first pulse width modulation signal Pw1 The pulse width of the second pulse width modulation signal Pw2 is modulated and output.

  The first pulse width correction circuit SV1 calculates a deviation between the first DC voltage Ar1 and the average reference voltage Ea, and based on the value of the deviation, the first pulse width modulation signal Pw1 and the second pulse width modulation are calculated. The pulse width of the signal Pw2 is corrected and output as the first pulse width correction signal Sv1 and the second pulse width correction signal Sv2.

  The second pulse width correction circuit SV2 calculates a deviation between the second DC voltage Ar2 and the average reference voltage Ea, and based on the value of the deviation, the first pulse width modulation signal Pw1 and the second pulse width modulation are calculated. The pulse width of the signal Pw2 is corrected and output as a third pulse width correction signal Sv3 and a fourth pulse width correction signal Sv4.

  The first inverter drive circuit SD1 outputs a first switching element drive signal Tr1 and a fourth switching element drive signal Tr4 according to the first pulse width correction signal Sv1, and according to the second pulse width correction signal Sv2. The second switching element drive signal Tr2 and the third switching element drive signal Tr3 are output.

  The second inverter drive circuit SD2 outputs a fifth switching element drive signal Tr5 and an eighth switching element drive signal Tr8 according to the third pulse width correction signal Sv3, and according to the fourth pulse width correction signal Sv4. The sixth switching element drive signal Tr6 and the seventh switching element drive signal Tr7 are output.

  FIG. 2 is a waveform timing chart for explaining the operation of the embodiment of the present invention. In FIG. 2, the waveform of FIG. 2A shows the first pulse width modulation signal Pw1, the waveform of FIG. 2B shows the second pulse width modulation signal Pw2, and the waveform of FIG. The ON time of the first switching element TR1 and the fourth switching element TR4 (not shown) is shown. The waveform in FIG. 4D shows the ON time of the second switching element TR2 and the third switching element TR3 (not shown). (E) shows the first DC voltage Ar1, the waveform (F) shows the first pulse width correction signal Sv1, and the waveform (G) shows the second pulse. The width correction signal Sv2 is shown, the waveform of FIG. 9H shows the ON time of the fifth switching element TR5 and the eighth switching element TR8 (not shown), and the waveform of FIG. TR6 and seventh switch on not shown The ON time of the element TR7 is shown, the waveform in FIG. 10J indicates the second DC voltage Ar2, the waveform in FIG. 10K indicates the third pulse width correction signal Sv3, and the waveform in FIG. The waveform indicates the fourth pulse width correction signal Sv4.

  A major factor of the current variation in parallel operation is a variation in the ON period of each inverter circuit, and this makes it impossible to balance the output currents of the N main circuits provided in parallel. Therefore, in the present invention, the output voltage on the secondary side of each main transformer is detected, the average output voltage is obtained by averaging the plurality of output voltages, and the average output voltage and the output voltage of each main transformer are When the pulse width of the pulse width modulation signal for controlling each inverter circuit is corrected so as to be substantially the same, variation in the ON period of each inverter circuit is suppressed, and the output currents of the two main circuits provided in parallel are substantially reduced. It becomes equilibrium.

The above operation will be described in detail with reference to the waveform timing chart of FIG.
When the start signal Ts is output from the start switch TS shown in FIG. 1, the pulse width modulation circuit PW is determined based on the deviation between the total output current detection signal Id and the output current setting signal Ir, as shown in FIG. A first pulse width modulation signal Pw1 having a pulse width time T1 is output.

  When the first pulse width modulation signal Pw1 shown in FIG. 2A is input to the first pulse width correction circuit SV1 at time t = t1 shown in FIG. 2, the first pulse width correction circuit SV1 The first pulse width modulation signal Sv1 shown in FIG. 4F is set to High in response to the High of the first pulse width modulation signal Pw1, and the first pulse width modulation signal Pw1 is a second pulse width correction circuit. Also input to SV2, the second pulse width correction circuit SV2 sets the third pulse width correction signal Sv3 shown in (K) to High in accordance with the High of the first pulse width modulation signal Pw1.

  When the first pulse width modulation signal Pw1 shown in FIG. 2A becomes Low at time t = t2 shown in FIG. 2, the first pulse width correction circuit SV1 changes to Low of the first pulse width modulation signal Pw1. Accordingly, the first pulse width correction signal Sv1 is set to Low, and the second pulse width correction circuit SV2 also sets the second pulse width correction signal Sv2 to Low according to the Low of the first pulse width modulation signal Pw1. .

  However, the first switching element TR1 and the fourth switching element TR4 are turned off due to variations in the components forming the first inverter drive circuit SD1 and the gate capacitances of the first switching element TR1 and the fourth switching element TR4. Is delayed, the first switching element TR1 and the fourth switching element TR4 are turned on for the time T2 shown in FIG. 2C, and are turned off at time t = t4.

  Further, the fifth switching element TR5 and the eighth switching element TR8 are turned off due to variations in the components forming the second inverter drive circuit SD2 and the gate capacitances of the fifth switching element TR1 and the eighth switching element TR8. And the fifth switching element TR5 and the eighth switching element TR8 are turned on at time T5 shown in FIG. 5H, and are turned off at time t = t3.

  When the second pulse width modulation signal Pw2 shown in FIG. 2B is input to the first pulse width correction circuit SV1 at time t = t5 shown in FIG. 2, the first pulse width correction circuit SV1 The second pulse width correction signal Sv2 shown in FIG. 5G is set to High in accordance with the High of the second pulse width modulation signal Pw2, and the second pulse width modulation signal Pw2 is a second pulse width correction circuit. Also input to SV2, the second pulse width correction circuit SV2 sets the fourth pulse width correction signal Sv4 shown in FIG. 5L to High in accordance with the High of the second pulse width modulation signal Pw2.

  When the second pulse width modulation signal Pw2 shown in FIG. 2B becomes Low at time t = t6 shown in FIG. 2, the first pulse width correction circuit SV1 changes to Low of the second pulse width modulation signal Pw2. Accordingly, the second pulse width correction signal Sv2 is set to Low, and the second pulse width correction circuit SV2 also sets the fourth pulse width correction signal Sv4 to Low according to the Low of the second pulse width modulation signal Pw2. .

  However, the second switching element TR2 and the third switching element TR3 are turned off due to variations in the components forming the second inverter drive circuit SD1 and the gate capacitances of the second switching element TR2 and the third switching element TR3. , The second switching element TR2 and the third switching element TR3 are turned on at time T2 shown in FIG. 2D, and are turned off at time t = t8.

  Further, the sixth switching element TR6 and the seventh switching element TR7 are turned off due to variations in the components forming the second inverter drive circuit SD2 and the gate capacitances of the sixth switching element TR6 and the seventh switching element TR7. , The sixth switching element TR6 and the seventh switching element TR7 are turned on at time T5 shown in FIG. 11I, and are turned off at time t = t7.

  Next, at time t = t8, the first pulse width correction circuit SV1 calculates a positive deviation value by obtaining the deviation between the first DC voltage Ar1 and the average reference voltage Ea in FIG.

  When the first pulse width modulation signal Pw1 shown in FIG. 2A is input to the first pulse width correction circuit SV1 at time t = t9, the first pulse width correction circuit SV1 The first pulse width correction signal Sv1 shown in FIG. 4F is set to High in accordance with the High of the width modulation signal Pw1. Then, based on the positive deviation value, correction is performed so that the ON time of the first pulse width correction signal Sv1 is shortened to T4. At time t = t10, the first pulse width correction signal Sv1 is set to Low, and predetermined At time t = t11 when the time has elapsed, the first pulse width modulation signal Pw1 becomes Low.

  The ON times of the first switching element TR1 and the fourth switching element TR4 are determined according to the corrected first pulse width correction signal Sv1, and the ON time of T3 shown in FIG. Turns off at t13.

  At time t = t8, the second pulse width correction circuit SV2 calculates a negative deviation value by obtaining the deviation between the second DC voltage Ar2 and the average reference voltage Ea in FIG.

  At time t = t9, when the first pulse width modulation signal Pw1 shown in FIG. 2A is input to the second pulse width correction circuit SV2, the second pulse width correction circuit SV2 The third pulse width correction signal Sv3 shown in FIG. 5K is set to High according to the High of the width modulation signal Pw1. Then, based on the negative deviation value, correction is performed so that the ON time of the third pulse width correction signal Sv3 is increased to T6, and the third pulse width correction signal Sv3 is set to Low at time t = t12.

  The ON time of the fifth switching element TR5 and the eighth switching element TR8 is determined according to the corrected third pulse width correction signal Sv3, and the ON time of T3 shown in FIG. Turns off at t13.

  When the second pulse width modulation signal Pw2 shown in FIG. 2B is input to the first pulse width correction circuit SV1 at time t = t14, the first pulse width correction circuit SV1 receives the second pulse. The second pulse width correction signal Sv2 shown in FIG. 4G is set to High in accordance with the High of the width modulation signal Pw2. Then, correction is performed so that the ON time of the second pulse width correction signal Sv2 is shortened to T4 based on the positive deviation value, and at time t = t15, the second pulse width correction signal Sv2 is set to Low, and predetermined At time t = t16 when the time has elapsed, the second pulse width modulation signal Pw2 becomes Low.

  The ON time of the second switching element TR2 and the third switching element TR3 is determined according to the corrected second pulse width correction signal Sv2, and the ON time of T3 shown in FIG. Turns off at t16.

  When the second pulse width modulation signal Pw2 shown in FIG. 2B is input to the second pulse width correction circuit SV2 at time t = t14, the second pulse width correction circuit SV2 receives the second pulse. The fourth pulse width correction signal Sv4 shown in FIG. 10K is set to High in accordance with the High of the width modulation signal Pw2. Then, correction is performed so that the ON time of the fourth pulse width correction signal Sv4 is increased to T6 based on the negative deviation value, and the fourth pulse width correction signal Sv4 is set to Low at time t = t17.

  The ON time of the sixth switching element TR6 and the seventh switching element TR7 is determined according to the corrected fourth pulse width correction signal Sv4, and the ON time of T3 shown in FIG. Turns off at t18. At this time, the ON times of the first to eighth switching elements forming each inverter circuit are substantially the same.

  With the above correction, at time t = t18, the first DC voltage Ar1 and the second DC voltage Ar2 become substantially the same, and the correction ends. After time t = t18, the first DC voltage Ar1 and the second DC voltage Ar2 The DC voltage Ar2 is substantially the same, the output currents of the inverter circuits provided in parallel are substantially balanced, and parallel operation is possible without using a plurality of expensive output current detection circuits.

  FIG. 3 shows an arc machining power supply apparatus according to the second embodiment (for example, two main circuits are provided in parallel). In the figure, components having the same reference numerals as those in the electrical connection diagrams of the arc machining power supply device shown in FIGS. 1 and 4 perform the same operations, and thus the description thereof will be omitted, and only components having different reference numerals will be described.

  The first output voltage detection circuit VD1 detects the AC output voltage of the secondary auxiliary winding of the first main transformer INT1, outputs it as the first output voltage detection signal Vd1, and detects the second output voltage detection The circuit VD2 detects the AC output voltage of the secondary auxiliary winding of the second main transformer INT2 and outputs it as the second output voltage detection signal Vd2. Thereafter, the same operation as described above is performed, and thus the description thereof is omitted.

It is an electrical connection diagram of the power supply device for arc machining of Embodiment 1 of this invention. It is a waveform timing diagram for demonstrating the operation | movement of this invention shown in FIG. FIG. 5 is an electrical connection diagram of the arc machining power supply device according to the second embodiment. It is an electrical connection figure of the power supply apparatus for arc processing of a prior art.

Explanation of symbols

AR1 first output voltage rectifier circuit AR2 second output voltage rectifier circuit AR3 third output voltage rectifier circuit C1 smoothing capacitor DR1 primary rectifier circuit DR2 first secondary rectifier circuit DR3 second secondary rectifier circuit DR4 second 3 secondary rectifier circuit DCL1 first DC reactor DCL2 second DC reactor DCL3 third DC reactor EA average reference voltage circuit ID total output current detection circuit ID1 first output current detection circuit ID2 second output current detection Circuit Id Total output current detection signal Id1 First output current detection signal Id2 Second output current detection signal IR Output current setting circuit Ir Output current setting value INT1 First main transformer INT2 Second main transformer INT3 Third Main transformer M Workpiece PW Pulse width modulation circuit PWI Current corresponding pulse width modulation circuit Pw1 Width modulation signal Pw2 second pulse width modulation signal Pw3 third pulse width modulation signal Pw4 fourth pulse width modulation signal SV1 first pulse width correction circuit SV2 second pulse width correction circuit Sv1 first pulse width Correction signal Sv2 Second pulse width correction signal Sv3 Third pulse width correction signal Sv4 Fourth pulse width correction signal SD1 First inverter drive circuit SD2 Second inverter drive circuit TH Torch TS Start switch Ts Start signal TR1 First 1 switching element TR2 2nd switching element TR3 3rd switching element TR4 4th switching element TR5 5th switching element TR6 6th switching element TR7 7th switching element TR8 8th switching element Tr1 1st switching Element drive signal Tr2 Second switch Switching element driving signal Tr3 Third switching element driving signal Tr4 Fourth switching element driving signal Tr5 Fifth switching element driving signal Tr6 Sixth switching element driving signal Tr7 Seventh switching element driving signal Tr8 Eighth switching element driving signal VD1 First Output voltage detection circuit VD2 Second output voltage detection circuit

Claims (4)

  A primary rectifier circuit that rectifies a commercial AC power supply and outputs a DC voltage, a smoothing capacitor that is provided in parallel with the primary rectifier circuit and smoothes the DC voltage, and a first inverter that converts the DC voltage into a high-frequency AC voltage Circuit, a first main transformer for converting the output of the first inverter circuit into a high-frequency AC voltage suitable for a predetermined load, and a first secondary for rectifying the output power of the first main transformer A rectifier circuit; a first DC reactor that smoothes the rectified output power and outputs the output power to an output terminal; and an inverter circuit, a main transformer, a secondary rectifier circuit, and a DC reactor between the smoothing capacitor and the output terminal (N-1) main circuits formed by connecting in series, a total output current detection circuit for detecting the total output current of the main circuit and outputting it as a total output current detection signal, and a predetermined output Current setting signal An output current setting circuit to be set, and pulse width modulation for modulating the pulse width of the first pulse width modulation signal and the second pulse width modulation signal based on the deviation between the total output current detection signal and the output current setting signal A first output voltage detection circuit for detecting an output voltage of the first main transformer to an Nth output voltage detection circuit for detecting an output voltage of the Nth main transformer; A first output voltage rectifier circuit that rectifies an output voltage and outputs it as a first DC voltage to an Nth output voltage rectifier circuit that rectifies the Nth output voltage and outputs it as an Nth DC voltage; An average reference voltage circuit that calculates an average of the DC voltage to the Nth DC voltage and outputs the average as the average reference voltage, and the first DC voltage and the average reference voltage are substantially equal to each other. Pulse width modulation signal and second pulse width variation The first pulse width correction circuit that corrects the pulse width of the signal and outputs it as the first pulse width correction signal and the second pulse width correction signal, and the values of the Nth DC voltage and the average reference voltage are substantially the same. The pulse widths of the first pulse width modulation signal and the second pulse width modulation signal are corrected so as to become the (2N-1) th pulse width correction signal and the (2N) pulse width correction signal. N pulse width correction circuits, a first inverter driving circuit for driving the first inverter circuit in accordance with the first pulse width correction signal and the second pulse width correction signal, through the (2N-1) th to (2N-1) th inverter circuits. An inverter power supply apparatus comprising: an Nth inverter drive circuit that drives the Nth inverter circuit in response to a pulse width correction signal and a (2N) th pulse width correction signal.   The correction of the pulse width of the pulse width modulation signal is to calculate a deviation between the average reference voltage and the DC voltage, and when the deviation value is positive, the pulse width is shortened based on the positive value, and the deviation The inverter power supply device according to claim 1, wherein when the value of is negative, the pulse width is lengthened based on the negative value.   The first output voltage detection circuit to the Nth output voltage detection circuit are formed by providing an auxiliary winding on the secondary side of the first main transformer to the Nth main transformer. The inverter power supply device according to claim 1 or 2.   An arc machining power supply device, wherein the output voltage of the inverter power supply device according to any one of claims 1 to 3 is converted into an arc machining voltage suitable for an arc load.

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