JP5048350B2 - Memory device - Google Patents

Description

  The present invention relates to a memory device using a circuit using a superconductor and a method for manufacturing the same.

  Conventionally, semiconductor materials have been mainly used for devices (memory) that are mounted on network devices and information terminals and store information. As one of the memories using a semiconductor, a DRAM (Dynamic Random Access Memory) is widely used (see Non-Patent Document 1). A unit storage element (hereinafter referred to as a memory cell) of a DRAM is composed of one storage capacitor and one MOSFET (Metal-oxide-semiconductor field effect transistor), and the charge stored in the storage capacitor of the selected memory cell. The voltage corresponding to the state is taken out as “on” or “off” of the electrical digital signal from the bit line, so that the stored data is read out.

  However, in the DRAM, when the power is turned off, it is impossible to maintain the state of the storage capacity, and the stored information is erased. In other words, DRAM is a volatile memory element. As is well known, a DRAM requires a refresh operation for rewriting data, and has a drawback that the operation speed is reduced.

  In order to realize the recent expansion of the multimedia information society, and further to realize ubiquitous services, more sophisticated memories are required. For example, the functions required of the memory installed in ubiquitous terminals include high speed, long-term retention period, environmental resistance, low power consumption, and non-volatility that keeps stored information even when the power is turned off. It is said that. ROM (Read only Memory) is well known as a non-volatile memory, but once stored (written) data cannot be erased, and has a major disadvantage that it cannot be rewritten. Yes.

  On the other hand, although it is a kind of ROM, a flash memory using an EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing and writing a limited number of times has been developed (patent) Reference 1, Non-patent document 1, Non-patent document 2). This flash memory is used in many fields as a practical non-volatile memory.

  In a memory cell of a typical flash memory, a gate electrode portion of a MOSFET has a stack gate structure including a plurality of layers each having a control gate electrode and a floating gate electrode. In the flash memory, data can be recorded by utilizing the fact that the threshold value of the MOSFET changes depending on the amount of charge accumulated in the floating gate.

  Writing data in the flash memory is performed by hot carriers generated by applying a high voltage to the drain region overcoming the energy barrier of the gate insulating film. In addition, data is written by injecting electric charges (generally electrons) from the semiconductor substrate to the floating gate by applying a high electric field to the gate insulating film to flow an FN (Fowler-Nordheim) tunnel current. Is done. Data is erased by extracting charges from the floating gate by applying a high electric field in the opposite direction to the gate insulating film.

  A flash memory does not require a refresh operation like a DRAM, but requires a high voltage of about 18 V in order to use the FN tunnel phenomenon, and the time required for writing and erasing data is orders of magnitude higher than that of a DRAM. There is a problem of becoming longer. Further, when data writing / erasing is repeated, the gate insulating film deteriorates, so that the number of rewrites is limited to some extent.

  On the other hand, in the vice field where high performance is required, further low power consumption operation and high-speed switching operation are required. In order to realize these, a memory device using a digital circuit using a superconductor has been proposed (see Non-Patent Document 3).

  Superconductivity is a phenomenon that occurs in metals or oxides in an ultra-low temperature environment, and is called in this way because its electric resistance becomes zero. A substance that causes a superconducting phenomenon is called a superconductor, and a current that flows in a superconducting state is called a superconducting current. In 1911, it was first reported by Heike Camerling Neos (Netherlands) that the electrical resistance of mercury would be zero at 4.2K. Since this discovery, many superconducting elements and materials have been discovered. A single element having the highest superconducting transition temperature is niobium, and this superconducting transition temperature is 9.3 K (under atmospheric pressure and atmospheric pressure).

  Although many metals exhibit superconductivity under normal pressure, some metals or nonmetallic elements that do not exhibit superconductivity under normal pressure may exhibit superconductivity under high pressure (in the case of nonmetal, simultaneously with metallization). In addition, superconductivity in heavy electron systems, high-temperature superconductivity, and materials that coexist with ferromagnetism and superconductivity have been discovered that have different characteristics from conventional superconductors. The basic mechanism of the superconducting phenomenon has been elucidated by the theory (BCS theory) of John Bardin, Leon Cooper, and Robert Shelleyfer, published in 1957.

  With regard to the superconducting phenomenon, much research has been actively conducted even now, nearly 100 years after its discovery, focusing on searching for substances that cause superconductivity at higher temperatures. However, a large-scale and high-speed memory device using a superconductor material has not been realized. This lack of memory elements has been a major impediment to the realization of practical superconductor digital circuits.

  Several attempts have been made to realize a memory device using a superconductor. A typical example is an application of a superconducting quantum interface device (SQUID). Since the SQUID can store a perpetual current and a flux quantum, it is applied as a memory (see Non-Patent Documents 4 and 5). However, there is a problem that it is difficult to create a large-scale memory because there is a limit to the miniaturization of the cell size in order to handle magnetic flux quanta and the technology for creating SQUID is not easy. Yes.

  There are also attempts to realize a memory device using a superconductor by combining it with other memory technologies. One example is a memory device that combines a Josephson Junction and a CMOS (Complementary Metal-Oxide Semiconductor) (see Non-Patent Document 6). However, it is not easy to operate a CMOS at an extremely low temperature, and it has not been realized yet.

  In addition, there are some which are intended to be realized by combining a nonvolatile memory operating at room temperature and a Josephson junction (see Non-Patent Document 7 and Non-Patent Document 8). In the technique shown in Non-Patent Document 7, a ferromagnetic memory (Magnetoresist RAM: MRAM) using a ferromagnetic reluctance is used for controlling a superconducting single flux quantum (SFQ). Yes.

  In addition, as shown in FIG. 17, one using SFQ hybrid RAM / superconducting latching has been proposed (see Patent Document 2, Patent Document 3, and Non-Patent Document 5). There is also a report of application to random access memory (see Patent Document 4).

JP-A-8-031960 JP 2000-260187 A Japanese Patent Application Laid-Open No. 10-269883 Japanese Patent Laid-Open No. 10-15497 Simon G., Physics of Semiconductor Devices, 1981 (S.M.Sze, "Physics of Semiconductor Devices", John Wiley and Sons, Inc.) Fujio Tsujioka, “Current Status and Prospects of Non-Volatile Memory”, Applied Physics, Vol. 73, No. 9, pp. 1166-1171, 2004. S. Yoruzu, et al., "Progress of Single Flux Quantum Packet Switch Technology", IEEE Transactions on Applied Superconductivity, Vol.15, No.2, pp411-414, 2005. S. Nagasawa et al., "A 380 ps, 9.5mW Josephson 4-Kbit RAM Operated at a High Bit Yield", IEEE Transactions on Applied Superconductivity, Vol.5, No.2, pp2447-2452, 1995. S. Nagasawa, et al., "Superconducting Lctching / SFQ Hybrid RAM", IEEE Transactions on Applied Superconductivity, Vol.11, No.1, pp533-536, 2001. U.Ghoshal, et al., "SUPERCONDUCTR-SEMCONDUCTOR MEMORIES", IEEE Transactions on Applied Superconductivity, Vol.3, No.1, pp2315-2318,1993. T. Van Duzer, "Cryogenic Memories for RSFQ Ultra-High-Speed Processor", Proceedings of the 2005 ACM / IEEE Supercomputing Conference, pp 66-68, 2005. KKLikharev, et al., "RSFQ Logic / Memory Family: A New Josephson-Junction Technology for Sub-Teraherz-Clock-Frequency Digital Systems", IEEE Transactions on Applied Superconductivity, Vol.1, No.1, pp3-28, 1991. M. Yamaguchi, et al., "Effect of Grain Size on Bi4Ti3O12 Thin Film Properties", Jpn. J. Appl. Phys. Vol. 37, pp. 5166-5170, 1998.

However, since the MRAM described above is difficult to integrate itself, and the MRAM is used only for selection of the cell array, it has not yet reached a solution for high integration.
As described above, in the conventional technology, it is not easy to highly integrate a superconducting digital circuit, and it is far from realizing a memory device using a digital circuit using a superconductor.

  The present invention has been made to solve the above problems, and an object of the present invention is to realize a memory device for a superconducting digital circuit capable of storing and holding data at a higher density in a stable state.

A memory device according to the present invention includes an input terminal and an output terminal, a first coil and a second coil connected in series between the input terminal and the output terminal, a first voltage terminal to which a predetermined voltage is applied, and an input A first resistor connected between the terminal and the first connection node between the first coil, a first Josephson junction connected to the first connection node, a second voltage terminal to which a predetermined voltage is applied, A second resistor connected between the first coil and the second connection node between the second coil, a second Josephson junction connected to the second connection node, and a third voltage terminal to which a predetermined voltage is applied. And a third resistor connected to the third connection node between the second coil and the output terminal, and a third Josephson junction connected to the third connection node, wherein the second resistor is Bi ₄ Ti _3. containing excess Ti as compared to the stoichiometric composition of O ₁₂ A base layer in an amorphous state, and a metal oxide layer composed of a plurality of fine particles having a stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ in the base layer, and the metal oxide layer is applied The resistance value changes depending on the electrical signal.

  Therefore, when the resistance state of the metal oxide layer changes, the state of the current input to the second Josephson junction changes according to the voltage applied to the second voltage terminal. Here, if the sum of the current value due to the signal input from the input terminal and the current input to the second Josephson junction due to the voltage applied to the second voltage terminal is smaller than a predetermined value, the second Josephson The superconducting state of the junction is maintained. For this reason, when the resistance state of the metal oxide layer changes and the total current becomes smaller than a predetermined value, the superconducting state of the second Josephson junction is maintained, and the signal input from the input terminal is It flows through the Josephson junction, does not flow through the second coil, and is not output from the output terminal.

In the memory device, the input terminal is input with the same input current as that of the single flux quantum in the form of a triangular wave .

In the memory device, the metal oxide layer is in a first state having a first resistance value when a voltage exceeding the first voltage value is applied, and when a voltage exceeding a second voltage value having a polarity different from that of the first voltage is applied. The second state has a second resistance value higher than the first resistance value. Further, the fine particles may be those analyzed to be amorphous by X-ray diffraction .

In the above memory device, the metal oxide layer may be any one which is formed below 30 ° C. or higher 180 ° C. by sputtering.

As described above, according to the present invention, the second resistor connected between the second voltage terminal to which a predetermined voltage is applied and the second connection node between the first coil and the second coil is Bi. ₄ Ti ₃ O ₁₂ in the stoichiometric base layer in the amorphous state containing excess Ti as compared to the composition, and a plurality of the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ in said base layer A superconducting digital circuit that consists of a metal oxide layer composed of fine particles , and the metal oxide layer has a resistance value that changes according to an applied electrical signal, so that memory can be stored at a higher density in a stable state. Therefore, an excellent effect can be obtained that a memory device can be easily realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit showing a configuration of a memory device according to an embodiment of the present invention. The equivalent circuit shown in FIG. 1 is a circuit similar to a general Josephson Transmission Line (JTL), but the resistance R ₃ (= R _M ) in the circuit is a material that exhibits a resistance change phenomenon. It is completely different that it consists of For JTL, refer to Non-Patent Document 8.

In FIG. 1, V ₁ , V ₂ , V ₃ , V ₄ and V ₅ are power supplies, and JJ ₁ , JJ ₂ , JJ ₃ , JJ ₄ and JJ ₅ are Josephson junctions. L ₁₂ , L ₂₃ , L ₃₄ and L ₄₅ are coils, and R ₁ , R ₂ , R ₃ (= R _M ), R ₄ and R ₅ are resistors, and T ₁ , T ₂ , T ₃ , T ₄ , and T ₅ are voltage terminals to which a voltage generated from a voltage source (not shown) is supplied.

In this memory device, coils L ₁₂ , L ₂₃ , L ₃₄ , and L ₄₅ are connected in series between an input terminal T _in and an output terminal I _in . The first resistor R ₁ is connected between a connection node between the voltage terminals T ₁ and the input terminal T _in and the coil L ₁₂ to which a predetermined voltage is applied, the Josephson junction JJ ₁ to the connection node Connected. Josephson junction JJ ₁ is connected between the ground and the connection node. A resistor R ₂ is connected between a voltage terminal T ₂ to which a predetermined voltage is applied and a connection node between the coil L ₁₂ and the coil L ₂₃ , and a Josephson junction JJ ₂ is connected to the connection node. Yes. Josephson junction JJ ₂ is also connected between ground and the connection node.

Further, a resistor R _M (second resistor) is connected between the voltage terminal T ₃ to which a predetermined voltage is applied and a connection node (second connection node) between the coil L ₂₃ and the coil L _34. A Josephson junction JJ ₃ (third Josephson junction) is connected to the node. Josephson junction JJ ₃ is also connected between ground and the connection node. Further, a resistor R ₄ is connected between a voltage terminal T ₄ to which a predetermined voltage is applied and a connection node between the coil L ₃₄ and the coil L ₄₅ , and a Josephson junction JJ ₄ is connected to this connection node. Yes. Josephson junction JJ ₄ is also connected between ground and the connection node. A resistor R ₅ is connected between a voltage terminal T ₅ to which a predetermined voltage is applied and a connection node between the coil L ₄₅ and the output terminal T _out , and a Josephson junction JJ ₅ is connected to this connection node. ing. Josephson junction JJ ₅ is also connected between ground and the connection node.

In the equivalent circuit shown in FIG. 1, an input current I _in is input from the input terminal T _in . At this time, the input current I _in is in the form of a triangular wave and is the same as the single flux quantum (SFQ). If this SFQ can pass through each of the Josephson junctions JJ ₁ , JJ ₂ , JJ ₃ , JJ ₄ , JJ ₅ , an output signal having the same magnitude as the input SFQ appears at the output terminal T _out shown. . By controlling the flow of SFQ from the input terminal T _in to the output terminal T _out described above, a memory function can be provided by setting a state where an output signal can be obtained or a state where an output signal cannot be obtained. it can. Specifically, the resistance R _M (R ₃ ) is realized by forming a material that exhibits a resistance change phenomenon.

Resistor R _M is a high-resistance state (High-Resistance State: HRS) and the low resistance state: with two states (Low-Resistance State LRS). Although this state will be specifically described later, the resistance value is repeatedly increased and decreased by an external electric signal (DC voltage, pulse voltage, etc.). In other words, the resistance R _M is a HRS and LRS is a controllable elements by an external electric signal.

For the circuit shown in FIG. 1 for controlling the SFQ, when the resistance state of the resistance R _M of LRS, the same resistance value as the other resistors R1, R2, R4, R5. The resistance state of the resistance R _M is the case of HRS, several orders of magnitude greater than the resistance value when the LRS. Therefore, the resistance R _M of the resistance value R _M of the time of _{HRS, HRS,} the resistance value R _M of the resistor R _M during _LRS, when the _{LRS, R M, HRS >> R} M, LRS = R 1 = R The formula ₂ = R ₄ = R ₅ = R holds. When the element is operated, a voltage V ₁ = V ₂ = V ₃ = V ₄ = V ₅ = V generated from a voltage source (not shown) is applied to voltage terminals T ₁ , T ₂ , T ₃ , T ₄ , supplied to the T _5.

  In general, in the superconducting state, a permanent current flows when a small current flows, but it is known that when a current of a certain magnitude or more flows, the superconducting state collapses and becomes a normal state. Yes. The current at which this superconducting state cannot be maintained is called the Josephson critical current. Even if the superconducting state cannot be maintained beyond the Josephson critical current, the superconducting state is restored by setting the current to the Josephson critical current or less again.

Josephson junction JJ ₁ of the equivalent circuit shown in FIG. 1, JJ _2, Josephson critical current of JJ _4, JJ ₅ has a _{V 1 = V 2 = V 3} = V 4 = V 5 = V becomes the voltage, R _{M , LRS} = R ₁ = R ₂ = R ₄ = R ₅ = R current I _B = V / R or less, and the Josephson critical current of Josephson junction JJ ₃ is R _{M, LRS} = R _M = R The current I _BM is designed to be equal to or less than V / R. In other words, the superconducting state is maintained even if the current I _B flows through each of the Josephson junctions JJ ₁ , JJ ₂ , JJ ₄ , and JJ ₅ and the current I _BM flows through the Josephson junction JJ ₃ . However, when SFQ is input to the input terminal T _in this state, that is, a current of I _B + I _in is input to each of the Josephson junctions JJ ₁ , JJ ₂ , JJ ₄ , and JJ _5. When a current of I _BM + I _in is input to the son junction JJ ₃ , it is designed so that the superconducting state cannot be maintained because the current exceeds the Josephson critical current.

First, the resistance state of the resistance R _M is, consider the case of the LRS. Voltages V ₁ = V ₂ = V ₃ = V ₄ = V ₅ = V are supplied from the voltage terminals T ₁ , T ₂ , T ₃ , T ₄ and T ₅ , and R _{M, LRS} = R ₁ = R ₂ = Since R ₄ = R ₅ = R, a current of I _B = V / R flows through Josephson junctions JJ ₁ , JJ ₂ , JJ ₄ , and JJ _5, and since R _{M, LRS} = R _M = R, Joseph A current of I _BM = V / R flows through the son junction JJ ₃ . Since the currents flowing through the Josephson junctions JJ ₁ , JJ ₂ , JJ ₃ , JJ ₄ , and JJ ₅ are less than the Josephson critical current, the superconducting state is maintained.

At this time, from the input terminal T _in, enter the SFQ consisting of a current of the input current I _in. And I _in the SFQ entered by I _B due to the voltage supplied from the voltage terminal T _1, the superconducting state of Josephson junction JJ ₁ can no longer be maintained, Josephson junction JJ ₁ becomes normal state, resistance appear. Then, the SFQ flows through the low-resistance coil L ₁₂ and passes through the Josephson junction JJ ₁ .

SFQ that flows through the Josephson junction JJ ₁ and flows to the coil L ₁₂ is input to the Josephson junction JJ ₂ , but is caused by I _in of the input SFQ and I _B by the voltage supplied from the voltage terminal T _2. The Josephson junction JJ ₂ can no longer maintain the superconducting state, becomes a normal conducting state, and generates resistance. Then, SFQ flows through the coil L ₂₃ having low resistance and passes through the Josephson junction JJ ₂ .

SFQ that flows through the Josephson junction JJ ₂ and flows into the coil L ₂₃ is input to the Josephson junction JJ ₃ , but is caused by I _in of the input SFQ and I _BM due to the voltage supplied from the voltage terminal T _3. The Josephson junction JJ ₃ cannot maintain the superconducting state, becomes a normal conducting state, and generates resistance. Then, SFQ flows through the low-resistance coil L ₃₄ and passes through the Josephson junction JJ ₃ .

SFQ that flows through the Josephson junction JJ ₃ and flows into the coil L ₃₄ is input to the Josephson junction JJ ₄ , but by I _in of the input SFQ and I _B due to the voltage supplied from the voltage terminal T _4. Josephson junction JJ ₄ becomes normally conducting state can not be maintained superconducting state, the resistance is generated. Then, SFQ flows through the coil L ₄₅ having a low resistance and passes through the Josephson junction JJ ₄ .

Finally, SFQ that flows through the Josephson junction JJ ₄ and flows into the coil L ₄₅ is input to the Josephson junction JJ _5, and depends on the input SFQ I _in and the voltage supplied from the voltage terminal T _5. the I _B, Josephson junction JJ ₅ becomes normal state can not be maintained superconducting state, the resistance is generated. Then, the SFQ passes through the Josephson junction JJ ₅ and is output to the output terminal T _out , and as a result, an output signal can be observed at the output terminal T _out . The Josephson junctions JJ ₁ , JJ ₂ , JJ ₃ , JJ ₄ , and JJ ₅ after the SFQ has passed become less than the Josephson critical current and return to the superconducting state. Thus, when the resistance state of R ₃ = R _M is the low resistance state (LRS), when SFQ is input to the input terminal T _in , an output signal is observed at the output terminal T _out .

Next, the resistance state of the resistance R _M is, consider the case of HRS. In this case, the current I _BM flowing through the Josephson junction JJ ₃ is I _BM = R _{M, HRS} , but since R _{M, HRS} >> R _{M, LRS} , V / R _{M, LRS5} >> V / And R _{M, HRS} , and I _BM hardly flows.

At this time, the input terminal T _in, the SFQ consisting current of the input current I _in is input, the I _B due to the voltage supplied from the I _in and the voltage terminal T ₁ of the this SFQ, the Josephson junction JJ ₁ The superconducting state cannot be maintained, and the Josephson junction JJ ₁ becomes a normal conducting state, and resistance is generated. As a result, as described above, the SFQ passes through the Josephson junction JJ ₁ . This also applies to the Josephson junction JJ _2.

However, in the Josephson junction JJ _3, this state is different. As described above, if the resistance state of the resistance R _M is a HRS, because current I _BM is sufficiently small, the current of I _in by SFQ is input I _in + I _BM is also inputted to the Josephson junction JJ ₃ The Josephson junction JJ ₃ maintains the superconducting state. For this reason, the SFQ that has passed through the coil L ₂₃ cannot be passed through the Josephson junction JJ ₃ and is reflected. As a result, an output signal cannot be observed at the output terminal _Tout . Thus, when the resistance state of R ₃ = R _M is the high resistance state (HRS), an output signal cannot be observed at the output terminal T _out even if SFQ is input to the input terminal T _in .

Figure 2 summarizes the relationship between resistance state between the input signal and the output signal of the resistance R _M of the resistance change in the equivalent circuit shown in FIG. If there is no input signal, no output signal is obtained. Entering the input signal, the resistance state of the resistance R _M is the case of the HRS, the output signal is not obtained. First output signal is obtained when the resistance state of the resistance R _M of _{LRS (= R 1 = R 2} = R 4 = R 5). That is, by controlling the resistance state of the resistance R _M, controls the flow of SFQ, can be output to / not but control of the output terminal T _in the signal.

Hereinafter, means for realizing the memory device (circuit) in the present embodiment will be described. A Josephson junction is formed in a superconducting state at a certain temperature or lower. Superconductors include niobium (Nb), which is the simplest element and has the highest superconducting transition temperature, as well as YBa ₂ Cu ₃ O _7-x (YBCO: Y123), Bi ₂ Sr ₂ Ca ₂ discovered in the 1980s. Copper oxide high-temperature superconductors (mostly perovskite structures) such as Cu ₃ O ₁₀ (BSCCO: Bi2233 Visco), La-Ba-Cu-O, and magnesium diboride discovered in this century (MgB ₂ ) and the like.

  On the other hand, materials that exhibit a resistance change phenomenon include manganese oxides such as PrCaMnO, SrTiO doped with a metal element, transition metal oxides such as NiO, TiO, and CuO. The inventors have found this resistance change phenomenon in a bismuth titanate film which is also a ferroelectric. For example, as shown in the cross-sectional view of FIG. 3, a metal oxide layer 104 made of a ferroelectric material that causes the above-described resistance switch phenomenon is sandwiched between a lower electrode layer 103 and an upper electrode 105, and the upper electrode 105 and the lower electrode By applying a voltage between the electrode layer 103 and the resistance value of the metal oxide layer 104 from the high resistance state to the low resistance state, and the phenomenon of switching from the low resistance state to the high resistance state is reversibly stable. Appear in This phenomenon is also called a giant electric field resistance change (Colossal electro-resistance: CER) effect, and RRAM (Resistance RAM, ReRAM) applying this phenomenon has attracted attention as a post-flash memory.

Will be specifically described with reference to FIG resistor R _M which causes a resistance change phenomenon for realizing the circuit of Figure 1. First, the element shown in FIG. 3 will be described. This element includes, for example, a metal oxide layer 104 (resistor R) having a thickness of about 30 to 200 nm formed of an insulating layer 102, a lower electrode layer 103, Bi, Ti, and O on a substrate 101 made of single crystal silicon. _M ), an upper electrode 105 is provided.

  The substrate 101 may be made of any conductive material such as a semiconductor, an insulator, or a metal. When the substrate 101 is made of an insulating material, the insulating layer 102 is not necessary. Further, when the substrate 101 is made of a conductive material, the insulating layer 102 and the lower electrode layer 103 may not be provided. In this case, the substrate 101 made of the conductive material serves as a lower electrode.

The lower electrode layer 103 and the upper electrode 105 may be made of transition metal including noble metals such as platinum (Pt), ruthenium (Ru), gold (Au), and silver (Ag). The lower electrode layer 103 and the upper electrode 105 are made of titanium nitride (TiN), hafnium nitride (HfN), strontium ruthenate (SrRuO ₂ ), zinc oxide (ZnO), tin lead (ITO), lanthanum fluoride (LaF). ₃ ) transition metal nitrides, compounds such as oxides and fluorides, and a composite film in which these are laminated.

The insulating layer 102 includes oxides such as LiNbO ₃ , LiCaAlF ₆ , LiSrAlF ₆ , LiYF ₄ , LiLuF ₄ , which are composed of light metals such as lithium dioxide, beryllium, magnesium, and calcium, including silicon dioxide, silicon oxynitride film, and alumina. , KMgF ₃ and other fluorides may be used. The insulating layer 102 includes scandium, titanium, strontium, yttrium, zirconium, hafnium, tantalum, and transition metal oxides and nitrides including the lanthanum series, or silicates (metal, silicon, oxygen, and the like). Ternary compounds), aluminates containing these elements (ternary compounds of metals, aluminum and oxygen), and oxides and nitrides containing two or more of these elements. Furthermore, a multilayer structure of films made of these insulating materials may be used.

A specific example of the element will be described. For example, the lower electrode layer 103 has a stacked structure of a Ti layer with a thickness of 10 nm and a Pt layer with a thickness of 10 nm, and the metal oxide layer 104 has a Bi ₄ thickness of 30 nm. It is a Ti ₃ O ₁₂ film, and the upper electrode 105 is made of gold. Note that, as described above, the structures of the substrate 101 and the insulating layer 102 are not limited to this, and other materials can be appropriately selected as long as the electrical characteristics are not affected.

  The insulating layer 102, the lower electrode layer 103, the metal oxide layer 104, and the upper electrode 105 described above will be described in detail later, but a metal target or metal can be formed by an ECR sputtering apparatus as shown in FIG. The target may be formed by generating ECR plasma composed of argon gas, xenon gas, oxygen gas, and nitrogen gas with a plasma source, and sputtering using particles in the generated plasma.

  Here, the ECR sputtering apparatus will be described with reference to the schematic cross-sectional view of FIG. The ECR sputtering apparatus shown in FIG. 4 includes a processing chamber 401 and a plasma generation chamber 402 communicating with the processing chamber 401. The processing chamber 401 communicates with an evacuation device (not shown), and the inside of the processing chamber 401 is evacuated together with the plasma generation chamber 402 by the evacuation device.

  The processing chamber 401 is provided with a substrate holder 404 to which the substrate 101 on which a film is to be formed is fixed. The substrate holder 404 is inclined at a desired angle by a rotation mechanism (not shown) and is rotatable. By tilting and rotating the substrate holder 404, it is possible to improve the in-plane uniformity of the film and the step coverage with the material to be deposited. Further, a ring-shaped target 405 is provided in the opening region where the plasma from the plasma generation chamber 402 in the processing chamber 401 is introduced so as to surround the opening region.

  The target 405 is placed in a container 405 a made of an insulator, and the inner surface is exposed in the processing chamber 401. In addition, a high frequency power source 422 is connected to the target 405 via a matching unit 421 so that, for example, a high frequency of 13.56 MHz can be applied. When the target 405 is a conductive material, direct current may be applied. In addition, the target 405 may be not only a circular shape but also a polygonal state as viewed from above.

  The plasma generation chamber 402 communicates with the vacuum waveguide 406, and the vacuum waveguide 406 is connected to the waveguide 408 through a quartz window 407. The waveguide 408 communicates with a microwave generator (not shown). In addition, a magnetic coil (magnetic field forming means) 410 is provided around the plasma generation chamber 402 and at the top of the plasma generation chamber 402. The microwave generator, the waveguide 408, the quartz window 407, and the vacuum waveguide 406 constitute microwave supply means. There is also a configuration in which a mode converter is provided in the middle of the waveguide 408.

The operation example of the ECR sputtering apparatus of FIG. 4 will be described. First, after the processing chamber 401 and the plasma generation chamber 402 are evacuated, Ar gas or Xe gas, which is an inert gas, is introduced from an inert gas introduction unit 411. In addition, a reactive gas is introduced from the reactive gas introduction unit 412 to bring the inside of the plasma generation chamber 402 to a pressure of about 10 ⁻⁵ to 10 ⁻⁴ Pa, for example. In this state, a magnetic field of 0.0875 T (Tesla) is generated from the magnetic coil 410 in the plasma generation chamber 402, and then the plasma generation chamber 402 is passed through the waveguide 408, the quartz window 407, and the vacuum waveguide 406. A 2.45 GHz microwave is introduced into the inside, and an electron cyclotron resonance (ECR) plasma is generated. Note that 1T = 10000 Gauss.

  The ECR plasma forms a plasma flow in the direction of the substrate holder 404 by the divergent magnetic field from the magnetic coil 410. Among the generated ECR plasma, electrons pass through the target 405 by the divergent magnetic field formed by the magnetic coil 410, are extracted toward the substrate 101, and are irradiated onto the surface of the substrate 101. At the same time, positive ions in the ECR plasma are drawn out to the substrate 101 side so as to neutralize the negative charge due to electrons, that is, weaken the electric field, and are irradiated onto the surface of the layer being formed. Thus, while each particle is irradiated, some of the positive ions are combined with electrons to become neutral particles.

  In the thin film forming apparatus of FIG. 4, microwave power supplied from a microwave generation unit (not shown) is once branched in the waveguide 408, and plasma is supplied to the vacuum waveguide 406 above the plasma generation chamber 402. The generation chamber 402 is coupled from the side through a quartz window 407. By doing so, it becomes possible to prevent the scattered particles from adhering to the quartz window 407 from the target 405, and the running time can be greatly improved. In addition, a shutter or the like may be provided between the substrate to be processed and the target 405 to control the arrival of the raw material with respect to the substrate.

Next, an example of a method for manufacturing the element described with reference to FIG. 3 will be described with reference to FIG. First, as shown in FIG. 5 (a), a main surface resistivity plane orientation (100) is 1～2Omu ^- providing a substrate 101 made of cm p-type silicon, over the acid the surface of the substrate 101 It is washed with a mixed solution of hydrogen oxide water, pure water and dilute hydrogen fluoride water, and then dried. Next, the insulating layer 102 is formed on the cleaned and dried substrate 101. In the formation of the insulating layer 102, the above-described ECR sputtering apparatus is used, pure silicon (Si) is used as the target 405, and argon (Ar) and oxygen gas are used as the plasma gas, and the substrate 101 is subjected to ECR sputtering. A metal mode insulating layer 102 made of Si—O molecules is formed to cover the surface.

For example, argon (Ar) gas, which is a rare gas, is supplied at a flow rate of about 20 sccm from the inert gas introduction unit 411 into the plasma generation chamber 402 set to a high vacuum pressure of about 10 ⁻⁴ to 10 ⁻⁵ Pa. Introduced in. Further, an oxygen gas, which is a reactive gas, is inserted from the reactive gas introduction unit 412 at a flow rate of about 5 sccm. In this way, each gas is introduced, and the internal pressure of the ECR sputtering apparatus is set to about 10 ⁻³ to 10 ⁻² Pa. In this state, by supplying a 2.45 GHz microwave (about 500 W) and a 0.0875 T magnetic field to the plasma generation chamber 402 to satisfy electron cyclotron resonance conditions, Ar plasma is generated in the plasma generation chamber 402. Let it be a generated state. Sccm is a unit of flow rate, and indicates that a fluid at 0 ° C. and 1 atm flows 1 cm ³ per minute. T (Tesla) is a unit of magnetic flux density, and 1T = 10000 gauss.

  The plasma generated as described above is emitted from the plasma generation chamber 402 to the processing chamber 401 side by the divergent magnetic field of the magnetic coil 410. Further, a high frequency power of 13.56 MHz (for example, 500 W) is supplied from a high frequency power supply 422 to a target 405 disposed at the outlet of the plasma generation chamber 402. As a result, Ar ions collide with the target 405, causing a sputtering phenomenon, and Si particles pop out. The Si particles that have jumped out of the target 405 reach the surface of the substrate 101 together with the plasma released from the plasma generation chamber 402 and the oxygen gas that has been introduced and activated by the plasma, and are oxidized by the activated oxygen and silicon dioxide. It becomes. As described above, the insulating layer 102 made of silicon dioxide and having a thickness of, for example, about 100 nm can be formed on the substrate 101 (FIG. 5A).

  Note that the insulating layer 102 is insulated so that when a voltage is applied to the lower electrode layer 103 and the upper electrode 105 to be formed later, the voltage does not leak to the substrate 101 and the desired electrical characteristics are not affected. Is. For example, a silicon oxide film formed by oxidizing the surface of a silicon substrate by a thermal oxidation method may be used as the insulating layer 102. The insulating layer 102 only needs to maintain insulating properties, and may be made of an insulating material other than silicon oxide. The thickness of the insulating layer 102 is not limited to 100 nm, and may be thinner or thicker. Also good. The insulating layer 102 is not heated to the substrate 101 in the above-described film formation by ECR sputtering, but the film may be formed while the substrate 101 is heated.

  After the base insulating layer is formed as described above, the substrate is carried out from the apparatus to the atmosphere, and then the lower electrode layer 103 is formed on the formed insulating layer 102 as shown in FIG. Is formed. The lower electrode layer 103 is composed of a titanium layer and a platinum layer, as will be described below. The titanium layer and the platinum layer are formed by using the above-described ECR sputtering apparatus, fixing the substrate 101 to the substrate holder 404 in the processing chamber 401, using pure titanium (Ti) and pure platinum (Pt) as the target 405, and plasma gas The Ti layer and the Pt layer are formed on the Ti layer so as to cover the surface by ECR sputtering using xenon (Xe).

First, the formation of the titanium layer will be described in detail. In the ECR sputtering apparatus described above, first, the inside of the plasma generation chamber 402 is evacuated to a high vacuum state of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the plasma generation chamber 402 is formed. The inert gas introduction unit 411 introduces, for example, Xe gas at a flow rate of 26 sccm, and sets the pressure in the plasma generation chamber 402 to, for example, the order of 10 ⁻¹ to 10 ⁻² Pa. Note that sccm is a unit of flow rate and indicates that 1 cm ³ of fluid at 1 atm flows at 0 ° C. per minute. Further, in the plasma generation chamber 402, a magnetic field of electron cyclotron resonance condition is applied by supplying a coil current to the magnetic coil 410 at, for example, 26A.

  In addition, a 2.45 GHz microwave (for example, 500 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 408, the quartz window 407, and the vacuum waveguide 406. It introduce | transduces in 402, It is set as the state by which the plasma (ECR plasma) was produced | generated in the plasma production | generation chamber 402 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 402 to the processing chamber 401 side by the divergent magnetic field of the magnetic coil 410. Further, high frequency power (for example, 500 W) is supplied from a high frequency power source 422 to a target 405 made of Ti disposed at the outlet of the plasma generation chamber 402. As a result, Xe particles collide with the target 405 to cause a sputtering phenomenon, and Ti particles jump out of the target 405. Ti particles that have jumped out of the target 405 reach the insulating layer 102, whereby Ti is deposited on the insulating layer 102 to form a titanium layer.

  By the Ti deposition by the ECR sputtering method described above, for example, a state in which a titanium layer having a thickness of about 10 nm is formed can be obtained. Thereafter, the film formation is stopped by keeping the above-described shutter closed so that the sputtered raw material does not reach the substrate 101. Thereafter, the plasma irradiation is stopped by stopping the supply of microwave power, the supply of each gas is stopped, the temperature of the substrate 101 is lowered to a predetermined value, and the insulating layer 102 from the inside of the processing chamber 401 is reduced. The substrate 101 on which the titanium layer is formed is unloaded. Note that the thickness of the titanium layer is not limited to 10 nm.

Next, the formation of the platinum layer will be described in detail. In the above-described ECR sputtering apparatus, first, the inside of the plasma generation chamber 402 is evacuated to a high vacuum state of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then plasma generation is performed. For example, Xe gas is introduced at a flow rate of 10 sccm from the inert gas introduction unit 411 into the chamber 402, and the pressure in the plasma generation chamber 402 is set to, for example, about 10 ⁻¹ to 10 ⁻² Pa. Further, in the plasma generation chamber 402, a magnetic field of electron cyclotron resonance condition is applied by supplying a coil current to the magnetic coil 410 at, for example, 26A.

  In addition, a 2.45 GHz microwave (for example, 800 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 408, the quartz window 407, and the vacuum waveguide 406. It introduce | transduces in 402, It is set as the state by which the plasma (ECR plasma) was produced | generated in the plasma production | generation chamber 402 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 402 to the processing chamber 401 side by the divergent magnetic field of the magnetic coil 410. Further, high frequency power (for example, 500 W) is supplied from a high frequency power source 422 to a target 405 made of Pt disposed at the outlet of the plasma generation chamber 402. As a result, Xe particles collide with the target 405 to cause a sputtering phenomenon, and Pt particles jump out of the target 405. The Pt particles that have jumped out of the target 405 reach the titanium layer that has already been formed. As a result, Pt is deposited on the titanium layer to form a platinum layer.

  By depositing Pt by the ECR sputtering method described above, for example, a state in which a platinum layer having a thickness of about 10 nm is formed can be obtained. Thereafter, the film formation is stopped by keeping the above-described shutter closed so that the sputtered raw material does not reach the substrate 101. Thereafter, the plasma irradiation is stopped by stopping the supply of the microwave power, the supply of each gas is stopped, the temperature of the substrate 101 is lowered to a predetermined value, and the upper portion of the titanium layer is The substrate 101 on which the platinum layer is formed is unloaded. The film thickness of the platinum layer is not limited to 10 nm. As a result, a state in which the lower electrode layer 103 made of the titanium layer and the platinum layer formed thereon is formed is obtained (FIG. 5B).

As described above, after the lower electrode layer 103 is formed in a desired thickness, the metal oxide layer 104 is formed on and in contact with the lower electrode layer 103 as shown in FIG. It is assumed that In the formation of the metal oxide layer 104, the substrate 101 is fixed to the substrate holder 404 in the processing chamber 401 using the same ECR sputtering apparatus as described above, and a Bi (Ti) ratio of 4: 3 is used as the target 405. Bi-Ti-O) is used, and the metal oxide layer 104 is formed so as to cover the surface of the lower electrode layer 103 by ECR sputtering using Ar and oxygen (O ₂ ) as plasma gases.

The formation of the metal oxide layer 104 will be described in detail. In the ECR sputtering apparatus described above, first, the inside of the plasma generation chamber 402 is evacuated to a high vacuum state of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the substrate 101 is The plasma generation chamber 402 is heated to 30 ° C. to 700 ° C., and, for example, Ar gas is introduced at a flow rate of 20 sccm from the inert gas introduction unit 411 into the plasma generation chamber 402, and the pressure in the plasma generation chamber 402 is set to 10 ^−2, for example. Set to 10 ^-3 Pa. Further, in the plasma generation chamber 402, a magnetic field of electron cyclotron resonance condition is applied by supplying a coil current to the magnetic coil 410 at, for example, 27A.

  In addition, a 2.45 GHz microwave (for example, 500 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 408, the quartz window 407, and the vacuum waveguide 406. It introduce | transduces in 402, It is set as the state by which the plasma (ECR plasma) was produced | generated in the plasma production | generation chamber 402 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 402 to the processing chamber 401 side by the divergent magnetic field of the magnetic coil 410. Further, high frequency power (for example, 500 W) is supplied from the high frequency power source 422 to the target 405 disposed at the outlet of the plasma generation chamber 402. As a result, Ar particles collide with the target 405 to cause a sputtering phenomenon, and Bi particles and Ti particles jump out of the target 405.

  Bi particles and Ti particles that have jumped out of the target 405 are formed on the surface of the lower electrode layer 103 together with the plasma released from the plasma generation chamber 402 and the oxygen gas introduced from the reactive gas introduction unit 412 and activated by the plasma. It reaches and is oxidized by the activated oxygen. The oxygen gas may be introduced from the reactive gas introduction unit 412 at about 1 sccm, for example. The target 405 is a sintered body and contains oxygen. By supplying oxygen, oxygen deficiency in the deposited film can be prevented. The temperature condition of the substrate 101 may be 30 to 180 ° C. as will be described later.

  By forming the film by the ECR sputtering method described above, for example, a state in which the metal oxide layer 104 with a film thickness of about 30 nm is formed on the lower electrode layer 103 is obtained (FIG. 5B). Thereafter, the film formation is stopped by keeping the above-described shutter closed so that the sputtered raw material does not reach the substrate 101. Thereafter, the plasma irradiation is stopped by stopping the supply of microwave power, the supply of each gas is stopped, the temperature of the substrate 101 is lowered to a predetermined value, and the metal oxide is supplied from the inside of the processing chamber 401. The substrate 101 on which the layer 104 is formed is unloaded.

  Next, as shown in FIG. 5C, the upper electrode 105 made of gold having a predetermined area is formed on the metal oxide layer 104. For example, the upper electrode 105 having a predetermined area can be formed by processing a gold film by patterning using a well-known photolithography technique and etching technique. The upper electrode 105 is not limited to gold, and may be composed of other metal materials such as Ru, Pt, titanium nitride, or conductive materials.

  Next, the metal oxide layer 104 formed by ECR sputtering as described above will be described in more detail. The inventors have found that the film characteristics of the metal oxide layer formed by temperature can be controlled by carefully observing the formation of the metal oxide layer composed of Bi, Ti, and oxygen using the ECR sputtering method. . In this sputtering film formation, an oxide sintered body target formed so that Bi and Ti have a composition of 4: 3 is used.

  The characteristics shown in FIG. 6 show changes in the deposition rate and refractive index with respect to the substrate temperature in the sputter deposition. FIG. 6 shows a case where the film is formed under the same gas conditions as those for forming the metal oxide layer 104 by the ECR sputtering method described above. As shown in FIG. 6, it can be seen that the deposition rate and the refractive index change with temperature.

First, paying attention to the refractive index, the refractive index is as small as about 2 in a low temperature region up to about 250 ° C., and shows amorphous characteristics. In the intermediate region at 300 ° C. to 600 ° C., the refractive index is about 2.6, which is close to the bulk reported in the paper, and it can be seen that the crystallization of Bi ₄ Ti ₃ O ₁₂ is progressing. Regarding these figures, for example, Yamaguchi et al., Japanese Journal Applied Physics, No. 37, pages 5166-5170, 1998 (M. Yamaguchi, et al. “Effect of Grain Size on Bi ₄ Ti ₃ O ₁₂ Thin Film Properties ", Jpn. J. Appl. Phys., 37, pp. 5166-5170, (1998)).

However, in a temperature region exceeding about 600 ° C., the refractive index increases, the surface morphology (surface irregularities) increases, and the crystallinity seems to change. This temperature is lower than the Bi ₄ Ti ₃ O ₁₂ Curie temperature of 675 ° C., but energy is supplied by irradiating the surface of the substrate on which the film is formed with ECR plasma, and the temperature of the substrate surface rises. If crystallinity such as oxygen deficiency is deteriorated, it is considered that there is no contradiction in the above results.

  Looking at the temperature dependence of the deposition rate, the deposition rate increases with temperature up to about 180 ° C. However, the film formation rate rapidly decreases in the region of about 180 ° C. to 300 ° C. When the temperature reaches about 300 ° C., the deposition rate becomes constant up to 600 ° C. The film formation rate in each oxygen region at this time was about 3 nm / min in the oxygen region C.

  Next, the crystallinity of the film formed in each temperature region was analyzed by X-ray diffraction. In a low temperature range from room temperature of about 30 ° C. to 180 ° C., it was confirmed to be amorphous. Further, it was confirmed that the crystal was composed of microcrystals in a temperature range of 180 ° C. to 300 ° C. It was also found that the film was oriented in the (117) direction in the temperature range of 300 ° C. or higher.

  When the cross-sectional shape of the state of the metal oxide layer in the temperature region of 300 ° C. or higher was observed with a transmission electron microscope, the results shown in the configuration diagram of FIG. 7 and the micrograph of FIG. 8 were obtained. In forming the film, a metal oxide composed of Bi, Ti, and oxygen was directly deposited on the silicon substrate 701 at a deposition temperature of 420 ° C.

From the results shown in FIGS. 7 and 8, the metal oxide layer 704 is formed, in the base layer containing excess Ti as compared to the stoichiometric composition of _{Bi 4 Ti 3 O 12, Bi} 4 Ti It was found to be composed of a plurality of fine crystal grains having a stoichiometric composition of ₃ O ₁₂ of about ₃ nm to 15 nm. Electron diffraction on the fine crystal grains confirmed that the fine crystal grains had a (117) plane of Bi ₄ Ti ₃ O ₁₂ .

  Further, detailed observation of the photograph in FIG. 8 revealed the presence of the interface layer 702 and the interface layer 703 at the interface between the metal oxide layer 704 and the silicon substrate 701. It has been confirmed that the interface layer 702 is formed by oxidizing the silicon substrate 701, and the interface layer 703 is formed by reaction of Bi and Ti with silicon.

  Next, characteristics of the metal oxide layer formed at the film forming temperature of about 420 ° C. described above will be described. This characteristic is that an element in which the metal oxide layer is sandwiched between a lower electrode layer and an upper electrode made of Ru is formed, and an appropriate voltage is applied between the lower electrode layer and the upper electrode. It has been investigated. When a voltage was applied between the lower electrode layer and the upper electrode by a power source and the current when the voltage was applied was observed with an ammeter, the result shown in FIG. 9 was obtained. In FIG. 9, the horizontal axis represents the voltage value applied to the upper electrode, and the vertical axis represents the absolute value of the current value in logarithm.

  Hereinafter, the characteristics of the above-described element (metal oxide layer) will be described with reference to FIG. 9, but the voltage value and current value described here are used as an example observed in an actual element. Therefore, this phenomenon is not limited to the following numerical values. Other numerical values may be observed depending on the material and thickness of the film actually used for the element and other conditions. In the following, positive voltage application and negative voltage application are described based on voltage application to the upper electrode. However, when voltage application to the lower electrode layer is used as a reference, there is a relationship between positive and negative. Reverse.

First, when a positive voltage is applied to the upper electrode, as shown in [1] in FIG. 9, in the range of 0 to 0.8 V, for example, +0.5 V is applied, the current is as small as 10 ⁻⁶ A, and high It is a state of resistance. On the other hand, as shown in [2] in FIG. 9, when the applied voltage exceeds 0.8 V, a positive current suddenly flows and a low resistance state is entered. However, when a voltage is applied in the range of 0 to 0.8 V so that a positive current as shown in [2] in FIG. 9 does not flow, a high resistance state as shown in [1] Is maintained.

In addition, when a positive voltage is applied to the upper electrode after the low resistance state as shown in [2] in FIG. 9, a voltage of about 0.5 V is applied as shown in [3] in FIG. A positive current of about 1 × 10 ⁻⁵ A flows. Even if a negative voltage is applied to the upper electrode from this state, a current of about 3 × 10 ⁻⁵ A flows when a voltage of about −0.5 V flows as shown in [4] in FIG. The state of is maintained.

On the other hand, when a negative voltage exceeding −0.8 V is applied to the upper electrode, as indicated by [5] in FIG. 9, current suddenly stops flowing, and the state transitions to the high resistance state. Even after a negative voltage is applied as shown in [6] in FIG. 9 after this state is reached, the current flowing by applying a voltage of -0.5 V is 10 ^-6 A or less, and the high resistance state is maintained. Is done.

In this state, when a positive voltage is applied to the upper electrode, the high resistance state is maintained until a voltage of about + 0.8V is applied as shown in [1] in FIG. 9, but it exceeds + 0.8V. By applying a positive voltage, a transition is made to a low resistance state, as indicated by [2] in FIG.
As described above, according to the element using the above-described metal oxide layer, a phenomenon in which the high resistance state and the low resistance state are switched reversibly is stably observed.

  In addition, the inventors examined the formation of the metal oxide layer by ECR sputtering described above in a sufficiently low temperature range of about 30 to 180 ° C. As shown in FIG. 6, this low temperature region is a region where the refractive index is about 2.0 to 2.1 and the film formation rate is increased by the temperature rise. However, when the substrate temperature is 30 ° C., that is, when the substrate is not heated, the actual temperature of the substrate surface on which the film is formed may rise to about 100 ° C. because the ECR plasma with energy is irradiated. It has been confirmed. However, when the substrate temperature is set to 100 ° C. to 150 ° C., the substrate heating temperature and the plasma heating temperature are approximately the same, and the substrate heating is suppressed by the control of the temperature controller. It becomes about 180 ° C to 180 ° C.

  In this low temperature region, a metal oxide layer made of Bi, Ti, and oxygen was formed on the silicon substrate using ECR sputtering. A cross-sectional observation of the transmission electron microscope at this time is shown in the photomicrograph of FIG. Specifically, the substrate was not heated, and the film was formed using the gas conditions of the metal oxide layer using the ECR sputtering method described above. As shown in FIG. 10, it can be seen that fine particles having a size of 3 nm to 5 nm are present in the formed metal oxide layer despite being deposited without heating the substrate.

As a result of analyzing the composition of the fine particles and the peripheral portion by a technique in which characteristic X-rays generated from the irradiated portion by direct irradiation with an electron beam are directly detected by a semiconductor detector and converted into an electrical signal, the base layer ( Where the particles are not fine particles), Ti is contained more excessively than the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ , and the fine particles contain more Bi than the base layer, and Bi ₄ Ti ₃ it was found close to the stoichiometric composition of O _12. The measured fine particles are very small, 3nm to 5nm, so it is difficult to identify the exact composition by electron diffraction, but the same structure as the base layer and microcrystals observed in the high temperature region above 300 ° C is confirmed. did it.

As described with reference to FIG. 6 described above, the results of XRD, about one formed at a low temperature, it has been confirmed that the amorphous state. It is considered that the fine particles have not been confirmed in such a low temperature film formation, and it was observed because the film was formed by the ECR sputtering method having an appropriate energy of about 10 to 30 eV. When a metal oxide layer composed of Bi, Ti, and oxygen is formed on a silicon substrate in a low temperature region of 30 ° C. to 180 ° C., the interface layer 702 and the interface layer 703 as seen in FIGS. Is not observed. When the film was formed at such a low temperature, the interface between the silicon 1101 and the formed metal oxide layer 1104 was in a good state as shown in the schematic cross-sectional view of FIG.

  Further, the inventors have found that the two resistance states are maintained as described below even in the metal oxide layer composed of Bi, Ti, and oxygen formed in the low temperature region described above. Similar to the above, this characteristic is that an element in which a metal oxide layer formed in a low temperature region is sandwiched between a lower electrode layer and an upper electrode, and an appropriate voltage is applied between the lower electrode layer and the upper electrode. It was investigated by applying. When a voltage was applied between the lower electrode layer and the upper electrode by a power source and the current when the voltage was applied was observed with an ammeter, the result shown in FIG. 12 was obtained. In FIG. 12, the horizontal axis represents the voltage value applied to the upper electrode, and the vertical axis represents the absolute value of the current value in logarithm.

  Hereinafter, the characteristics of the above-described element (metal oxide layer) will be described with reference to FIGS. 12A and 12B. The voltage value and current value described here are also used as an example observed in an actual element. Therefore, this phenomenon is not limited to the following numerical values. Other numerical values may be observed depending on the material and thickness of the film actually used for the element and other conditions. Also, in the following, positive voltage application and negative voltage application are described with reference to voltage application to the upper electrode, but when voltage application to the lower electrode layer is used as a reference, there is a relationship between positive and negative. Reverse.

First, when a positive voltage is applied to the upper electrode, as shown by [1] in FIG. 12, in the range of 0 to 1.7 V, for example, when +0.3 V is applied, the current is as low as 10 ⁻⁶ A or less, and It is a state of high resistance. On the other hand, as shown in [2] in FIG. 12, when the applied voltage exceeds 1.7 V, a positive current suddenly flows and a low resistance state is entered. However, when a voltage is applied in the range of 0 to 1.7 V so that the positive current as shown in [2] in FIG. 12 does not flow, the high resistance state as shown in [1] Is maintained.

Further, when a positive voltage is applied to the upper electrode after the low resistance state as shown in [2] in FIG. 12, a voltage of about 0.1 V is applied as shown in [3] in FIG. A positive current of about 1 × 10 ⁻⁴ A flows. Even if a negative voltage is applied to the upper electrode from this state, a current of about 1 × 10 ⁻³ A flows when a voltage of about −0.5 V flows as shown in [4] in FIG. State is maintained.

On the other hand, when a negative voltage exceeding −0.7 V is applied to the upper electrode, as indicated by [5] in FIG. 12, current suddenly stops flowing, and the state transitions to the high resistance state. Even if a negative voltage is applied as shown in [6] in FIG. 9 after this state is reached, the current that flows when a voltage of about −0.5 V is applied is about 3 × 10 ⁻⁶ A, which is a high resistance. State is maintained.

In this state, when a positive voltage is applied to the upper electrode, the high resistance state is maintained until a voltage of about +1.7 V is applied as shown in [1] in FIG. 12, but it exceeds +1.7 V. By applying a positive voltage, a transition is made to a low resistance state as indicated by [2] in FIG.
As described above, the phenomenon in which the high resistance state and the low resistance state are reversibly switched is also stably observed in the element using the metal oxide layer formed at a low temperature as described above.

  Furthermore, in order to realize the circuit shown in FIG. 1, it is necessary to confirm whether or not the element described with reference to FIG. 3 causes a resistance change phenomenon at a low temperature at which the superconductor state of the superconductor can be maintained. . Therefore, the resistance change phenomenon was observed at a low temperature up to the helium temperature.

  Generally, in the electrical measurement with the measurement temperature changed, a change in contact resistance between the probe and the electrode becomes a problem. This is because each coefficient of thermal expansion is different, and stress or the like changes to cause the contact resistance to fluctuate so that accurate resistance measurement cannot be performed.

  Therefore, the inventors prepared a cross-point type sample element having four terminals 1301, 1302, 1303, and 1304 as shown in FIG. FIG. 13B is an equivalent circuit of the sample element shown in FIG. In this sample element, the metal oxide layer 1340 having the above-described configuration is sandwiched between a lower electrode 1330 including a terminal 1302 and a terminal 1304 and an upper electrode 1350 including a terminal 1301 and a terminal 1303. A power source 1310 and an ammeter 1311 are connected in series between the terminal 1301 and the terminal 1304.

In the equivalent circuit, V ₁ , V ₂ , V ₃ , and V ₄ are voltages at terminals 1301, 1302, 1303, and 1304, and R ₁ , R ₂ , R ₃ , and R ₄ are connected to the terminals. Parasitic resistance associated with each probe, and R _M is the resistance of the metal oxide layer 1340. In addition, the voltage V _B is supplied from the power source 1310. Measuring system using the sample elements of the structure described above is for measuring the resistance R _M of the metal oxide layer 1340 in personality.

In resistance measurement using two general terminals, for example, a voltage is applied to the terminal 1301 and the terminal 1304 in FIG. 13A, and the current is read at the terminal 1301 and the terminal 1304 at the same time. At this time, looking at the equivalent circuit in FIG. 13 (b), because of the parasitic resistor R ₁ and the parasitic resistance R _4, the applied voltage V _B is not only resistance R _M to be measured, the parasitic resistance It is also distributed to R ₁ and parasitic resistance R ₄ . That is, the current I _M observed between the lower electrode 1330 and the upper electrode 1350 is IM = V _B / (R ₁ + R ₄ + R _M ). If the temperature to be measured is changed, it can not be measured accurately R _M to greatly contributes contact resistance to the parasitic resistance largely changes.

For the above measurement, an accurate _RM was determined using the 4-terminal method. That is, a current is passed between the terminal 1301 and the terminal 1304, and a voltage between the terminal 1302 and the terminal 1303 is measured. Resistor R _M voltage V _MI of the previous and the voltage immediately after the V _MO, since the applied voltage V _B is known, determining the resistance is determined from _{R M = V M / (V} MI -V MO). On the other hand, since V _MI = V ₃ and V _MO = V ₂ , R _M = V _M / (V ₃ −V ₂ ), and the resistance R _M is obtained by obtaining the difference between the voltages measured at the terminal 1303 and the terminal 1302. Can be obtained accurately. This method is called the 4-terminal method. Here, V ₃ -V ₂ = V _M, and the sample element voltage.

13 the results of the resistance R _M were measured using a sample element of (a) shown in FIG. 14. A metal oxide layer 1340 made of bismuth, titanium, and oxygen was formed on the lower electrode 1330 made of Ru under the condition of a film forming temperature of 450 ° C. The upper electrode 1350 is also made of Ru. The metal oxide layer 1340 has a thickness of 30 nm, the upper electrode 1350 has a thickness of 20 nm, and the lower electrode 1330 has a thickness of 20 nm. The sample element was cooled by being immersed in liquid helium.

  In FIG. 14, the horizontal axis represents the sample element voltage applied to the upper electrode 1350, and the vertical axis represents the absolute value of the current value measured between the terminal 1303 and the terminal 1302 in logarithm. The measurement was performed at 250K (corresponding to −23 ° C.) and 4.2K (corresponding to −269 ° C.). The results at 250K are indicated by white circles, and the results at 4.2L are indicated by black circles.

  Hereinafter, FIG. 14 will be described. The voltage values and current values described here are those observed with actual elements as an example. Therefore, this phenomenon is not limited to the following numerical values. Other numerical values may be observed depending on the material and thickness of the film actually used for the element and other conditions.

First, when a positive voltage is applied to the upper electrode 1350 during the measurement at 250 K, the current is 10 ⁻⁷ A with respect to +0.1 V and a high resistance state at 0 to 1.9 V with respect to +0.1 V. However, when it exceeds 1.9V, a positive current suddenly flows and a low resistance state is entered. Note that the high resistance state is maintained when a voltage of 0 to 1.9 V is applied so as not to be in a low resistance state where an abrupt positive current flows.

When a positive voltage is applied to the upper electrode 1350 in a low resistance state by applying a positive voltage exceeding 1.9 V, a positive current of about 1 × 10 ⁻³ A flows at about 0.1 V. When a negative voltage is applied to the upper electrode 1350 in this state, a current of about 1 × 10 ⁻³ A flows at about −0.1 V, indicating that the state is a low resistance state. However, when a negative voltage exceeding −0.5 V is applied to the upper electrode 1350, current suddenly stops flowing, and a transition is made to a high resistance state.

After this state is reached, a high resistance state of about 1 × 10 ⁻⁷ A is maintained at −0.1 V even when a negative voltage is applied. Subsequently, when a positive voltage is applied to the upper electrode 1350, it is in a high resistance state up to about + 1.9V, but transitions to a low resistance state by applying a positive voltage exceeding + 1.9V. Hereinafter, a phenomenon in which the high resistance state and the low resistance state are switched reversibly is stably observed.

Next, the sample element was cooled to 4.2 K and measured. First, when a positive voltage is applied to the upper electrode 1350, the current is low at 10 ⁻¹¹ A or less with respect to +0.1 V at 0 to 2.6 V and is in a high resistance state. However, when the applied voltage exceeds 2.6 V, a positive current suddenly flows and a low resistance state is entered. The high resistance state is maintained when a voltage of 0 to 2.6 V is applied so as not to be in a low resistance state where an abrupt positive current flows.

When a positive voltage is applied to the upper electrode 1350 in a low resistance state by applying a positive voltage exceeding 2.6 V, a positive current of about 1 × 10 ⁻³ A flows at about 0.1 V. When a negative voltage is applied to the upper electrode 1350 in this state, a current of about 1 × 10 ⁻³ A flows at about −0.1 V, indicating that the state is a low resistance state. However, when a negative voltage exceeding −0.8 V is applied to the upper electrode 1350, the current suddenly stops flowing, and a transition is made to the high resistance state.

After this state, even if a negative voltage is applied, a high resistance state of about 1 × 10 ⁻¹¹ A is maintained at −0.1V. Subsequently, when a positive voltage is applied to the upper electrode 1350, it is in a high resistance state up to about + 2.6V, but transitions to a low resistance state by applying a positive voltage exceeding + 2.6V. Hereinafter, a phenomenon in which the high resistance state and the low resistance state are reversibly switched can be observed stably.

  As shown above, it should be noted that a stable resistance change phenomenon is observed even at a cryogenic temperature of 4.2K.

  FIG. 15 shows the current ratio at 0.1 V between the high resistance state and the low resistance state when the measurement temperature is changed. This current ratio corresponds to the resistance ratio (On / Off) between the On state and the Off state. FIG. 15 shows that the On / Off ratio was about 4 digits at room temperature (300 K), but the On / Off ratio increased as the temperature was lowered. / Off ratio can be obtained. In other words, it is possible to easily determine the resistance state even when the temperature is lowered, and it is possible to easily determine as the temperature is lowered.

  This indicates that the memory operation of the memory element (metal oxide layer) is possible at a sufficiently low temperature that the superconductor can maintain the superconducting phenomenon. This element is equivalent to the equivalent circuit shown in FIG. This shows that the memory device of this embodiment can be realized.

  Although the manufacturing method and characteristics of the metal oxide layer that exhibits the resistance change phenomenon have been shown, the manufacturing method for realizing the memory device will also be described.

As described above, a superconductor that realizes a superconducting state may be manufactured by using a manufacturing method similar to that of a general Josephson transmission line (JTL). By adding a process for forming a resistance R _M (metal oxide layer) exhibiting a resistance change phenomenon, the memory device according to the present embodiment can be realized.

As described above, the metal oxide layer made of bismuth and titanium exhibiting a resistance change phenomenon can be formed in a temperature range from no heating to around 600 ° C. For this reason, a metal oxide layer can be formed according to the film forming conditions of the superconductor material. Furthermore, as shown in the equivalent circuit of FIG. 1, it is only necessary to place the resistor R _M showing the resistance changing phenomenon in the Josephson transmission line, which is superior in capacity. FIG. 16 shows a configuration diagram of a NOR circuit in the case where the memory device (cell) of this embodiment is integrated in the memory area 1501.

  In this apparatus, an N × N matrix memory array is provided in the memory area 1501, and the SFQ-NOR decoder circuit in the X and Y axis directions, the driver circuit in the X and Y axis directions, the clock circuit, the input terminal, and the output The terminal includes an impedance matching line, an address buffer circuit (not shown), and a data read / write converter circuit (not shown). For example, on the word line selected by the X-axis SFQ-NOR address circuit and applied with a voltage by the X-axis driver circuit, and selected by the Y-axis SFQ-NOR address circuit and applied by the Y-axis driver circuit. The memory state can be sensed by selecting the overlapping memory cell on the bit line and reading the state of the selected memory cell. Similarly, the memory state of the selected memory cell can be changed.

By the way, in the above-described embodiment of the present invention, the bismuth titanate film is used as the metal oxide layer exhibiting a resistance change. However, the present invention is not limited to this, and a layer made of another metal oxide may be used. Good. For example, a material having a perovskite structure, a material having a pseudo-ilmenite structure, a material having a tungsten bronze structure, a material having a bismuth layer structure, or a material having a pyrochlore structure may be used. Specifically, BaTiO ₃ , Pb (Zr, Ti) O ₃ , (Pb, La) (Zr, Ti) O ₃ , LiNbO ₃ , LiTaO ₃ , PbNb ₃ O ₆ , PbNaNb ₅ O ₁₅ , Cd ₂ Nb ₂ O ₇ , Pb ₂ Nb ₂ O ₇ , Bi ₄ Ti ₃ O ₁₂ , (Bi, La) ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O _{9 and the} like.

  Further, in the above-described example of the present invention, the base insulating layer on the substrate made of silicon, the metal thin film, and the ECR sputtering method are used. However, the method for forming each of these layers is not limited to the ECR sputtering method.

  For example, the insulating layer formed on the silicon substrate may be formed by a thermal oxidation method, a chemical vapor deposition (CVD) method, an ALD method, a conventional sputtering method, an MOCVD method, or the like.

  The lower electrode layer may be formed by other methods such as CVD, MBE, IBD, conventional sputtering, and PDL.

  However, a flat and good insulating film and metal film can be easily obtained by using the ECR sputtering method.

  In the above embodiment, after each layer is formed, it is once taken out to the atmosphere. However, the processing chambers for realizing each ECR sputtering may be connected to the vacuum transfer chamber by continuous processing. As a result, the substrate to be processed can be transported in a vacuum, and is less susceptible to disturbances such as moisture, leading to improved film quality and interface characteristics.

  Further, as disclosed in Japanese Patent Application Laid-Open No. 2003-077911, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the characteristics. Further, after each layer is formed, as shown in Japanese Patent Application Laid-Open No. 2004-273730, annealing may be performed in an appropriate gas atmosphere to improve the characteristics.

Also, the thickness of the metal thin film for constituting the electrodes and wirings should be set to an optimal and optimal thickness. For example, in consideration of peeling due to film stress, the metal thin film preferably has a thickness of 100 nm or less. Further, considering the resistance value as the wiring, it is better to make it thicker than 10 nm.
As a result of experiments by the inventors, if the thickness of the metal oxide layer is 10 to 100 nm, the operation of the memory is confirmed, and the best state is when the thickness of the metal oxide layer is 30 nm. Obtained.

  In the above embodiment, the result of using a semiconductor substrate called silicon has been described. However, an insulator such as a glass substrate, a quartz substrate, or a sapphire substrate may be used as a base (substrate). For example, when a glass substrate is used, a hole may be made in the glass substrate and electrical contact may be made from the back surface of the substrate. With this structure, application to a glass substrate that can be easily processed becomes possible.

  Further, an insulating layer may be formed in contact with a conductive substance such as a metal substrate and used as a base. Further, a conductive substance such as a metal substrate may be used as the base.

3 is an equivalent circuit illustrating a configuration of a memory device according to an embodiment of the present invention. It is an explanatory view illustrating a relationship between resistance state between the input signal and the output signal of the resistance R _M of the resistance change in the valence circuit of the memory device in this embodiment. It is a block diagram which shows the structure (cross section) of the element for implement _| achieving resistance RM shown in FIG. It is a block diagram which shows the structure of an ECR sputtering apparatus. It is process drawing which shows the example of the manufacturing method of the element demonstrated using FIG. 3 shows changes in the deposition rate and refractive index of the metal oxide layer with respect to the substrate temperature in sputter deposition. It is a block diagram which shows typically the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is a microscope picture which shows the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is a characteristic view which shows the result of having observed the electric current when an electric current was applied with respect to the metal oxide layer formed in the temperature range of 300 degreeC or more from the upper electrode to the lower electrode layer with the ammeter. It is the microscope picture obtained by the cross-sectional observation by the transmission electron microscope of the metal oxide layer which consists of Bi, Ti, and oxygen formed on the silicon substrate using the ECR sputtering method in a low temperature region of 180 ° C. or lower. It is a block diagram for demonstrating the state of the microscope picture shown in FIG. It is a characteristic view which shows the result of having observed the electric current when an electric voltage was applied with respect to the metal oxide layer formed in the low temperature area | region below 180 degreeC from an upper electrode to a lower electrode layer with an ammeter. It is the top view (a) and equivalent circuit (b) which show the structure of the sample element of the crosspoint type | mold structure produced for the characteristic investigation. Is a characteristic diagram showing the results of a resistor R _M were measured using a sample device of FIG. 13 (a). It is a characteristic view which shows the current ratio at the time of 0.1V of a high resistance state and a low resistance state when changing measurement temperature. It is a block diagram which shows the structure of the NOR type circuit at the time of integrating the memory device (cell) of this Embodiment. 3 is an equivalent circuit showing a configuration of a memory device using SFQ hybrid RAM / superconducting latching.

Explanation of symbols

R ₁ , R ₂ , R ₃ (= R _M ), R ₄ , R ₅ ... Resistor, L ₁₂ , L ₂₃ , L ₃₄ , L ₄₅ ... coil, JJ ₁ , JJ ₂ , JJ ₃ , JJ ₄ , JJ ₅ ... Josephson junction, T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ... voltage terminal, T _in ... input terminal, T _out ... output terminal, 101 ... substrate, 102 ... lower electrode layer, 103 ... lower electrode layer 104 ... Metal oxide layer, 105 ... Upper electrode.

Claims (5)

An input terminal and an output terminal;
A first coil and a second coil connected in series between the input terminal and the output terminal;
A first resistor connected between a first voltage terminal to which a predetermined voltage is applied and a first connection node between the input terminal and the first coil;
A first Josephson junction connected to the first connection node;
A second resistor connected between a second voltage terminal to which a predetermined voltage is applied and a second connection node between the first coil and the second coil;
A second Josephson junction connected to the second connection node;
A third resistor connected between a third voltage terminal to which a predetermined voltage is applied and a third connection node between the second coil and the output terminal;
And at least a third Josephson junction connected to the third connection node,
Said second resistor, Bi ₄ Ti ₃ O ₁₂ in the stoichiometric base layer in the amorphous state containing excess Ti as compared to the composition, and the chemical of Bi ₄ Ti ₃ O ₁₂ in said base layer Consists of a metal oxide layer composed of a plurality of fine particles of stoichiometric composition ,
A resistance value of the metal oxide layer is changed by an applied electric signal. The memory device according to claim 1.
The memory device, wherein the input terminal is inputted with the same input current as a single flux quantum in the form of a triangular wave . The memory device according to claim 1 or 2,
The metal oxide layer is
When a voltage exceeding the first voltage value is applied, the first state having the first resistance value is obtained.
The memory device, wherein a second state having a second resistance value higher than the first resistance value is obtained by applying a voltage exceeding a second voltage value having a polarity different from that of the first voltage. The memory device according to any one of claims 1 to 3 ,
The memory device, wherein the fine particles are analyzed to be amorphous by X-ray diffraction . 5. The memory device according to claim 4 , wherein
The memory device, wherein the metal oxide layer is formed at 30 ° C. or higher and lower than 180 ° C. by a sputtering method.