JP2008182154A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a matrix type large capacity memory device employing a resistance change memory cell. <P>SOLUTION: A memory element 100 has an intermediate electrode layer 102, a metal oxide layer 103 and an upper electrode 104 on a semiconductor substrate 101 wherein an ohmic contact 105 is provided at a part of the semiconductor substrate 101. The metal oxide layer 103 is composed of bismuth (Bi), titanium (Ti) and oxygen, and formed to have a film thickness of 30-200 nm or formed on the intermediate electrode layer 102 in contact therewith. For example, the metal oxide layer 103 is composed of a base layer containing excessive Ti as compared with the stoichiometric composition of Bi<SB>4</SB>Ti<SB>3</SB>O<SB>12</SB>, and a plurality of microcrystal grains which are about 3-15 nm of the stoichiometric composition of Bi<SB>4</SB>Ti<SB>3</SB>O<SB>12</SB>diffused in the base layer. Since the memory cell M has rectification characteristics, sneak current to a nonselect memory cell can be suppressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory device using a resistance change type memory cell that stores information by a change in electric resistance.

  Conventionally, semiconductor materials have been mainly used for devices (memory) that are mounted on network devices and information terminals and store information. As one of the memories using a semiconductor, a DRAM (Dynamic Random Access Memory) is widely used (see Non-Patent Document 1). A unit storage element (hereinafter referred to as a memory cell) of a DRAM is composed of one storage capacitor and one MOSFET (Metal-oxide-semiconductor field effect transistor), and the charge stored in the storage capacitor of the selected memory cell. The voltage corresponding to the state is taken out as “on” or “off” of the electrical digital signal from the receiving wiring (bit line), so that the stored data is read out.

  However, in the DRAM, when the power is turned off, it is impossible to maintain the state of the storage capacity, and the stored information is erased. In other words, DRAM is a volatile memory element. As is well known, a DRAM requires a refresh operation for rewriting data, and has a drawback that the operation speed is reduced.

  In order to realize the recent expansion of the multimedia information society, and further to realize ubiquitous services, more sophisticated memories are required. For example, the functions required of the memory installed in ubiquitous terminals include high speed, long-term retention period, environmental resistance, low power consumption, and non-volatility that keeps stored information even when the power is turned off. It is said that. ROM (Read only Memory) is well known as a non-volatile memory, but once stored (written) data cannot be erased, and has a major disadvantage that it cannot be rewritten. Yes.

  On the other hand, although it is a kind of ROM, a flash memory using an EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing and writing a limited number of times has been developed (patent) Reference 1, Non-Patent Documents 1 and 2). This flash memory is used in many fields as a practical non-volatile memory.

  In a memory cell of a typical flash memory, a gate electrode portion of a MOSFET has a stack gate structure including a plurality of layers each having a control gate electrode and a floating gate electrode. In the flash memory, data can be recorded by utilizing the fact that the threshold value of the MOSFET changes depending on the amount of charge accumulated in the floating gate.

  Writing data in the flash memory is performed by hot carriers generated by applying a high voltage to the drain region overcoming the energy barrier of the gate insulating film. In addition, data is written by injecting electric charges (generally electrons) from the semiconductor substrate to the floating gate by applying a high electric field to the gate insulating film to flow an FN (Fowler-Nordheim) tunnel current. Is done. Data is erased by extracting charges from the floating gate by applying a high electric field in the opposite direction to the gate insulating film.

  A flash memory does not require a refresh operation like a DRAM, but requires a high voltage of about 18 V in order to use the FN tunnel phenomenon, and the time required for writing and erasing data is orders of magnitude higher than that of a DRAM. There is a problem of becoming longer. Further, when data writing / erasing is repeated, the gate insulating film deteriorates, so that the number of rewrites is limited to some extent.

  In contrast to the flash memory described above, as a new non-volatile memory, a ferroelectric memory using ferroelectric polarization (hereinafter referred to as FeRAM (Ferroelectric RAM)) or a ferromagnetic memory using ferromagnetic resistance ( Hereinafter, MRAM (Magnetoresist RAM) and the like have attracted attention and are actively studied.

  Furthermore, recently, a resistance change type memory cell for storing information according to a change in electrical resistance has been proposed. If a cross-point structure is formed using such a resistance change type memory sail, a large capacity It is expected that a memory can be realized (see Non-Patent Document 3 and Non-Patent Document 4).

FIG. 14 is an equivalent circuit diagram showing a basic configuration of a conventional memory device using resistance change type memory cells. In FIG. 14, M is a resistance change type memory cell arranged in a matrix, W _{1 to} W _m are word lines provided for the memory cells in each row, and B _{1 to} B _n are for each memory cell in each column. This is a provided bit line.

In the memory device shown in FIG. 14, when _one desired memory cell M is selected by the word lines W _{1 to} W _m and the bit lines B _{1 to} B _n , the value of the current flowing through the bit line connected to the memory cell M Thus, the resistance value of the memory cell M can be read out. Each memory cell M maintains either a low resistance state (for example, data “1”) or a high resistance state (for example, data “0”). When the selected memory cell M is in a low resistance state, a large current I _{H: LRS} flows through the bit line. When the selected memory cell M is in a high resistance state, a small current I _{L: HRS} is applied through the bit line. Flowing. Thus, either “1” or “0” information held in the memory cell M can be read.

JP-A-8-031960 Simon G., Physics of Semiconductor Devices, 1981 (S.M.Sze, "Physics of Semiconductor Devices", John Wiley and Sons, Inc.) Fujio Tsujioka, “Current Status and Prospects of Non-Volatile Memory”, Applied Physics, Vol. 73, No. 9, pp. 1166-1171, 2004. "Research on non-volatile memory", written by the Japan Society for the Promotion of Mechanical Systems and the New Functional Device Research and Development Association, March 2004. J. Campbell Scott, "Is There an Immortal Memory?", Science, Vol.304, pp.62-63, 2004.

By the way, in the case of the memory device having the matrix structure shown in FIG. 14, a desired memory cell for reading to a memory cell (referred to as a “selected memory cell”) selected by the word lines W _{1 to} W _m and the bit lines B _{1 to} B _n is used. The state of the selected memory cell is read by applying the voltage V and observing the value of the current flowing through the selected memory cell. However, in reality, since the memory cells are connected to each other via the word lines W _{1 to} W _m and the bit lines B _{1 to} B _n , the memory cell is selected when the read voltage V is applied to the selected memory cell. Some voltage is also applied to the memory cells that are not (referred to as “non-selected memory cells”).

  Therefore, when reading the information of the selected memory cell, a current flows not only to the selected memory cell but also to the unselected memory cell. Therefore, in practice, the state of the selected memory cell must be identified by a combined current of the current flowing through the selected memory cell and the current flowing through the non-selected memory cell. The current flowing through the unselected memory cells is maximized when all the unselected memory cells are in the low resistance state, and is minimized when all the unselected memory cells are in the high resistance state.

Here, as shown in FIG. 15 (a), the memory device having an array of memory cells M ₁₁ to the memory cell M ₃₃ in 3 rows × 3 columns of a matrix, obtaining the current value I _read observed at the time of reading. In FIG. 15, Mij (i and j are integers) indicates each element of the memory cell. Here, for the sake of explanation, when the read voltage V is applied to the word line W ₂ and the bit line B _{3 is set} to the ground potential (that is, V = 0), the current I _read flowing through the bit line B ₃ is obtained. Here, M ₂₃ in the third row and the second column is the selected memory cell, and the other memory cells M ₁₁ , M ₁₂ , M ₁₃ , M ₂₁ , M ₂₂ , M ₃₁ , M ₃₂ , and M ₃₃ are unselected memory cells. Become.

In order to clarify the information readable condition, it is assumed that all the non-selected memory cells have the same resistance value R _ns and the resistance value of the selected memory cell M ₂₃ is R _tg . Due to the symmetry of the circuit, the potential between the bit lines (B ₁ and B ₂ ) other than the selected bit line is the same (referred to as V _B ). Similarly, the same potential is set between the word lines (W ₁ and W ₂ ) other than the selected word line (referred to as Vw). As a result, the current flowing through each of the memory cells M ₁₁ , M ₃₁ , M ₁₂ , and M ₃₂ is (V _B −V _w ) / R _ns . The current flowing through the memory cell M ₁₃ and the memory cell M ₃₃ is a respective V _w / R _ns. Further, the current flowing through the memory cell M ₂₁ and the memory cell M ₂₂ is a respective _{(V-V B) / R} ns. Incidentally, current flows in V / R _tg is applied to the selected memory cell M _23.

Incidentally, the current flowing into the word line W ₂ is equal to the current I _read flowing out from the bit line B ₃ according to Kirchhoff's law that “the sum of currents flowing into one point is 0”. That is, I _read is equal to the sum of currents flowing through the memory cells M ₂₃ , M ₁₃ , and M ₃₃ , and further to the sum of currents flowing through the memory cells M ₂₃ , M ₂₁ , and M _22. The equation shown below holds.

I _read = V / R _tg + 2V _W / R _ns = V / R _tg +2 (V−V _B ) / R _ns (1)

The current flowing through the memory cell M ₂₁ is equal to the sum of the current flowing through the current and the memory cell M ₃₁ flowing through the memory cell M _11, holds the equation shown in the following equation (2).

(V−V _B ) / R _ns = 2 (V _B −V _W ) / R _ns (2)

Further, the current flowing through the memory cell M ₁₃ is equal to the sum of the current flowing through the memory cell M ₁₁ and the current flowing through the memory cell M ₁₂ . By this relationship, the following equation (3) is established.

V _W / R _ns = 2 (V _B −V _W ) / R _ns (3)

When these simultaneous equations are solved, the potentials of V _B and V _w are V _B = 3 / 5V and V _w = 2 / 5V. Thus, the current I _read flowing through the bit line B ₃ is represented by the following equation (4).

I _read = V / R _tg + 2V _W / R _ns = V / R _tg + (4/5) × (V / R _ns ) (4)

The current value (I _read = I _{L: HRS} ) when the selected memory cell M ₂₃ is in the high resistance state (R _tg = R _H ) is the other non-selected memory cells (M ₁₁ , M ₁₂ , M ₁₃ , M ₂₁ , M ₂₂ , M ₃₁ , M ₃₂ , and M ₃₃ ) vary depending on the resistance distribution, but all the unselected memory cells are in a low resistance state (R _ns = R _L ) and all the unselected memory cells are high. Within the range of the resistance state (R _ns = R _H ), the inequality shown in the following equation (5) holds.

V / R _H + (4/5) × (V / R _L )> _{IL: HRS} > V / R _H + (4/5) × (V / R _H ) (5)

In Expression (5), V / R _H + 4V / 5R _L is the case where the selected memory cell M ₂₃ is in the high resistance state and all the non-selected memory cells are in the low resistance state (R _ns = R _L ). The current value I _read is V / R _H + 4V / 5R _H when the selected memory cell M ₂₃ is in the high resistance state and all the unselected memory cells are in the high resistance state (R _ns , = R _H ). The current value I _read in this case.

On the other hand, when the selected memory cell M ₂₃ is in the low resistance state (R _tg = R _L ), the current value (I _read = I _{H: LRS} ) indicates that all the unselected memory cells are in the low resistance state (R _ns , = R _L ) and all unselected memory cells are in the high resistance state (R _ns = R _H ), and the inequality shown in the following equation (6) is established.

V / R _L + (4/5) × (V / R _L )> I _{H: LRS} > V / R _L + (4/5) × (V / R _H ) (6)

In Expression (6), V / R _L + 4V / 5R _L is the case where the selected memory cell M ₂₃ is in the low resistance state and all the unselected memory cells are in the low resistance state (R _ns = R _L ). The current value I _read is V / R _L + 4V / 5R _H when the selected memory cell M ₂₃ is in the low resistance state and all the unselected memory cells are in the high resistance state (R _ns = R _H ). Current value _Iread .

In order to be able to determine whether the selected memory cell is in the high resistance state or the low resistance state using the current value I _read , it is required that I _{H: LRS} > I _{L: HRS} holds, so “{V / R _L + (4/5) × (V / R _L )> I _{H: LRS} > V / R _L + (4/5) × (V / R _H )}> {V / R _H + (4/5) × (V / R _L )> _{IL: HRS} > V / R _H + (4/5) × (V / R _H )} ”, and in order to always distinguish between I _{H: LRS} and I _{L: HRS} , The following equation (7) needs to be satisfied.

V / R _L + (4/5) × (V / R _H )> V / R _H + (4/5) × (V / R _L ) (7)

From equation (7), it can be seen that R _H > R _L always holds. Thus, the memory device arranged in 3 rows × 3 columns of a matrix of FIG. 15 (a), it can be seen that identify the state of the selected memory cell M _23.

Next, as shown in FIG. 15B, a description will be given of _obtaining a current I _read observed at the time of reading for a memory device arranged in a matrix of 3 rows × 4 columns by the same method as described above. To select the selected memory cell M ₂₃ located at the intersection of the word line W ₂ and the bit line B _3, the read voltage V is applied to the word line W _2, when the bit line B ₂ to the ground potential, the bit line For the current I _read flowing through B ₂ , simultaneous equations shown in the following equations (8), (9), and (10) hold.

I _read = V / R _tg + 2V _W / R _ns = V / R _tg +3 (V−V _B ) / R _ns (8)
(V−V _B ) / R _ns = 2 (V _B −V _W ) / R _ns (9)
V _W / R _ns = 3 (V _B −V _W ) / R _ns (10)

When these simultaneous equations are solved, the potentials of V _B and V _W are V _B = 2 / 3V and V _W = 1 / 3V. Thus, the current I _read flowing through the bit line B ₃ is expressed by the following equation (11) from the equation (8).

I _read = V / R _tg + V / R _ns (11)

When the current I _{L: HRS} when the selected memory cell M ₂₃ is in the high resistance state is obtained as in the equation (5), the following equation (12) is obtained.

V / R _H + V / R _L > I _{L: HRS} > V / R _H + V / R _H (12)

Further, when the current I _{H: LRS} when the selected memory cell M ₂₃ is in the low resistance state is obtained as in the equation (6), the following equation (13) is obtained.

V / R _L + V / R _L > I _{H: LRS} > V / R _H + V / R _L (13)
By the way, from Expression (12) and Expression (13), “V / R _H + V / R _L = V / R _L + V / R _H (14)”. This is because the maximum value of the current _{IL: HRS} when the selected memory cell is in the high resistance state (current value when the selected memory cell is in the high resistance state and all the unselected memory cells are in the low resistance state) and the selected memory cell The current I _{H: LRS in} the low resistance state is equal to the minimum value (the current value when the selected memory cell is in the low resistance state and all the unselected memory cells are in the high resistance state), and the selected memory cell is in the high resistance state. This indicates that it is impossible to determine whether the resistance state is low.

Thus, the memory device shown in FIG. 15 (b), it is extremely difficult to identify without erroneous state of the selected memory cell M _23. As described above, in the conventional memory device using the resistance change type memory cell, there is a possibility that an error occurs when reading information. This phenomenon of error in reading information does not appear in a matrix of 3 rows × 3 columns, but appears in a matrix larger than 3 rows × 4 columns, and becomes more prominent as the number of rows and columns increases. Come.

Next, an example of a memory device having a more general matrix structure that does not cause the above-described read error will be described below. FIG. 16 is a diagram illustrating a voltage distribution at each point when reading is performed in a memory device having a two-dimensional matrix structure using resistance change memory cells. FIG. 16 equivalently represents each memory cell in the form of a resistance change element. First, as shown in FIG. 16, a current distribution is obtained in a memory device in which memory cells are arranged in a matrix of m rows × n columns (m and n are integers of 2 or more). In FIG. 16, the memory cell in the 2nd row × (n−1) th column is a selected memory cell M _tg, and all other memory cells are unselected memory cells M _ns . Also, I _tg is the current flowing in the selected memory cell M _tg, I _ns is the current through the non-selected memory cells M _ns. Further, W _{1 to} W _m indicate word lines provided for the memory cells in each row, and B _{1 to} B _n indicate bit lines provided for the memory cells in each column.

When the wiring connected to the non-selected memory cell _Mns is in an open state, the potentials of the wiring between columns or rows are the same due to the symmetry of the circuit. Further, according to Kirchhoff's law, each potential has a value as shown in FIG. That is, when the read voltage V is applied to the word line W ₂ and the bit line B _{n−1 is set} to the ground potential, the potentials of the word lines W ₁ , W _{3 to} W _m are (n−1) V / (m + n−). 1), and the potential of the bit line _{B1 ~W n-2, W n} , a (n) V / (m + n-1).

The current I _read flowing from the bit line B _n−1 connected to the selected memory cell M _tg is the sum of the current flowing from each memory cell connected to the bit line B _n−1 . The current flowing through the memory cell can be obtained by dividing the potential of the word line by the resistance of the memory cell. When the resistance value of the selected memory cell M _tg and R _tg, current I _tg flowing through the selected memory cell M _tg becomes I _tg = V / R _tg. Since it is assumed that the non-selected memory cells M _ns all have the same resistance, if the resistance value of the non-selected memory cell M _ns is R _ns , the contribution of the non-selected memory cell M _ns Current (n-1) V / {(m + n-1) R _ns } multiplied by the number of memory cells (m-1), that is, (m-1) (n-1) V / {(m + n -1) R _ns }.

Since the current I _read is the sum of the currents flowing from the memory cells connected to the bit line B _n−1 , the current I _read is expressed by the following equation (15).

I _read = V / R _tg + (m−1) (n−1) V / {(m + n−1) R _ns } (15)

Also, the selected memory cell M _tg current I _H flows from the bit line W _n-1 in the case of low-resistance state (R _tg = R _L): in order to have a _LRS minimum value, the non-selected memory cells M _ns This is a case of a high resistance state (R _ns = R _H ). That is, the following equation (16) is established.

I _{H: LRS} > V / R _L + (m−1) (n−1) V / {(m + n−1) R _H } (16)
On the other hand, when the selected memory cell M _tg is in the high resistance state (R _tg = R _H ), in order for the current I _{L: HRS} flowing out from the bit line W _n-1 to have the maximum value, the unselected memory cell M _ns In the low resistance state (R _ns = R _L ). That is, the following equation (17) is established.

I _{L: HRS} <V / R _H + (m−1) (n−1) V / {(m + n−1) R _L } (17)

In order to correctly identify the state of the selected memory cell M _tg , I _{H: LRS} > I _{L: HRS} must always be satisfied. That is, the inequality shown in the following equation (18) is established.

I _{H: LRS} > V / R _L + (m−1) (n−1) V / {(m + n−1) R _H }> V / R _H + (m−1) (n−1) V / { (M + n−1) R _L }> I _{L: HRS} (18)

In Expression (18), R _L represents the resistance value of the selected memory cell M _tg and the non-selected memory cell M _{ns in} the low resistance state, and R _H represents the selected memory cell M _tg and the non-selected memory cell in the high resistance state. The resistance value of M _ns is shown.

  Summarizing equation (18), the following equation (19) is established.

{1- (m-1) (n-1) / (m + n-1)} R _H > {1- (m-1) (n-1) / (m + n-1)} R _L (19 )

Thus, in order to correctly identify the state of the selected memory cell M _tg , the inside of {} in the equation (19) needs to be positive, and the condition of the following equation (20) is required.

{1- (m-1) (n-1) / (m + n-1)}> 0,
2 (m + n-1)> mn (20)
In the formula (20), m and n are each a positive integer.

When m = 1 or m = 2, equation (20) is established regardless of what n is brought, so that the state of the selected memory cell M _tg can be identified. Also, in the case of m = 3 and n = 1 to 3, the state can be identified because Expression (20) is established. However, when the scale exceeds m = 3 and n = 1 to 3, Equation (20) is not satisfied, and an error occurs in state identification for each selected memory cell.

In addition, in the memory device using the conventional resistance change type memory cell, there is a problem even when writing is performed. When the wiring connected to the non-selected memory cell M _ns is in an open state, three non-selected memory cells M _ns connected in series (for example, the non-selected memory located at the intersection of the bit line B ₂ and the word line W ₂ ) and the cell M _ns, and the non-selected memory cells M _ns located at the intersection of the bit line B ₂ and the word line W _1, the non-selected memory cells M _ns located at the intersection of the bit line B _n-1 and the word line W ₁ If only one of them is in the high resistance state and the other two are in the low resistance state, almost the same voltage as that of the selected memory cell M _tg is applied to the non-selected memory cell M _ns in the high resistance state. There is a possibility that the state of the selected memory cell M _ns is rewritten, so that the number of rows and columns of memory cells can be increased even if the resistance ratio between the low resistance state and the high resistance state is simply increased. The memory capacity could not be increased.

  In order to solve such a problem at the time of reading and writing, a transistor (for example, MOSFET) serving as a selection switch is provided for each memory cell as shown in an equivalent circuit diagram (FIG. 17) showing a basic configuration of the memory device. By adopting the structure of the transistor 1 resistance element (1T1R), the current flows only in the selected memory cell, and the state of the selected memory cell can be identified. However, since it is necessary to provide a transistor for each memory cell, the area of the transistor occupying the memory cell is increased, and it is difficult to increase the capacity of the memory.

In the conventional resistance change type memory cell shown in FIG. 16 and satisfying the equation (20), a current flowing from the word line to the bit line and a current flowing from the bit line to the word line when a certain voltage is applied are obtained. It was almost equal. In other words, the memory cell has no rectification characteristics. If the direction from the word line to the bit line is positive (forward direction) and the opposite is negative (reverse direction), the memory cell is in a high resistance state due to the current flowing by applying positive and negative voltages. And the low resistance state were almost the same. For this reason, in a matrix structure that does not satisfy Equation (20), when a voltage is applied to identify the state of the selected memory cell M _tg , the unselected memory cell M _ns wraps around regardless of the state identification of the selected memory cell. A current flows, and the state of the selected memory cell M _tg cannot be identified. In addition to this, the state of the unselected memory cell _Mns may be rewritten.

  The present invention has been made to solve the above-described problems, and an object thereof is to realize a large capacity in a memory device using a resistance change type memory cell.

  A memory device according to the present invention is a memory device including a plurality of memory elements in which information is stored by a change in electrical resistance. The memory element includes a semiconductor substrate formed of a semiconductor and an upper surface of the semiconductor substrate. The intermediate electrode layer is formed on the intermediate electrode layer, the metal oxide layer is formed on the intermediate electrode layer, and the electric resistance is changed. The upper electrode is formed on the metal oxide layer. In this memory device, the memory element has a rectifying characteristic in which a current in one direction flows more easily than a current in the other direction. According to the memory device configured as described above, when a p-type semiconductor substrate is used, for example, current flows easily when a positive voltage is applied to the upper electrode, and current hardly flows when a negative voltage is applied. It has a rectifying characteristic. Further, if an n-type semiconductor is used, it has reverse rectification characteristics.

  In the memory device, a plurality of word lines connected to one end of each memory element, a plurality of bit lines connected to the other end of each memory element, and a read voltage or a write voltage for the selected word line Word line selection means to be applied, bit line selection means for applying a read voltage or a write voltage to the selected bit line, and resistance values of memory elements connected to the selected word line and the selected bit line Reading means for reading a current value flowing through the selected bit line. For example, the reading means only needs to read the resistance value of the memory element by simultaneously detecting the current flowing through the memory element and the voltage generated in the memory element and comparing the detected voltage and current.

  In the memory device, the metal oxide layer includes a base layer composed of at least a first metal and oxygen, and a plurality of layers composed of the first metal, the second metal, and oxygen and dispersed in the base layer. It may be composed of fine particles. For example, the fine particles are amorphous. Further, the base layer is composed of the first metal, the second metal, and oxygen, and the composition ratio of the second metal is smaller than the stoichiometric composition. The base layer is made of a first metal, a second metal, and oxygen and is amorphous. The metal oxide layer is in a first state having a first resistance value when a voltage exceeding the first voltage value is applied, and from the first resistance value when a voltage exceeding a second voltage value having a polarity different from that of the first voltage is applied. A second state having a high second resistance value is obtained.

  In the memory device, for example, the metal oxide layer may be formed at 30 ° C. or higher and lower than 180 ° C. by a sputtering method. The first metal is titanium, the second metal is bismuth, and the base layer may be in an amorphous state composed of a layer containing excess titanium as compared with the stoichiometric composition.

  As described above, according to the present invention, a memory element constituting a memory device includes a semiconductor substrate made of a semiconductor, an intermediate electrode layer formed on the semiconductor substrate, and an upper surface of the intermediate electrode layer. Since the metal oxide layer formed on the metal oxide layer changes its electric resistance and the upper electrode formed on the metal oxide layer, the capacity of the memory device using the resistance change type memory cell can be increased. An excellent effect that it can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A is a circuit diagram equivalently showing the configuration of the memory device according to the present embodiment, and FIG. 1B is a cross-sectional view schematically showing the configuration of the memory element 100 constituting the memory cell M. FIG. The memory device according to the present embodiment shown in FIG. 1 is composed of a memory cell array in which memory cells M each including a memory element 100 having a rectifying characteristic and having a variable resistance value are arranged in a matrix.

One end of each memory cell M is connected to the corresponding word line W _{1 to} W _m, and the other end of the memory cell M (memory element 100) is connected to the corresponding bit line B _{1 to} B _n . In addition, a read voltage or a write voltage is applied to the selected word line by the word line selection circuit 110, and a read voltage or a write voltage is applied to the selected bit line by the bit line selection circuit 111. Further, the information (resistance value) stored in the selected memory cell M is read by the read circuit 112 as a current value flowing through the selected bit line.

  Next, the memory element 100 will be described. The p-type semiconductor substrate 101 includes an intermediate electrode layer 102, a metal oxide layer 103, and an upper electrode 104, and a part of the semiconductor substrate 101 is ohmic. A contact 105 is provided. The metal oxide layer 103 is composed of bismuth (Bi), titanium (Ti), and oxygen, and is formed to have a thickness of 30 to 200 nm, for example, and is in contact with the intermediate electrode layer 102. Further, a wiring that becomes the word line W is connected to the upper electrode 104 via an interlayer insulating layer (not shown), for example, and a wiring that becomes the bit line B is connected to the ohmic contact 105 via an interlayer insulating film (not shown). In the memory device of this embodiment shown in FIG. 1A, a plurality of memory elements 100 are arranged. In the semiconductor substrate 101, each memory element 100 is insulated and isolated by an element isolation region. Has been.

  The semiconductor substrate 101 is, for example, p-type single crystal silicon. Further, the semiconductor substrate 101 is not limited to silicon, and may be composed of any of semiconductors such as germanium (Ge) and diamond, and compound semiconductors such as GaAs, InP, and GaN. The ohmic contact 105 is a region where an alloy layer such as silicide is formed. By applying a voltage from a power source between the upper electrode 104 and the ohmic contact 105, a voltage can be applied to the metal oxide layer 103 sandwiched between the semiconductor substrate 101 and the upper electrode 104. Therefore, the semiconductor substrate 101 becomes one electrode paired with the upper electrode 104.

The upper electrode 104 may be made of a noble metal such as platinum (Pt), Ru, gold (Au), silver (Ag), or a transition metal including tungsten (W). In addition, titanium nitride (TiN), hafnium nitride (HfN), tantalum nitride (TaN), strontium ruthenate (SrRuO ₂ ), zinc oxide (ZnO), tin lead oxide (IZO), lanthanum fluoride (LaF ₃ ), etc. Compounds such as transition metal nitrides, oxides, and fluorides, and composite layers obtained by laminating these may also be used.

  As will be described in detail later, the memory cell M has a rectifying characteristic with respect to an applied voltage, and current easily flows in the direction (forward direction) from the word line (upper electrode 104) to the bit line (semiconductor substrate 101). Conversely, current does not easily flow from the bit line to the word line (reverse direction). Note that when the conductivity type of the semiconductor substrate 101 is n-type, reverse rectification characteristics are obtained. Each memory cell M is a resistance change type memory cell and has two states of a high resistance state (HRS) and a low resistance state (LRS). These two resistance states exist stably when no voltage is applied, and either of the two resistance states can be repeatedly switched by the voltage supplied from the bit line or the word line to change the state.

  As described above, by using the resistance change type memory cell having the rectifying characteristic as the resistance change type memory cell, it becomes possible to suppress the sneak current to the non-selected memory cell which cannot be achieved by the conventional method, and the equation (20) Even in a matrix structure exceeding the above limit, the state of the selected memory cell can be correctly identified.

  The intermediate electrode layer 102, the metal oxide layer 103, and the upper electrode 104 described above will be described in detail later, but a metal target or a metal target is formed by using an ECR sputtering apparatus as shown in FIG. ECR plasma composed of gas, xenon gas, oxygen gas, and nitrogen gas may be generated by a plasma source and sputtered using particles in the generated plasma.

  Here, the ECR sputtering apparatus will be described with reference to the schematic cross-sectional view of FIG. The ECR sputtering apparatus first includes a processing chamber 201 and a plasma generation chamber 202 communicating with the processing chamber 201. The processing chamber 201 communicates with an evacuation device (not shown), and the inside of the processing chamber 201 and the plasma generation chamber 202 is evacuated by the evacuation device.

  The processing chamber 201 is provided with a substrate holder 204 to which the semiconductor substrate 101 to be film-formed is fixed. The substrate holder 204 is inclined at a desired angle by a rotation mechanism (not shown) and is rotatable. By tilting and rotating the substrate holder 204, it is possible to improve the in-plane uniformity of the film and the step coverage with the material to be deposited. Further, a ring-shaped target 205 is provided so as to surround the opening region in the opening region into which the plasma from the plasma generation chamber 202 in the processing chamber 201 is introduced.

  The target 205 is placed in a container 205 a made of an insulator, and the inner surface is exposed in the processing chamber 201. Further, a high frequency power source 222 is connected to the target 205 via a matching unit 221 so that, for example, a high frequency of 13.56 MHz can be applied. When the target 205 is a conductive material, direct current may be applied. Note that the target 205 may be not only a circular shape but also a polygonal state as viewed from above.

  The plasma generation chamber 202 communicates with the vacuum waveguide 206, and the vacuum waveguide 206 is connected to the waveguide 208 through a quartz window 207. The waveguide 208 communicates with a microwave generation unit (not shown). In addition, a magnetic coil (magnetic field forming means) 210 is provided around the plasma generation chamber 202 and on the upper portion of the plasma generation chamber 202. These microwave generator, waveguide 208, quartz window 207, and vacuum waveguide 206 constitute microwave supply means. There is a configuration in which a mode converter is provided in the middle of the waveguide 208.

An operation example of the ECR sputtering apparatus partially shown in FIG. 2 will be described. First, the processing chamber 201 and the plasma generation chamber 202 are evacuated to an internal pressure of 10 ⁻⁵ to 10 ⁻⁴ Pa, Ar gas or Xe gas, which is an inert gas, is introduced from the active gas introduction unit 211, and a reactive gas is introduced from the reactive gas introduction unit 212. The inside of the plasma generation chamber 202 is, for example, 10 ⁻³ to 10 ^−2. The pressure is about Pa. In this state, a magnetic field of 0.0875 T (Tesla) is generated in the plasma generation chamber 202 from the magnetic coil 210, and then the plasma generation chamber 202 is passed through the waveguide 208, the quartz window 207, and the vacuum waveguide 206. A 2.45 GHz microwave is introduced into the inside, and an electron cyclotron resonance (ECR) plasma is generated. Note that 1T = 10000 Gauss.

  The ECR plasma forms a plasma flow in the direction of the substrate holder 204 by the divergent magnetic field from the magnetic coil 210. Of the generated ECR plasma, electrons penetrate through the target 205 by the divergent magnetic field formed by the magnetic coil 210 and are extracted toward the semiconductor substrate 101 and are irradiated onto the surface of the semiconductor substrate 101. At the same time, positive ions in the ECR plasma are drawn out to the semiconductor substrate 101 side so as to neutralize the negative charge due to electrons, that is, to weaken the electric field, and are irradiated on the surface of the layer being formed. . Thus, while each particle is irradiated, some of the positive ions are combined with electrons to become neutral particles.

  In the ECR sputtering apparatus described above, the microwave power supplied from the microwave generation unit (not shown in FIG. 2) is once branched in the waveguide 208, and is supplied to the vacuum waveguide 206 above the plasma generation chamber 202. They are coupled from the side of the plasma generation chamber 202 through a quartz window 207. By doing so, it becomes possible to prevent the scattered particles from adhering to the quartz window 207 from the target 205, and the running time can be greatly improved. In addition, a shutter or the like may be provided between the substrate to be processed and the target 205 to control the arrival of the raw material with respect to the substrate.

  Next, an example of a method for manufacturing the memory element 100 in this embodiment will be described with reference to FIGS. First, as shown in FIG. 3A, a semiconductor substrate 101 made of p-type silicon having a main surface with a plane orientation (100) and a resistivity of 1 to 2 Ω-cm is prepared, and the surface of the semiconductor substrate 101 is made of sulfuric acid. And a mixture of pure water and hydrogen peroxide, and a mixture of pure water and dilute hydrogen fluoride water, followed by drying.

  Next, as shown in FIG. 3B, the above-described metal thin film 302 to be the intermediate electrode layer 102 is formed on the cleaned and dried semiconductor substrate 101. In forming the metal thin film 302, the above-described ECR sputtering apparatus is used, the semiconductor substrate 101 is fixed to the substrate holder 204 in the processing chamber 201, pure ruthenium (Ru) is used as the target 205, and xenon (Xe) is used as the plasma gas. By the ECR sputtering method used, the Ru film (metal thin film 302) is formed so as to cover the surface.

The formation of the Ru film will be described in detail. In the ECR sputtering apparatus described above, first, the inside of the plasma generation chamber 202 is evacuated to a high vacuum state of about 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the plasma generation chamber 202 is filled. Then, for example, Xe gas is introduced at a flow rate of 26 sccm from the inert gas introduction unit 211, and the pressure in the plasma generation chamber 202 is set to, for example, 10 ⁻¹ to 10 ⁻² Pa. Note that sccm is a unit of flow rate and indicates that 1 cm ³ of fluid at 1 atm flows at 0 ° C. per minute. In addition, a magnetic field of electron cyclotron resonance condition is provided in the plasma generation chamber 202 by supplying a coil current to the magnetic coil 210 at 26 A, for example.

  In addition, a 2.45 GHz microwave (for example, 800 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 208, the quartz window 207, and the vacuum waveguide 206. It introduce | transduces in 202, It is set as the state by which the plasma was produced | generated in the plasma production chamber 202 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 202 to the processing chamber 201 side by the divergent magnetic field of the magnetic coil 210. Further, high frequency power (for example, 500 W) is supplied from the high frequency power supply 222 to the target 205 disposed at the outlet of the plasma generation chamber 202. As a result, Xe particles collide with the target 205 to cause a sputtering phenomenon, and Ru particles jump out of the target 205. The Ru particles that have jumped out of the target 205 reach the semiconductor substrate 101, whereby Ru is deposited on the semiconductor substrate 101 to form a metal thin film 302.

  By the Ru deposition by the ECR sputtering method described above, for example, a state in which the metal thin film 302 with a film thickness of about 20 nm is formed (FIG. 3B). Thereafter, the film formation is stopped by preventing the sputtered raw material from reaching the semiconductor substrate 101 with the aforementioned shutter closed. Thereafter, the plasma irradiation is stopped by stopping the supply of microwave power, the supply of each gas is stopped, the temperature of the semiconductor substrate 101 is lowered to a predetermined value, and a metal thin film is formed from the inside of the processing chamber 201. The semiconductor substrate 101 on which the 302 is formed is carried out. The film thickness of the metal thin film 302 is not limited to 20 nm. The metal thin film 302 forming the intermediate electrode layer 102 is not limited to Ru, and may be composed of other metal materials or conductive materials such as gold, platinum, and titanium nitride.

  By the way, in the formation of the Ru film by the above-described ECR sputtering method, the substrate is not heated. However, the present invention is not limited to this, and a metal thin film such as a Ru film may be formed while the substrate is overheated. For example, when the Ru film is formed without heating, the adhesion of the Ru film to the silicon oxide may be reduced and the Ru film may be peeled off. The problem can be suppressed.

As described above, after the metal thin film 302 was formed in a desired thickness, the metal oxide layer 103 was formed on and in contact with the metal thin film 302 as shown in FIG. State. In the formation of the metal oxide layer 103, an ECR sputtering apparatus similar to that described above is used, the semiconductor substrate 101 is fixed to the substrate holder 204 in the processing chamber 201, and a Bi / Ti ratio of 4: 3 is used as the target 205. The metal oxide layer 103 is formed so as to cover the surface of the metal thin film 302 by ECR sputtering using (Bi—Ti—O) and using Ar and oxygen (O ₂ ) as plasma gases.

The formation of the metal oxide layer 103 will be described in detail. In the above-described ECR sputtering apparatus, first, the inside of the plasma generation chamber 202 is evacuated to a high vacuum state on the order of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the semiconductor substrate 101. Is heated to 30 ° C. to 700 ° C., and, for example, Ar gas is introduced at a flow rate of 20 sccm from the inert gas introduction unit 211 into the plasma generation chamber 202, and the pressure in the plasma generation chamber 202 is set at 10 ⁻ Set to ² to 10 ^-3 Pa. In addition, a magnetic field under electron cyclotron resonance conditions is provided in the plasma generation chamber 202 by supplying a coil current to the magnetic coil 210 at 27 A, for example.

  In addition, a 2.45 GHz microwave (for example, 500 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 208, the quartz window 207, and the vacuum waveguide 206. It introduce | transduces in 202, It is set as the state by which the plasma was produced | generated in the plasma production chamber 202 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 202 to the processing chamber 201 side by the divergent magnetic field of the magnetic coil 210. Further, high frequency power (for example, 500 W) is supplied from the high frequency power supply 222 to the target 205 disposed at the outlet of the plasma generation chamber 202. As a result, Ar particles collide with the target 205 to cause a sputtering phenomenon, and Bi particles and Ti particles jump out of the target 205.

  Bi particles and Ti particles jumping out from the target 205 reach the surface of the metal thin film 302 together with the plasma released from the plasma generation chamber 202 and the oxygen gas introduced from the reactive gas introduction unit 212 and activated by the plasma. And oxidized by the activated oxygen. The oxygen gas may be introduced at about 1 sccm from the reactive gas introduction unit 212, for example. The target 205 is a sintered body and contains oxygen, but oxygen supply can prevent oxygen deficiency in the deposited film. As will be described later, the temperature condition of the semiconductor substrate 101 may be 30 to 180 ° C.

  By forming the film by the ECR sputtering method described above, for example, a state in which the metal oxide layer 103 having a film thickness of about 30 nm is formed on the metal thin film 302 is obtained (FIG. 3B). Thereafter, the film formation is stopped by preventing the sputtered raw material from reaching the semiconductor substrate 101 with the aforementioned shutter closed. Thereafter, the plasma irradiation is stopped by stopping the supply of the microwave power, the supply of each gas is stopped, the temperature of the semiconductor substrate 101 is lowered to a predetermined value, and the metal oxide is supplied from the inside of the processing chamber 201. The semiconductor substrate 101 on which the layer 103 is formed is unloaded.

  Next, as shown in FIG. 3C, the upper electrode 104 made of Ru having a predetermined area is formed on the metal oxide layer 103. For example, the upper electrode 104 having a predetermined area can be formed by processing the Ru film by patterning using a well-known photolithography technique and etching technique. Note that the upper electrode 104 is not limited to Ru, and may be made of another metal material such as gold, platinum, titanium nitride, or a conductive material.

  Thereafter, a part of the metal oxide layer 103 and the metal thin film 302 is removed to expose a part of the semiconductor substrate 101, and an intermediate electrode layer 102 is formed thereon as shown in FIG. The metal oxide layer 103 is disposed, and an ohmic contact 105 for connecting a wiring or the like is formed on the semiconductor substrate 101 serving as one electrode. Thus, the memory element 100 using the metal oxide layer 103 is obtained.

  Next, the metal oxide layer 103 formed by ECR sputtering as described above will be described in more detail. The inventors have found that the film characteristics of the metal oxide layer formed by temperature can be controlled by carefully observing the formation of the metal oxide layer composed of Bi, Ti, and oxygen using the ECR sputtering method. . In this sputtering film formation, an oxide sintered body target formed so that Bi and Ti have a composition of 4: 3 is used.

  The characteristics shown in FIG. 4 indicate changes in the deposition rate and refractive index with respect to the substrate temperature in the sputter deposition. FIG. 4 shows a case where the film is formed under the same gas conditions as those for forming the metal oxide layer 103 by the ECR sputtering method described above. As shown in FIG. 4, it can be seen that the deposition rate and the refractive index change with temperature.

First, paying attention to the refractive index, the refractive index is as small as about 2 in the low temperature region up to about 250 ° C., and shows amorphous characteristics. In the intermediate region at 300 ° C. to 600 ° C., the refractive index is about 2.6, which is close to the bulk reported in the paper, and it can be seen that the crystallization of Bi ₄ Ti ₃ O ₁₂ is progressing. Regarding these figures, for example, Yamaguchi et al., Japanese Journal Applied Physics, No. 37, 5166-5170, 1998, (M. Yamaguchi, et al. “Effect of Grain Size on Bi ₄ Ti ₃ O ₁₂ Thin Film Properties ", Jpn. J. Appl. Phys., 37, pp. 5166-5170, (1998)).

However, in a temperature region exceeding about 600 ° C., the refractive index increases, the surface morphology (surface irregularities) increases, and the crystallinity seems to change. This temperature is lower than the Bi ₄ Ti ₃ O ₁₂ Curie temperature of 675 ° C., but energy is supplied by irradiating the surface of the substrate on which the film is formed with ECR plasma, and the temperature of the substrate surface rises. If crystallinity such as oxygen deficiency is deteriorated, it is considered that there is no contradiction in the above results.

  Looking at the temperature dependence of the deposition rate, the deposition rate increases with temperature up to about 180 ° C. However, the film formation rate rapidly decreases in the region of about 180 ° C. to 300 ° C. When the temperature reaches about 300 ° C., the deposition rate becomes constant up to 600 ° C. The film formation rate in each oxygen region at this time was about 3 nm / min in the oxygen region C.

  Next, the crystallinity of the film formed in each temperature region was analyzed by X-ray diffraction. In a low temperature range from room temperature of about 30 ° C. to 180 ° C., it was confirmed to be amorphous. Further, it was confirmed that the crystal was composed of microcrystals in a temperature range of 180 ° C. to 300 ° C. It was also found that the film was oriented in the (117) direction in the temperature range of 300 ° C. or higher.

  When the cross-sectional shape of the state of the metal oxide layer in the temperature region of 300 ° C. or higher was observed with a transmission electron microscope, the results shown in the configuration diagram of FIG. 5 and the micrograph of FIG. 6 were obtained. In the formation of the observed film, a metal oxide composed of Bi, Ti, and oxygen was directly deposited on the Si substrate 501 at a deposition temperature of 420 ° C.

From the results shown in FIGS. 5 and 6, the metal oxide layer 504 is formed, in the base layer containing excess Ti as compared to the stoichiometric composition of _{Bi 4 Ti 3 O 12, Bi} 4 Ti It was found that a plurality of microcrystalline grains having a stoichiometric composition of ₃ O ₁₂ of about ₃ nm to 15 nm were dispersed. Electron diffraction on the fine crystal grains confirmed that the fine crystal grains had a (117) plane of Bi ₄ Ti ₃ O ₁₂ . Note that the metal oxide layer 504 corresponds to the metal oxide layer 103 of the memory element 100 illustrated in FIG. In other words, the metal oxide layer 103 may, Bi ₄ Ti ₃ O ₁₂ and the base layer containing excess Ti as compared to the stoichiometric composition of, arranged dispersed in the Bi ₄ Ti ₃ O ₁₂ And a plurality of microcrystalline grains having a stoichiometric composition of about 3 nm to 15 nm.

  However, by observing the photograph in FIG. 6 in detail, an interface oxide layer 502 formed by oxidizing the silicon substrate 501 and Bi and Ti are formed on the interface between the metal oxide layer 504 and the silicon substrate 501. It was found that there was an interface reaction layer 503 formed by the reaction. When an interface layer such as the interface oxide layer 502 and the interface reaction layer 503 is formed, a film having a low dielectric constant is formed, which may cause a large amount of leakage current to be deteriorated. There is.

  Therefore, the inventors examined the formation of a metal oxide layer in a sufficiently low temperature region such that the interface oxide layer and the interface reaction layer are not formed. Specifically, it is a low temperature region of 30 ° C. to 180 ° C. shown in FIG. 4, that is, a region in which the refractive index is about 2.0 to 2.1 and the film formation rate increases as the temperature rises. However, when the substrate temperature is 30 ° C., that is, when the substrate is not heated, the actual temperature of the substrate surface on which the film is formed may rise to about 100 ° C. because the ECR plasma with energy is irradiated. It has been confirmed. However, when the substrate temperature is set to 100 ° C. to 150 ° C., the substrate heating temperature and the plasma heating temperature are approximately the same, and the substrate heating is suppressed by the control of the temperature controller. It becomes about 180 ° C to 180 ° C.

  In this low temperature region, a metal oxide layer made of Bi, Ti, and oxygen was formed on the silicon substrate using ECR sputtering. A micrograph of FIG. 7 shows a cross-sectional observation of the transmission electron microscope at this time. Specifically, the substrate was not heated, and the film was formed using the gas conditions of the metal oxide layer using the ECR sputtering method described above. As shown in FIG. 7, it can be seen that fine particles of 3 nm to 5 nm are present in the formed metal oxide layer despite being deposited without heating the substrate.

As a result of analyzing the composition of the fine particles and the peripheral portion by a technique in which characteristic X-rays generated from the irradiated portion by direct irradiation with an electron beam are directly detected by a semiconductor detector and converted into an electrical signal, the base layer ( Where the particles are not fine particles), Ti is contained more excessively than the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ , and the fine particles contain more Bi than the base layer, and Bi ₄ Ti ₃ it was found close to the stoichiometric composition of O _12. The measured fine particles are very small, 3nm to 5nm, so it is difficult to identify the exact composition by electron diffraction, but the same structure as the base layer and microcrystals observed in the high temperature region above 300 ° C is confirmed. did it.

  As described above with reference to FIG. 4, the results of XRD confirm that the film formed at a low temperature is in an amorphous (non-crystalline) state. It is considered that the fine particles have not been confirmed in such a low temperature film formation, and it was observed because the film was formed by the ECR sputtering method having an appropriate energy of about 10 to 30 eV. When a metal oxide layer composed of Bi, Ti, and oxygen is formed on a silicon substrate in a low temperature range of 30 ° C. to 180 ° C., the interface oxide layer 502 and the interface reaction as seen in FIGS. Layer 503 is not observed. When the film was formed at such a low temperature, the interface between the silicon 801 and the formed metal oxide layer 804 was in a good state as shown in the schematic cross-sectional view of FIG.

Further, the inventors have described in detail the electrical characteristics of the memory element 100 configured as shown in FIG. 1B using the metal oxide layer made of Bi, Ti, and oxygen formed in the low temperature region as described above. By investigating, I discovered that a new phenomenon appears. In other words, the chemistry of Bi ₄ Ti ₃ O ₁₂ is formed in the base layer formed by the low-temperature sputtering method as described above and containing excess Ti compared to the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ . According to an element (memory element 100) using a metal oxide layer in which a plurality of microcrystalline grains having a stoichiometric composition of about 3 nm to 15 nm are dispersed, two states are maintained as will be described later. It has been found that a functional element can be realized.

  Characteristics of the memory element 100 illustrated in FIG. 1B will be described. This characteristic has been investigated by applying an appropriate voltage between the semiconductor substrate 101 (ohmic contact 105) and the upper electrode 104. When a voltage was applied between the ohmic contact 105 and the upper electrode 104 by a power source and the current when the voltage was applied was observed with an ammeter, the result shown in FIG. 9 was obtained. In FIG. 9, the horizontal axis represents the voltage value applied to the upper electrode 104, and the vertical axis represents the absolute value of the current value in logarithm.

  Hereinafter, the characteristics of the memory element 100 shown in FIG. 1 will be described with reference to FIG. 9, but the voltage value and current value described here are used as an example observed in an actual element. Therefore, this phenomenon is not limited to the following numerical values. Other numerical values may be observed depending on the material and thickness of the film actually used for the element and other conditions. In the following, positive voltage application and negative voltage application are described with reference to voltage application to the upper electrode 104. However, when voltage application to the semiconductor substrate 101 is used as a reference, the relationship between positive and negative is described. Is reversed.

First, in the initial state when the device is manufactured (initial), the resistance of the metal oxide layer 103 is high. As shown in [1] in FIG. 9, the measured voltage value is about 10 ⁻¹¹ A with respect to the voltage application of −0.1 V to the upper electrode 104. However, when a negative voltage exceeding −1 V is applied to the upper electrode 104, a current suddenly flows as indicated by [2] in FIG. This is a phenomenon called “electrofoaming” and “foaming”. After this rapid current flow occurs, a reversible resistance change phenomenon appears.

When a negative voltage is applied to the upper electrode 104 after the above-described “electrofoaming” phenomenon appears, as shown by [3] in FIG. 9, 10 ^{−5 to} −0.1 V at 0 to −2 V. It can be seen that a current of about A flows and the resistance state is low. Further, even when a positive voltage is applied to the upper electrode 104, as shown in [4] in FIG.

However, as shown in [5] in FIG. 9, when a positive voltage exceeding 0.8 V is applied to the upper electrode 104 (voltage application exceeding the second voltage), it becomes difficult for the positive current to flow suddenly and the high resistance state. (Second state). However, in a state where a voltage of 0 to 0.8 V is applied, the metal oxide layer 103 maintains a low resistance state as indicated by [4] in FIG. When a positive voltage exceeding 0.8 V is applied to achieve a high resistance state and then a positive voltage is applied to the upper electrode 104 again, as shown by [6] in FIG. 9, 1 × 10 ^{− It} can be seen that a current of about ⁶ A flows (measured) and is in a high resistance state.

Subsequently, when a negative voltage is applied to the upper electrode 104 as shown in [7] in FIG. 9, a high resistance state is maintained up to about 0 to −0.8 V, but −0. When a negative voltage exceeding 9 V is applied (voltage application exceeding the first voltage), as shown in [8] in FIG. 9, a current flows rapidly and the state transitions to the low resistance state (first state). Thereafter, even if a negative voltage is applied to the upper electrode 104 as indicated by [3] in FIG. 9, a low resistance state of about 10 ⁻⁵ A is maintained at about −0.1V. Subsequently, when a positive voltage is applied to the upper electrode 104, as shown in [4] in FIG. 9, the applied voltage is in a low resistance state up to about + 0.8V, but the applied voltage exceeds + 0.8V. (Application of a voltage exceeding the second voltage) makes a transition to the high resistance state (second state) as indicated by [5] in FIG. As described above, according to the memory element 100 of the present embodiment, a phenomenon that the high resistance state and the low resistance state are switched reversibly is stably observed.

  In addition, according to the memory element 100 of the present embodiment shown in FIG. 1B, the intermediate electrode layer 102 is provided, and the metal oxide layer 103 is formed thereon. The formation of a low dielectric constant film such as the above-described interface layer on the surface is substantially suppressed. For this reason, the above-described change in resistance value is expressed in a more stable state.

  It should be noted here that the rectifying characteristic is greatly different between the current value in the low resistance state when a negative voltage is applied to the upper electrode 104 and the voltage value in the low resistance state when a positive voltage is applied. This is seen in the memory element 100. As shown in FIG. 9, the current value in the low resistance state ([4] low resistance mode) when a positive voltage is applied is the current value in the low resistance state ([3] low resistance mode) when a negative voltage is applied. You can see that it is bigger than In other words, the resistance value in the low resistance state when the negative voltage is applied is larger than the resistance value in the low resistance state when the positive voltage is applied.

  A diode is generally known as an element exhibiting rectification characteristics. A diode is a semiconductor element that allows current to flow only in one direction. A semiconductor originally has this property, but a diode is an element manufactured especially for the purpose of flowing a current in one direction. As a semiconductor material, there are many silicon, but there are other diodes using germanium or selenium.

  The electrical characteristics of a general silicon diode are shown in FIG. FIG. 10A shows a linear display of the vertical axis, and FIG. 10B shows a logarithmic display of the vertical axis. In general, the rectification characteristic appears from a Schottky barrier between a semiconductor and a metal, and FIG. 10 also shows a characteristic that current easily flows when a forward voltage is applied and hardly flows when a reverse voltage is applied. However, the characteristics shown in FIG. 9 are completely different from the rectification characteristics of the diode, and the voltage-current characteristics shown in FIG. 9 are not seen in the electrical characteristics of the diode. It is decisively different.

  The resistance change characteristic shown in FIG. 9 can be used by using the memory element 100 shown in FIG. 1B as the resistance change type memory cell of the memory device of the present embodiment shown in FIG. .

Hereinafter, the operation of the memory element 100 will be described with reference to FIG. 11 showing a part of FIG. First, when a negative voltage exceeding V ⁻ _HL is applied, the metal oxide layer 103 which is a resistance change film of the memory element 100 transitions to a low resistance state. On the other hand, when a positive voltage exceeding V ⁺ _LH is applied, the metal oxide layer 103 transitions to a high resistance state.

The metal oxide layer 103 has two stable states, a low resistance state and a high resistance state, and each state is in any state unless a voltage is applied to the extent that the resistance state does not change. To maintain. In addition, when a sufficiently small voltage (−V or + V) not exceeding V ⁻ _HL is applied, a small current value I _{L: HRS} flows when the selected memory cell is in a high resistance state, and a large current value I in a low resistance state. _{H: LRS} flows. In this way, by applying the read voltage V and observing the current value when the read voltage is applied, the memorized state can be read as the resistance value.

Due to the metal oxide layer 103 having such current-voltage characteristics, in the configuration of the memory device of this embodiment, the contribution of the sneak current flowing in the non-selected memory cell at the time of reading is not a problem as described below. . For example, when reading the information of the selected memory cell M _tg = M _{2, n−1} located at the intersection of the word line W ₂ and the bit line W _n−1 , as shown in FIG. A read voltage V is applied to the word line W ₂ (not shown), a read voltage −V is applied to the bit line B _n-1 from the bit line selection circuit (not shown), and the other word lines W ₁ , W _{1 When 3 to} W _m and the bit lines B _{1 to} B _n-2 and B _n are set to the ground potential, the current I _read flowing through the bit line B _n-1 is changed to the selected memory cell M _tg (the word line W ₂ and the bit line B _n-1 intersection memory cells) and unselected memory cells (all memory cells other than the selected memory cell M _tg ).

At this time, as shown in FIG. 12, the current flowing through the non-selected memory cell has I _ns ⁻ and I _ns ⁺ depending on the direction of the sneak current. I _ns ⁺ is a forward current, and I _ns ⁻ is a reverse current. However, the voltage of the non-selected memory cell is suppressed as compared with the wiring directly connected to the selected memory cell M _tg . Therefore, the state of the selected memory cell M _tg can be easily discriminated regardless of the resistance state of the non-selected memory cell. Further, for example, when the selected memory cell is in a low resistance state, as shown in the characteristic diagram of FIG. 11 (FIG. 9), the resistance value (R _ns ⁺ ) in the forward direction from the rectification characteristic is the resistance in the reverse direction. Smaller than the value (R _ns ⁻ ). For this reason, if there is a reverse direction even at one place in the path of the current that wraps around, the resistance value in this path increases by a digit, making it difficult for the current to flow. Actually, in a matrix structure of m rows × n columns, there is always a reverse current in the path of current passing through non-selected memory cells other than the selected memory cell M _tg , and information on the non-selected memory cells can be ignored. It becomes possible to identify the information of the selected memory cell M _tg .

On the other hand, consider a case where information is written to the selected memory cell M _tg = M _{2, n−1} located at the intersection of the word line W ₂ and the bit line B _n−1 . As shown in FIG. 12B, a write voltage −V _HL is applied from the word line selection circuit (not shown) to the word line _W2, and the write voltage V is applied from the bit selection circuit (not shown) to the bit line B _{n−1. When HL} is applied and the other word lines W ₁ , W _{3 to} W _m and bit lines B _{1 to} B _n-2 and B _n are set to the ground potential, the selected memory cell M _tg is brought into, for example, a low resistance state. can do. At this time, V _HL is about half the voltage of V ⁻ _{HL which changes} from the low resistance state to the high resistance state in the characteristic diagram shown in FIG. 11 (FIG. 9). In this case, the voltage applied to the non-selected memory cell can be made half of the voltage V _LH applied to the selected memory cell M _tg , and information on the non-selected memory cell can be prevented from being erroneously rewritten.

Further, the write voltage V _LH is applied from the word line selection circuit (not shown) to the word line W _2, a write voltage -V _LH is applied from the bit selection circuit (not shown) to the bit line B _n-1, other When the word lines W ₁ , W _{3 to} W _m and the bit lines B _{1 to} B _n−2 and B _n are set to the ground potential, the selected memory cell M _tg can be brought into a high resistance state, for example. At this time, V _LH is a voltage about half of V ⁺ _{LH that} makes a transition from the high resistance state to the low resistance state in the characteristic diagram shown in FIG. 11 (FIG. 9).

  As described above, according to the memory device of the present embodiment, information stored in the selected memory cell M can be read correctly. Further, since there is no need to provide a selection element such as a transistor, the chip area can be efficiently allocated to the memory cell, and the capacity of the memory can be increased. Further, according to the memory device shown in FIG. 1, the information stored in the memory cell M can be read correctly, and the capacity of the memory device can be increased. In the memory device shown in FIG. 1, the word line is connected to the upper electrode 104 side of the memory element 100 and the bit line is connected to the semiconductor substrate 101 side. However, the present invention is not limited to this. Needless to say, may be connected in reverse.

  By the way, in the memory device using the resistance change type memory cell, since the wiring resistance is connected in series to the memory cell, there is a possibility that the selected memory cell cannot be read due to the wiring resistance. Since the current of the memory cell flows through the word line, the bit line, or the plate electrode line connected to the memory cell, the current value observed in the read circuit is observed with these wiring resistances added. Since the memory size is also affected by the width of the wiring, the thinning of the wiring due to the increased capacity of the memory causes an increase in the resistance of the wiring, and the ratio of the wiring resistance to the resistance value observed in the readout circuit becomes larger .

  For example, in a copper wiring having a pattern width of 50 nm and a thickness of 100 nm, if the length occupied by the memory is 1 cm, the wiring resistance is 40 kΩ. Further, the wiring resistance increases as the distance between the selected memory cell and the reading circuit increases. As a result, the wiring resistance changes depending on the position of the selected memory cell, for example, in the range of 0 to 40 kΩ, which makes it difficult to measure the resistance value of the memory cell body and may lead to inaccurate reading. is there.

In order to solve this problem, for example, the influence of the wiring resistance may be removed by utilizing the principle of the four-terminal method. FIG. 13A is a circuit diagram for explaining the principle of the readout circuit. A read voltage −V is applied to the selected word line W from a word line selection circuit (not shown), and a read voltage V is applied to the selected bit line B from a bit line selection circuit (not shown). In reading, the current flowing through the selected memory cell M _tg is measured by the ammeter 1301, and the voltage generated across the selected memory cell M _tg is measured by the voltmeter 1302. The input resistance of the voltmeter 1302 is, for example, 1 MΩ or more, which is larger than the wiring resistance. For this reason, almost no current flows through the selected word line W and the selected bit line B between the selected memory cell M _tg and the voltmeter 1302. As a result, the voltage generated across the selected memory cell M _tg can be accurately obtained. By dividing this voltage by the current value measured by the ammeter 1301, the resistance value of the selected memory cell M _tg can be accurately measured without being affected by the wiring resistance.

Further, by configuring as shown in FIG. 13B, the same effect as the configuration of FIG. 13A can be obtained. A voltage is applied to the selected word line W by a word line selection circuit (not shown) to turn on the transistor T, and a read voltage −V is applied to the selected bit line B from the bit line selection circuit (not shown). A read voltage V is applied to the selected plate electrode line P from a plate electrode line selection circuit (not shown). The read circuit (not shown) measures the current flowing through the selected memory cell M _tg with the ammeter 1301, measures the voltage generated at both ends of the selected memory cell M _tg with the voltmeter 1302, and calculates the voltage measured with the voltmeter 1302. By dividing by the current measured by the ammeter 1301, the resistance value of the selected memory cell M _tg can be obtained. Thus, by utilizing the principle of the four-terminal method, the influence of the wiring resistance can be removed, and the state of the selected memory cell can be correctly identified.

In the above-described example, the metal oxide layer 103 is composed of Bi, Ti, and oxygen mainly composed of Bi ₄ Ti ₃ O ₁₂ (bismuth titanate), but is not limited thereto. . For example, a material with a perovskite structure, a material with a pseudo-ilmenite structure, a material with a tungsten bronze structure, a material with a bismuth layer structure, or a metal oxide containing at least two metals with a pyrochlore structure It may be done.

Specifically, a metal oxide composed of lanthanum, titanium, and oxygen (La ₂ Ti ₂ O ₇ ), a metal oxide composed of barium, titanium, and oxygen (BaTiO ₃ ), a metal oxide composed of lead, titanium, and oxygen (PbTiO ₃ ). ₃ ), a metal oxide composed of lead, zirconia, titanium and oxygen (Pb (Zr _1-x Ti _x ) O ₃ ), a metal oxide composed of lead, lanthanum, zirconia, titanium and oxygen ((Pb _1-y La _y ) (Zr _1-x Ti _x ) O ₃ ) and the like.

  In the description of the manufacturing method using FIG. 3, after forming the metal oxide layer 103, the processing chamber for forming the metal oxide layer 103 and the layer serving as the upper electrode 104 was once taken out to the atmosphere. You may connect with a vacuum conveyance chamber by continuous processing. As a result, the semiconductor substrate 101 to be processed can be transported in a vacuum, and is less susceptible to disturbances such as moisture, leading to improved film quality and interface characteristics.

  Further, as disclosed in Japanese Patent Application Laid-Open No. 2003-077911, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the characteristics. Further, after forming each layer, as shown in Japanese Patent Application Laid-Open No. 2004-273730, annealing may be performed in an appropriate gas atmosphere to improve the characteristics of the formed layer. As a result of experiments by the inventors, if the thickness of the metal oxide layer 103 is 10 to 100 nm, the function of maintaining two states in the memory element 100 shown in FIG. 1B (memory operation) Was confirmed.

1A is a circuit diagram equivalently showing a configuration of a memory device according to an embodiment of the present invention, and FIG. 2B is a configuration diagram showing a configuration of a memory element 100; It is a block diagram which shows the structural example of an ECR sputtering apparatus. FIG. 10 is a process diagram for describing the manufacturing method example of the memory element 100 in the embodiment. It is the characteristic view which showed the film-forming speed | rate and refractive index change of the metal oxide layer with respect to the substrate temperature in sputtering film-forming. It is a block diagram which shows typically the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is a microscope picture which shows the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is the microscope picture obtained by the cross-sectional observation by the transmission electron microscope of the metal oxide layer which consists of Bi, Ti, and oxygen formed on the silicon substrate using the ECR sputtering method in a low temperature region of 180 ° C. or lower. It is a block diagram for demonstrating the state of the microscope picture shown in FIG. FIG. 6 is a characteristic diagram showing a result of observing a current when a voltage is applied between the semiconductor substrate 101 and the upper electrode 104 of the memory element 100 according to the embodiment using an ammeter. It is explanatory drawing which shows the electrical property of a silicon diode. FIG. 6 is a characteristic diagram showing a result of observing a current when a voltage is applied between the semiconductor substrate 101 and the upper electrode 104 of the memory element 100 according to the embodiment using an ammeter. 3 is a circuit diagram equivalently showing the configuration of the memory device according to the exemplary embodiment of the present invention; FIG. It is a circuit diagram for demonstrating the principle of a read-out circuit. It is an equivalent circuit diagram showing a basic configuration of a conventional memory device using a resistance change type memory cell. FIG. 14 is an explanatory diagram for describing an operation example of the memory device having the circuit configuration illustrated in FIG. 13. FIG. 14 is an explanatory diagram for describing an operation example of the memory device having the circuit configuration illustrated in FIG. 13. 1 is a circuit diagram showing a basic configuration of a conventional memory device including one transistor and one resistance element. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Memory element, 101 ... Semiconductor substrate, 102 ... Intermediate electrode layer, 103 ... Metal oxide layer, 104 ... Upper electrode, 105 ... Ohmic contact, 110 ... Word line selection circuit, 111 ... Bit line selection circuit, 112 ... Reading Circuit 112, M... Memory cell.

Claims (11)

A memory device composed of a plurality of memory elements in which information is stored by a change in electrical resistance,
The memory element is
A semiconductor substrate composed of a semiconductor;
An intermediate electrode layer formed on the semiconductor substrate;
A metal oxide layer that is formed on the intermediate electrode layer and changes its electrical resistance;
A memory device comprising: an upper electrode formed on the metal oxide layer. The memory device according to claim 1.
The memory device has a rectifying characteristic in which a current in one direction flows more easily than a current in the other direction. The memory device according to claim 1 or 2,
A plurality of word lines connected to one end of each of the memory elements;
A plurality of bit lines connected to the other end of each of the memory elements;
Word line selection means for applying a read voltage or a write voltage to the selected word line;
Bit line selection means for applying a read voltage or a write voltage to the selected bit line;
A memory device, comprising: a reading unit that reads a resistance value of the memory element connected to the selected word line and the selected bit line with a current value flowing through the selected bit line. The memory device according to claim 3.
The reading means simultaneously detects a current flowing through the memory element and a voltage generated in the memory element, and reads a resistance value of the memory element by comparing the detected voltage and current. apparatus. The memory device according to claim 1,
The metal oxide layer includes a base layer composed of at least a first metal and oxygen, and a plurality of fine particles composed of the first metal, the second metal, and oxygen and dispersed in the base layer. A memory device comprising: 6. The memory device according to claim 5, wherein
The memory device, wherein the fine particles are amorphous. The memory device according to claim 5 or 6,
The memory device, wherein the base layer is composed of the first metal, the second metal, and oxygen, and has a smaller composition ratio of the second metal compared to the stoichiometric composition. The memory device according to claim 5 or 6,
The memory device, wherein the base layer is made of the first metal, the second metal, and oxygen and is amorphous. The memory device according to claim 1,
The metal oxide layer is
When a voltage exceeding the first voltage value is applied, the first state having the first resistance value is obtained.
The memory device, wherein a second state having a second resistance value higher than the first resistance value is obtained by applying a voltage exceeding a second voltage value having a polarity different from that of the first voltage. The memory device according to claim 1,
The memory device, wherein the metal oxide layer is formed at 30 ° C. or higher and lower than 180 ° C. by a sputtering method. The memory device according to claim 1,
The first metal is titanium, the second metal is bismuth, and the base layer is in an amorphous state composed of a layer containing excess titanium compared to the stoichiometric composition. Memory device.