JP5046451B2 - Method for manufacturing semiconductor display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor display device having a circuit formed of a thin film transistor (hereinafter abbreviated as TFT) and a manufacturing method thereof. As the semiconductor display device, for example, there are electro-optical devices such as a liquid crystal display and an EL (electroluminescence) display constituted by TFTs.
[0002]
[Prior art]
In recent years, active matrix liquid crystal display technology using TFTs has attracted attention. The active matrix display is more advantageous than the passive matrix display in terms of response speed, viewing angle, and contrast, and has become the mainstream of current notebook personal computers and liquid crystal televisions.
[0003]
A TFT generally uses amorphous silicon or polycrystalline silicon as a channel layer. In particular, a polycrystalline silicon TFT manufactured by a low-temperature process (generally 600 ° C. or less) has a low electric field and a large area, and at the same time, electrons or holes have a large electric field mobility. As a feature, it is possible to achieve integration of not only the transistors for the driver but also the driver, which is a peripheral circuit, and development has been promoted by each liquid crystal display manufacturer.
[0004]
However, in the case of a polycrystalline silicon TFT, when driven continuously, degradation such as a decrease in mobility and on-current (current that flows when the TFT is on) and an increase in off-current (current that flows when the TFT is off). A phenomenon may be observed, which is a big problem in reliability. This phenomenon is called a hot carrier phenomenon, and is known to be a work of hot carriers generated by a high electric field near the drain.
[0005]
By the way, this hot carrier phenomenon is a phenomenon first discovered in a MOS transistor. For this reason, various basic studies have been conducted so far as measures against hot carriers. In MOS transistors having a design rule of 1.5 μm or less, LDD (Lightly-Doped) is used as a measure against hot carrier phenomenon due to a high electric field near the drain. Abbreviation of -Drain) structure is adopted. In the LDD structure, a low-concentration impurity region (n-region) is provided at the drain end using the sidewall of the gate sidewall, and the concentration of the electric field in the vicinity of the drain is reduced by providing a gradient in the impurity concentration of the drain junction. Yes.
[0006]
In the (but) LDD structure, the drain breakdown voltage is considerably improved as compared with the single drain structure, but the drain current is reduced because the resistance of the low concentration impurity region (n− region) is large. In addition, there is a high electric field region directly under the sidewall, where impact ionization is maximized and hot electrons are injected into the sidewall, so that the low concentration impurity region (n− region) is depleted and the resistance is further increased. The degradation mode peculiar to the LDD that becomes a problem is a problem. As the channel length is reduced, the above problem has become apparent. Therefore, in a MOS transistor having a thickness of 0.5 μm or less, a structure for overcoming this problem overlaps with the end portion of the gate electrode to form a low-concentration impurity region (n A GOLD (abbreviation of Gate-Overlapped LDD) structure that forms a region is devised and adopted.
[0007]
Against this background, the adoption of the LDD structure and the GOLD structure in the polycrystalline silicon TFT which is a constituent element of the liquid crystal display is studied for the purpose of relaxing the high electric field in the vicinity of the drain as in the MOS transistor. Yes. In the case of the LDD structure, a low-concentration impurity region (n− region) is formed in the polycrystalline silicon layer corresponding to the outer region of the gate electrode, and a high-concentration impurity region (n + region) serving as a source / drain region is formed outside thereof. However, the effect of suppressing off-current is high, but the effect of suppressing hot carriers due to electric field relaxation near the drain is small. In the case of one GOLD structure, the low concentration impurity region (n− region) of the LDD structure is formed so as to overlap with the end portion of the gate electrode, and the hot carrier suppressing effect is large as compared with the LDD structure. Has the disadvantage of becoming larger.
[0008]
In addition, as a study example of the GOLD structure in the n-channel type polycrystalline silicon TFT, there is, for example, “Mutuko Hatano, Hajime Akimoto and Takesi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997”, and the basic characteristics of the GOLD structure TFT Is disclosed. The basic structure of the GOLD structure TFT is that a gate electrode and an LDD side wall are formed of polycrystalline silicon, and an active layer (formed of polycrystalline silicon) immediately below the LDD side wall is a low concentration impurity region (electric field relaxation region). n-region) and a high-concentration impurity region (n + region) which is a source region or a drain region is formed outside thereof. The basic characteristics are that, compared with a normal LDD structure TFT, a large drain current can be obtained along with the relaxation of the drain electric field, and the drain avalanche hot carrier (Drain-Avalanche-Hot-Carrier) suppression effect is large. It has been.
[0009]
[Problems to be solved by the invention]
A semiconductor display device such as a liquid crystal display composed of polycrystalline silicon TFTs is composed of a pixel region and a peripheral circuit which is a drive circuit, and the TFT characteristics required for each circuit are different. For example, an LDD structure polycrystalline silicon TFT having a large effect of suppressing off-current is suitable for the pixel region, and a GOLD structure polycrystalline silicon TFT having a high hot carrier resistance is suitable for a peripheral circuit as a drive circuit. From the viewpoint of improving the performance of the semiconductor display device, it is preferable that the pixel region is composed of an LDD structure polycrystalline silicon TFT and the peripheral circuit as a drive circuit is composed of a GOLD structure polycrystalline silicon TFT, but the manufacturing process is complicated. Therefore, an increase in manufacturing costs and a decrease in yield are major issues.
[0010]
An object of the present invention is to provide a semiconductor display device and a manufacturing method thereof that can solve the above-described problems.
[0011]
[Means for solving the problems]
When a semiconductor display device such as a liquid crystal display is configured with a polycrystalline silicon TFT having both hot carrier resistance of the GOLD structured polycrystalline silicon TFT and an off-current suppressing effect of the LDD structured polycrystalline silicon TFT, the pixel region and the drive circuit In the peripheral circuit, it is not necessary to separately form the GOLD structure and the LDD structure, and the manufacturing process can be simplified.
[0012]
A structural feature of the GOLD structure polycrystalline silicon TFT is that a low concentration impurity region (n− region or p− region) existing inside a high concentration impurity region (n + region or p + region) which is a source region or a drain region is It overlaps with the gate electrode. A structural feature of the LDD structure polycrystalline silicon TFT is that the low-concentration impurity region (n-region or p-region) does not overlap the gate electrode. Therefore, a TFT structure having both a low-concentration impurity region (defined as Lov region) overlapping with the gate electrode and a low-concentration impurity region (defined as Loff region) not overlapping with the gate electrode was examined. (Since the TFT having this structure is a kind of GOLD structure, it is hereinafter referred to as a GOLD structure).
[0013]
FIG. 1 shows the main steps of forming the GOLD structure polycrystalline silicon TFT. In the figure, the gate electrode has a two-layer structure of a first layer gate electrode 104 having a small thickness and a large width and a second layer gate electrode 105 having a large thickness and a small width. That is, the first layer gate electrode 104 is longer in the channel direction than the second layer gate electrode 105. The substrate structure on the lower side of the gate electrode is a substrate structure in which a semiconductor layer 102 made of a polycrystalline silicon film and a gate insulating film 103 are stacked on a glass substrate 101, and the first layer gate electrode 104 is formed on the substrate. And the second-layer gate electrode 105 is formed. Further, a high concentration impurity region (n + region or p + region) 106 which is a source region or a drain region is formed in the semiconductor layer 102. Note that the substrate used here is not limited to the glass substrate 101, but may be any transparent insulating substrate having heat resistance (see FIG. 1A).
[0014]
Next, a negative resist having a predetermined thickness is formed, and exposure processing is performed from the back surface of the substrate using the first layer gate electrode 104 as a mask. Since the first layer gate electrode 104 is made of a conductive metal material, it has the property of shielding exposure light from the back surface. However, the glass substrate 101, the semiconductor layer 102 made of a polycrystalline silicon film, and the gate insulating film 103 are It has translucency. Therefore, in the developing process, the negative resist film in the region shielded from light by the first layer gate electrode 104 is dissolved in the developer, and the negative resist film in the region not shielded from light becomes insoluble in the developer. Is formed. At this time, since the boundary between the light shielding region and the non-light shielding region is uniquely determined by the end portion of the first layer gate electrode 104, the negative resist pattern 107 is formed in a self-aligning manner using the first layer gate electrode 104 as a mask. The developed negative resist pattern 107 is baked to form a final negative resist pattern 107 (see FIG. 1B).
[0015]
Next, low-concentration ion implantation of n-type or p-type impurities is performed on the semiconductor layer 102 made of a polycrystalline silicon film corresponding to the region where the first layer gate electrode 104 is exposed. By this low-concentration ion implantation of n-type or p-type impurities, a low-concentration impurity region (n− region or p− region) 108 that is a Lov region is formed. At this time, since the mask for ion implantation is composed of the negative resist pattern 107 and the thick second layer gate electrode 105, the ability to block implanted ions is extremely high, and the acceleration voltage and ion implantation amount during ion implantation are reduced. By selecting appropriately, an impurity having an appropriate concentration can be independently ion-implanted by through doping only into the semiconductor layer 102 corresponding to the exposed region of the first layer gate electrode 104 (see FIG. 1-C).
[0016]
Here, the definition of the term ion implantation is clarified. In general, the term ion implantation is applied when implanting mass-separated impurity ions, and ion doping when implanting impurity ions that have not been mass-separated. In a broad sense, the process of introducing impurities into the crystalline silicon film is defined as ion implantation.
[0017]
Next, after removing the negative resist pattern 107, low-concentration ion implantation of n-type or p-type impurities is performed on the semiconductor layer 102 corresponding to the outside of the first layer gate electrode 104. By this ion implantation, a low-concentration impurity region (n−− region or p−− region) 109 which is a Loff region is formed. At this time, ions are also implanted into the high-concentration impurity region (n + region or p + region) 106 that is already formed as source / drain regions, but there is almost no influence because the amount of ion implantation is small. Further, the low concentration impurity region (n-region or p-region) 108, which is the Lov region below the first layer gate electrode 104, is simultaneously ion-implanted through the first layer gate electrode 104 (through doping). Since most of the implanted ions are blocked by the first layer gate electrode 104, the substantial amount of implanted ions can be suppressed to a level with no problem. In this case, the ion implantation is performed after the negative resist pattern 107 is removed. However, the ion implantation is basically the same even if it is performed at the stage of FIG. 1-A (see FIG. 1-D).
[0018]
Through the above steps, a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region can be formed. FIG. 2 shows the result of examination on the TFT characteristics of the GOLD structure polycrystalline silicon TFT formed here. Figure 2 shows the mobility (μ _FE ) The relationship between the deterioration rate and the amount of n-type impurity (P ions) implanted into the Lov region, and the relationship between the off-current and the amount of n-type impurity (P ions) implanted into the Loff region. The evaluation was performed under the condition that both the dimensions of the regions were the same at about 0.7 μm. Here, as an evaluation method for hot carrier resistance, mobility (μ _FE ) Evaluation was made using the deterioration rate as an index. The black points and white points in FIG. 2 are the results related to the Lov region and the Loff region, respectively. As can be seen from this figure, mobility (μ _FE ) To reduce the deterioration rate, 0.8 × 10 ¹⁴ ions / cm ² ~ 1.7 × 10 ¹⁴ ions / cm ² A P ion implantation amount of about a degree is necessary, and in order to reduce the off-current, 1 × 10 6 in the Loff region. ¹³ ions / cm ² It can be seen that a P ion implantation amount of a certain degree is necessary. As a result of this study, mobility (μ _FE ) It is possible to form a GOLD structure polycrystalline silicon TFT capable of achieving both a reduction in degradation rate and a reduction in off current, that is, a GOLD structure polycrystalline silicon TFT having both hot carrier resistance and an off current suppressing effect. This was confirmed (see FIG. 2).
[0019]
The structure of the GOLD structure polycrystalline silicon TFT used in this experiment will be described below. The semiconductor layer in which the source region or the drain region is formed is a polycrystalline silicon film with a thickness of 50 nm, the gate insulating film is a silicon oxynitride film with a thickness of 110 nm, the first layer gate electrode is a TaN film with a thickness of 30 nm, Each layer gate electrode is composed of a W film having a thickness of 370 nm. In addition, ion implantation was examined using an ion doping apparatus in which ions are implanted in a mass unseparated state (see FIG. 2).
[0020]
Next, FIG. 15 shows a result of examination by simulation on the characteristics of the n-channel GOLD structure polycrystalline silicon TFT. FIG. 15-A is simulation data of the maximum electron temperature in the vicinity of the drain-channel junction when the P ion implantation amount into the Lov region is varied. From this result, the amount of P ion implantation into the Lov region is 1.5 × 10 5. ¹⁴ ions / cm ² In this case, the result that the electron temperature is minimized was obtained. This is because the amount of P ion implantation into the Lov region is 1.5 × 10 5. ¹⁴ ions / cm ² In this case, it is suggested that the hot carrier generation rate is minimized, and the above experimental results are almost compatible. FIG. 15-B shows that the amount of P ion implantation into the Lov region is 1.5 × 10 5. ¹⁴ ions / cm ² This is simulation data of the maximum electron temperature and the off-current (Ioff) in the vicinity of the drain-channel junction when the amount of P ion implantation into the Loff region is varied in a fixed state. From this result, the amount of P ion implantation into the Loff region is 1.5 × 10 5. ¹³ ions / cm ² To 0.75 × 10 ¹³ ions / cm ² As a result, both the maximum electron temperature and the off-current (Ioff) in the vicinity of the drain-channel junction were drastically reduced. In the above experimental results, the off-current (Ioff) decreases linearly in proportion to the decrease in the amount of P ion implantation into the Loff region, but there is no major contradiction when variations are considered. Think of things. On the other hand, regarding the on-current (Ion), as shown in FIG. 15C, the on-current (Ion) decreases in proportion to the amount of P ion implantation into the Loff region decreasing. Injection amount 0.75 × 10 ¹³ ions / cm ² Even in this case, the on-current (Ion) is about 50 μA and the on-current (Ion) is slightly small, but it can be applied as a peripheral circuit (see FIG. 15).
[0021]
Therefore, the effectiveness of the n-channel GOLD structure polycrystalline silicon TFT was also confirmed from the simulation results shown in FIG. Here, a supplementary explanation will be given below for the device structure, etc., which is a prerequisite for this simulation. The structure of the GOLD structure polycrystalline silicon TFT is as follows: W / L = 8/6 μm, Lov region = Loff region = 0.75 μm, a polycrystalline silicon film having a film thickness of 50 nm as a silicon film which is a formation layer of source / drain regions, etc. Suppose a silicon oxynitride film (dielectric constant = 4.1) having a thickness of 110 nm as the gate insulating film, a TaN film having a thickness of 30 nm as the first layer gate electrode, and a W film having a thickness of 370 nm as the second layer gate electrode. Further, simulation was performed by adjusting the impurity profile of SIMS analysis data as channel doping and impurity ion implantation (ion doping method) into the source / drain regions. In this simulation, since the carrier activation rate is unknown, the simulation is performed by artificially setting the activation rate to 20%. In addition, since direct evaluation of hot carrier reliability is impossible in simulation, the maximum electron temperature (equivalent to electron kinetic energy) at the drain-channel junction is calculated, and hot carrier evaluation is performed indirectly. ing.
[0022]
What is important here is that, in order to form a GOLD structure polycrystalline silicon TFT having both hot carrier resistance and an off-current suppressing effect, the appropriate values of the impurity concentrations in the Lov region and the Loff region are different from each other. It is necessary to control. For this reason, in the formation process of the GOLD structure polycrystalline silicon TFT, the ion implantation into the Lov region is performed independently of the ion implantation into the Loff region by using a negative resist pattern formed in a self-aligned manner as a mask. Is.
[0023]
In the present invention, as already described, the negative resist pattern 107 is formed in a self-aligning manner using the first layer gate electrode 104 as a mask by a combination of a negative resist and a back exposure method. Here, it is also possible to form a resist pattern by a normal photolithography process using a positive resist and an exposure apparatus, but in this case, since self-alignment technology is not applied, overlay depending on the alignment accuracy of the exposure apparatus is performed. An error occurs, and a minute gap is generated between the first layer gate electrode 104 and the resist pattern. As a result, at the time of low concentration ion implantation in the next process, there is a possibility that ions are implanted simultaneously into the region of the semiconductor layer 102 corresponding to the minute gap between the first layer gate electrode 104 and the resist pattern. The application of a normal photolithography process that does not utilize is problematic. In order to avoid this problem, in the present invention, a combination of a negative resist and a back exposure method is applied for forming a resist pattern.
[0024]
The features of the present invention are briefly described below. In manufacturing a semiconductor display device such as a liquid crystal display, the present invention includes a GOLD structure polycrystalline silicon TFT having a pixel region and a peripheral circuit which is a driving circuit as both a Lov region and a Loff region. It is characterized by realizing both simplification and performance improvement of a semiconductor display device.
[0025]
In the present invention, in the formation of the GOLD structure polycrystalline silicon TFT having both the Lov region and the Loff region, ion implantation into the Lov region is independently performed using a negative resist pattern formed in a self-aligned manner by the backside exposure method as a mask. By doing so, the impurity concentration in the Lov region and the Loff region can be independently controlled. This enables formation of a GOLD structure polycrystalline silicon TFT having both hot carrier resistance and an off-current suppressing effect.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
A method for forming a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region will be described with reference to FIG.
[0027]
In the substrate structure used in the present embodiment, a semiconductor layer 202 made of a polycrystalline silicon film, a gate insulating film 203, a first layer gate electrode film 204, and a second layer gate electrode film 205 are each formed on a glass substrate 201 with a predetermined thickness. Use a laminated substrate. A resist pattern 206 for forming a gate electrode is formed on the substrate having the above structure (see FIG. 3A).
[0028]
Next, a first step of dry etching is performed using the resist pattern 206 as a mask. By this dry etching process for a predetermined time, only the second layer gate electrode film 205 is isotropically etched to form the second layer gate electrode 208 having a tapered shape. At this time, the resist pattern 206 used as a mask for dry etching is reduced in resist film due to the problem of the selectivity between the resist film and the second-layer gate electrode film 205 which is the film to be etched. It is deformed into a shape 207 (see FIG. 3-B).
[0029]
Next, the second step of the dry etching process is continuously performed. By this dry etching process for a predetermined time, the first layer gate electrode film 204 is anisotropically etched using the second layer gate electrode 208 having the tapered shape formed in the first step process as a mask, and the first layer gate is formed. An electrode 211 is formed. During the over-etching process, the underlying gate insulating film 203 is exposed to plasma and slightly etched, so that it is deformed into the shape of the gate insulating film 212 (see FIG. 3C).
[0030]
Next, high-concentration ion implantation of n-type impurities, which is a first ion implantation process, is performed using the gate electrode formed of the first layer gate electrode 211 and the second layer gate electrode 210 as a mask. At this time, P (phosphorus) is used as the n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose is 5 × 10. ¹⁴ ~ 5x10 ¹⁵ ions / cm ² Ion implantation is performed under the following ion implantation conditions. By this first ion implantation process, a high concentration impurity region (n + region) 213 of an n-type impurity serving as a source region or a drain region is formed in the semiconductor layer 202 made of a polycrystalline silicon film corresponding to the outside of the gate electrode. (See FIG. 3-C).
[0031]
Next, the third step of the dry etching process is performed. By the dry etching process for a predetermined time, both the first layer gate electrode 211 and the second layer gate electrode 210 are isotropically etched, and the first layer gate electrode 216 and the second layer gate electrode 215 having a tapered shape are formed. The The resist pattern, which is an etching mask, is further reduced in film thickness and deformed into the shape of the resist pattern 214. In addition, the underlying gate insulating film is further reduced in the region exposed to plasma, and is deformed into the shape of the gate insulating film 217 (see FIG. 3D).
[0032]
Next, the fourth step of the dry etching process is continuously performed. By this dry etching process for a predetermined time, the second layer gate electrode 215 having a tapered shape is anisotropically etched using the resist pattern 214 as a mask to form a second layer gate electrode 218 having a rectangular shape. At this time, as the etching of the second layer gate electrode 218 proceeds, the first layer gate electrode is exposed to the plasma from the end portion, so that the first layer gate electrode 219 becomes thinner as it approaches the end portion. It is formed in a tapered shape. In addition, since the thickness of the base gate insulating film 217 is further reduced in the region exposed to plasma, the gate insulating film 217 is deformed into the shape of the gate insulating film 220. Thereafter, the resist pattern which is an etching mask is removed (see FIG. 3E).
[0033]
Next, a negative resist film having a predetermined thickness is applied and baked to form a negative resist film, and exposure is performed from the back surface of the substrate using the first layer gate electrode 219 as a mask. Since the first layer gate electrode 219 is made of a conductive metal material, the first layer gate electrode 219 has a property of shielding exposure light from the back surface, and a region other than the first layer gate electrode 219 has a light transmitting property. Further, since the semiconductor layer 202 and the gate insulating film 220 are stacked, the exposure light from the back surface cannot be shielded. Therefore, in the next development step, the negative resist film in the region shielded from light by the first layer gate electrode 219 is dissolved in the developer, and the negative resist film in the region not shielded from light becomes insoluble in the developer. A pattern 221 is formed. At this time, since the boundary between the light shielding region and the non-light shielding region is uniquely determined by the end portion of the first layer gate electrode 219, the negative resist pattern 221 is formed in a self-aligned manner using the first layer gate electrode 219 as a mask. Thereafter, baking is performed to form a final negative resist pattern 221 (see FIG. 3F).
[0034]
Next, an n-type impurity that is a second ion implantation process is applied to the semiconductor layer 202 made of a polycrystalline silicon film corresponding to a region where the first layer gate electrode 219 is exposed from the second layer gate electrode 218 (exposed region). Perform low concentration ion implantation. Here, since the negative resist pattern 221 and the thick second layer gate electrode 218 are used as an ion implantation mask, the ability to block implanted ions is extremely high, and the acceleration voltage and ion implantation amount during ion implantation are appropriately set. By selecting, an impurity having an appropriate concentration can be independently ion-implanted by through doping only in the semiconductor layer 202 corresponding to the exposed region of the first layer gate electrode 219. As specific ion implantation conditions, P (phosphorus) is used as an n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose is 0.8 × 10. ¹⁴ ions / cm ² ~ 1.7 × 10 ¹⁴ ions / cm ² Ion implantation is performed under the following conditions. As a result, in the region of the semiconductor layer 202, a low concentration impurity region (n− region) 222 which is a Lov region is formed. Note that the first layer gate electrode 219 has a tapered shape in which the film thickness becomes thinner as it approaches the end of the gate electrode. Therefore, the impurity in the low concentration impurity region (n− region) 222 into which ions are implanted by through doping. There is a concentration gradient in the concentration, and the impurity concentration tends to gradually increase as it approaches the end portion of the first layer gate electrode 219, that is, the high concentration impurity region (n + region) 213 which is the source region or the drain region. (See FIG. 3-G).
[0035]
Next, after removing the negative resist pattern 221, low-concentration ion implantation of n-type impurities is performed on the semiconductor layer 202 corresponding to the outside of the first layer gate electrode 219. By this ion implantation, a low concentration impurity region (n−− region) 223 which is a Loff region is formed. As ion implantation conditions, P (phosphorus) is used as an n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose is 1 × 10. ¹³ ions / cm ² Ion implantation is performed under the following conditions. At this time, ions are also implanted into the high-concentration impurity region (n + region) 213 that is already formed as a source region or a drain region, but there is almost no influence because the amount of ion implantation is small. Further, the low concentration impurity region (n− region) 222, which is the Lov region under the first layer gate electrode 219, is simultaneously ion-implanted through the first layer gate electrode 219 (through doping). Is blocked by the first layer gate electrode 219, the substantial amount of implanted ions can be suppressed to a problem-free level. In this case, the ion implantation is performed after the negative resist pattern 221 is removed. However, even if the ion implantation is performed at the stage of FIG. 3-E, the ion implantation is basically the same (see FIG. 3-H).
[0036]
Through the above steps, a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region can be formed, and the GOLD structure polycrystalline silicon TFT has advantages of both hot carrier resistance and off-current suppression effect. There are features.
[0037]
[Embodiment 2]
Another method for forming a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region will be described with reference to FIG. Although this embodiment is almost the same as Embodiment 1, there is a slight difference in the formation method of the gate electrode. Therefore, this point will be described mainly.
[0038]
In the substrate structure used in this embodiment, a semiconductor layer 302 made of a polycrystalline silicon film, a gate insulating film 303, a first layer gate electrode film 304, and a second layer gate electrode film 305 are each formed on a glass substrate 301 with a predetermined thickness. Use a laminated substrate. A resist pattern 306 for forming a gate electrode is formed on the substrate having the above structure (see FIG. 4-A).
[0039]
Using the resist pattern 306 as a mask, the first and second steps of the dry etching process are successively performed, thereby forming the first layer gate electrode 311 and the second layer gate electrode 310 having a tapered shape. At this time, the resist pattern 306 that is a mask for dry etching is deformed into the shape of the resist pattern 309 after dry etching, and the underlying gate insulating film 303 is deformed into the shape of the gate insulating film 312 due to film thickness reduction (FIG. 4-B and FIG. 4-C).
[0040]
Next, high-concentration ion implantation of n-type impurities, which is a first ion implantation process, is performed using a gate electrode including the first layer gate electrode 311 and the second layer gate electrode 310 as a mask. By this first ion implantation process, a high-concentration impurity region (n + region) 313 of n-type impurities to be a source / drain region is formed (see FIG. 4C).
[0041]
Next, the third step of the dry etching process is performed. By this dry etching process for a predetermined time, the second-layer gate electrode 310 having a tapered shape is anisotropically etched using the resist pattern 309 as a mask to form a second-layer gate electrode 315 having a rectangular shape. At this time, as the etching of the second layer gate electrode 310 proceeds, the first layer gate electrode is exposed to the plasma from the end portion, so that the first layer gate electrode 316 has a thin remaining film as it approaches the end portion. It is formed into a tapered shape. Further, the gate insulating film 312 is also deformed into the shape of the gate insulating film 317 because the thickness of the base gate insulating film 312 is further reduced in the region exposed to plasma (see FIG. 4-D).
[0042]
Next, the fourth step of the dry etching process is continuously performed. By this dry etching process for a predetermined time, the first layer gate electrode 316 exposed from the second layer gate electrode 315 is further thinned by reducing the remaining film thickness of the tapered region, and the end of the tapered region is receded. Thus formed first layer gate electrode 319 is formed. At this time, the dimensions of the first layer gate electrode 319 can be freely adjusted within the range of the tapered region by appropriately changing the processing conditions of the dry etching. Further, the underlying gate insulating film exposed from the first layer gate electrode 319 is further reduced by dry etching, and is deformed into the shape of the gate insulating film 320. Thereafter, the resist pattern which is a mask for dry etching is removed (see FIG. 4-E).
[0043]
Next, a negative resist pattern by backside exposure is formed in a self-aligning manner using the first layer gate electrode 319 as a mask (see FIG. 4-F).
[0044]
Next, low-concentration ion implantation of n-type impurities, which is a second ion implantation process, is performed on the semiconductor layer 302 made of a polycrystalline silicon film corresponding to a region where the first layer gate electrode 319 is exposed from the second layer gate electrode 318 ( Acceleration voltage: 60-100 kV / dose amount: 1 × 10 ¹⁴ ions / cm ² )I do. By this ion implantation process, a low concentration impurity region (n− region) 322 that is a Lov region is formed (see FIG. 4G).
[0045]
After removing the negative resist pattern 321, low-concentration ion implantation of n-type impurities (acceleration voltage: third ion implantation process) is performed on the semiconductor layer 302 made of a polycrystalline silicon film corresponding to the outside of the first layer gate electrode 319. 60-100 kV / dose amount: 1 × 10 ¹³ ions / cm ² )I do. By this ion implantation process, a low concentration impurity region (n−− region) 323 which is a Loff region is formed (see FIG. 4-H).
[0046]
【Example】
[Example 1]
A method for manufacturing an active matrix type liquid crystal display including a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region will be specifically described with reference to FIGS.
[0047]
First, a first layer of silicon oxynitride film 402a and a second layer of silicon oxynitride film 402b having different composition ratios are deposited on a glass substrate 401 by plasma CVD with a thickness of 100 nm, respectively. A base film 402 is formed. The glass substrate 401 used here includes quartz glass, barium borosilicate glass, alumino borosilicate glass, or the like. Next, after depositing an amorphous silicon film 55 nm on the base film 402 (402a and 402b) by plasma CVD, a nickel-containing solution was held on the amorphous silicon film. This amorphous silicon film was dehydrogenated (500 ° C. for 1 hour), then thermally crystallized (550 ° C. for 4 hours), and further subjected to laser annealing to obtain a polycrystalline silicon film. A polycrystalline silicon film thermally crystallized using a catalytic element such as a nickel-containing aqueous solution has a higher electric field effect because crystal grains are oriented in substantially the same direction as a conventional polycrystalline silicon film. In the present specification, it is also called a crystalline silicon film because it has characteristics such as mobility (see FIG. 5-A).
[0048]
Next, the polycrystalline silicon film was patterned by a photolithography process and an etching process to form semiconductor layers 403 to 407. At this time, after forming the semiconductor layers 403 to 407, doping with an impurity element (boron or phosphorus) for controlling Vth of the TFT may be performed. Next, a gate insulating film 408 made of a silicon oxynitride film having a thickness of 110 nm is formed by plasma CVD so as to cover the semiconductor layers 403 to 407, and a first layer made of a TaN film having a thickness of 30 nm is further formed on the gate insulating film 408. A gate electrode film 409 and a second layer gate electrode film 410 comprising a 370 nm thick W film were deposited by sputtering. Here, as a material of the first layer gate electrode film 409 and the second layer gate electrode film 410, a refractory metal that can withstand a later process temperature and a compound containing a refractory metal, such as a metal nitride or a metal silicide, are used. Can be mentioned. In this example, a TaN film was used as the first layer gate electrode film 409 and a W film was used as the second layer gate electrode film 410 (see FIG. 5-A).
[0049]
Resist patterns 411a to 414a for forming a gate electrode and resist patterns 415a to 416a for forming an electrode are formed on the substrate having the above structure by photolithography (see FIG. 5-B).
[0050]
Next, a first step of a dry etching process is performed using the resist patterns 411a to 416a as a mask. By this dry etching process for a predetermined time, only the second layer gate electrode film 410 made of the W film is isotropically etched to form second layer gate electrodes 417 to 420 and second layer electrodes 421 to 422 having tapered shapes. Is done. At this time, the resist patterns 411a to 416a used as masks for dry etching are reduced because of the problem of the selectivity between the resist film and the second-layer gate electrode film (W film) 410 that is the film to be etched. After dry etching, the resist patterns 411b to 416b are deformed (see FIG. 6A).
[0051]
Next, the second step of the dry etching process is continuously performed. By this dry etching process for a predetermined time, the first layer gate electrode film 409 is anisotropically etched using the second layer gate electrodes 417 to 420 having a tapered shape formed in the first step process as a mask, and the first layer gate electrode film 409 is anisotropically etched. Layer gate electrodes 429 to 432 are formed. Further, the first layer gate electrode film 409 is anisotropically etched using the tapered second layer electrodes 421 to 422 as masks, so that first layer electrodes 433 to 434 are formed. At this time, the gate insulating film 408 made of the underlying silicon oxynitride film is reduced by about 20 nm by etching, and the remaining film thickness is about 90 nm. The film of the second layer electrode is also reduced to 423-426, 427-428.
(See FIG. 6-B).
[0052]
Next, a first ion implantation process is performed using the gate electrode composed of the first layer gate electrodes 429 to 432 and the second layer gate electrodes 423 to 426 and the electrode composed of the first layer electrode 433 and the second layer electrode 427 as a mask. High concentration ion implantation of an n-type impurity is performed. At this time, P (phosphorus) is used as the n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose is 5 × 10. ¹⁴ ~ 5x10 ¹⁵ ions / cm ² Ion implantation is performed under the following ion implantation conditions. By this first ion implantation process, high-concentration impurity regions (n + regions) 435 to n-type impurities serving as source / drain regions are formed in the semiconductor layers 403 to 406 made of a polycrystalline silicon film corresponding to the outside of the gate electrode. 438 is formed. On the other hand, in the semiconductor layer 407, which is a formation region of the storage capacitor 505, ions are implanted using the electrode for forming the capacitor as a mask, and a high concentration impurity region (n + region) is formed in a region (exposed region) corresponding to the outside of the electrode. 439 is formed. The impurity concentration of the high concentration impurity regions (n + regions) 435 to 439 is generally 1 × 10 6 in the highest concentration region. ²⁰ ~ 1x10 ^{twenty two} atoms / cm ^Three (See FIG. 6-B).
[0053]
Here, the P element concentrations in the high concentration impurity regions (n + regions) 435 to 439 were examined in detail based on the SIMS analysis data of FIG. FIG. 16 shows a 5% concentration phosphine (PH _Three ) / Hydrogen (H ₂ (1) TaN film (15 nm) / silicon oxide film, (2) TaN film (30 nm) / silicon oxide film, and (3) silicon oxide film are accelerated by an ion doping apparatus. Voltage-current density is 90kV-0.5μA / cm ² Dose amount 1.5 × 10 under the conditions of ¹⁴ ions / cm ² Is SIMS analysis data in the case of ion implantation. Further, in the same figure, the impurity profile in the depth direction is the impurity profile in the silicon oxide film excluding the TaN film. The film structure of the high-concentration impurity regions (n + regions) 435 to 439 is composed of a silicon oxynitride film (residual film thickness of about 90 nm due to etching film reduction) and a polycrystalline silicon film (50 nm thickness) from the surface. The ion stopping ability of the polycrystalline silicon film is almost the same as the ion stopping ability of the silicon oxide film. Therefore, referring to the impurity profile of (3) silicon oxide film substrate in FIG. 16, the impurity concentration of the high concentration impurity region (n + region) 435 to 439, that is, the impurity concentration in the polycrystalline silicon film (50 nm thickness) is examined. did. Dose amount 1.5 × 10 ¹⁴ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is 5 × 10. ¹⁸ ~ 8x10 ¹⁸ atoms / cm ^Three The actual dose amount is 5 × 10 ¹⁴ ~ 5x10 ¹⁵ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is set to 1.7 × 10 6 by proportional calculation. ¹⁹ ~ 2.7 × 10 ²⁰ atoms / cm ^Three It is thought to be about. In actual ion implantation, since the acceleration voltage has a range of 60 to 100 kV, the impurity concentration range is expected to further expand due to the influence of the set acceleration voltage. Considering this point, the range of the impurity concentration of the high concentration impurity regions (n + regions) 435 to 439 is assumed to be a range obtained by multiplying the minimum value by a correction factor of about 0.2 times and the maximum value by about 20 times as the maximum range. Is done. Therefore, the impurity concentration of the high-concentration impurity regions (n + regions) 435 to 439 is 3 × 10 ¹⁸ ~ 5x10 ^{twenty one} atoms / cm ^Three Degree, more preferably 1.7 × 10 ¹⁹ ~ 2.7 × 10 ²⁰ atoms / cm ^Three The degree is estimated (see FIG. 16).
[0054]
Next, the third step of the dry etching process is performed. By this dry etching process for a predetermined time, the second-layer gate electrodes 423 to 426 and the second-layer electrodes 427 to 428 having a taper shape are anisotropically etched using the resist patterns 411c to 416c as masks to form a rectangular second layer. Gate electrodes 440 to 443 and second layer electrodes 444 to 445 are formed. At this time, as the etching of the second layer gate electrodes 423 to 426 and the second layer electrodes 427 to 428 progresses, the first layer gate electrode and the first layer electrode existing therebelow are exposed to plasma from the end portions. Therefore, the first layer gate electrodes 446 to 449 and the first layer electrodes 450 to 451 are formed in a tapered shape in which the remaining film thickness decreases as the end portion is approached. Further, the base gate insulating film is gradually reduced in a region exposed to plasma, and is deformed into a shape of the gate insulating film 452 (see FIG. 7A).
[0055]
Next, the fourth step of the dry etching process is continuously performed. By this dry etching process for a predetermined time, the first layer gate electrodes 446 to 449 exposed from the second layer gate electrodes 440 to 443 are further thinned due to the film thickness reduction of the tapered region, and the tapered region First layer gate electrodes 453 to 456 whose ends are set back are formed. At this time, the dimensions of the first layer gate electrodes 453 to 456 can be freely adjusted within the range of the tapered region by appropriately changing the processing conditions of the dry etching. Similarly, in the exposed first layer electrodes 450 to 451, the remaining film thickness of the tapered region is further reduced by the film reduction, and the first layer electrodes 457 to 458 in which the end portions of the tapered region are set back are formed. . Further, the base gate insulating film is further reduced in thickness by dry etching, and is deformed into the shape of the gate insulating film 459. At this stage, the gate insulating film 459 made of the underlying silicon oxynitride film is further reduced in thickness, with a remaining film thickness of about 50 nm in a thick film area and a remaining film thickness of about 30 nm in a thin film area. It has become. Thereafter, the resist pattern which is a mask for dry etching is removed (see FIG. 7B).
[0056]
Next, a negative resist film having a predetermined thickness is applied and baked to form a negative resist film, and exposure is performed from the back surface of the substrate using the first layer gate electrodes 453 to 456 and the first layer electrodes 457 to 458 as masks. Process. The first layer gate electrodes 453 to 456 and the first layer electrodes 457 to 458 are made of a TaN film having a thickness of 30 nm and have a transmittance of about 14% with respect to light having a wavelength of about 350 to 450 nm (FIG. 11). Therefore, most of the exposure light (representative wavelengths: g-line 436 nm, h-line 405 nm, i-line 365 nm) from the back surface is shielded. On the other hand, the regions other than the first layer gate electrodes 453 to 456 and the first layer electrodes 457 to 458 have a laminated structure of a light-transmitting glass substrate 401, semiconductor layers 403 to 407, and a gate insulating film 459. The exposure light from can not be shielded. Therefore, in the next development process, the negative resist film in the region shielded from light by the first layer gate electrodes 453 to 456 and the first layer electrodes 457 to 458 is dissolved in the developer, and the negative resist in the region not shielded from light. The film becomes insoluble in the developer, and negative resist patterns 460 to 468 are formed. Since the boundary between the light shielding region and the non-light shielding region is uniquely determined by the end portions of the first layer gate electrodes 453 to 456 and the first layer electrodes 457 to 458, the negative resist patterns 460 to 468 have the first layer gate electrode 453 to 456 and the first layer electrodes 457 to 458 are formed in a self-aligning manner. Thereafter, a baking process is performed to form final negative resist patterns 460 to 468 (see FIG. 8A).
[0057]
Next, the first layer gate electrodes 453 to 456 and the first layer electrode 457 are formed on the semiconductor layers 403 to 407 corresponding to the regions exposed from the second layer gate electrodes 440 to 443 and the second layer electrode 444, Low concentration ion implantation of n-type impurities, which is an ion implantation process, is performed. Here, since the negative resist patterns 460 to 468 and the thick second layer gate electrodes 440 to 443 and the second layer electrode 444 are used as a mask for ion implantation, the blocking ability against implanted ions is extremely high. For this reason, by appropriately selecting the acceleration voltage and ion implantation amount at the time of ion implantation, only the regions of the semiconductor layers 403 to 407 corresponding to the exposed regions of the first layer gate electrodes 453 to 456 and the first layer electrode 457 are used. Through doping, ions of appropriate concentration can be independently implanted. As specific ion implantation conditions, P (phosphorus) is used as an n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose is 1 × 10. ¹⁴ ions / cm ² Ion implantation is performed under the following conditions. As a result, low concentration impurity regions (n−regions) 469 to 472 that are Lov regions are formed in the semiconductor layers 403 to 406 for forming the gate electrodes, and low concentration impurity regions (n−regions) are formed in the semiconductor layer 407 for forming the capacitors. ) 473 (not a Lov region because it is not a gate electrode formation region). Note that the first layer gate electrodes 453 to 456 and the first layer electrode 457 have a tapered shape in which the film thickness becomes thinner toward the end of the gate electrode. There is a concentration gradient in the impurity concentration of (n− region) 469 to 473, and the impurity concentration tends to gradually increase as it approaches the high concentration impurity region (n + region) 435 to 439 (FIG. 8). -See A).
[0058]
Here, the P element concentrations in the low-concentration impurity regions (n− regions) 469 to 472 were examined in detail based on the SIMS analysis data of FIG. 16. FIG. 16 shows a 5% concentration phosphine (PH _Three ) / Hydrogen (H ₂ (1) TaN film (15 nm) / silicon oxide film, (2) TaN film (30 nm) / silicon oxide film, and (3) silicon oxide film are accelerated by an ion doping apparatus. Voltage-current density is 90kV-0.5μA / cm ² Dose amount 1.5 × 10 under the conditions of ¹⁴ ions / cm ² Is SIMS analysis data in the case of ion implantation. The film structure of the low-concentration impurity regions (n− regions) 469 to 472 includes first layer gate electrodes 453 to 456 (TaN film thickness: about 0 to 30 nm for etching film reduction) and a silicon oxynitride film (from the surface). 110 nm thickness) and a polycrystalline silicon film (50 nm thickness), the ion blocking ability of the silicon oxynitride film and the polycrystalline silicon film is almost the same as that of the silicon oxide film. Therefore, referring to the impurity profiles of (2) TaN film (30 nm) / silicon oxide film and (3) silicon oxide film in FIG. 16, the impurity concentration of the low concentration impurity regions (n− regions) 469 to 472, that is The impurity concentration in the crystalline silicon film (thickness 50 nm) was examined. Dose amount 1.5 × 10 ¹⁴ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is 1.5 × 10 5. ¹⁷ ~ 8x10 ¹⁸ atoms / cm ^Three The actual dose is 1 × 10 ¹⁴ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is set to 1 × 10 5 by proportional calculation. ¹⁷ ~ 5.3 × 10 ¹⁸ atoms / cm ^Three It is thought to be about. In actual ion implantation, since the acceleration voltage has a range of 60 to 100 kV, the impurity concentration range is expected to further expand due to the influence of the set acceleration voltage. Considering this point, the impurity concentration range of the low-concentration impurity regions (n−regions) 469 to 472 is a range obtained by multiplying the minimum value by 0.2 times and the maximum value by a correction factor of about 5 times as the maximum range. is assumed. Therefore, the impurity concentration of the low-concentration impurity regions (n− regions) 469 to 472 is 2 × 10 ¹⁶ ~ 2.7 × 10 ¹⁹ atoms / cm ^Three , More preferably 1 × 10 ¹⁷ ~ 5.3 × 10 ¹⁸ atoms / cm ^Three The degree is estimated (see FIG. 16).
[0059]
Next, after removing the negative resist patterns 460 to 468, the semiconductor layers 403 to 407 corresponding to the outside of the first layer gate electrodes 453 to 456 and the first layer electrode 457 are n-type which is a third ion implantation process. Perform low concentration ion implantation of impurities. By this ion implantation, low-concentration impurity regions (n−− regions) 474 to 477 which are Loff regions are formed in the semiconductor layers 403 to 406 for forming the gate electrodes, and low-concentration impurity regions (n—) are formed in the semiconductor layer 407 for forming the capacitors. n--region) 478 is formed. At this time, P (phosphorus) is used as the n-type impurity, the acceleration voltage is 60 to 100 kV, and the dose amount is 1 × 10. ¹³ ions / cm ² Ion implantation is performed under the following conditions. Further, although ions are simultaneously implanted into the already formed high concentration impurity regions (n + regions) 435 to 439, there is almost no influence because the amount of ion implantation is small. Also, the already formed low-concentration impurity regions (n− regions) 469 to 473 are simultaneously ion-implanted through the first layer gate electrodes 453 to 456 and the first layer electrode 457 (through doping). Is blocked by the first layer gate electrodes 453 to 456 and the first layer electrode 457, so that the substantial amount of implanted ions can be suppressed to a level with no problem. Here, the ion implantation is performed after removing the negative resist patterns 460 to 468. However, the ion implantation is basically the same even if the fourth step of the dry etching is completed in FIG. 7B. Yes (see FIG. 8-B).
[0060]
Here, the P element concentration in the low concentration impurity regions (n−− regions) 474 to 477 was examined in detail based on the SIMS analysis data of FIG. 16. FIG. 16 shows a 5% concentration phosphine (PH _Three ) / Hydrogen (H ₂ (1) TaN film (15 nm) / silicon oxide film, (2) TaN film (30 nm) / silicon oxide film, and (3) silicon oxide film are accelerated by an ion doping apparatus. Voltage-current density is 90kV-0.5μA / cm ² Dose amount 1.5 × 10 under the conditions of ¹⁴ ions / cm ² Is SIMS analysis data in the case of ion implantation. The low-concentration impurity regions (n−− regions) 474 to 477 are composed of a silicon oxynitride film (estimated to have a remaining film thickness of about 50 nm due to etching film reduction) and a polycrystalline silicon film (50 nm thickness) from the surface. Since the ion stopping ability of the silicon oxynitride film and the polycrystalline silicon film is almost the same as the ion stopping ability of the silicon oxide film, the low concentration impurity is referred to by referring to the impurity profile of (3) silicon oxide film substrate in FIG. The impurity concentration in the region (n−− region) 474 to 477, that is, the impurity concentration in the polycrystalline silicon film (50 nm thickness) was examined. Dose amount 1.5 × 10 ¹⁴ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is 7 × 10. ¹⁸ ~ 8x10 ¹⁸ atoms / cm ^Three The actual dose amount is 1 × 10 ¹³ ions / cm ² In this case, the impurity concentration in the polycrystalline silicon film is determined to be 4.7 × 10 6 by proportional calculation. ¹⁷ ~ 5.3 × 10 ¹⁷ atoms / cm ^Three It is thought to be about. In actual ion implantation, since the acceleration voltage has a range of 60 to 100 kV, the impurity concentration range is expected to further expand due to the influence of the set acceleration voltage. Considering this point, the impurity concentration range of the low-concentration impurity regions (n−− regions) 474 to 477 is a range obtained by multiplying the minimum value by a correction factor of about 0.01 times and the maximum value by about 5 times as the maximum range. Is assumed. Therefore, the impurity concentration of the low-concentration impurity regions (n−− regions) 474 to 477 is 4.7 × 10 7. ¹⁵ ~ 2.7 × 10 ¹⁸ atoms / cm ^Three , More preferably 4.7 × 10 ¹⁷ ~ 5.3 × 10 ¹⁷ atoms / cm ^Three The degree is estimated (see FIG. 16).
[0061]
Next, resist patterns 479 to 481 are formed by photolithography to form a resist opening in the region of the p-channel TFT 502 in the driving circuit 506 and the region of the storage capacitor 505 in the pixel region 507 (FIG. 9). -See A).
[0062]
Using the resist patterns 479 to 481 as a mask, high-concentration ion implantation of p-type impurities, which is a fourth ion implantation process, is performed. The semiconductor layer 404, which is a region where the p-channel TFT 502 is formed, has a B-type impurity which is a p-type impurity imparting a conductivity type opposite to the one conductivity type using the first layer gate electrode 454 and the second layer gate electrode 441 as a mask. (Boron) or the like is ion-implanted. As a result, a high-concentration impurity region (p + region) 482 serving as a source / drain region is formed in a region corresponding to the outside of the first layer gate electrode 454, and the region where only the first layer gate electrode 454 is exposed is reduced by through doping. Concentration impurity regions (p− regions) 483 are formed simultaneously. The semiconductor layer 404 is already ion-implanted with P (phosphorus), which is an n-type impurity, but the concentration of B (boron) is 2 × 10. ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three Therefore, a high concentration impurity region (p + region) 482 and a low concentration impurity region (p− region) 483 of a p-type impurity are formed, and can function as a p-channel TFT 502. it can. Also in the semiconductor layer 407, which is the formation region of the storage capacitor 505, a high-concentration impurity region (p + region) 484 of a p-type impurity is formed in a region corresponding to the outside of the first layer gate electrode 457. A low-concentration impurity region (p− region) 485 is simultaneously formed in the region where only the layer gate electrode 457 is exposed by through doping. In the storage capacitor 505 region, the same structure as that of the p-channel TFT 502 is formed. However, since it is a capacitor formation region, it is not a TFT structure (see FIG. 9A).
[0063]
Next, after removing the resist patterns 479 to 481, a first interlayer insulating film 486 made of a silicon oxynitride film having a thickness of 150 nm is deposited by plasma CVD. Thereafter, thermal annealing is performed at 550 ° C. for 4 hours to thermally activate the impurity elements (n-type impurity and p-type impurity) implanted into the semiconductor layers 403 to 407. In this embodiment, Ni (nickel), which is a catalyst for crystallization of the semiconductor layers 403 to 407, is converted into an n-type impurity simultaneously with the thermal activation treatment of the impurity element in order to reduce the off-current value and improve the field effect mobility. Gettering is performed with a high concentration of P (phosphorus). By this gettering treatment, the nickel (Ni) concentration in the semiconductor layers 403 to 407 is reduced. The polycrystalline silicon TFT manufactured by this method has high field effect mobility, and can exhibit good electrical characteristics such as a decrease in off-current value. The thermal activation process may be performed before the deposition of the first interlayer insulating film 486. However, when the heat resistance of the wiring material such as the gate electrode is weak, the thermal activation process is performed after the deposition of the first interlayer insulating film 486. It is preferable to implement. Thereafter, in order to terminate dangling bonds in the semiconductor layers 403 to 407, a hydrogenation treatment at 410 ° C. for 1 hour is performed in a nitrogen atmosphere containing 3% hydrogen (see FIG. 9B).
[0064]
Next, a second interlayer insulating film 487 made of an acrylic resin film having a thickness of 1.6 μm is formed on the first interlayer insulating film 486. Thereafter, contact holes are formed in the second interlayer insulating film 487 by photolithography and dry etching. At this time, the contact hole is formed so as to connect the electrodes (first layer electrode 458 and second layer electrode 445) functioning as source wiring and the high concentration impurity regions 435, 437, 438, 482, 484 ( (See FIG. 10-A).
[0065]
Next, metal wirings 488 to 493 are formed to be electrically connected to the high concentration impurity regions 435, 437, and 482 of the drive circuit 506. At the same time, connection electrodes 494, 496, and 497 and a gate wiring 495 in the pixel region 507 are formed. At this time, the metal wiring material is composed of a laminated film of a 50 nm thick Ti film and a 500 nm thick Al—Ti alloy film. The connection electrode 494 is formed to electrically connect an electrode functioning as a source wiring (first layer electrode 458 and second layer electrode 445) and the pixel TFT 504 through the impurity region 438. The connection electrode 496 is electrically connected to the impurity region 438 of the pixel TFT 504, and the connection electrode 497 is electrically connected to the impurity region 484 of the storage capacitor 505. The gate wiring 495 is formed to electrically connect a plurality of gate electrodes (the first layer gate electrode 456 and the second layer gate electrode 443) of the pixel TFT 504. Next, after a transparent conductive film such as ITO (Indium-Tin-Oxides) is deposited to a thickness of 80 to 120 nm, a pixel electrode 498 is formed by photolithography and etching. The pixel electrode 498 is electrically connected to the impurity region 438 that is the source / drain region of the pixel TFT 504 through the connection electrode 496, and is also electrically connected to the impurity region 484 of the storage capacitor 505 through the connection electrode 497. Connected (see FIG. 10-B).
[0066]
Through the above manufacturing process, an active matrix liquid crystal display composed of a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region can be manufactured.
[0067]
[Example 2]
The present invention can be applied to various semiconductor display devices (active matrix liquid crystal display devices, active matrix EL display devices, active matrix EC display devices). Therefore, the present invention can be applied to all electronic devices in which the semiconductor display device is incorporated as a display medium.
[0068]
Examples of the electronic device include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggles type display), a game machine, a car navigation system, a personal computer, and a portable information terminal (mobile computer, cellular phone, electronic Books) etc., and specific examples thereof are shown in FIGS.
[0069]
FIG. 12A illustrates a personal computer including a main body 1001, a video input unit 1002, a display device 1003, and a keyboard 1004. The present invention can be applied to the display device 1003 and other circuits.
[0070]
FIG. 12B illustrates a video camera, which includes a main body 1101, a display device 1102, an audio input unit 1103, an operation switch 1104, a battery 1105, and an image receiving unit 1106. The present invention can be applied to the display device 1102 and other circuits.
[0071]
FIG. 12C illustrates a mobile computer, which includes a main body 1201, a camera unit 1202, an image receiving unit 1203, an operation switch 1204, and a display device 1205. The present invention can be applied to the display device 1205 and other circuits.
[0072]
FIG. 12D shows a goggle type display, which is composed of a main body 1301, a display device 1302, and an arm portion 1303. The present invention can be applied to the display device 1302 and other circuits.
[0073]
FIG. 12E shows a player used as a recording medium (hereinafter abbreviated as recording medium) in which a program is recorded, and includes a main body 1401, a display device 1402, a speaker unit 1403, a recording medium 1404, and an operation switch 1405. This apparatus uses a DVD, a CD, or the like as a recording medium, and can be used for music appreciation, games, or the Internet. The present invention can be applied to the display device 1402 and other circuits.
[0074]
FIG. 12-F shows a mobile phone, which includes a display panel 1501, an operation panel 1502, a connection unit 1503, a display unit 1504, an audio output unit 1505, an operation key 1506, a power switch 1507, an audio input unit 1508, and an antenna 1509. Is done. The display panel 1501 and the operation panel 1502 are connected by a connection unit 1503. An angle θ between the surface of the display panel 1501 on which the display unit 1504 is installed and the surface of the operation panel 1502 on which the operation key 1506 is installed can be arbitrarily changed in the connection unit 1503. The present invention can be applied to the display portion 1504.
[0075]
FIG. 13A shows a front projector, which includes a light source optical system and display device 1601 and a screen 1602. The present invention can be applied to the display device 1601 and other circuits.
[0076]
FIG. 13B shows a rear projector, which includes a main body 1701, a light source optical system and display device 1702, mirrors 1703 to 1704, and a screen 1705. The present invention can be applied to the display device 1702 and other circuits.
[0077]
13C is a diagram showing an example of the structure of the light source optical system and display device 1601 in FIG. 13A and the light source optical system and display device 1702 in FIG. 13B. The light source optical system and display devices 1601 and 1702 include a light source optical system 1801, mirrors 1802 and 1804 to 1806, a dichroic mirror 1803, an optical system 1807, a display device 1808, a phase difference plate 1809, and a projection optical system 1810. The projection optical system 1810 is composed of a plurality of optical lenses provided with a projection lens. This configuration is called a three-plate type because three display devices 1808 are used. In addition, in the optical path indicated by the arrow in the figure, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like.
[0078]
FIG. 13-D is a diagram showing an example of the structure of the light source optical system 1801 in FIG. 13-C. In this embodiment, the light source optical system 1801 includes a reflector 1811, a light source 1812, lens arrays 1813 to 1814, a polarization conversion element 1815, and a condenser lens 1816. The light source optical system shown in the figure is an example and is not limited to this configuration. For example, the practitioner may appropriately provide a light source optical system with an optical lens and a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like.
[0079]
FIG. 14A shows an example of a single plate type. The light source optical system and display device shown in FIG. 1 includes a light source optical system 1901, a display device 1902, a projection optical system 1903, and a phase difference plate 1904. The projection optical system 1903 is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and display device shown in FIG. 13 can be applied to the light source optical system and display devices 1601 and 1702 in FIGS. 13A and 13B. The light source optical system 1901 may be the light source optical system shown in FIG. Note that the display device 1902 is provided with a color filter (not shown) to color the display image.
[0080]
The light source optical system and display device shown in FIG. 14-B is an application example of FIG. 14-A. Instead of providing a color filter, a display image is colored using an RGB rotating color filter disc 1905. . The light source optical system and display device shown in FIG. 13 can be applied to the light source optical system and display device 1601 and display device 1702 in FIGS. 13A and 13B.
[0081]
Further, the light source optical system and the display device shown in FIG. 14-C are called a color filterless single plate type. In this system, a microlens array 1915 is provided in a display device 1916, and a display image is colored using a dichroic mirror (green) 1912, a dichroic mirror (red) 1913, and a dichroic mirror (blue) 1914. The projection optical system 1917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and display device shown in FIG. 13 can be applied to the light source optical system and display device 1601 and display device 1702 in FIGS. 13A and 13B. The light source optical system 1911 may be an optical system using a coupling lens and a collimator lens in addition to the light source.
[0082]
As shown above, the application range of the semiconductor display device composed of the GOLD structure polycrystalline silicon TFT having both the Lov region and the Loff region is very wide, and the present invention is an electronic apparatus incorporating semiconductor display devices in various fields. It is applicable to.
[0083]
【The invention's effect】
According to the present invention, in the formation of a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region, ion implantation into the Lov region is independently performed using a negative resist pattern formed in a self-aligned manner by a backside exposure method as a mask. By doing so, the impurity concentration in the Lov region and the Loff region can be independently controlled, and the following effects can be given.
[0084]
(Effect 1) By controlling the impurity concentration in the Lov region and the Loff region, the GOLD structure polycrystalline silicon TFT can have both hot carrier resistance and an off-current suppressing effect. Therefore, the pixel region and the peripheral circuit of the semiconductor display device Can be formed with TFTs having the same structure, which is effective in simplifying the manufacturing process of the semiconductor display device.
[0085]
(Effect 2) Since the present invention can simplify the manufacturing process of the semiconductor display device, it is effective for improving the yield of the semiconductor display device and reducing the cost.
[0086]
(Effect 3) Since the GOLD structure polycrystalline silicon TFT can have both hot carrier resistance and an off-current suppressing effect, it is effective in improving the performance of the semiconductor display device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for forming a GOLD structure polycrystalline silicon TFT having both a Lov region and a Loff region.
[Fig. 2] Mobility (μ _FE ) A graph showing the dependence of the deterioration rate and off-current on the n-type impurity implantation amount.
FIG. 3 is a cross-sectional view showing a method (1) of forming a GOLD structure polycrystalline silicon TFT to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 4 is a cross-sectional view showing a formation method (2) of a GOLD structure polycrystalline silicon TFT to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 5 is a cross-sectional view showing a manufacturing method (1) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 6 is a cross-sectional view showing a manufacturing method (2) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 7 is a cross-sectional view showing a manufacturing method (3) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 8 is a cross-sectional view showing a manufacturing method (4) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 9 is a cross-sectional view showing a manufacturing method (5) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 10 is a cross-sectional view showing a manufacturing method (6) of a semiconductor display device (liquid crystal display) to which a two-layer structure gate electrode formation technique and a backside exposure technique are applied.
FIG. 11 is a graph showing transmittance data of a TaN film.
FIG. 12 is a schematic diagram of an electronic apparatus showing an application example (1) to a semiconductor display device.
FIG. 13 is a schematic view of an electronic apparatus showing an application example (2) to a semiconductor display device.
FIG. 14 is a schematic diagram of an electronic apparatus showing an application example (3) to a semiconductor display device.
FIG. 15 is simulation data of an n-channel GOLD structure polycrystalline silicon TFT.
FIG. 16 shows SIMS analysis data when P ions are implanted.
[Explanation of symbols]
101: Glass substrate
102: Semiconductor layer (polycrystalline silicon film)
103: Gate insulation film
104: First layer gate electrode
105: Second layer gate electrode
106: High concentration impurity region (n + region or P + region)
107: Negative resist pattern
108: Low-concentration impurity region (n-region or P-region)
109: Low-concentration impurity region (n−− region or P−− region)
201: Glass substrate
202: Semiconductor layer (polycrystalline silicon film)
203: Gate insulation film
204: First layer gate electrode film
205: Second layer gate electrode film
206: Resist pattern
207: Resist pattern after dry etching (after first step of dry etching)
208: Second layer gate electrode (after first step of dry etching)
209: Resist pattern after dry etching (after the second step of dry etching)
210: Second layer gate electrode (after the second step of dry etching)
211: First layer gate electrode (after the second step of dry etching)
212: Gate insulating film (after the second step of dry etching)
213: High concentration impurity region (n + region)
214: Resist pattern after dry etching (after third step of dry etching)
215: Second layer gate electrode (after third step treatment of dry etching)
216: First layer gate electrode (after third step of dry etching)
217: Gate insulating film (after the third step of dry etching)
218: Second layer gate electrode (after the fourth step of dry etching)
219: First layer gate electrode (after the fourth step of dry etching)
220: Gate insulating film (after the fourth step of dry etching)
221: Negative resist pattern
222: Low-concentration impurity region (n-region)
223: Low-concentration impurity region (n−− region)
301: Glass substrate
302: Semiconductor layer (polycrystalline silicon film)
303: Gate insulating film
304: First layer gate electrode film
305: Second layer gate electrode film
306: Resist pattern
307: Resist pattern after dry etching (after first step of dry etching)
308: Second layer gate electrode (after first step of dry etching)
309: Resist pattern after dry etching (after the second step of dry etching)
310: Second layer gate electrode (after the second step of dry etching)
311: First layer gate electrode (after the second step of dry etching)
312: Gate insulating film (after the second step of dry etching)
313: High concentration impurity region (n + region)
314: Resist pattern after dry etching (after the third step of dry etching)
315: Second layer gate electrode (after third step of dry etching)
316: First layer gate electrode (after the third step of dry etching)
317: Gate insulating film (after the third step of dry etching)
318: Second layer gate electrode (after the fourth step of dry etching)
319: First layer gate electrode (after the fourth step of dry etching)
320: Gate insulating film (after the fourth step of dry etching)
321: Negative resist pattern
322: Low-concentration impurity region (n− region)
323: Low concentration impurity region (n−− region)
401: Glass substrate
402: Underlayer
402a: First layer silicon oxynitride film
402b: Second layer silicon oxynitride film
403 to 407: Semiconductor layer (polycrystalline silicon film)
408: Gate insulating film (silicon oxynitride film)
409: First layer gate electrode film (TaN film)
410: Second layer gate electrode film (W film)
411a to 416a: Resist pattern
411b to 416b: Resist pattern after dry etching (after first step of dry etching)
411c to 416c: Resist pattern after dry etching (after the second step of dry etching)
411d to 416d: Resist pattern after dry etching (after third step of dry etching)
417 to 420: Second layer gate electrode (after the first step of dry etching)
421 to 422: Second layer electrode (after the first step of dry etching)
423 to 426: Second layer gate electrode (after the second step of dry etching)
427 to 428: Second layer electrode (after the second step treatment of dry etching)
429 to 432: first layer gate electrode (after the second step of dry etching)
433-434: 1st layer electrode (after the 2nd step process of dry etching)
435 to 439: high-concentration impurity region (n + region)
440 to 443: Second layer gate electrode (after third step treatment of dry etching)
444 to 445: Second layer electrode (after third step treatment of dry etching)
446 to 449: first layer gate electrode (after third step treatment of dry etching)
450 to 451: First layer electrode (after the third step of dry etching)
452: Gate insulating film (after the third step of dry etching)
453 to 456: First layer gate electrode (after the fourth step of dry etching)
457 to 458: First layer electrode (after the fourth step of dry etching)
459: Gate insulating film (after the fourth step of dry etching)
460-468: Negative resist pattern
469 to 473: Low concentration impurity region (n− region)
474 to 478: low concentration impurity region (n−− region)
479 to 481: resist pattern
482: High concentration impurity region (p + region)
483: Low-concentration impurity region (p-region)
484: High concentration impurity region (p + region)
485: Low-concentration impurity region (p-region)
486: First interlayer insulating film (silicon oxynitride film)
487: Second interlayer insulating film (acrylic resin film)
488-493: Metal wiring
494: Connection electrode
495: Gate wiring
496 to 497: Connection electrodes
498: Pixel electrode (ITO etc.)
501: n-channel TFT
502: p-channel TFT
503: n-channel TFT
504: Pixel TFT
505: Holding capacity
506: Drive circuit
507: Pixel area

Claims (6)

A first step of sequentially laminating a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film on a transparent insulating substrate from the side closest to the transparent insulating substrate;
A second step of forming a resist pattern for forming a gate electrode on the second layer gate electrode film;
A third step of dry-etching using the resist pattern as a mask to form a first-shaped gate electrode comprising a first-layer gate electrode and a second-layer gate electrode;
A first impurity region that does not overlap with the first shape gate electrode is formed by ion-implanting one conductivity type impurity into a region of the semiconductor layer that is not covered with the first shape gate electrode. A fourth step;
Using the resist pattern present on the first shape gate electrode as a mask, the first layer gate electrode and the second layer gate electrode of the first shape gate electrode are additionally etched to form a first layer of the second shape gate electrode. Forming a gate electrode and a second layer gate electrode, wherein the first layer gate electrode of the second shape gate electrode is shorter in the channel direction than the first layer gate electrode of the first shape gate electrode, and the first shape gate electrode A fifth step of making the dimension in the channel direction longer than the second-layer gate electrode of the two-shaped gate electrode;
A sixth step of forming a resist on the second-shaped gate electrode, performing backside exposure using the first-layer gate electrode of the second-shaped gate electrode as a mask, and forming a negative resist pattern in a self-aligning manner; ,
The second shape gate electrode is formed by ion-implanting an impurity having the same conductivity type as the one conductivity type into a region of the semiconductor layer that overlaps the exposed region of the first layer gate electrode of the second shape gate electrode. A seventh step of forming a second impurity region overlapping with the first layer gate electrode ;
An eighth step of removing the negative resist pattern;
By implanting ions of the same conductivity type as the one conductivity type into a region of the semiconductor layer that is not covered with the second shape gate electrode, a third layer that does not overlap with the second shape gate electrode is formed. and a ninth step of forming an impurity region,
The dose amount when forming the second impurity region is lower than the dose amount when forming the first impurity region, and higher than the dose amount when forming the third impurity region. A method for manufacturing a semiconductor display device. A first step of sequentially forming a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film on a transparent insulating substrate from the side closer to the transparent insulating substrate;
A second step of forming a resist pattern for forming a gate electrode on the second layer gate electrode film;
A third step of dry-etching using the resist pattern as a mask to form a first-shaped gate electrode comprising a first-layer gate electrode and a second-layer gate electrode;
A first impurity region which does not overlap with the first shape gate electrode is formed by implanting impurity ions of one conductivity type into a region of the semiconductor layer which is not covered with the first shape gate electrode. A fourth step;
Using the resist pattern present on the first shape gate electrode as a mask, the first layer gate electrode and the second layer gate electrode of the first shape gate electrode are additionally etched to form a first layer of the second shape gate electrode. Forming a gate electrode and a second layer gate electrode, wherein the first layer gate electrode of the second shape gate electrode is shorter in the channel direction than the first layer gate electrode of the first shape gate electrode, and the first shape gate electrode A fifth step of making the dimension in the channel direction longer than the second-layer gate electrode of the two-shaped gate electrode;
By implanting ions of the same conductivity type as the one conductivity type into a region of the semiconductor layer that is not covered with the second shape gate electrode, a third layer that does not overlap with the second shape gate electrode is formed. A sixth step of forming an impurity region ;
A seventh step of forming a resist on the second shape gate electrode, performing backside exposure using the first layer gate electrode of the second shape gate electrode as a mask, and forming a negative resist pattern in a self-aligning manner; ,
The second shape gate electrode is formed by ion-implanting an impurity having the same conductivity type as the one conductivity type into a region of the semiconductor layer that overlaps the exposed region of the first layer gate electrode of the second shape gate electrode. and a eighth step of forming a second impurity area overlapping with the first-layer gate electrode,
The dose amount when forming the second impurity region is lower than the dose amount when forming the first impurity region, and higher than the dose amount when forming the third impurity region. A method for manufacturing a semiconductor display device. In claim 1 or claim 2,
A method for manufacturing a semiconductor display device, wherein impurity concentrations of the second impurity region and the third impurity region are independently controlled. In any one of Claims 1 thru | or 3,
A method for manufacturing a semiconductor display device, wherein different types of refractory metals or compounds containing refractory metals are applied to the first layer gate electrode film and the second layer gate electrode film. In any one of Claims 1 thru | or 4,
A TaN film, which is a compound containing a refractory metal, is applied as the first layer gate electrode film, and a W film, which is a refractory metal, is applied as the second layer gate electrode film. Method. In any one of Claims 1 thru | or 5,
A method for manufacturing a semiconductor display device, wherein the semiconductor layer is formed of a polycrystalline silicon film.

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