JP5045921B2 - Discharge lamp lighting device and lighting fixture - Google Patents

Description

  The present invention relates to a discharge lamp lighting device for lighting a discharge lamp by an inverter circuit, and a lighting fixture including the same.

  Generally, a discharge lamp lighting device including an inverter circuit lights a discharge lamp at a constant brightness by controlling a switching frequency or a switching duty ratio of a switching unit according to a lighting state of the discharge lamp and a power supply voltage. It is configured to be able to.

  In recent years, with the development of various digital devices, digital control of the discharge lamp lighting device has been increasing in order to make it possible to control the discharge lamp lighting device from a digitized external device. In this case, it is common to digitize the control device that controls the drive of the inverter circuit. By digitizing the control device in this way, it becomes easier to obtain desired control characteristics and control with quick response is possible. I can expect.

  A digital signal processing device (DSP), which is a digitized control device, generates a PWM signal to be supplied to the inverter circuit by digital arithmetic processing. In such digital arithmetic processing, the power supply voltage, the lighting state of the discharge lamp, etc. are detected, a PWM signal is generated in response to this detection, and is input to the inverter circuit, for example, the lighting frequency of the discharge lamp and the output voltage. The discharge lamp is lit stably by controlling the on-duty of the lamp.

  However, when a PWM signal is generated by digital arithmetic processing in this way, there is a problem that the frequency of the PWM signal depends on the operation clock of the digital signal processing device. That is, when the operation clock of the digital signal processing apparatus is relatively small, in other words, in the case of a low-speed control means, it is not easy to perform fine frequency control.

  On the other hand, when the operation clock of the digital signal processing apparatus is improved, there is a problem that power consumption increases or costs increase.

In view of this, there is known a technique in which the frequency of the PWM signal is adjusted during the stop by stopping the digital signal processing apparatus for a predetermined period by interrupt processing (see, for example, Patent Document 1).
JP 2000-150180 A (page 8, FIG. 4)

  However, in the above-described discharge lamp lighting device, the digital signal processing device is stopped when the frequency of the PWM signal is adjusted, so that during the adjustment, other processing cannot be performed by the digital signal processing device. Has the problem.

  The present invention has been made in view of the above points, and provides a discharge lamp lighting device capable of fine dimming control without stopping other processing regardless of an operation clock, and a lighting fixture including the discharge lamp lighting device. For the purpose.

The discharge lamp lighting device according to claim 1, wherein an inverter circuit that converts a DC voltage into a high-frequency voltage and outputs it to light the discharge lamp; and a signal generator that generates a PWM signal having a frequency depending on a predetermined operation clock In addition, either the rising edge or the falling edge of the PWM signal generated by the signal generator is inverted at a timing independent of the predetermined operation clock without depending on the predetermined operation clock. By inverting the other of the falling edges at a timing that depends on the predetermined operation clock, the pulse width can be set shorter than the predetermined operation clock, and the duty ratio is set to be substantially constant based on the previous duty. A signal generating means including a duty setting unit for setting; a PWM generated by the signal generating means; Those that include a; and control means for driving and controlling the inverter circuit in accordance with the Patent.

  The discharge lamp is preferably a low-pressure mercury discharge lamp such as a fluorescent lamp, but is not limited thereto.

  As the inverter circuit, for example, a half bridge type including a pair of switching elements is used, but the inverter circuit is not limited thereto.

  The signal generation unit is, for example, an MPU (arithmetic element) such as a microcomputer, and operates at a timing corresponding to the operation clock generated by the operation clock generation unit to generate a PWM signal having a frequency corresponding to the state of the discharge lamp. It is a digital part.

  The duty setting unit is, for example, an MPU that operates independently of the operation clock of the signal generation unit to set the duty ratio of the PWM signal, or an MPU having an equivalent peripheral circuit.

  The previous duty means at least one of on-duty and off-duty in a previous cycle of the PWM signal for which the duty ratio is to be set by the duty setting unit.

  The control means is, for example, a high side driver connected to the switching element of the inverter circuit.

Then, the pulse width of the PWM signal having a frequency that depends on the predetermined operation clock is inverted at a timing independent of the predetermined operation clock without depending on either the rising edge or the falling edge. The duty setting unit that sets the PWM signal to be shorter than the predetermined operation clock by inverting the other of the rising and falling edges of the PWM signal at a timing that depends on the predetermined operation clock. The duty ratio is substantially constant based on the previous duty. Thus, regardless of the operation clock, the frequency of the PWM signal can be continuously finely changed without stopping other processes, and fine dimming control can be performed.

  The discharge lamp lighting device according to claim 2 is the discharge lamp lighting device according to claim 1, wherein the duty setting unit sets the duty ratio by switching on and off the next cycle of the PWM signal at a timing independent of a predetermined operation clock. It is to set.

  The duty setting unit can set the duty ratio of the PWM signal to be shorter than the predetermined operation clock by setting the duty ratio by switching on / off the next cycle of the PWM signal at a timing independent of the predetermined operation clock. The duty setting unit is easily realized.

  According to a third aspect of the present invention, there is provided a lighting fixture comprising: a fixture main body to which the discharge lamp is attached; and the discharge lamp lighting device according to the first or second aspect that controls lighting of the discharge lamp.

  The lighting fixture may be any one of outdoor lighting, indoor lighting, general lighting, display, and the like, and may have any shape. Further, the discharge lamp lighting device may be integrated with or separated from the instrument body.

  By providing the discharge lamp lighting device according to claim 1 or 2, it becomes possible to change the frequency of the PWM signal continuously and finely without stopping other processing regardless of the operation clock. Dimming control becomes possible.

According to the discharge lamp lighting device of the first aspect, the pulse width of the PWM signal having a frequency depending on the predetermined operation clock is set so that one of the rising edge and the falling edge does not depend on the predetermined operation clock. A duty setting unit that inverts at a timing independent of the predetermined operation clock and inverts the other of the rising edge and the falling edge of the PWM signal at a timing depending on the predetermined operation clock to set the duty signal shorter than the predetermined operation clock. By setting the duty ratio to be substantially constant based on the previous duty, the frequency of the PWM signal can be changed continuously and finely without stopping other processing regardless of the operation clock. Dimming control is possible.

  According to the discharge lamp lighting device of the second aspect, in addition to the effect of the discharge lamp lighting device of the first aspect, the duty setting unit turns on / off the next cycle of the PWM signal at a timing independent of a predetermined operation clock. By setting the duty ratio by switching, it is possible to easily realize a duty setting unit that can set the duty of the PWM signal to be shorter than a predetermined operation clock.

  According to the lighting apparatus of the third aspect, by providing the discharge lamp lighting device of the first or second aspect, the frequency of the PWM signal is continuously fined without stopping other processes regardless of the operation clock. It can be changed and fine dimming control can be performed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a discharge lamp lighting device, FIG. 2 is a bottom view of a part of a lighting fixture provided with the discharge lamp lighting device, and FIG. 3 shows a relationship between an operation clock of the discharge lamp lighting device and a PWM signal. FIG. 4 is a timing chart showing the operation of the power supply unit of the discharge lamp lighting device, FIG. 5 is a graph showing the relationship between the operation cycle of the inverter circuit of the general discharge lamp lighting device and the lamp voltage, and FIG. FIG. 7 is a graph corresponding to each minimum resolution in the table shown in FIG. 6. FIG. 7 is a table showing the difference in lamp voltage for each output resolution of the discharge lamp lighting device.

  As shown in FIG. 2, a ceiling-embedded lighting fixture 11 as a lighting fixture is a ceiling-embedded lighting fixture installed on a system ceiling in which, for example, T bars are assembled in a grid shape, and is a light source as a load. As a discharge lamp (discharge lamp), that is, a polygonal annular lamp, a quadrangular annular (square annular) lamp 12 is used. The lamp 12 is, for example, a lamp having a tube diameter of 15 mm to 18 mm, and has a quadrangular annular shape having four straight sides 13 and four corners 14 that connect the ends of the four sides 13 at substantially right angles. The arc tube 15 is formed, and has a base 16 that connects both ends of the arc tube 15 at the center of one side of the arc tube 15 and has a coldest part formed in the vicinity thereof. Connection pins (not shown) connected to electrodes (not shown) provided at both ends of the arc tube 15 are projected.

  Then, the ceiling-embedded lighting fixture 11 has a fixture main body 21, and the fixture main body 21 is formed in a rectangular box shape having an open bottom surface, and has a rectangular top plate portion 23, the top plate portion 23. The side plate portion 24 is bent downward from the peripheral edge portion thereof, and the frame portion 25 is formed in a substantially L shape around the lower end of the side plate portion 24. The outer dimension of the frame portion 25 of the instrument main body 21 is formed to be smaller than the inner dimension of the embedded opening surrounded on all sides by the T-bar of the system ceiling.

  A square-shaped opening 26 is formed in the central region of the top plate 23, and the lower surface side of the opening 26 can be attached to the lower surface of the ceiling plate 23 by screws or the like. It is attached.

  Between the top plate portion 23 and the side plate portion 24 of the fixture main body 21 and the side surface portion 33 of the ceiling-attached equipment attachment body 31, a quadrangular annular lamp accommodating portion 37 having an open lower surface is formed. A lamp 12 is accommodated.

  Further, on the lower surface of the top plate portion 23 of the appliance main body 21, the lighting device mounting portion 23a that is an edge portion of one side of the opening portion 26 is provided with the power input side 40 at one end along the edge portion of the opening portion 26. In addition, a discharge lamp lighting device 42 (hereinafter referred to as a lighting device 42) as a load control device having a lamp output side 41 arranged at the other end is attached, and an opening in which the lighting device 42 is attached on the power input side 40 of the lighting device 42 The power terminal block 43 is attached to the edge of the side that intersects one side of the section 26, and the edge of the side opposite to the side of the opening 26 to which the power terminal block 43 is attached on the lamp output side 41 of the lighting device 42. A lamp socket 44 that is connected to the base 16 of the lamp 12 and also serves as a lamp holder that detachably holds the base 16 of the lamp 12 is attached. The lighting device 42 and the power terminal block 43 are disposed inside the ceiling-attached facility attachment body 31 and are covered together with the opening 26.

  In the lighting device 42, as shown in FIG. 1, an inverter circuit 52 is connected to a power source 51 that rectifies and smoothes a commercial AC power source e, and an output terminal of the inverter circuit 52 is connected to a lamp via a resonance circuit 53. Twelve filaments FLa and FLb are connected. In addition, a preheating circuit 55 for the filaments FLa and FLb of the lamp 12 is connected to a connection portion between the inverter circuit 52 and the resonance circuit 53. Further, a digital signal processing device 56 (hereinafter referred to as DSP 56), which is a circuit control means as a control device, is connected to the power supply unit 51, the inverter circuit 52, and the preheating circuit 55. The commercial AC power source e, the power source 51, the inverter circuit 52, the resonance circuit 53, the preheating circuit 55, the DSP 56, and the like constitute a lighting circuit 57 as an operating circuit, and the lighting circuit 57 and the lamp 12 are connected to each other. As a result, the main circuit 58 is configured.

  The power supply unit 51 is a step-up chopper power supply having a power factor improvement (PFC) function of a so-called critical mode (discontinuous mode) that matches the phase of the input current I0 and the input voltage V0. A bridge diode BD as a rectifier is connected, and a boost chopper circuit 59 is connected to the output side of the bridge diode BD. In the boost chopper circuit 59, a series circuit of a chopper choke L1 that is a boosting transformer and a reverse blocking diode D1 is connected to the output side of the bridge diode BD between the inverter circuit 52 and the chopper chopper circuit 59. A first switching element as a switching element, that is, a field effect transistor (FET) Q1, which is a chopping switching element, is connected in parallel to the connection point between the choke L1 and the anode of the diode D1, and the cathode of the diode D1 and the inverter An electrolytic capacitor C1, which is a smoothing capacitor, is connected in parallel to the connection point with the circuit 52.

  The chopper choke L1 has a primary winding L1a and a secondary winding L1b. The primary winding L1a is connected between the output side of the bridge diode BD and the anode of the diode D1, and the secondary winding One end side of L1b is connected to the ground, and the other end side is connected to a set terminal of a flip-flop 61 which is a sequential circuit as a control signal generation unit via a resistor R1 for detection. Therefore, the choke voltage V generated in the resistor R1 by the choke current I is input to the set terminal of the flip-flop 61 from the secondary winding L1b of the chopper choke L1.

  In the field effect transistor Q1, the drain terminal is connected to the connection point between the chopper choke L1 and the anode of the diode D1, the source terminal is connected to the ground via the resistor R2, and the gate terminal that is the control terminal The output terminal of the flip-flop 61 is connected.

  Here, the flip-flop 61 is a so-called RS type, and an output terminal of an analog comparator 63 which is a comparator as an operational amplifier, that is, a comparator, is connected to a reset terminal. In this analog comparator 63, one input terminal is connected to the connection point between the drain terminal of the field effect transistor Q1 and the resistor R2, and the voltage VQ generated in the resistor R2 by the switching current IQ of the field effect transistor Q1 is input. The other input terminal is connected to the DSP 56 via a resistor R3, and the connection point with the resistor R3 is connected to the ground via a capacitor C2.

  Then, with the flip-flop 61 and the analog comparator 63, etc., boost chopper circuit control means as a switching pulse generation circuit that controls the operation of the boost chopper circuit 59 based on the zero current phase of the choke current I and the switching current IQ. A certain chopping control unit 64 is configured.

  The inverter circuit 52 is a so-called half-bridge type in which field effect transistors Q2 and Q3, which are switching elements for inverters as second switching elements, are connected in series to the power supply unit 51.

  The gate terminals of the field effect transistors Q2 and Q3 are connected to the DSP 56 via a high side driver 65 as control means, and on / off is controlled by a signal supplied from the high side driver 65.

  The high-side driver 65 alternately turns on and off the field effect transistors Q2 and Q3 at a frequency of about several tens of kHz to 200 kHz, for example, 50 kHz or more in the present embodiment, according to the dimming PWM signal P supplied from the DSP 56 By doing (switching driving), a predetermined high-frequency alternating current is generated between the drain and source of the field effect transistor Q3.

  In the resonance circuit 53, a resonance capacitor C4 is connected in parallel between both ends of the field effect transistor Q3 via a capacitor C3 that cuts off a DC component and a resonance winding (resonance inductor) L2 in series.

  The preheating circuit 55 includes a series circuit of a preheating transformer L3, a capacitor C5, a field effect transistor Q4 as a preheating switching element and a resistor R4 for current detection, and a connection point between the capacitor C5 and the field effect transistor Q4 and a field effect. A diode D2 is connected between the source terminal of the transistor Q2.

  In the preheating transformer L3, the primary winding L3a, the first secondary winding L3b and the second secondary winding L3c are arranged to face each other, and the primary winding L3a is a connection point between the field effect transistors Q2 and Q3. And the resonance capacitor C4, and the secondary windings L3b and L3c are connected to the filaments FLa and FLb of the lamp 12 via the capacitors C6 and C7, respectively.

  In the field effect transistor Q4, a gate terminal as a control terminal is connected to the DSP 56, and switching control is performed by a preheating PWM signal supplied from the DSP 56.

  The DSP 56 is an MPU (arithmetic element) such as a so-called microcomputer that performs digital signal processing, and a voltage setting unit 71 that is a reference voltage setting unit as a reference waveform setting unit connected to an input terminal of the analog comparator 63. Preheating circuit controller 72 for controlling switching of field effect transistor Q4 of preheating circuit 55, lighting circuit 57 and lamp 12 by detecting at least one of discharge current, that is, lamp current IL and discharge voltage, that is, lamp voltage VL Of the field effect transistors Q2 and Q3 of the inverter circuit 52 based on the operation state detected by the state detection unit 73, the state detection unit 73 having a function of state detection means for detecting the operation state of the main circuit 58 (operation state of the main circuit 58) A dimming signal generation unit 74 that is an inverter circuit control unit as a signal generation unit that generates a PWM signal P for operation control is included. It has respectively with and provided integrally, ROM as a storage means (not shown), RAM, and I / O ports as an interface to. Each part of the DSP 56 operates at a timing depending on the operation clock CLK generated by the clock generation unit 76 as an operation clock generation unit.

  The DSP 56 integrally including the voltage setting unit 71, the preheating circuit control unit 72, the dimming signal generation unit 74, and the like means that the DSP 56 shares a software processing part.

  The voltage setting unit 71 is a software unit having a function of power supply voltage detection means for detecting at least one of the input voltage V0 and the output voltage V1 of the power supply unit 51, and at least one of the detected voltages V0 and V1 Based on the reference voltage VTH, a reference voltage VTH which is a reference voltage for comparison of the analog comparator 63 and is a PWM signal is set.

  Specifically, in the present embodiment, the reference voltage VTH is generated by a rectified power supply voltage waveform that becomes the reference waveform SW so as to be turned off depending on the magnitude of the voltage VQ input to the analog comparator 63 and the reference voltage VTH. The switching pulse SP of the field effect transistor Q1, which is a control signal for feedback control, that is, a PWM control signal, is set so that the output voltage V1 approaches a desired target value. The reference waveform SW can be varied corresponding to at least one of the output voltage V1 (output current I1) from the inverter circuit 52 and the power supply voltage, for example.

  In other words, the lighting device 42 generates the reference voltage VTH for switching for PFC control of the power supply unit 51 by the DSP 56, and generates the switching pulse SP for switching the field effect transistor Q1 by using the flip-flop 61 or the analog comparator. It is generated by a chopping control unit 64 configured by hardware such as 63.

  The preheating circuit control unit 72 is a software unit having a function of preheating current detection means for detecting the preheating current IP of the preheating circuit 55, and monitors the preheating current IP of the preheating circuit 55 while detecting the lamp detected by the state detection unit 73. The gate terminal of the field effect transistor Q4 of the preheating circuit 55 is set so that the optimum preheating condition, that is, the target value is set so as to follow the change of at least one of the current IL and the lamp voltage VL, and the preheating current IP approaches the target value. PWM signal PP for preheating to be supplied to is generated. Note that the preheating circuit control unit 72 may set the target value following a change in lamp power or a change in ambient temperature, which is the product of the lamp current IL and the lamp voltage VL, for example. The target value is preferably an upper limit set from an energy amount that does not cause a problem even at the end of the life of the filaments FLa and FLb.

  The state detection unit 73 is an A / D converter that is an arithmetic unit that converts at least one of the lamp current IL and the lamp voltage VL, which are analog signals, into digital frequency data corresponding to the lamp current IL and the lamp voltage VL. And outputs at least one of the A / D converted lamp current IL and lamp voltage VL to the preheating circuit control unit 72 or the dimming signal generation unit 74. The detection timing of the lamp current IL or the lamp voltage VL in the state detection unit 73 is, for example, at least one analog signal in the main circuit 58 such as a power supply voltage waveform or a voltage across the resonance capacitor C4, or The timing is synchronized with the peak phase of the lamp current IL or the lamp voltage VL based on predetermined frequency data which is a digital signal calculated based on the lamp current IL or the lamp voltage VL detected by the state detector 73. . In the present embodiment, for example, since the state detection unit 73 has a function of an A / D converter, it is based on predetermined frequency data that is a digital signal calculated based on the lamp current IL, the lamp voltage VL, and the like. Thus, the detection timing of the lamp current IL or the lamp voltage VL is determined.

  Then, the dimming signal generation unit 74 is a PWM having a frequency depending on the operation clock CLK based on the lighting state of the lamp 12 detected by the state detection unit 73, that is, at least one of the lamp current IL and the lamp voltage VL. In addition to having a function of a signal generation unit for generating the signal P, either the rising edge or the falling edge of the PWM signal P, in this embodiment, the falling edge does not depend on the operation clock CLK as shown in FIG. In other words, the frequency of the PWM signal P is operated by inverting it at a timing independent of the operation clock CLK. In other words, the timing of switching on and off of the PWM signal P is set as a timing independent of the operation clock CLK. This is a software unit having a function of a signal correction unit (edge inversion unit) that performs correction without depending on the clock CLK. Although not shown, a slight dead section is formed between the edge of the PWM signal P1 for the field effect transistor Q2 and the edge of the PWM signal P2 for the field effect transistor Q3.

  Accordingly, the dimming signal generation unit 74 can vary the timing of the falling edge of the PWM signal P without depending on the operation clock CLK, although the timing of the rising edge of the PWM signal P depends on the operation clock CLK in this embodiment. Thus, the frequency of the PWM signal P can be controlled (PFM control) by varying the on-duty (off-duty) at a timing independent of the operation clock CLK. In other words, the dimming signal generation unit 74 is a conversion unit that can convert a duty change of the PWM signal P into a frequency change.

  That is, the dimming signal generation unit 74 sets the timing (the pulse width of the PWM signal P) to invert the falling edge of the pulse of the PWM signal P as the duty (on duty or off duty) of the PWM signal P in the previous cycle. The duty setting unit functions to set the duty ratio of the PWM signal P in the next cycle to be constant based on the above. The frequency control of the PWM signal P is performed every cycle or every several cycles within a predetermined cycle, for example, 100 μsec cycle.

  Here, in the lighting device 42 using the resonance action by the resonance circuit 53, as shown in FIG. 5, the change in the lamp voltage VL with respect to the frequency of the PWM signal P (the switching frequency of the field effect transistors Q2 and Q3) becomes large. For this reason, when the inverter circuit 52 is digitally controlled, the output becomes stepped and stable lighting is not easy. Further, when the control cycle is delayed or feedback control is performed, stable lighting is not easy. Specifically, for example, as shown in the tables of FIGS. 6 and 7 showing the case where the inductance of the resonance winding L2 is 1.4 mH and the capacitance of the resonance capacitor C4 is 3300 pF, the period minimum resolution width of the PWM signal P is shown. When the change width ΔVL of the lamp voltage VL corresponding to (minimum resolution) is 2 V or more, the lighting state becomes unstable (shaded portion in the table of FIG. 6) such as the lamp 12 flickering. Therefore, in the present embodiment, the inverter circuit 52 is set so that the change width ΔVL of the ramp voltage VL corresponding to the minimum period resolution width of the PWM signal P is smaller than 2V (ΔVL <2 [V]). Yes.

  The period minimum resolution width means the width from the rising edge to the falling edge of the minimum pulse of the PWM signal P.

  The ROM stores in advance various programs to be executed by each part of the DSP 56, for example, the voltage setting unit 71, the preheating circuit control unit 72, the dimming signal generation unit 74, and the like.

  In the RAM, various digital values detected by the state detection unit 73 and the like are stored in areas assigned to them.

  Then, the lighting device 42 generates a switching pulse SP by the operation of the flip-flop 61 in the power supply unit 51 to switch the field effect transistor Q1, and adjusts the phase of the input voltage V0 and the input current I0 to increase the power factor. Improve.

  Specifically, as shown in FIGS. 1 and 4, when the field effect transistor Q1 is turned on by a starting circuit (not shown) or the like, a linearly increasing current flows through the chopper choke L1 (diode D1). A choke current I flows through the secondary winding L1b of the chopper choke L1, and electromagnetic energy is accumulated in the chopper choke L1. At the same time, when the voltage VQ (≧ reference voltage VTH) generated by the resistor R2 due to the switching current IQ when the field effect transistor Q1 is turned on is input to the analog comparator 63, the reset voltage VR ( = Voltage VQ) is input, and the switching pulse SP that is off from the output terminal of the flip-flop 61 is supplied to the gate terminal of the field effect transistor Q1 and the field effect transistor Q1 is turned off, so that it accumulates in the chopper choke L1. The released electromagnetic energy is released, and a linearly decreasing current flows through the chopper choke L1 (diode D1).

  By repeating this operation, an output current I1 is formed using the waveform of the input voltage V0, that is, the reference waveform SW which is a sine waveform subjected to full-wave rectification, as an envelope.

  The output voltage V1 generated by the power supply unit 51 is converted into a high-frequency AC voltage by operating the field effect transistors Q2 and Q3 of the inverter circuit 52 at a predetermined frequency such as 50 kHz and a predetermined on-duty, for example. .

  By this high frequency AC voltage, the resonance circuit 53 resonates and a resonance current flows, and the field effect transistor Q4 is switched by the preheating PWM signal PP having a predetermined frequency generated by the preheating circuit control unit 72. A preheating current IP flows through the secondary windings L3b and L3c of the preheating transformer L3 to preheat the filaments FLa and FLb of the lamp 12.

  A predetermined starting voltage is applied between the filaments FLa and FLb by preheating the filaments FLa and FLb, the lamp 12 is turned on (started), and the lamp 12 is steadily lit.

  At this time, in the lighting device 42, based on at least one of the lamp current IL and the lamp voltage VL detected by the state detection unit 73, the lamp power that is the lamp current IL, the lamp voltage VL, or a product thereof is a predetermined value. Feedback control is performed to achieve the target value.

  When dimming the lit lamp 12 as described above, the PWM signal P is input from the dimming signal generation unit 74 of the DSP 56 to the high side driver 65 of the lighting device 42 to vary the drive frequency of the inverter circuit 52. . By increasing or decreasing the drive frequency of the inverter circuit 52, the high frequency power from the inverter circuit 52 is suppressed or increased, the lamp current IL is suppressed or increased, and the lamp 12 is dimmed.

  The drive frequency of the inverter circuit 52, that is, the frequency of the PWM signal P is determined based on at least one of the lamp current IL and the lamp voltage VL detected by the state detection unit 73 in the dimming signal generation unit 74. After generating the PWM signal P having a frequency that depends on the operation clock CLK generated by 76, the dimming signal generation unit 74 uses the falling edge of the PWM signal P to turn on the PWM signal P of the previous cycle. Based on one of duty and off-duty, the duty ratio of the PWM signal P in the next cycle is set to be constant and inverted at a timing independent of the operation clock CLK, so that it does not depend on the operation clock CLK. Variable.

  The frequency control of the PWM signal P is performed every cycle or within a predetermined cycle, for example, every several cycles within a 100 μsec cycle, and the lighting state of the lamp 12 is immediately reflected in the frequency of the PWM signal P.

  Here, the inverter circuit 52 is controlled such that the change width ΔVL of the ramp voltage VL corresponding to the minimum period resolution width of the PWM signal P is smaller than 2V.

  In the preheating circuit 55, the preheating current is set to the target value set by the preheating circuit control unit 72 so as to follow the lamp current IL, the lamp voltage VL, the lamp power, or the ambient temperature change detected by the state detection unit 73. The field effect transistor Q4 is switched by the preheating PWM signal PP generated so that the IP approaches, thereby optimizing the amount of preheating during lighting that varies depending on the type of the lamp 12 and variations in the manufacturing process.

  As described above, on / off of the next cycle of the PWM signal P is switched based on either the on-duty or off-duty of the PWM signal P having a frequency depending on the operation clock CLK and at a timing independent of the operation clock CLK. The dimming signal generator 74 that corrects the frequency of the PWM signal P, in other words, can set the duty of the PWM signal P having a frequency that depends on the operation clock CLK shorter than the operation clock CLK. By setting the duty ratio to be substantially constant based on the previous duty, the frequency of the PWM signal P can be continuously finely changed without stopping other processing of the DSP 56 regardless of the operation clock CLK. It becomes possible, and fine dimming control becomes possible.

  That is, since the operation clock CLK is relatively small, in other words, the low-speed and inexpensive DSP 56 can be used, the cost of the lighting device 42 can also be reduced.

  The dimming signal generation unit 74 easily sets the duty ratio of the PWM signal P by inverting the edge of the next period of the PWM signal P at a timing independent of the operation clock CLK, thereby easily setting the duty of the PWM signal P to the operation clock CLK. Can be set shorter.

  Timing synchronized with the peak phase of the lamp current IL or lamp voltage VL determined based on at least one of the signals in the main circuit 58 or predetermined frequency data calculated based on the lamp current IL, lamp voltage VL, etc. By setting the lighting frequency of the lamp 12 by the dimming signal generation unit 74 setting the frequency of the PWM signal P at a predetermined timing such as, the lighting state of the lamp 12 can be set at an appropriate timing. As a result, even if the lamp 12 is in an unstable state between turning off and lighting, the lighting of the lamp 12 can be maintained, so that deep dimming is possible.

  The dimming signal generation unit 74 sets the frequency of the PWM signal P to 50 kHz or more, and performs feedback control of the operating frequency of the inverter circuit 52 within a period of 100 μsec based on the lighting state of the lamp 12, specifically, every period. The response of the inverter circuit 52 can be further improved.

  The inverter circuit 52 turns on the lamp 12 so that the change width ΔVL of the lamp voltage VL corresponding to the minimum resolution width of the PWM signal P is smaller than 2V, so that the lamp 12 having a relatively high lamp voltage VL is obtained. Even if it exists, the light can be dimmed stably and an energy saving system can be provided.

  Based on the lighting state of the lamp 12 detected by the state detection unit 73, a predetermined target value of the dimming signal generation unit 74 is set and feedback control is performed on the inverter circuit 52, so that the inverter corresponds to the lighting state of the lamp 12. The circuit 52 can be driven efficiently.

  Only the voltage setting unit 71 for setting the reference waveform SW based on the power supply voltage waveform is integrally provided in the DSP 56 together with the dimming signal generation unit 74, and the switching current IQ and the choke current I on the secondary winding L1b side of the chopper choke L1 are The chopping control unit 64 that generates the switching pulse SP for controlling the switching of the field effect transistor Q1 based on the reference waveform SW so that the switching current IQ corresponds to the reference waveform SW is configured by hardware separately from the DSP 56, so that the boost chopper circuit Compared with the case where the control signal 59 is generated by the DSP, the software processing load on the DSP 56 can be reduced, and the control of the boost chopper circuit 59 and the control of the inverter circuit 52 Can be compatible.

  Specifically, the reference voltage VTH set by the voltage setting unit 71 based on the detected input voltage V0 and output voltage V1 of the boost chopper circuit and the voltage VQ generated by the switching current IQ of the field effect transistor Q1 are output by the analog comparator 63. In comparison, the switching pulse SP of the field effect transistor Q1 is generated by the flip-flop 61 based on the output voltage of the analog comparator 63 and the choke voltage V on the secondary winding L1b side of the chopper choke L1. The switching pulse SP of the field effect transistor Q1 can be easily generated while reducing the software processing load.

  Since the software processing load on the DSP 56 can be reduced, the software processing load can be suppressed even if other controls are added to the DSP 56.

  When the output voltage of the inverter circuit 52 is low or the power supply voltage is low by changing the reference waveform SW of the switching current IQ of the field effect transistor Q1 by the voltage setting unit 71 corresponding to the output of the inverter circuit 52 or the power supply voltage. Even in such a case, the boost chopper circuit 59 can be operated while reducing the load.

  By determining the optimum value of the preheating amount of the filaments FLa and FLb while the lamp 12 is lit, it is possible to set the optimum preheating amount of the filament, which has a large variation in the lamp type and the lamp manufacturing process, and eliminates the overheating and shortage of preheating. Thus, the lamp 12 can be shortened in life and early blackening can be eliminated.

  The boost chopper circuit 59, the inverter circuit 52, the preheating circuit 55, and the like are digitally controlled by a single DSP 56, so that the configuration is simplified as compared with the case where a DSP dedicated to each control is provided. In addition to facilitating control while reflecting the operation state, for example, dimming useless light in combination with a sensor or the like can further save energy.

  In the above-described embodiment, the configurations of the power supply unit 51 and the preheating circuit 55, and the control thereof are not limited to the above configuration and control.

  Further, the inverter circuit 52 may attack the lamp 12 so that the change width ΔVL of the lamp voltage VL corresponding to the period minimum resolution width of the PWM signal P becomes smaller than 2V. In this case, even the lamp 12 having a relatively high lamp voltage VL can be started stably.

It is a circuit diagram of a discharge lamp lighting device showing an embodiment of the present invention. It is the bottom view which made a section of a lighting fixture provided with the same discharge lamp lighting device same as the above. It is a timing chart which shows the relationship between the operation clock of a discharge lamp lighting device same as the above, and a PWM signal. It is a timing chart which shows operation | movement of the power supply part of a discharge lamp lighting device same as the above. It is a graph which shows the relationship between the operation cycle of the inverter circuit of a general discharge lamp lighting device, and a lamp voltage. It is a table | surface which shows the difference of the lamp voltage according to output resolution of a discharge lamp lighting device same as the above. It is a graph corresponding to each minimum resolution of the table | surface shown in FIG.

Explanation of symbols

11 Recessed ceiling lighting fixtures as lighting fixtures
12 Lamp as discharge lamp
21 Instrument body
42 Discharge lamp lighting device
52 Inverter circuit
65 High-side driver as control means
74 Dimming signal generator as signal generator having functions of signal generator and duty setting unit

Claims (3)

An inverter circuit for converting a DC voltage into a high-frequency voltage and outputting it to turn on the discharge lamp;
A signal generator that generates a PWM signal having a frequency that depends on a predetermined operation clock, and one of the rising and falling edges of the PWM signal generated by the signal generator does not depend on the predetermined operation clock The pulse width can be set shorter than the predetermined operation clock by inverting it at a timing independent of this predetermined operation clock and inverting the other of the rising edge and falling edge of the PWM signal at a timing depending on the predetermined operation clock. And a signal generating means comprising a duty setting unit for setting the duty ratio so that the duty ratio becomes substantially constant based on the previous duty;
Control means for driving and controlling the inverter circuit in accordance with the PWM signal generated by the signal generating means;
A discharge lamp lighting device comprising: 2. The discharge lamp lighting device according to claim 1, wherein the duty setting unit sets the duty ratio by switching on and off the next cycle of the PWM signal at a timing independent of a predetermined operation clock. An instrument body to which a discharge lamp is attached;
The discharge lamp lighting device according to claim 1 or 2, which controls lighting of the discharge lamp;
The lighting fixture characterized by comprising.

Images