JP5042285B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a capacitor and a manufacturing method thereof.

  In recent years, semiconductor devices, particularly semiconductor memory devices represented by DRAM (Dynamic Random Access Memory) and the like, have been increasingly demanded for high integration and miniaturization. FIG. 114 is a schematic plan view of a part of a memory cell region of a conventional DRAM. Referring to FIG. 114, a conventional DRAM memory cell includes a field effect transistor, capacitors including capacitor lower electrodes 1170a and 1170b, word lines 1043a, 1043b, 1043e, and 1043f, and a bit line 1174. The field effect transistor includes word lines 1043a and 1043e that function as gate electrodes, and an active region 1039 that functions as a source / drain region. Specifically, an active region 1039 is formed on the main surface of the semiconductor substrate, and word lines 1043a, 1043b, 1043e, and 1043f are formed on the main surface of the semiconductor substrate. A first interlayer insulating film (not shown) is formed on word lines 1043a, 1043b, 1043e, 1043f and on the main surface of the semiconductor substrate. A bit line 1174 is formed on the first interlayer insulating film so as to be substantially orthogonal to the word lines 1043a, 1043b, 1043e, and 1043f. A second interlayer insulating film (not shown) is formed on the bit line 1174 and the first interlayer insulating film. Capacitor lower electrodes 1170a and 1170b are formed on the second interlayer insulating film. Bit line 1174 is electrically connected to active region 1039 in contact hole 1049. The capacitor lower electrodes 1170a and 1170b are electrically connected to one of the source / drain regions of the field effect transistor in the active region 1039 in the contact holes 1038a and 1038b, respectively. FIG. 115 shows a cross-sectional view of this DRAM memory cell taken along line 500-500.

  FIG. 115 is a cross-sectional view showing a cross section taken along line 500-500 in FIG. 114 and a cross section of the peripheral circuit region of the DRAM. Referring to FIG. 115, in the memory cell region of the DRAM, source / drain regions 1201a and 1201b of field effect transistors are formed in active region 1039 surrounded by trench isolation oxide film 1040. A gate electrode 1043a is formed on a channel region sandwiched between the pair of source / drain regions 1201a and 1201b with a gate insulating film 1042a interposed therebetween. A silicon nitride film 1044a is formed on the gate electrode 1043a. The gate electrode 1043a is made of n-type doped polysilicon. Side walls 1046a and 1046b made of a silicon nitride film are formed on the side surfaces of the gate electrode 1043a and the silicon nitride film 1044a. A non-doped silicon oxide film 1047 is formed on sidewalls 1046a and 1046b, silicon nitride film 1044a, and the main surface of semiconductor substrate 1. A gate electrode 1043b is formed on trench isolation oxide film 1040 with gate insulating film 1042b interposed. A silicon nitride film 1044b is formed on the gate electrode 1043b. Sidewalls 1046c and 1046d made of a silicon nitride film are formed on the side surfaces of the gate electrode 1043b and the silicon nitride film 1044b. A non-doped silicon oxide film 1047 is formed on the sidewalls 1046c and 1046d and the silicon nitride film 1044b. On this non-doped silicon oxide film 1047, a first interlayer insulating film 1048 is formed. A part of first interlayer insulating film 1048 and non-doped silicon oxide film 1047 is removed by etching, whereby contact hole 1049 is formed. A doped polysilicon film 1052 is formed inside contact hole 1049 and on first interlayer insulating film 1048. A refractory metal silicide film 1053 is formed on the doped polysilicon film 1052. Bit line 1174 is composed of doped polysilicon film 1052 and refractory metal silicide film 1053. A silicon nitride film 1054 is formed on the refractory metal silicide film 1053. Side walls 1055a and 1055b made of a silicon nitride film are formed on the side surfaces of the silicon nitride film 1054, the refractory metal silicide film 1053, and the doped polysilicon film 1052. A second interlayer insulating film 1037 is formed on the first interlayer insulating film 1048, the sidewalls 1055a and 1055b, and the silicon nitride film 1054. By removing a portion of first and second interlayer insulating films 1048 and 1037, contact hole 1038a for electrically connecting capacitor lower electrode 1170a and one of the source / drain regions is formed. A plug 1057 made of doped polysilicon is formed in the contact hole 1038a. A capacitor lower electrode 1170a is formed on the opening 1038a and the second interlayer insulating film 1037. The capacitor lower electrode 1170a has a cylindrical structure in order to secure the capacitance of the capacitor with a small occupied area. A dielectric film 1150 is formed on the capacitor lower electrode 1170a and the second interlayer insulating film 1037. A capacitor upper electrode 1151 is formed on the dielectric film 1150. A third interlayer insulating film 1205 is formed on the capacitor upper electrode 1151.

  In the peripheral circuit region, a field effect transistor that is an element constituting the peripheral circuit and a wiring 202 are formed. Source / drain regions 1201 d and 1201 e are formed on the main surface of the semiconductor substrate 1001. Gate electrodes 1043c and 1043d are formed on the channel regions adjacent to the source / drain regions 1201d and 1201e through gate insulating films 1042c and 1042d, respectively. Silicon nitride films 1044c and 1044d are formed on the gate electrodes 1043c and 1043d. Sidewalls 1046e to 1046g made of silicon nitride films are formed on the side surfaces of the gate electrodes 1043c and 1043d and the silicon nitride films 1044c and 1044d. A non-doped silicon oxide film 1047 is formed on the main surface of the semiconductor substrate 1001, the silicon nitride films 1044c and 1044d, and the sidewalls 1046e to 1046g. A first interlayer insulating film 1048 is formed on the non-doped silicon oxide film 1047. By removing a part of the first interlayer insulating film 1048, contact holes 1050 and 1051 are formed. A doped polysilicon film 1052 is formed on the first interlayer insulating film 1048 and in the contact holes 1050 and 1051. A refractory metal silicide film 1053 is formed on the doped polysilicon film 1052. A wiring layer 1202 in the peripheral circuit region is formed from this doped polysilicon film 1052 and refractory metal silicide film 1053. A silicon nitride film 1203 is formed on the refractory metal silicide film 1053. Side walls 1204 a and 1204 b made of silicon nitride films are formed on the side surfaces of the silicon nitride film 1203, the refractory metal silicide film 1053 and the doped polysilicon film 1052. A second interlayer insulating film 1037 is formed on the first interlayer insulating film 1048, the silicon nitride film 1203, and the sidewalls 1204a and 1204b. A capacitor dielectric film 1150 is formed on the second interlayer insulating film 1037 so as to extend from the memory cell region. A capacitor upper electrode 1151 is formed on the dielectric film 1150. A third interlayer insulating film 1205 is formed on the second interlayer insulating film 1037 and the capacitor upper electrode 1151.

  FIG. 116 shows a modification of the memory cell of the conventional DRAM shown in FIG. 115, and the shape of the capacitor lower electrode 1092 is a thick film type. Here, the structure other than the shape of capacitor lower electrode 1092 is substantially the same as that of the conventional DRAM shown in FIG.

  As shown in FIGS. 115 and 116, in a conventional DRAM memory cell, a capacitor lower electrode 1170a is formed to extend in the height direction in order to secure the capacitance of the capacitor while attaining high integration and miniaturization. ing. By forming in this way, even if the area occupied by the capacitor lower electrode 1170a in the memory cell region is reduced, the capacity required for the capacitor can be secured. However, since the structure of the capacitor lower electrode 1170a in the memory cell region extends in the height direction in this way, the height of the upper surface of the third interlayer insulating film 1205 in the memory cell region and the third surface in the peripheral circuit region. The difference from the height of the upper surface of the interlayer insulating film 1205 is increasing. Then, a wiring layer usually made of aluminum or the like is formed on the third interlayer insulating film 1205. In the photoengraving process for forming the wiring layer, there is a step on the upper surface of the third interlayer insulating film 1205 between the memory cell region and the peripheral circuit region. There was a problem that could not be taken. As described above, the focus margin at the time of photoengraving cannot be obtained, so that the pattern of the wiring formed on the third interlayer insulating film 1205 becomes unclear, which causes the problem of disconnection or short circuit of the wiring. It was. As a result, there has been a problem that the reliability of the semiconductor device is lowered.

  In the peripheral circuit region of the conventional DRAM, as shown in FIG. 117, wiring 1202 in the peripheral circuit region and wiring made of aluminum or the like formed on capacitor upper electrode 1151 and third interlayer insulating film 1205 (FIG. Contact holes 1144 and 1135 are formed in order to electrically connect to each other. The contact holes 1144 and 1135 are usually formed at the same time in the same etching process. However, since the positions in the depth direction in which the capacitor upper electrode 1151 and the wiring 1202 in the peripheral circuit region are formed are different, at the bottom of the contact hole 1135 The capacitor upper electrode 1151 is excessively etched until the contact hole 1144 reaches the wiring 1202. As a result, as shown in FIG. 117, the contact hole 1135 may penetrate through the capacitor upper electrode 1151 and the dielectric film 1150. Then, the wiring layer 1202 and other elements such as other field effect transistors in the peripheral circuit region may be damaged by the etching for forming the contact hole 1135. As a result, there has been a problem that the reliability of the semiconductor device is lowered such that the semiconductor device does not operate stably or malfunctions.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to achieve high integration and at the same time to ensure the capacitance of the capacitor and to have high reliability. It is to provide a semiconductor device having the characteristics.

  Another object of the present invention is to provide a method for manufacturing a semiconductor device that can achieve high integration while ensuring the capacitance of a capacitor and has high reliability.

A method for manufacturing a semiconductor device according to the present invention includes the following steps. A semiconductor substrate having a field effect transistor provided on its main surface, the bit line being electrically connected to one of a pair of source or drain regions of the field effect transistor, and a pair of field effect transistors A first step of preparing a semiconductor substrate further comprising a conductor electrically connected to the other of the source and drain regions and having an upper surface located higher than the upper surface of the bit line when viewed from the main surface. A second step of forming a silicon nitride film on the conductor after the first step. A third step of forming a first insulating film in contact with the upper surface of the silicon nitride film; A fourth step of forming a second insulating film in contact with the upper surface of the first insulating film; A fifth step of forming an opening exposing the conductor through the silicon nitride film, the first insulating film, and the second insulating film after the fourth step. After the fifth step, the opening width of the opening is set to the first width by performing an etching process in the opening under an etching condition in which the etching rate of the first insulating film is higher than that of the second insulating film and the silicon nitride film . The opening width in the second portion where the opening width of the opening is defined by the second insulating film and the third portion defined by the silicon nitride film is larger than the opening width in the first portion defined by the insulating film. A sixth step of narrowing A seventh step of forming, after the sixth step, the lower electrode of the capacitor electrically connected to the conductor along the inner surface of the opening without being in contact with the upper surface of the second insulating film; An eighth step of forming an upper electrode of the capacitor facing the lower electrode through the dielectric film after the seventh step;

  A semiconductor device according to the present invention includes a memory cell region and a peripheral circuit region, and includes an insulating film formed on a main surface of a semiconductor substrate, a capacitor lower electrode, a dielectric film, and a capacitor And an upper electrode. The insulating film having an upper surface is formed on the main surface of the semiconductor substrate so as to extend from the memory cell region to the peripheral circuit region. The capacitor lower electrode is formed on the main surface of the semiconductor substrate so as to extend above the upper surface of the insulating film in the memory cell region. The capacitor upper electrode is formed to extend to the upper surface of the insulating film with the dielectric film interposed on the capacitor lower electrode. The capacitor lower electrode includes a capacitor lower electrode portion that extends upward to face the capacitor upper electrode and has a top surface and a bottom surface. The upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode portion.

  Thus, in the semiconductor device, since the upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode portion, the capacitor lower electrode is partially embedded in the insulating film. It is in the state. Therefore, the step between the upper surface of the insulating film extending from the memory cell region to the peripheral circuit region and the top surface of the capacitor lower electrode portion in the memory cell region can be made smaller than before. As a result, even when an interlayer insulating film is formed on the capacitor lower electrode and the insulating film, the step on the upper surface of the interlayer insulating film is reduced between the memory cell region and the peripheral circuit region. It becomes possible. As a result, even when a wiring layer is formed on the insulating film by photolithography, it is possible to prevent the problem that the wiring pattern becomes unclear due to the step on the upper surface of the interlayer insulating film. As a result, it is possible to prevent problems such as disconnection or short circuit of the wiring due to unclear wiring patterns. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  In addition, since the capacitor lower electrode is partially embedded in the insulating film, the capacitor lower electrode positioned between the top surface of the capacitor lower electrode portion and the upper surface of the insulating film The capacitor upper electrode can be formed on the outer side surface of the portion with the dielectric film interposed therebetween. Thereby, the external side surface of the capacitor lower electrode portion can also be used as a capacitor, so that the capacitance of the capacitor can be increased.

  Further, by changing the position of the upper surface of the insulating film, the area of the external side surface of the capacitor lower electrode portion that can be used as a capacitor can be changed. As a result, the capacitance of the capacitor can be changed without changing the shape of the capacitor lower electrode.

  A semiconductor device according to the present invention includes a memory cell region and a peripheral circuit region, and includes a semiconductor substrate having a main surface, an insulating film, a capacitor lower electrode, a dielectric film, and a capacitor upper electrode. With. The insulating film is formed on the main surface of the semiconductor substrate so as to extend from the memory cell region to the peripheral circuit region. The capacitor lower electrode including the first and second capacitor lower electrodes is formed on the main surface of the semiconductor substrate so as to extend to substantially the same height as the upper surface of the insulating film in the memory cell region. Yes. The first and second capacitor lower electrodes are adjacent to each other through part of the insulating film. The capacitor upper electrode is formed to extend to the upper surface of the insulating film with the dielectric film interposed on the capacitor lower electrode. The capacitor lower electrode includes a capacitor lower electrode portion having a top surface and a bottom surface extending upward to face the capacitor upper electrode. A part of the insulating film has a width smaller than the minimum processing dimension that can be formed by photolithography.

  As described above, in the semiconductor device, the capacitor lower electrode is formed on the main surface of the semiconductor substrate so as to extend to almost the same height as the upper surface of the insulating film in the memory cell region. The capacitor lower electrode is entirely embedded in the insulating film. Therefore, it is possible to prevent the occurrence of a step due to the capacitor lower electrode on the upper surface of the insulating film formed in the memory cell region and the peripheral circuit region. Therefore, even when an interlayer insulating film is formed on the capacitor lower electrode portion and the insulating film, a step is generated on the upper surface of the interlayer insulating film between the memory cell region and the peripheral circuit region. Can be prevented. As a result, even when a wiring layer is formed on the interlayer insulating film by photolithography, the problem that the wiring pattern becomes unclear due to the step on the upper surface of the interlayer insulating film is prevented. it can. For this reason, since the pattern of the said wiring is unclear, it can prevent that the problem of the disconnection of the said wiring, or a short circuit generate | occur | produces. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  In addition, since the width of a part of the insulating film existing between the first and second capacitor lower electrodes is smaller than the minimum processing dimension that can be formed by photolithography, the first and second portions are more than conventional. The distance between the capacitor lower electrodes can be reduced. As a result, the semiconductor device can be more highly integrated.

  In the semiconductor device according to the present invention, the side surface of the capacitor lower electrode has a curved surface in the configuration described above. For this reason, the surface area of the side surface of the capacitor lower electrode can be increased as compared with the case where the side surface is flat like the conventional capacitor lower electrode. For this reason, it is possible to further reduce the area occupied by the capacitor while securing a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  In the semiconductor device, the insulating film includes an upper insulating film and a lower insulating film having different etching rates. For this reason, in the manufacturing process described later, the lower insulating film is selectively removed when performing a step of making the width of a part of the insulating film smaller than the minimum processing dimension that can be formed by photolithography using etching. By using the etching conditions, only a part of the side surface of the lower insulating film in the part of the insulating film can be removed by etching. For this reason, the width of a part of the insulating film can be reduced, and at the same time, the upper insulating film can be left without being etched. Thereby, it is possible to prevent the upper surface of the upper insulating film from being removed by etching in the etching step of reducing the width of a part of the insulating film. As a result, it is possible to prevent the height of the side surface of the capacitor lower electrode formed in the subsequent process from being lowered. As a result, the surface area of the capacitor lower electrode can be prevented from being reduced, and the capacitance of the capacitor can be prevented from decreasing.

  In the semiconductor device, the capacitor lower electrode includes first and second capacitor lower electrodes. The first and second capacitor lower electrodes are formed in the memory cell region so as to be adjacent to each other through a part of the insulating film. A part of the insulating film has a width smaller than the minimum processing dimension that can be formed by photolithography. As described above, since the width of a part of the insulating film existing between the first and second capacitor lower electrodes is smaller than the minimum processing dimension that can be formed by photolithography, the first and second capacitors can be formed as compared with the prior art. The distance between the two capacitor lower electrodes can be reduced. As a result, the semiconductor device can be more highly integrated.

  The semiconductor device includes a sidewall electrode portion formed on a side surface of the capacitor lower electrode located above the upper surface of the insulating film. For this reason, the surface area of the side surface of the capacitor lower electrode can be increased conventionally by forming the sidewall electrode portion. As a result, the capacitance of the capacitor can be increased. Therefore, the area occupied by the capacitor lower electrode can be reduced as compared with the prior art while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  The semiconductor device includes the dielectric film formed between only a part of a side surface or a bottom surface of the capacitor lower electrode portion and the insulating film. In this case, since the dielectric film is provided between only the side or bottom part of the capacitor lower electrode part and the insulating film, the side or bottom part of the capacitor lower electrode part is used as a capacitor. it can. For this reason, the capacitance of the capacitor can be increased without changing the shape of the capacitor lower electrode.

  Further, in the manufacturing process of the semiconductor device, the dielectric film is formed between the insulating film and a part of only the side surface or the bottom surface of the capacitor lower electrode portion. Therefore, the dielectric film is formed for this purpose. A void is formed in a region where Therefore, in the step of forming the gap, it is possible to keep the other part of the bottom surface of the capacitor lower electrode portion in contact with a layer such as another insulating film. For this reason, even when the semiconductor substrate on which the semiconductor device is formed is cleaned in the state where the gap is formed, the part in contact with the other part of the bottom surface of the capacitor lower electrode part. An insulating film or the like acts as a reinforcing member against physical impact. Accordingly, it is possible to prevent a problem that a part of the capacitor lower electrode is broken due to an impact such as vibration in the cleaning process. As a result, malfunction of the semiconductor device due to defects such as partial breakage of the capacitor lower electrode can be prevented, and a highly reliable semiconductor device can be obtained.

  The semiconductor device includes a granular crystal on a surface of the capacitor lower electrode or a surface of the sidewall electrode portion in the configuration. Therefore, the surface area of the capacitor lower electrode can be increased without increasing the area occupied by the capacitor lower electrode. As a result, the capacitance of the capacitor can be increased. For this reason, the area occupied by the capacitor lower electrode can be made smaller than before while securing the capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  In the above-described configuration, the semiconductor device includes a first wiring layer and a first interlayer insulating film. The first wiring layer is formed on the main surface of the semiconductor substrate in a region located under the capacitor lower electrode. The first interlayer insulating film is formed on the first wiring layer so as to be in contact with the first wiring layer and the capacitor lower electrode portion. Thus, since the first interlayer insulating film is formed so as to be in contact with the first wiring layer and the capacitor lower electrode portion, the first wiring layer and the first interlayer insulating film The number of layers formed in the memory cell region can be reduced as compared with the case where a protective insulating film for protecting the first wiring is formed therebetween. For this reason, the height of the top surface of the capacitor lower electrode portion in the memory cell region can be reduced. Thereby, even when an interlayer insulating film is formed on the capacitor lower electrode and the insulating film, the step on the upper surface of the interlayer insulating film between the memory cell region and the peripheral circuit region is reduced. Can do. As a result, even when a wiring layer is formed on the interlayer insulating film by photolithography, the occurrence of problems such as unclear wiring patterns due to the steps on the upper surface of the interlayer insulating film is prevented. it can. As a result, it is possible to more effectively prevent a problem such as disconnection or short circuit of the wiring due to the unclear wiring pattern.

  The semiconductor device includes, in its configuration, a first conductive region, a second interlayer insulating film, a second wiring layer, and a connection conductor film. The first conductive region is formed on the main surface of the semiconductor substrate in a region located under the capacitor lower electrode. The second interlayer insulating film is formed on the first conductive region, and has a first contact hole exposing the surface of the first conductive region. The second wiring layer is formed on the second interlayer insulating film. The connection conductor film is formed in the first contact hole so as to electrically connect the first conductive region and the second wiring layer. The second wiring layer has a width smaller than the width of the first contact hole.

  Thus, since the width of the second wiring layer is smaller than the width of the first contact hole, the width of the second wiring layer completely covers the first contact hole as in the prior art. The semiconductor device can be miniaturized as compared with the case of such a size.

  The semiconductor device includes, in its configuration, a second conductive region, a third interlayer insulating film, a third wiring layer, a wiring protective film, and a conductor film. The second conductive region is formed on the main surface of the semiconductor substrate in a region located under the capacitor lower electrode. The third interlayer insulating film is formed on the second conductive region and has a second contact hole exposing the surface of the second conductive region. The conductor film is formed in the second contact hole so as to electrically connect the second conductive region and the capacitor lower electrode. The wiring protective film is in contact with the capacitor lower electrode or the conductor film.

  Thus, since the wiring protective film is in contact with the capacitor lower electrode or the conductor film, as a mask for etching when forming the second contact hole in the manufacturing process of the semiconductor device, The wiring protective film can be used. For this reason, in order to form the said 2nd contact hole, the process of forming the resist pattern used as a mask independently becomes unnecessary, and the manufacturing process number of a semiconductor device can be reduced.

  The semiconductor device includes a fourth interlayer insulating film and a peripheral circuit element protective film in its configuration. The capacitor upper electrode is formed to extend to the peripheral circuit region. The fourth interlayer insulating film is formed on the capacitor upper electrode and has a third contact hole exposing the surface of the capacitor upper electrode. The peripheral circuit element protective film is formed under the insulating film in a region located under the third contact hole.

  Thus, since the peripheral circuit element protective film is formed under the insulating film in the region located under the third contact hole, when the third contact hole is formed by etching, Even when the third contact hole penetrates the capacitor upper electrode and reaches the insulating film, the progress of etching can be prevented in the peripheral circuit element protective film. For this reason, it is possible to prevent peripheral circuit elements such as field effect transistors and wirings in the peripheral circuit region from being damaged by the etching for forming the third contact hole. This can prevent the semiconductor device from malfunctioning due to damage to the element wiring in the peripheral circuit region. As a result, a highly reliable semiconductor device can be obtained.

  The semiconductor device includes a peripheral circuit insulating film and a fourth interlayer insulating film in its configuration. The peripheral circuit insulating film has a peripheral circuit region opening in the peripheral circuit region. The capacitor upper electrode is formed to extend to the inside of the peripheral circuit region opening. The fourth interlayer insulating film has a fourth contact hole formed on the peripheral circuit region opening and exposing the surface of the capacitor upper electrode.

  Thus, the capacitor upper electrode is formed so as to extend to the inside of the peripheral circuit region opening, and the fourth contact hole is formed on the peripheral circuit region opening. The fourth contact hole can be formed so as to reach the capacitor upper electrode inside the region opening. For this reason, by adjusting the depth of the peripheral circuit region opening and the film thickness of the capacitor upper electrode, the fourth difference is made so as to reduce the difference between the depths of the other contact holes in the peripheral circuit region. The reach depth of the contact hole can be changed. As a result, the fourth contact hole penetrates the capacitor upper electrode due to a difference in the arrival depth between the fourth contact hole and the other contact hole in the peripheral circuit region, and the field effect transistor It is possible to prevent peripheral circuit elements such as wiring and wiring from being damaged. Thereby, it is possible to prevent the semiconductor device from causing malfunction such as malfunction due to damage of the peripheral circuit element. As a result, a highly reliable semiconductor device can be obtained.

  The semiconductor device includes a fourth interlayer insulating film and a peripheral circuit element in its configuration. The capacitor upper electrode is formed to extend to the peripheral circuit region. The fourth interlayer insulating film is formed on the capacitor upper electrode and has a fifth contact hole exposing the surface of the capacitor upper electrode. The peripheral circuit element is formed under the insulating film in the peripheral circuit region. The fifth contact hole is formed in a region that does not overlap the peripheral circuit element in plan view. Thus, since the fifth contact hole is formed in a region that does not overlap with the peripheral circuit element in a plan view, the capacitor upper electrode is formed when etching for forming the fifth contact hole is performed. Even if the etching progresses through, the peripheral circuit element can be prevented from being damaged by the etching. Thereby, it is possible to prevent the semiconductor device from causing malfunction such as malfunction due to damage of the peripheral circuit element. As a result, a highly reliable semiconductor device can be obtained.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a memory cell region and a peripheral circuit region, and includes the following steps. An insulating film having an upper surface is formed on the main surface of the semiconductor substrate so as to extend from the memory cell region to the peripheral circuit region. In the memory cell region, an opening is formed by removing a part of the insulating film by etching. A capacitor lower electrode is formed inside the opening on the main surface of the semiconductor substrate. A capacitor upper electrode is formed to extend over the upper surface of the insulating film with a dielectric film interposed on the capacitor lower electrode. The step of forming the capacitor lower electrode includes a step of forming a capacitor lower electrode portion that extends upward to face the capacitor upper electrode and has a top surface and a bottom surface. The step of forming the insulating film includes a step of positioning the position of the upper surface of the insulating film between the top surface and the bottom surface of the capacitor lower electrode portion.

  As described above, the step of forming the insulating film includes the step of positioning the position of the upper surface of the insulating film between the top surface and the bottom surface of the capacitor lower electrode portion. The film can be partially embedded in the film. For this reason, the step between the upper surface of the insulating film extending from the memory cell region to the peripheral circuit region and the top surface of the capacitor lower electrode portion in the memory cell region can be reduced compared to the conventional case. it can. For this reason, even when an interlayer insulating film is formed on the capacitor lower electrode portion and the insulating film, the step on the upper surface of the interlayer insulating film is reduced between the memory cell region and the peripheral circuit region. It becomes possible to do. As a result, even when a wiring layer is formed on the interlayer insulating film by photolithography, the pattern of the wiring layer can be prevented from becoming unclear due to a step on the upper surface of the interlayer insulating film. For this reason, since the pattern of the said wiring layer is unclear, it can prevent that problems, such as a disconnection and a short circuit of the said wiring layer, generate | occur | produce. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  Further, since the capacitor lower electrode can be partially embedded in the insulating film, the capacitor lower electrode located between the top surface of the capacitor lower electrode portion and the upper surface of the insulating film. The capacitor upper electrode can be formed on the outer side surface of the electrode portion with the dielectric film interposed therebetween. Thereby, the external side surface of the capacitor lower electrode portion can be used as a capacitor, so that the capacitance of the capacitor can be increased.

  Further, by changing the position of the upper surface on the insulating film, the area of the external side surface of the capacitor lower electrode portion used as a capacitor can be changed. As a result, the capacitance of the capacitor can be controlled without changing the shape of the capacitor lower electrode.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a memory cell region and a peripheral circuit region, and includes the following steps. An insulating film having an upper surface is formed on the main surface of the semiconductor substrate so as to extend from the memory cell region to the peripheral circuit region. In the memory cell region, a part of the insulating film is removed by etching, thereby forming an opening including the adjacent first and second openings. By expanding the width of the opening by etching, the width of a part of the insulating film formed between the first and second openings is smaller than the minimum processing dimension that can be formed by photolithography. To do. A capacitor lower electrode is formed in the opening so as to extend to substantially the same height as the upper surface of the insulating film on the main surface of the semiconductor substrate. A capacitor upper electrode is formed to extend over the upper surface of the insulating film with a dielectric film interposed on the capacitor lower electrode. The step of forming the capacitor lower electrode includes the step of forming first and second capacitor lower electrodes in the first and second openings, respectively. Further, the step of forming the capacitor lower electrode includes a step of forming a capacitor lower electrode portion extending upward facing the capacitor upper electrode and having a top surface and a bottom surface.

  In this way, the capacitor lower electrode is formed in the opening so as to extend to the same height as the upper surface of the insulating film on the main surface of the semiconductor substrate. Therefore, the capacitor lower electrode is formed on the insulating film. Can be embedded entirely. Therefore, it is possible to prevent the occurrence of a step due to the capacitor lower electrode on the upper surface of the insulating film formed with the memory cell region and the peripheral circuit region. Therefore, even when an interlayer insulating film is formed on the capacitor lower electrode and the insulating film, a step is generated on the upper surface of the interlayer insulating film between the memory cell region and the peripheral circuit region. Can be prevented. As a result, even when the wiring layer is formed on the interlayer insulating film by photolithography, it is possible to prevent the pattern of the wiring layer from becoming unclear due to the step on the upper surface of the interlayer insulating film. For this reason, since the pattern of the said wiring layer is unclear, it can prevent that the problem of the disconnection of the said wiring layer or a short circuit generate | occur | produces. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  In addition, since the width of a part of the insulating film existing between the first and second capacitor lower electrodes is smaller than the minimum processing dimension that can be formed by photolithography, the first and second types have been conventionally achieved. The interval between the capacitor lower electrodes can be reduced. As a result, the semiconductor device can be more highly integrated.

  In the method of manufacturing the semiconductor device, in the configuration, the step of increasing the width of the opening by etching includes a step of forming a side surface of the opening to have a curved surface. Therefore, in the step of forming the capacitor lower electrode inside the opening, the side surface of the capacitor lower electrode can also be formed to have a curved surface. Thereby, the surface area of the side surface of the capacitor lower electrode can be made larger than the planar side surface of the conventional capacitor lower electrode. As a result, the area occupied by the capacitor can be further reduced while securing a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  In the structure of the method for manufacturing a semiconductor device, in the configuration, the step of forming the insulating film includes a step of forming a lower insulating film, and an upper insulating film having a different etching rate from the lower insulating film. Forming. For this reason, in the step of reducing the width of a part of the insulating film to be smaller than the minimum processing dimension that can be formed by photolithography, one condition of the insulating film is obtained by using a condition that the lower insulating film is selectively etched. Only a part of the side surface of the lower insulating film, which is a part, can be removed by etching. Thereby, the width of a part of the insulating film can be reduced, and at the same time, the upper insulating film can be left without being etched. Thereby, in the step of reducing the width of a part of the insulating film, the upper surface of the upper insulating film is removed by etching, so that the height of the side surface of the capacitor lower electrode formed thereafter is reduced. Can be prevented. As a result, the surface area of the capacitor lower electrode can be prevented from being reduced, and the capacitance of the capacitor can be prevented from being reduced.

  In the method of manufacturing the semiconductor device, in the configuration, the step of forming the insulating film includes a step of forming a lower insulating film, and an upper insulating film having a different etching rate from the lower insulating film on the lower insulating film. Forming. The step of positioning the upper surface of the insulating film between the top surface and the bottom surface of the capacitor lower electrode portion includes a step of removing the upper insulating film. For this reason, the position of the upper surface of the insulating film can be arbitrarily changed by changing the film thickness of the upper insulating film. For this reason, the area of the external side surface of the capacitor lower electrode portion used as a capacitor can be changed. As a result, the capacitance of the capacitor can be changed without changing the shape of the capacitor lower electrode.

  In the method of manufacturing the semiconductor device, in the configuration, the step of positioning the upper surface of the insulating film between the top surface and the bottom surface of the capacitor lower electrode portion is a step of removing a part of the insulating film by etching. including. Therefore, in the step of removing a part of the insulating film by etching, the position of the upper surface of the insulating film is arbitrarily changed by changing the film thickness of a part of the insulating film to be removed by the etching. be able to. Thereby, the area of the external side surface of the capacitor lower electrode portion used as a capacitor can be changed. As a result, the capacitance of the capacitor can be changed without changing the shape of the capacitor lower electrode.

  In the method of manufacturing the semiconductor device, in the configuration, the step of forming the opening includes removing the part of the insulating film by etching, so that the first opening and the second opening adjacent to each other Forming a step. The step of forming the capacitor lower electrode includes a step of forming first and second capacitor lower electrodes in the first and second openings, respectively. Then, by widening the width of the first and second openings by etching, the width of a part of the insulating film formed between the first and second openings is changed to photolithography. The process of making smaller than the minimum processing dimension which can be formed is provided. Thus, the width of a part of the insulating film formed between the first and second openings is made smaller than the minimum processing dimension that can be formed by photolithography, so that the first The interval between the first and second capacitor lower electrodes can be reduced. As a result, the semiconductor device can be more highly integrated.

  The method for manufacturing a semiconductor device includes a step of forming a sidewall electrode portion on a side surface of the capacitor lower electrode located above the upper surface of the insulating film. Thus, by forming the sidewall electrode portion, the surface area of the side surface of the capacitor lower electrode can be increased as compared with the conventional case. As a result, the capacitor capacity can be increased. Therefore, the area occupied by the capacitor lower electrode can be reduced as compared with the prior art while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  The semiconductor device manufacturing method further includes the following steps in its configuration. A gap forming insulating film is formed on a part of the side or bottom of the opening. After forming the capacitor lower electrode, by removing at least part of the gap forming insulating film by etching, a gap is formed between only the side or bottom part of the capacitor lower electrode part and the insulating film. Form. Thus, since a gap is formed between only part of the side surface or bottom surface of the capacitor lower electrode portion and the insulating film, the dielectric film and the capacitor upper electrode are formed on the capacitor lower electrode portion in the gap. As a result, a part of the side surface or bottom surface of the capacitor lower electrode portion can be used as a capacitor. For this reason, the capacitance of the capacitor can be increased without changing the shape of the capacitor lower electrode.

  In addition, since a gap is formed between only part of the side surface or bottom surface of the capacitor lower electrode part and the insulating film, another part of the bottom surface of the capacitor lower electrode part is formed with another layer such as an insulating film. It can be kept in contact. Therefore, even in the step of cleaning the semiconductor substrate on which the semiconductor device is formed in the state where the gap is formed, the insulating film that is in contact with the other part of the bottom surface of the capacitor lower electrode portion Etc. act as a reinforcing member. Accordingly, it is possible to prevent a problem that a part of the capacitor lower electrode is broken due to physical vibration in the cleaning process. As a result, malfunction of the semiconductor device due to defects such as partial breakage of the capacitor lower electrode can be prevented, and a highly reliable semiconductor device can be obtained.

  The method for manufacturing a semiconductor device includes a step of forming a granular crystal on at least a part of the surface of the capacitor lower electrode or the surface of the sidewall. For this reason, it is possible to increase the surface area of the capacitor lower electrode without increasing the area occupied by the capacitor lower electrode. As a result, the area occupied by the capacitor lower electrode can be reduced as compared with the prior art while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  The semiconductor device manufacturing method includes the following steps in its configuration. In a region located under the capacitor lower electrode, a first wiring layer is formed on the main surface of the semiconductor substrate. A first interlayer insulating film is formed on the first wiring layer so as to be in contact with the first wiring layer. The step of forming the capacitor lower electrode includes the step of forming the capacitor lower electrode portion so as to be in contact with the first interlayer insulating film. Thus, since the first interlayer insulating film is formed so as to be in contact with the first wiring layer and the capacitor lower electrode portion, the first wiring layer and the first interlayer insulating film The height of the top surface of the capacitor lower electrode portion in the memory cell region can be made lower than when a protective insulating film for protecting the first wiring is formed therebetween. Thereby, even when an interlayer insulating film is formed on the capacitor lower electrode and the insulating film, the step on the upper surface of the interlayer insulating film between the memory cell region and the peripheral circuit region is reduced. Can do. As a result, even when a wiring layer is formed on the interlayer insulating film by photolithography, the pattern of the wiring layer can be prevented from becoming unclear due to a step on the upper surface of the interlayer insulating film. For this reason, since the pattern of the said wiring layer is unclear, it can prevent that the problem of the disconnection of the said wiring layer or a short circuit generate | occur | produces. As a result, it is possible to obtain a semiconductor device having high reliability while ensuring the capacitance of the capacitor while achieving high integration.

  The semiconductor device manufacturing method further includes the following steps in its configuration. In a region located under the capacitor lower electrode, a first conductive region is formed on the main surface of the semiconductor substrate. A second interlayer insulating film is formed on the first conductive region. A second wiring layer is formed on the second interlayer insulating film. A part of the second interlayer insulating film is removed by etching to form a first contact hole. A connection conductor film for electrically connecting the first conductive region and the second wiring layer is formed inside the first contact hole. The step of forming the second wiring layer includes a step of making the width of the second wiring layer smaller than the width of the first contact hole.

  As described above, since the width of the second wiring layer is smaller than the width of the first contact hole, the width of the second wiring layer is set to the first contact hole as in the prior art. The semiconductor device can be made finer than the case where the size of the semiconductor device is completely covered.

  The semiconductor device manufacturing method further includes the following steps in its configuration. In a region located below the capacitor lower electrode, a second conductive region is formed on the main surface of the semiconductor substrate. A third interlayer insulating film is formed on the second conductive region. A third wiring layer is formed on the third interlayer insulating film. A wiring protective film is formed on the third wiring layer. In order to electrically connect the second conductive region and the capacitor lower electrode, at least a part of the third interlayer insulating film is removed by etching to form a second contact hole. The wiring protective film is used as part of a mask used for etching in the step of forming the second contact hole.

  Thus, since the wiring protective film is used as a mask in the etching in the step of forming the second contact hole, a resist pattern used as a mask independently is used to form the second contact hole. The forming step can be omitted. Thereby, the number of manufacturing steps of the semiconductor device can be reduced.

  The semiconductor device manufacturing method further includes the following steps in its configuration. The capacitor upper electrode is formed so as to extend to the peripheral circuit. A fourth interlayer insulating film is formed on the capacitor upper electrode. In the peripheral circuit region, a third contact hole is formed by removing at least a part of the fourth interlayer insulating film by etching. In the region located under the third contact hole, a peripheral circuit element protective film is formed under the insulating film. The step of forming the third contact hole includes a step of exposing a part of the capacitor upper electrode on a side surface or a bottom surface of the third contact hole.

  As described above, since the peripheral circuit element protective film is formed, when the third contact hole is formed by etching, the third contact hole penetrates the capacitor upper electrode and reaches the insulating film. Even in this case, the progress of etching can be prevented by the peripheral circuit element protective film. For this reason, it is possible to prevent peripheral circuit elements such as field effect transistors and wirings in the peripheral circuit region from being damaged by the etching for forming the third contact hole. Thereby, it is possible to prevent the semiconductor device from malfunctioning due to the damage of the peripheral circuit element. As a result, a highly reliable semiconductor device can be obtained.

  The semiconductor device manufacturing method further includes the following steps in its configuration. A peripheral circuit insulating film is formed in the peripheral circuit region. A peripheral circuit region opening is formed by removing a part of the peripheral circuit insulating film by etching. The capacitor upper electrode is formed so as to extend to the inside of the peripheral circuit region opening. A fourth interlayer insulating film is formed on the capacitor upper electrode. A part of the fourth interlayer insulating film in the region located on the peripheral circuit region opening is removed by etching to form a fourth contact hole. The step of forming the fourth contact hole includes a step of exposing a part of the capacitor upper electrode at the bottom of the fourth contact hole.

  Thus, the capacitor upper electrode is formed so as to extend to the inside of the peripheral circuit region opening, and the fourth contact hole is formed on the peripheral circuit region opening. Within the opening, the fourth contact hole can be formed to reach the capacitor upper electrode. Therefore, by adjusting the depth of the peripheral circuit region opening and the thickness of the capacitor upper electrode, the difference between the reach depth of other contact holes in the peripheral circuit region is reduced. The reach depth of the contact hole can be changed. As a result, the fourth contact hole penetrates the capacitor upper electrode due to a difference in reach depth between the fourth contact hole and the other contact hole in the peripheral circuit region, and the field effect type It is possible to prevent peripheral circuit elements such as transistors and wirings from being damaged. Thereby, it is possible to prevent the semiconductor device from malfunctioning due to damage to the peripheral circuit element. As a result, a highly reliable semiconductor device can be obtained.

  The semiconductor device manufacturing method further includes the following steps in its configuration. The capacitor upper electrode is formed to extend to the peripheral circuit region. A fourth interlayer insulating film is formed on the capacitor upper electrode. In the peripheral circuit region, a fifth contact hole is formed by removing at least part of the fourth interlayer insulating film by etching. In the peripheral circuit region, a peripheral circuit element is formed in a region located under the insulating film. The step of forming the fifth contact hole further includes the following steps. A part of the capacitor upper electrode is exposed at the bottom of the fifth contact hole. The fifth contact hole is formed in a region that does not overlap the peripheral circuit element in plan view.

  Thus, since the fifth contact hole is formed in a region that does not overlap with the peripheral circuit element in a planar manner, the capacitor upper electrode is formed when performing etching for forming the fifth contact hole. Even if etching proceeds through the substrate, the peripheral circuit element can be prevented from being damaged. Thereby, it is possible to prevent the semiconductor device from malfunctioning due to the damage of the peripheral circuit element. As a result, a highly reliable semiconductor device can be obtained.

  As described above, according to the present invention, the semiconductor includes a memory cell region and a peripheral circuit region, and includes an insulating film, a capacitor lower electrode including a capacitor lower electrode portion, a dielectric film, and a capacitor upper electrode. Configure the device. The upper surface of the insulating film is substantially the same as the top surface of the capacitor lower electrode portion or between the top surface and the bottom surface of the capacitor lower electrode portion. As a result, it is possible to provide a highly reliable semiconductor device and a method for manufacturing the same, while ensuring a certain capacitor capacity and simultaneously achieving high integration.

1 is a schematic plan view of a memory cell of a DRAM according to a first embodiment of the present invention. 1 is a cross-sectional view of a memory cell region and a peripheral circuit region of a DRAM according to Embodiment 1 of the present invention. FIG. 5 is a cross sectional view for illustrating a first step of a manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIG. FIG. 10 is a cross sectional view for illustrating a second step of the manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIG. FIG. 10 is a cross sectional view for illustrating a third step of the DRAM manufacturing process according to the first embodiment of the present invention shown in FIG. FIG. 10 is a cross sectional view for illustrating a fourth step of the DRAM manufacturing process according to the first embodiment of the present invention shown in FIG. 2. FIG. 10 is a cross sectional view for illustrating a fifth step of the DRAM manufacturing step according to the first embodiment of the present invention shown in FIG. 2. It is sectional drawing for demonstrating the 6th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 7th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 8th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 9th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 10th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 11th process of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. FIG. 11 is a cross sectional view for illustrating a first step in a variation of the manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIG. 2. It is sectional drawing for demonstrating the 2nd process of the modification of the manufacturing process of DRAM by Embodiment 1 of this invention shown in FIG. It is sectional drawing for demonstrating the 1st modification of DRAM by Embodiment 1 of this invention. It is sectional drawing for demonstrating the 2nd modification of DRAM by Embodiment 1 of this invention. FIG. 18 is a cross sectional view for illustrating a first step of a manufacturing process of the second modification example of the DRAM according to the first embodiment of the present invention shown in FIG. 17. FIG. 18 is a cross sectional view for illustrating a second step of the manufacturing process of the second modification of the DRAM according to the first embodiment of the present invention shown in FIG. 17. FIG. 18 is a cross sectional view for illustrating a third step of the manufacturing process of the second modification example of the DRAM according to the first embodiment of the present invention shown in FIG. 17. It is sectional drawing for demonstrating the 3rd modification of DRAM by Embodiment 1 of this invention. FIG. 23 is a cross sectional view for illustrating a first step of a manufacturing process of the third modification of the DRAM according to the first embodiment of the present invention shown in FIG. 21. FIG. 23 is a cross sectional view for illustrating a second step of the manufacturing process of the third modification of the DRAM according to the first embodiment of the present invention shown in FIG. 21. FIG. 22 is a cross sectional view for illustrating a third step of the manufacturing step of the third modification of the DRAM according to the first embodiment of the present invention shown in FIG. 21. It is sectional drawing for demonstrating the 4th modification of DRAM by Embodiment 1 of this invention. FIG. 26 is a cross sectional view for illustrating a first step of a manufacturing process of the fourth variation of the DRAM according to the first embodiment of the present invention shown in FIG. 25. It is sectional drawing for demonstrating DRAM by Embodiment 2 of this invention. FIG. 28 is a cross sectional view for illustrating a first step of a manufacturing process of the DRAM according to the second embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross sectional view for illustrating a second step of the DRAM manufacturing process according to the second embodiment of the present invention shown in FIG. 27. It is sectional drawing for demonstrating the 1st modification of DRAM by Embodiment 2 of this invention. FIG. 31 is a cross sectional view for illustrating a first step of a manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention shown in FIG. 30. FIG. 31 is a cross sectional view for illustrating a second step of a manufacturing step of the first modification of the DRAM according to the second embodiment of the present invention shown in FIG. 30. It is sectional drawing for demonstrating the 2nd modification of DRAM by Embodiment 2 of this invention. FIG. 34 is a cross sectional view for illustrating a first step of a manufacturing step of the second modification of the DRAM according to the second embodiment of the present invention shown in FIG. 33. It is sectional drawing for demonstrating the 3rd modification of DRAM by Embodiment 2 of this invention. FIG. 36 is a cross sectional view for illustrating a first step of a manufacturing process of the third modification of the DRAM according to the second embodiment of the present invention shown in FIG. 35. It is sectional drawing for demonstrating the 4th modification of DRAM by Embodiment 2 of this invention. FIG. 38 is a cross sectional view for illustrating a first step of a manufacturing process of the fourth modification example of the DRAM according to the second embodiment of the present invention shown in FIG. 37. It is sectional drawing for demonstrating DRAM by Embodiment 3 of this invention. FIG. 40 is a cross sectional view for illustrating a first step of a manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. 39. FIG. 40 is a cross sectional view for illustrating a second step of the manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. 39. FIG. 40 is a cross sectional view for illustrating a third step of the manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. 39. It is sectional drawing for demonstrating the 1st modification of DRAM by Embodiment 3 of this invention. FIG. 44 is a cross sectional view for illustrating a first step of a manufacturing step of the first modification of the DRAM according to the third embodiment of the present invention shown in FIG. 43. FIG. 44 is a cross sectional view for illustrating a second step of the manufacturing step of the first modification of the DRAM according to the third embodiment of the present invention shown in FIG. 43. FIG. 44 is a cross sectional view for illustrating a third step of the manufacturing process of the first modification of the DRAM according to the third embodiment of the present invention shown in FIG. 43. It is sectional drawing for demonstrating the 2nd modification of DRAM by Embodiment 3 of this invention. It is sectional drawing for demonstrating the 1st process of the manufacturing process of the 2nd modification of DRAM by Embodiment 3 of this invention. FIG. 48 is a cross sectional view for illustrating a second step of the manufacturing step of the second modification of the DRAM according to the third embodiment of the present invention shown in FIG. 47. It is sectional drawing for demonstrating the structure of DRAM by Embodiment 4 of this invention. FIG. 52 is a cross sectional view for illustrating a first step of a manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIG. 50. FIG. 52 is a cross sectional view for illustrating a second step of the DRAM manufacturing process according to the fourth embodiment of the present invention shown in FIG. 50. FIG. 52 is a cross sectional view for illustrating a third step of the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIG. 50. FIG. 52 is a cross sectional view for illustrating a fourth step of the DRAM manufacturing process according to the fourth embodiment of the present invention shown in FIG. 50. FIG. 52 is a cross sectional view for illustrating a fifth step of the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIG. 50. It is sectional drawing for demonstrating the 1st modification of DRAM by Embodiment 4 of this invention. FIG. 57 is a cross sectional view for illustrating a first step of a manufacturing process of the first modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 56. It is sectional drawing for demonstrating the 2nd modification of DRAM by Embodiment 4 of this invention. FIG. 59 is a cross sectional view for illustrating a first step of a manufacturing process of the second modification example of the DRAM according to the fourth embodiment of the present invention shown in FIG. 58. It is sectional drawing for demonstrating the 3rd modification of DRAM by Embodiment 4 of this invention. FIG. 67 is a cross sectional view for illustrating a first step of a manufacturing process of the third modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 60. FIG. 67 is a cross sectional view for illustrating a second step of the manufacturing step of the third modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 60. FIG. 67 is a cross sectional view for illustrating a third step of the manufacturing step of the third modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 60. It is sectional drawing for demonstrating the 4th modification of DRAM by Embodiment 4 of this invention. FIG. 67 is a cross sectional view for illustrating a first step of a manufacturing process of the fourth modification example of the DRAM according to the fourth embodiment of the present invention shown in FIG. 64. It is sectional drawing for demonstrating the structure of DRAM by Embodiment 5 of this invention. It is sectional drawing for demonstrating the 1st process of the manufacturing process of DRAM by Embodiment 5 of this invention. FIG. 67 is a cross sectional view for illustrating a second step of the DRAM manufacturing process according to the fifth embodiment of the present invention shown in FIG. 66. FIG. 67 is a cross sectional view for illustrating a third step of the DRAM manufacturing process according to the fifth embodiment of the present invention shown in FIG. 66. It is sectional drawing which showed the modification of DRAM by Embodiment 5 of this invention. FIG. 71 is a cross sectional view for illustrating a first step of a manufacturing process of a variation of the DRAM according to the fifth embodiment of the present invention shown in FIG. 70. It is sectional drawing for demonstrating the structure of DRAM by Embodiment 6 of this invention. FIG. 73 is a cross sectional view for illustrating a first step of a DRAM manufacturing process according to the sixth embodiment of the present invention shown in FIG. 72. FIG. 73 is a cross sectional view for illustrating a second step of the DRAM manufacturing process according to the sixth embodiment of the present invention shown in FIG. 72. FIG. 73 is a cross sectional view for illustrating a third step of the DRAM manufacturing process according to the sixth embodiment of the present invention shown in FIG. 72. FIG. 73 is a cross sectional view for illustrating a fourth step of the DRAM manufacturing process according to the sixth embodiment of the present invention shown in FIG. 72. FIG. 73 is a cross sectional view for illustrating a fifth step of a DRAM manufacturing step according to the sixth embodiment of the present invention shown in FIG. 72. It is sectional drawing which showed the 1st modification of DRAM by Embodiment 6 of this invention. It is sectional drawing which showed the 2nd modification of DRAM by Embodiment 6 of this invention. FIG. 80 is a cross sectional view for illustrating a first step of a manufacturing process of the second modification example of the DRAM according to the sixth embodiment of the present invention shown in FIG. 79. It is sectional drawing which showed the 3rd modification of DRAM by Embodiment 6 of this invention. It is sectional drawing which showed the 4th modification of DRAM by Embodiment 6 of this invention. It is sectional drawing which showed the 5th modification of DRAM by Embodiment 6 of this invention. It is sectional drawing which showed the 6th modification of DRAM by Embodiment 6 of this invention. It is a plane schematic diagram of the memory cell of DRAM by Embodiment 7 of this invention. It is sectional drawing of DRAM by Embodiment 7 of this invention. It is sectional drawing which showed the modification of DRAM by Embodiment 7 of this invention. It is sectional drawing which showed DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 1st modification of DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 2nd modification of DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 3rd modification of DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 1st modification of the wiring of DRAM by Embodiment 8 of this invention. FIG. 93 is a cross sectional view for illustrating a first step of a manufacturing process of the first modification example of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 92; FIG. 93 is a cross sectional view for illustrating a second step of the manufacturing process of the first modification example of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 92. FIG. 93 is a cross sectional view for illustrating a third step of the manufacturing step of the first modification of the wiring of DRAM according to the eighth embodiment of the present invention shown in FIG. 92. FIG. 93 is a cross sectional view for illustrating a fourth step of the manufacturing process of the first modification example of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 92. FIG. 93 is a cross sectional view for illustrating a first step in a variation of the manufacturing process of the first variation of the DRAM wiring according to the eighth embodiment of the present invention shown in FIG. 92; FIG. 93 is a cross sectional view for illustrating a second step of the modification of the manufacturing step of the first modification of the DRAM wiring according to the eighth embodiment of the present invention shown in FIG. 92; FIG. 93 is a cross sectional view for illustrating a third step of the modification of the manufacturing step of the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 92. FIG. 93 is a cross sectional view for illustrating a fourth step of a modification of the manufacturing process of the first modification of the DRAM wiring according to the eighth embodiment of the present invention shown in FIG. 92; It is sectional drawing which showed the 2nd modification of the wiring of DRAM by Embodiment 8 of this invention. It is sectional drawing for demonstrating the 1st process of the manufacturing process of the 2nd modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing for demonstrating the 2nd process of the manufacturing process of the 2nd modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing for demonstrating the 3rd process of the manufacturing process of the 2nd modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing which showed the 3rd modification of the wiring of DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 4th modification of the wiring of DRAM by Embodiment 8 of this invention. It is sectional drawing which showed the 5th modification of the wiring of DRAM by Embodiment 8 of this invention. It is sectional drawing for demonstrating the 1st process of the manufacturing process of the 5th modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing for demonstrating the 2nd process of the manufacturing process of the 5th modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing explaining the 3rd process of the manufacturing process of the 5th modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing explaining the 4th process of the manufacturing process of the 5th modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing explaining the 5th process of the manufacturing process of the 5th modification of the wiring of DRAM by Embodiment 8 of this invention shown in FIG. It is sectional drawing which shows the 6th modification of the wiring of DRAM by Embodiment 8 of this invention. It is a schematic plan view of a conventional DRAM memory cell. It is sectional drawing of the conventional DRAM. It is sectional drawing of DRAM by another conventional example. In the peripheral circuit area | region of the conventional DRAM, it is sectional drawing which shows the state which the contact hole penetrated the capacitor upper electrode. It is sectional drawing of the conventional wiring. FIG. 119 is a cross sectional view for illustrating a first step of the conventional wiring manufacturing steps shown in FIG. 118. FIG. 119 is a cross sectional view for illustrating a second step of the conventional wiring manufacturing step shown in FIG. 118. It is sectional drawing which showed the wiring by the other conventional example. It is sectional drawing for demonstrating the 1st process of the manufacturing process of the wiring by the other conventional example shown in FIG. It is sectional drawing for demonstrating the 2nd process of the manufacturing process of the wiring by the other conventional example shown in FIG. It is sectional drawing for demonstrating the 3rd process of the manufacturing process of the wiring by the other conventional example shown in FIG.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic plan view of a memory cell region of a DRAM according to the first embodiment of the present invention. Referring to FIG. 1, a DRAM memory cell according to a first embodiment of the present invention includes an active region 39 formed on the main surface of a semiconductor substrate and a field effect transistor formed on the main surface of the semiconductor substrate. It includes word lines 43a, 43b, 43e, 43f that also function as gate electrodes, bit lines 174, and capacitors including capacitor lower electrodes 170a, 170b. Bit line 174 is electrically connected to active region 39 in contact hole 49. The capacitor lower electrodes 170a and 170b are electrically connected to the active region 39 in the contact holes 38a and 38b. FIG. 2 shows a cross-sectional view of the memory cell region taken along line segment 500-500.

  FIG. 2 shows a cross-sectional view taken along line 500-500 of the memory cell of the DRAM according to the first embodiment of the present invention and a partial cross-sectional view of the peripheral circuit region. The structure of the DRAM according to the first embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 2, in the memory cell region of the DRAM according to the first embodiment of the present invention, source / drain regions 201a to 201c of field effect transistors are formed in active region 39 surrounded by trench isolation oxide film 40. Is formed. On the channel region sandwiched between the pair of source / drain regions 201a and 201b, a gate electrode 43a is formed via a gate insulating film 42a. Here, the gate insulating film 42a is composed of a thermal oxide film, a silicon nitride film, a nitrided oxide film, or the like. The gate electrode 43a may be composed of polysilicon or amorphous silicon doped with phosphorus or arsenic, a refractory metal film such as tungsten or titanium, or a silicide film thereof, or a multilayer in which these materials are stacked. It may be a structure. A silicon nitride film 44a is formed on the gate electrode 43a. Side walls 46a and 46b made of a silicon nitride film are formed on the side surfaces of the gate electrode 43a and the silicon nitride film 44a. A non-doped silicon oxide film 47 is formed on the sidewall 46a and the silicon nitride film 44a.

  A gate electrode 43b is formed on the trench isolation oxide film 40 via a gate insulating film 42b. A silicon nitride film 44b is formed on the gate electrode 43b. Side walls 46c and 46d made of a silicon nitride film are formed on the side surfaces of the gate electrode 43b and the silicon nitride film 44b. A non-doped silicon oxide film 47 is formed on the sidewall 46d and the silicon nitride film 44b. A first interlayer insulating film 48 is formed on the non-doped silicon oxide film 47. A contact hole 49 is formed by removing a part of the first interlayer insulating film 48 and the non-doped silicon oxide film 47 by etching. A doped polysilicon film 52 is formed inside the contact hole 49 and on the first interlayer insulating film 48. A refractory metal silicide film 53 is formed on the doped polysilicon film 52. Bit line 174 is formed from doped polysilicon film 52 and refractory metal silicide film 53. A silicon nitride film 54 is formed on the refractory metal silicide film 53. Side walls 55a and 55b made of a silicon nitride film are formed on the side surfaces of the silicon nitride film 54, the refractory metal silicide film 53, and the doped polysilicon film 52. A second interlayer insulating film 37 is formed on the first interlayer insulating film 48, the side walls 55 a and 55 b, and the silicon nitride film 54.

  Contact holes for electrically connecting capacitor lower electrode 170a and one of the source / drain regions by removing portions of first and second interlayer insulating films 48 and 37 and non-doped silicon oxide film 47 38a is formed. A plug 57 made of doped polysilicon is formed in the contact hole 38a. A silicon nitride film 58 is formed on the second interlayer insulating film 37. A capacitor lower electrode 170a is formed on the plug 57a and the second interlayer insulating film 37. The capacitor lower electrode 170a has a cylindrical structure in order to secure the capacitance of the capacitor with a small occupied area. A third interlayer insulating film 59 is formed on the silicon nitride film 58 and on the side surface of the capacitor lower electrode 170a. The upper surface of the third interlayer insulating film 59 is formed so as to be positioned between the top surface 301 and the bottom surface 302 of the capacitor lower electrode portion which is the side surface portion of the cylindrical capacitor lower electrode 170a. . A dielectric film 150 is formed on the capacitor lower electrode 170 a and the third interlayer insulating film 59. A capacitor upper portion 151 is formed on the dielectric film 150. A fourth interlayer insulating film 205 is formed on the capacitor upper electrode 151.

  In the peripheral circuit region of the DRAM according to the first embodiment of the present invention, field effect transistors and wirings 202 are formed on the main surface of semiconductor substrate 1. Specifically, source / drain regions 201 d and 201 e are formed on the main surface of the semiconductor substrate 1. Gate electrodes 43c and 43d are formed on the channel region adjacent to the source / drain regions 201d and 201e via gate insulating films 42c and 42d. Silicon nitride films 44c and 44d are formed on the gate electrodes 43c and 43d. Sidewalls 46e to 46g made of a silicon nitride film are formed on the side surfaces of the gate electrodes 43c and 43d and the silicon nitride films 44c and 44d. A non-doped silicon oxide film 47 is formed on the main surface of the semiconductor substrate 1, the silicon nitride films 44c and 44d, and the sidewalls 46e to 46g. A first interlayer insulating film 48 is formed on the non-doped silicon oxide film 47. Contact holes 50 and 51 are formed by removing a part of first interlayer insulating film 48, non-doped silicon oxide film 47, and silicon nitride film 44c. A doped polysilicon film 52 is formed on the first interlayer insulating film 48 and in the contact holes 50 and 51. A refractory metal silicide film 53 is formed on the doped polysilicon film 52. A wiring 202 in the peripheral circuit region is formed from the doped polysilicon film 52 and the refractory metal silicide film 53. A silicon nitride film 203 is formed on the refractory metal silicide film 53. Side walls 204 a and 204 b made of a silicon nitride film are formed on the side surfaces of the silicon nitride film 203 and the wiring layer 202. A second interlayer insulating film 37 is formed on the first interlayer insulating film 48, the silicon nitride film 203, and the sidewalls 204a and 204b. A silicon nitride film 58 is formed on the second interlayer insulating film 37. A third interlayer insulating film 59 is formed on the silicon nitride film 58. A capacitor dielectric film 150 is formed on the third interlayer insulating film 59 so as to extend from the memory cell region. A capacitor upper electrode 151 is formed on the dielectric film 150. A fourth interlayer insulating film 205 is formed on the third interlayer insulating film 59 and the capacitor upper electrode 151 so as to extend from the memory cell region.

  As described above, in the DRAM according to the first embodiment of the present invention, the capacitor lower electrode 170a is partially embedded in the third interlayer insulating film 59. Therefore, the step between the upper surface of the third interlayer insulating film 59 and the top surface 301 of the capacitor lower electrode 170a can be reduced. Therefore, even when the fourth interlayer insulating film 205 is formed, the step between the upper surface of the fourth interlayer insulating film 205 in the memory cell region and the upper surface of the peripheral circuit region can be made smaller than before. it can. Therefore, even when a wiring layer made of aluminum or the like is formed on the fourth interlayer insulating film 205 by photolithography, the pattern of this wiring layer is caused by the step on the upper surface of the fourth interlayer insulating film 205. Can be prevented from becoming blurred. For this reason, since the said pattern is unclear, it can prevent that the problem like the disconnection of the said wiring layer and the short circuit generate | occur | produced. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  Further, in the DRAM according to the first embodiment of the present invention, capacitor lower electrode 170a is partially embedded in third interlayer insulating film 59, so that it is on the outer side surface of capacitor lower electrode 170a. Also, the dielectric film 150 and the capacitor upper electrode 151 can be formed. For this reason, since the external side surface of the capacitor lower electrode 170a can also be used as a capacitor, the capacitance of the capacitor can be increased.

  Further, by changing the position of the upper surface of the third interlayer insulating film 59, the area of the external side surface of the capacitor lower electrode 170a used as a capacitor can be changed. As a result, the capacitance of the capacitor can be changed without changing the shape of the capacitor lower electrode 170a.

  3 to 13 are cross-sectional views for explaining the manufacturing process of the DRAM according to the first embodiment of the present invention. Hereinafter, a manufacturing process of the DRAM according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 3 is a cross-sectional view for explaining a first step of the manufacturing process of the DRAM according to the first embodiment of the present invention. Referring to FIG. 3, trench isolation oxide film 40 is formed on the main surface of semiconductor substrate 1 in the memory cell region of the DRAM according to the first embodiment of the present invention. An insulating film (not shown) to be a gate insulating film is formed on the main surface of the semiconductor substrate 1. A polysilicon film (not shown) is formed on this insulating film. A silicon nitride film (not shown) is formed on the polysilicon film. After a resist pattern (not shown) is formed on the silicon nitride film, a part of the insulating film, the doped polysilicon film, and the silicon nitride film is removed by anisotropic etching using the resist pattern as a mask. . Thereafter, the resist pattern is removed. In this way, gate insulating films 42a and 42b, gate electrodes 43a and 43b, and silicon nitride films 44a and 44b as shown in FIG. 3 are formed. Then, by using the silicon nitride films 44a and 44b as a mask, impurities are implanted into the active region 39 of the semiconductor substrate 1 to form source / drain regions 201a to 201c of the field effect transistor. Thereafter, the entire surface of the semiconductor substrate is oxidized in a dry atmosphere of 900 ° C. or lower. Thus, an oxide film (not shown) having a thickness of about 50 to 100 mm is formed on the silicon nitride films 44a and 44b, the side surfaces of the gate electrodes 43a and 43b, and the main surface of the semiconductor substrate 1. . Thereafter, a silicon nitride film 45 is formed so as to cover the whole.

  In the peripheral circuit region, the source / drain regions 201d and 201e of the field effect transistor, the gate insulating films 42c and 42d, and the gate electrode are formed on the semiconductor substrate 1 by a process similar to the manufacturing process performed in the memory cell region. 43c, 43d and silicon nitride films 42c, 42d, 45 are formed.

  Next, by removing a part of the silicon nitride film 45 by anisotropic etching, the sidewalls 46a to 46g are formed on the side surfaces of the silicon nitride films 44a to 44d, the gate electrodes 43a to 43d, and the gate insulating films 42a to 42d. Form. Then, as shown in FIG. 4, a non-doped silicon oxide film 47 is formed so as to cover the whole. A first interlayer insulating film 48 made of a phosphorus-doped silicon oxide film is formed on the non-doped silicon oxide film 47. The non-doped silicon oxide film 47 and the first interlayer insulating film 48 made of a phosphorus-doped silicon oxide film are formed using a reduced pressure or atmospheric pressure CVD method. Here, two layers of a non-doped silicon oxide film 37 and a first interlayer insulating film 48 made of a phosphorus-doped silicon oxide film are formed, but the first interlayer insulating film is formed of either one of the materials. May be. Then, after forming the first interlayer insulating film 48, the surface of the first interlayer insulating film 48 is planarized by a chemical mechanical polishing method (CMP method) or a reflow method.

  Next, after forming a resist pattern (not shown) on the first interlayer insulating film 48, the first interlayer insulating film 48, the non-doped silicon oxide film 47, and the like are etched by using the resist pattern as a mask. By removing a part of the contact hole 49, a contact hole 49 is formed as shown in FIG. Thereafter, the resist pattern is removed. In the etching for forming the contact hole 49, the contact hole 49 may be formed in a self-aligning manner using the silicon nitride film 44a and the side wall 46a formed on the gate electrode 43a as a part of the mask. Good.

  Next, a resist pattern (not shown) is formed on the first interlayer insulating film 48 in the peripheral circuit region, and the first interlayer insulating film 48 and the non-doped silicon oxide film 47 are formed using the resist pattern as a mask. By removing a part of the silicon nitride film 44c, contact holes 50 and 51 as shown in FIG. 6 are formed. Thereafter, the resist pattern is removed.

  Next, a doped polysilicon film (not shown) is formed in the contact holes 49, 50, 51 and on the first interlayer insulating film 48. A refractory metal silicide film (not shown) is formed on the doped polysilicon film. A silicon nitride film (not shown) is formed on the refractory metal silicide film. A resist pattern (not shown) is formed on the silicon nitride film. By using this resist pattern as a mask, a part of the silicon nitride film, the refractory metal silicide film and the doped polysilicon film is removed by etching, so that the doped poly-silicon constituting the bit line 174 is formed as shown in FIG. A silicon film 52, a refractory metal silicide film 53, and a silicon nitride film 54 are formed. Similarly, a doped polysilicon film 52 and a refractory metal silicide film 53 that form the wiring 202 in the peripheral circuit region, and a silicon nitride film 203 are formed. Then, after forming a silicon nitride film (not shown) so as to cover the whole, a part of this silicon nitride film is removed by anisotropic etching to form sidewalls 55a, 55b, 204a, 204b. To do. In this way, a structure as shown in FIG. 7 is obtained.

  Next, a second interlayer insulating film 37 made of a phosphorus-doped silicon oxide film on the first interlayer insulating film 48, the silicon nitride films 54 and 203, and the sidewalls 55a, 55b, 204a, and 204b (see FIG. 8). Form. After a resist pattern (not shown) is formed on the second interlayer insulating film 37, the second interlayer insulating film 37, the first interlayer insulating film 48, and the non-doped layer are etched by using the resist pattern as a mask. By removing a part of the silicon oxide film 47, a contact hole 38a (see FIG. 8) is formed. In the etching for forming the contact hole 38a, a reactive ion etching method (Reactive Ion Etching method: hereinafter referred to as RIE method) may be used. Alternatively, the contact holes 38a may be formed in a self-aligning manner using the sidewalls 46b and 46c as part of the mask. Thereafter, a polysilicon film 56 is formed in the contact hole 38a and on the second interlayer insulating film 37 by CVD. The polysilicon film 56 may be an amorphous silicon film. In this way, a structure as shown in FIG. 8 is obtained.

  Then, the polysilicon film 56 located on the second interlayer insulating film 37 is removed by CMP or dry etching. In this way, a structure as shown in FIG. 9 is obtained.

  Next, a silicon nitride film 58 (see FIG. 10) is formed so as to cover the whole. On the silicon nitride film 58, a third interlayer insulating film 59 (see FIG. 10) made of a silicon oxide film is formed. A boron-doped silicon oxide film 60 (see FIG. 10) is formed on the third interlayer insulating film 59. Instead of the boron-doped silicon oxide film 60, a phosphorus-doped silicon oxide film may be used. After a resist pattern (not shown) is formed on the boron-doped silicon oxide film 60, a part of the boron-doped silicon oxide film 60 and the third interlayer insulating film 59 is etched by using this resist pattern as a mask. By removing, an opening 61 (see FIG. 10) is formed. A part of the silicon nitride film 58 existing at the bottom of the opening 61 is removed by phosphoric acid solution or dry etching. Thereafter, the resist pattern is removed. In this way, a structure as shown in FIG. 10 is obtained. Note that the RIE method may be used for etching for forming the opening 61.

  Next, a polysilicon film 62 (see FIG. 11) is formed so as to cover the whole. Instead of this polysilicon film 62, amorphous silicon may be used. In this way, a structure as shown in FIG. 11 is obtained.

  Next, a resist 70 (see FIG. 12) is formed on the polysilicon film 62 located inside the opening 61. Thereafter, the polysilicon film 62 located on the boron-doped silicon oxide film 60 is removed by dry etching. In this way, the capacitor lower electrode 170a is separated as shown in FIG. Here, in the step of removing the polysilicon film 62 located on the boron-doped silicon oxide film 60, a CMP method may be used.

  Next, the boron-doped silicon oxide film 60 is removed by using vapor phase HF to obtain a structure as shown in FIG. Here, polysilicon or amorphous silicon is used as the material of the capacitor lower electrode 170a. However, when a high dielectric film such as BST or PZT is used as the capacitor dielectric film, a metal such as platinum or ruthenium, A high melting point metal such as titanium, titanium nitride, or a film formed of a plurality of these layers may be used.

  Thereafter, a dielectric film 150 (see FIG. 2) is formed on the capacitor lower electrode 170a and the third interlayer insulating film 59. A capacitor upper electrode 151 (see FIG. 2) is formed on the dielectric film 150. By forming a fourth interlayer insulating film 205 (see FIG. 2) on the capacitor upper electrode 151 and the third interlayer insulating film 59, a structure as shown in FIG. 2 is obtained.

  14 and 15 are cross-sectional views for explaining a modification of the manufacturing process according to the first embodiment of the present invention. A modification of the manufacturing process of the DRAM according to the first embodiment of the present invention will be described with reference to FIGS.

  After performing the seventh step shown in FIG. 9 of the manufacturing process of the DRAM according to the first embodiment of the present invention, silicon nitride film 58 (see FIG. 14), third interlayer insulating film 59 (see FIG. 14), boron A doped silicon oxide film 60 (see FIG. 14) is formed. Then, a polysilicon film 141 (see FIG. 14) is formed on the boron-doped silicon oxide film 60. Then, a resist pattern (not shown) is formed on the polysilicon film 141, and a part of the polysilicon film 141 is removed by anisotropic etching using the resist pattern as a mask. Thereafter, the resist pattern is removed. Then, using the polysilicon film 141 as a mask, a part of the boron-doped silicon oxide film 60 and the third interlayer insulating film 59 is removed, thereby forming an opening 61. Then, the silicon nitride film 58 is removed at the bottom of the opening 61 to obtain a structure as shown in FIG. Here, since a conductive film such as the polysilicon film 141 is used as an etching mask for forming the opening 61, a mask pattern with higher accuracy than when a resist or the like is used as the mask is formed. Can do. Therefore, high integration of the semiconductor device can be achieved.

  Thereafter, as shown in FIG. 15, a polysilicon film 62 is formed on the inside of the opening 61 and on the polysilicon film 141. As for the manufacturing steps after this step, the same steps as those of the DRAM according to the first embodiment of the present invention shown in FIGS.

FIG. 16 is a cross-sectional view for explaining a first modification of the DRAM according to the first embodiment of the present invention. Referring to FIG. 16, the first modification of the DRAM according to the first embodiment of the present invention basically has the same structure as that of the first embodiment of the present invention shown in FIG. However, in the first modification of the DRAM of the first embodiment of the present invention, the granular crystal 74 made of silicon is formed on the surface of the capacitor lower electrode 170a. As a method of forming the granular crystal 74, the capacitor lower electrode 170a is formed of amorphous silicon doped with phosphorus or arsenic or non-doped amorphous silicon, and SiH ₄ gas is used as part of the atmospheric gas in a heating furnace. Then, silicon nuclei are attached to the exposed surface of the capacitor lower electrode 170a. Thereafter, PH ₃ gas is introduced as part of the atmospheric gas, and annealing is performed at a high temperature to form granular crystals 74. When non-doped amorphous silicon is used for the capacitor lower electrode 170a, after forming the granular crystal 74, phosphorus or arsenic may be introduced into the capacitor lower electrode 170a using an ion implantation method or a vapor phase method. . Thus, since the granular crystal 74 is formed on the surface of the capacitor lower electrode 170a, the surface area of the capacitor lower electrode 170a can be increased. As a result, the capacitance of the capacitor can be increased. Therefore, the area occupied by the capacitor lower electrode 170a can be reduced as compared with the conventional one while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  As a manufacturing method of the first modification of the DRAM according to the first embodiment, the method as described above is used on the surface of the capacitor lower electrode 170a after the manufacturing process shown in FIG. 13 of the DRAM according to the first embodiment. Thus, the granular crystal 74 is formed. Thereafter, the dielectric film 150 (see FIG. 16), the capacitor upper electrode 151 (see FIG. 16), and the fourth interlayer insulating film 205 (see FIG. 16) are formed by the same process as the DRAM according to the first embodiment. A structure as shown in FIG. 16 is obtained.

  FIG. 17 is a cross-sectional view for explaining a second modification of the DRAM according to the first embodiment of the present invention. Referring to FIG. 17, the second modification of the DRAM according to the first embodiment of the present invention basically has the same structure as the DRAM according to the first embodiment of the present invention shown in FIG. However, in this second modification, granular crystals 74 are formed on the inner side surface and the bottom surface of capacitor lower electrode 170a. Thus, in the second modification of the DRAM of the first embodiment, the granular crystal 74 is formed as in the first modification shown in FIG. 16, so the surface area of the capacitor lower electrode 170a is increased. be able to. For this reason, the effect similar to the 1st modification shown in FIG. 16 is acquired.

  18 to 20 are cross-sectional views for explaining a manufacturing process of the second modification of the DRAM according to the first embodiment of the present invention. A manufacturing process of the second modification of the DRAM according to the first embodiment of the present invention will be described below with reference to FIGS.

  After the manufacturing process shown in FIG. 11 of the DRAM according to the first embodiment of the present invention, granular crystals 74 are formed on the polysilicon film 62 as shown in FIG.

  Thereafter, a resist 70 (see FIG. 19) is formed on the granular crystal 74 inside the opening 61, and then the granular crystal 74 and the polysilicon film 62 located on the boron-doped silicon oxide film 60 are used by dry etching. And remove. In this way, a structure as shown in FIG. 19 is obtained.

  Next, after removing the resist 70, the boron-doped silicon oxide film 60 is removed using vapor phase HF. In this way, a structure as shown in FIG. 20 is obtained.

  Thereafter, the dielectric film 150 (see FIG. 17), the capacitor upper electrode 151 (see FIG. 17), the fourth interlayer insulating film 205 (see FIG. 17), and the like are manufactured in the DRAM manufacturing process according to the first embodiment of the present invention. By forming in the same process, a structure as shown in FIG. 17 is obtained.

  FIG. 21 is a sectional view showing a third modification of the DRAM according to the first embodiment of the present invention. Referring to FIG. 21, the third modification of the DRAM according to the first embodiment of the present invention basically has the same structure as the second modification shown in FIG. However, in the third modification example, as shown in a manufacturing process described later, the upper portion of the third interlayer insulating film 77 is removed by etching or the like to obtain a structure as shown in FIG.

  22 to 24 are cross-sectional views for explaining a manufacturing process of the third modification of the DRAM according to the first embodiment of the present invention. A manufacturing process of the third modification of the DRAM according to the first embodiment of the present invention will be described below with reference to FIGS.

  First, after performing the manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIGS. 3 to 9, a silicon nitride film 58 (see FIG. 22) is formed on the second interlayer insulating film 37 (see FIG. 22). Form. Thereafter, a third interlayer insulating film 77 (see FIG. 22) is formed on the silicon nitride film 58. After a resist pattern (not shown) is formed on the third interlayer insulating film 77, a part of the third interlayer insulating film 77 and the silicon nitride film 58 is removed using the resist pattern as a mask. Opening 61 (see FIG. 22) is formed. A polysilicon film 62 (see FIG. 22) is formed inside the opening 61 and on the third interlayer insulating film 77. A granular crystal 74 (see FIG. 22) is formed on the surface of the polysilicon film 62. In this way, a structure as shown in FIG. 22 is obtained.

  Next, after a resist 70 (see FIG. 23) is formed on the granular crystal 74 in the opening 61, the polysilicon film 62 and the granular crystal 74 located on the third interlayer insulating film 77 are removed by dry etching. To do. In this way, a structure as shown in FIG. 23 is obtained.

  Next, after removing the resist 70, a part of the third interlayer insulating film 77 is removed with an HF aqueous solution. In this way, a structure as shown in FIG. 24 is obtained. In this way, a part of the third interlayer insulating film 77 is removed by the HF aqueous solution, so that the third interlayer insulating film is controlled by controlling the time during which the third interlayer insulating film 77 is in contact with the HF aqueous solution. The film thickness removed from the film 77 can be controlled. Thus, the exposed area on the outer side surface of the capacitor lower electrode 170a can be changed. Thus, the capacitance of the capacitor can be controlled by changing the area of the external side surface of the capacitor lower electrode 170a used as the capacitor.

  Thereafter, a dielectric film 150 (see FIG. 21) and the like are formed in the same manner as the DRAM manufacturing process according to the first embodiment of the present invention, thereby obtaining a structure as shown in FIG.

  FIG. 25 is a cross sectional view showing a fourth modification of the DRAM according to the first embodiment of the present invention. Referring to FIG. 25, the fourth modification of the DRAM according to the first embodiment of the present invention is basically the same as the third modification of the first embodiment of the present invention shown in FIG. Provide structure. However, in the fourth modification, the third interlayer insulating film 77 (see FIG. 21) is almost removed. Then, by forming the granular crystal 74 on the inner side surface of the capacitor lower electrode 170a, the height of the capacitor lower electrode 170a from the upper surface of the second interlayer insulating film 37 is lowered. Thereby, the step difference on the upper surface of the fourth interlayer insulating film 205 between the memory cell region and the peripheral circuit region is reduced.

  FIG. 26 is a cross-sectional view for illustrating a manufacturing step of the fourth modification of the DRAM according to the first embodiment of the present invention.

  In the manufacturing process of the fourth modification of the DRAM according to the first embodiment of the present invention, the third interlayer insulating film 77 (see FIG. 23) is almost completed after the manufacturing process of the third modification shown in FIG. All are removed by etching. In this way, a structure as shown in FIG. 26 is obtained.

  Thereafter, a dielectric film 150 (see FIG. 25) is formed to obtain a structure as shown in FIG.

(Embodiment 2)
FIG. 27 is a cross-sectional view of a DRAM according to the second embodiment of the present invention. Referring to FIG. 27, the DRAM according to the second embodiment of the present invention basically has the same structure as the DRAM according to the first embodiment of the present invention shown in FIG. However, in the DRAM according to the second embodiment, the capacitor lower electrode 92 is a thick film type. Since the capacitor lower electrode 92 is partially embedded in the third interlayer insulating film 59 in this way, the upper surface of the third interlayer insulating film 59 and the upper surface of the capacitor lower electrode 92 The step can be made smaller than before. Thereby, the step on the upper surface of the fourth interlayer insulating film 205 in the memory cell region and the peripheral circuit region can be made smaller than in the conventional case. Further, by changing the position of the upper surface of the third interlayer insulating film 59, the surface area of the capacitor lower electrode 92 that acts as a capacitor can be changed, whereby the capacitance of the capacitor can be arbitrarily changed. .

  28 and 29 are cross-sectional views for illustrating a manufacturing process of the DRAM according to the second embodiment of the present invention. A manufacturing process of the DRAM according to the second embodiment of the present invention will be described below with reference to FIGS.

  First, the DRAM manufacturing process according to the first embodiment of the present invention shown in FIGS. 3 to 10 is performed, and then, as shown in FIG. 28, a polycrystal is formed inside the opening 61 and on the boron-doped silicon oxide film 60. A silicon film 91 is formed.

  Next, the polysilicon film 91 located on the boron-doped silicon oxide film 60 is removed by dry etching or CMP. Then, the boron-doped silicon oxide film 60 is removed using vapor phase HF. In this way, a structure as shown in FIG. 29 is obtained.

  Thereafter, by forming a dielectric film 150 (see FIG. 27), a capacitor upper electrode 151 (see FIG. 27), a fourth interlayer insulating film 205 (see FIG. 27), etc., the structure as shown in FIG. 27 is obtained. obtain. The peripheral circuit region is formed by the same manufacturing process as the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIGS.

  FIG. 30 is a cross sectional view for illustrating a first modification of the DRAM according to the second embodiment of the present invention. Referring to FIG. 30, the first modification of the DRAM according to the second embodiment of the present invention basically has the same structure as the DRAM according to the second embodiment of the present invention shown in FIG. However, in the first modification, sidewalls 96 and 97 made of polysilicon are formed on the upper side surface of the capacitor lower electrode 92. The surfaces of the sidewalls 96 and 97 have curved portions. Therefore, the surface area of the capacitor lower electrode 92 acting as a capacitor can be made larger than when the sidewalls 96 and 97 are not formed. As a result, the capacitance of the capacitor can be increased. For this reason, the area occupied by the capacitor lower electrode 92 can be reduced as compared with the prior art while securing the capacitance of the capacitor. As a result, the semiconductor device can be further miniaturized.

  31 and 32 are cross-sectional views for illustrating a manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention. A manufacturing process of the second modification of the DRAM according to the second embodiment of the present invention will be described below with reference to FIGS.

  First, after the DRAM manufacturing process according to the second embodiment of the present invention shown in FIGS. 28 and 29 is performed, an amorphous layer is formed on third interlayer insulating film 59 and capacitor lower electrode 92 as shown in FIG. A silicon film 95 is formed.

  Next, a part of the amorphous silicon film 95 is removed by anisotropic etching to form side walls 96 and 97 as shown in FIG.

  Thereafter, a structure as shown in FIG. 30 is obtained by forming dielectric film 150 (see FIG. 30), capacitor upper electrode 151 (see FIG. 30), fourth interlayer insulating film 205 (see FIG. 30), and the like. .

  FIG. 33 is a cross sectional view showing a second modification of the DRAM according to the second embodiment of the present invention. Referring to FIG. 33, the second modification of the DRAM according to the second embodiment of the present invention basically has the same structure as the DRAM according to the second embodiment of the present invention shown in FIG. However, in the second modification, the granular crystal 74 is formed on the surface of the capacitor lower electrode 92 located above the third interlayer insulating film 59. As a result, the surface area of the capacitor lower electrode can be increased without increasing the area occupied by the capacitor lower electrode 92. Thereby, the capacity of the capacitor can be increased.

  FIG. 34 is a cross-sectional view for illustrating a manufacturing step of the second modification of the DRAM according to the second embodiment of the present invention. A manufacturing process of the second modification of the DRAM according to the second embodiment of the present invention will be described below with reference to FIG.

  First, after performing the manufacturing process of the DRAM according to the second embodiment of the present invention shown in FIGS. 28 and 29, a granular crystal 74 is formed on the surface of the capacitor lower electrode 92 as shown in FIG. As a method for forming the granular crystal 74, a method similar to the method used in the first modification or the second modification of the first embodiment of the present invention is used.

  Thereafter, a dielectric film 150 (see FIG. 33) is formed to obtain a structure as shown in FIG.

  FIG. 35 is a cross sectional view showing a third modification of the DRAM according to the second embodiment of the present invention. Referring to FIG. 35, the third modification of the DRAM according to the second embodiment of the present invention is basically the same as the first modification of the DRAM according to the second embodiment of the present invention shown in FIG. The structure is provided. However, in the third modification, granular crystals 98 made of silicon are formed on the surfaces of the side walls 96 and 97 made of amorphous silicon. For this reason, in the third modification, the surface area of the capacitor lower electrode 92 can be increased by the formation of the sidewalls 96 and 97, and at the same time, the surface area of the capacitor lower electrode 92 can be increased by the granular crystal 98. Thereby, the capacity of the capacitor can be further increased.

  FIG. 36 is a cross sectional view for illustrating a manufacturing step of the third modification of the DRAM according to the second embodiment of the present invention shown in FIG. A manufacturing process of the third modification of the DRAM according to the second embodiment of the present invention will be described below with reference to FIG.

  First, after the manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention shown in FIGS. 31 and 32, the second process of the DRAM according to the second embodiment of the present invention shown in FIG. The granular crystal 98 is formed on the surfaces of the sidewalls 96 and 97 by the same process as that for forming the granular crystal 74 (see FIG. 33) in the modified example.

  Thereafter, a dielectric film 150 (see FIG. 35) and the like are formed to obtain a structure as shown in FIG.

  FIG. 37 is a cross sectional view showing a fourth modification of the DRAM according to the second embodiment of the present invention. Referring to FIG. 37, the fourth modification of the DRAM according to the second embodiment of the present invention is basically the same as the first modification of the DRAM of the second embodiment of the present invention shown in FIG. The structure is provided. However, in the fourth modification, granular crystals 98 are formed on the surfaces of the capacitor lower electrode 92 and the sidewalls 96 and 97. For this reason, the surface area of the capacitor lower electrode can be increased as compared with the case where the sidewalls 96 and 97 and the granular crystal 98 are not formed, and the capacitance of the capacitor can be further increased. As a result, the area occupied by the capacitor lower electrode can be made smaller than before, while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  FIG. 38 is a cross sectional view for illustrating a manufacturing process of the fourth modification example of the DRAM according to the second embodiment of the present invention shown in FIG. Referring to FIG. 38, description will be given of a manufacturing process of the fourth modification example of the DRAM according to the second embodiment of the present invention shown in FIG.

  First, the manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention shown in FIGS. 31 and 32 is performed. At that time, the capacitor lower electrode 92 is formed of amorphous silicon. Then, as shown in FIG. 38, the surfaces of the capacitor lower electrode 92 and the sidewalls 96 and 97 were used in the manufacturing process of the second modification of the first embodiment of the present invention as shown in FIG. The granular crystal 98 is formed by the process.

  Thereafter, a dielectric film 150 (see FIG. 37) is formed to obtain a structure as shown in FIG.

(Embodiment 3)
FIG. 39 is a cross sectional view for illustrating a DRAM according to the third embodiment of the present invention. 39 is a cross-sectional view taken along line 600-600 in FIG. Referring to FIG. 39, a trench isolation oxide film 40 is formed on the main surface of semiconductor substrate 1 so as to surround active region 39 in the memory cell region of the DRAM according to the third embodiment of the present invention. Source / drain regions 201 a to 201 c are formed on the main surface of the semiconductor substrate 1. On the channel region adjacent to the source / drain regions 201a to 201c, gate electrodes 43a, 43b, and 43e are formed through gate insulating films 42a, 42b, and 42e. Silicon nitride films 44a, 44b and 44e are formed on the gate electrodes 43a, 43b and 43e. Side walls 46a to 46d, 46h, 46i made of silicon nitride films are formed on the side surfaces of the gate insulating films 42a, 42b, 42e, the gate electrodes 43a, 43b, 43e, and the silicon nitride films 44a, 44b, 44e. Has been. A non-doped silicon oxide film 47 is formed on the silicon nitride films 44 a, 44 b and 44 e, the sidewalls 46 a to 46 d, 46 h and 46 i and the main surface of the semiconductor substrate 1. A first interlayer insulating film 48 is formed on the non-doped silicon oxide film 47. A second interlayer insulating film 37 is formed on the first interlayer insulating film 48. By removing a part of the first and second interlayer insulating films 48 and 37 and the non-doped silicon oxide film 47, contact holes 38a and 38b are formed. Plugs 57a and 57b made of polysilicon are formed in the contact holes 38a and 38b, respectively. A silicon nitride film 58 is formed on a part of the upper surface of the second interlayer insulating film 37. Capacitor lower electrodes 170 a and 170 b are formed on the plugs 57 a and 57 b and the second interlayer insulating film 37. A third interlayer insulating film 77 is formed beside the capacitor lower electrodes 170a and 170b. Granular crystals 74 are formed on the inner surfaces of the capacitor lower electrodes 170a and 170b. A capacitor dielectric film 150 is formed on the granular crystal 74 and the third interlayer insulating film 77. A capacitor upper electrode 151 is formed on the dielectric film 150. A fourth interlayer insulating film 205 is formed on the capacitor upper electrode 151. The width W2 of a part of the third interlayer insulating film 77 located between the capacitor lower electrodes 170a and 170b is smaller than the minimum processing dimension that can be formed by photolithography.

  The cross-sectional view in the peripheral circuit region of the DRAM according to the third embodiment of the present invention basically shows the same structure as the cross-sectional view in the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIG. .

  As described above, in the DRAM according to the third embodiment of the present invention, as shown in FIG. 39, the heights of the top surfaces of the capacitor lower electrodes 170a and 170b and the upper surface of the third interlayer insulating film 77 are approximately equal. Since they are the same, it is possible to prevent occurrence of a step on the upper surface of the fourth interlayer insulating film 205 between the memory cell region and the peripheral circuit region. For this reason, even when the wiring layer is formed on the fourth interlayer insulating film 205 by photolithography, it is possible to prevent the pattern of the wiring layer from becoming unclear due to the step. Thereby, it is possible to prevent a problem such as disconnection or short circuit of the wiring due to the unclear pattern of the wiring layer. As a result, it is possible to obtain a highly reliable semiconductor device while achieving high integration and securing the capacitance of the capacitor. Further, since the width W2 of the third interlayer insulating film 77 is smaller than the minimum processing dimension that can be formed by photolithography, the distance between the capacitor lower electrodes 107a and 107b can be made smaller than before. As a result, the semiconductor device can be more highly integrated. In the first and second embodiments, similar to the third embodiment, if the width of the interlayer insulating film between the capacitor lower electrodes is made smaller than the minimum processing dimension that can be formed by photolithography, the same applies. The effect is obtained.

  40 to 42 are cross-sectional views for illustrating a manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. Hereinafter, a manufacturing process of the DRAM according to the third embodiment of the present invention will be described with reference to FIGS.

  First, in the memory cell region of the DRAM according to the third embodiment of the present invention, trench isolation oxide film 40 (see FIG. 40) is formed on the main surface of semiconductor substrate 1 (see FIG. 40). A silicon oxide film (not shown) serving as a gate insulating film is formed on the main surface of semiconductor substrate 1. A polysilicon film (not shown) to be a gate electrode is formed on the silicon oxide film. A silicon nitride film (not shown) is formed on the polysilicon film. A resist pattern is formed on the silicon nitride film. By using this resist pattern as a mask, the silicon nitride film, the polysilicon film, and the silicon oxide film are etched, whereby the gate insulating films 42a, 42b, and 42e, the gate electrodes 43a, 43b, and 43e, and the silicon nitride films 44a and 44b. , 44e (see FIG. 40). Then, a silicon nitride film (not shown) is formed so as to cover the whole. Thereafter, the silicon nitride film is anisotropically etched to form sidewalls 46a to 46d, 46h, and 46i (see FIG. 40). Then, a non-doped silicon oxide film 47 (see FIG. 40) is formed so as to cover the whole. On the non-doped silicon oxide film 47, a first interlayer insulating film 48 (see FIG. 40) made of a phosphorus-doped silicon oxide film is formed. A second interlayer insulating film 37 (see FIG. 40) is formed on the first interlayer insulating film 48. After a resist pattern is formed on second interlayer insulating film 37, a part of first and second interlayer insulating films 48 and 37 and non-doped silicon oxide film 47 are removed using this resist pattern as a mask. Then, contact holes 38a and 38b (see FIG. 40) are formed. Plugs 57a and 57b made of polysilicon are formed in the contact holes 38a and 38b. A silicon nitride film 58 (see FIG. 40) is formed on the second interlayer insulating film 37 and the plugs 57a and 57b. A third interlayer insulating film 77 made of a silicon oxide film is formed on the silicon nitride film 58. After a resist pattern is formed on third interlayer insulating film 77, openings 61a and 61b are removed by removing portions of third interlayer insulating film 77 and silicon nitride film 58 using this resist pattern as a mask. Form. In this way, a structure as shown in FIG. 40 is obtained. Here, the width of the opening 61a is L1, and the width of a part of the third interlayer insulating film 77 located between the openings 61a and 61b is W1.

  Next, a part of the surface of the third interlayer insulating film 77 is removed by wet etching using an aqueous solution of alkali or acid. As a result, the width of the opening 61a increases from L1 to L2 (see FIG. 41), and at the same time, the width of a part of the third interlayer insulating film 77 located between the openings 61a and 61b is changed from W1 to W2. (Refer to FIG. 41). In this way, a structure as shown in FIG. 41 is obtained.

  Next, by using the manufacturing process of the third modification of the DRAM according to the first embodiment of the present invention shown in FIGS. 22 and 23, on the third interlayer insulating film 77 and inside the openings 61a and 61b. An amorphous silicon film (not shown) is formed. Then, a granular crystal 74 (see FIG. 42) is formed on the amorphous silicon film. Then, the structure shown in FIG. 42 is obtained by removing the amorphous silicon film and the granular crystal located on the upper surface of the third interlayer insulating film 77 using dry etching or the like.

  Thereafter, a dielectric film 150 (see FIG. 39) or the like is formed on the granular crystal 74 and the third interlayer insulating film 77, thereby obtaining a structure as shown in FIG. The peripheral circuit region is formed by the same manufacturing process as the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIGS.

  FIG. 43 is a cross sectional view showing a first modification of the DRAM according to the third embodiment of the present invention. Referring to FIG. 43, the first modification of the DRAM according to the third embodiment of the present invention basically has the same structure as the DRAM according to the third embodiment of the present invention shown in FIG. However, in the first modification of the DRAM according to the third embodiment of the present invention shown in FIG. 43, the third interlayer insulating film is composed of non-doped silicon oxide film 85 and boron-doped silicon oxide film 86. ing. In this way, by forming the third interlayer insulating film in a two-layer structure, when expanding the width of the openings 61a and 61b in the manufacturing process to be described later, the upper layer non-doped silicon oxide is used by using vapor phase HF. Without etching the film 85, only the boron-doped silicon oxide film 86 can be etched to widen the widths of the openings 61a and 61b. As a result, in the step of expanding the width of the openings 61a and 61b and reducing the width of a part of the third interlayer insulating film located therebetween, the upper surface of the third interlayer insulating film is removed by etching. Can be prevented. For this reason, it can prevent that the height of the side surface of capacitor lower electrode 170a, 170b formed after that becomes low. As a result, the surface area of the capacitor lower electrode can be prevented from being reduced, and the capacitance of the capacitor can be prevented from being reduced.

  44 to 46 are cross-sectional views for illustrating a manufacturing process of the first modification of the DRAM according to the third embodiment of the present invention shown in FIG. A manufacturing process of the first modification of the DRAM according to the third embodiment of the present invention will be described below with reference to FIGS.

  First, a structure as shown in FIG. 44 is obtained by a process basically similar to the manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. However, in the process shown in FIG. 40, the third interlayer insulating film 77 has one layer, whereas in the process shown in FIG. 44, the third interlayer insulating film is formed on the silicon nitride film 58. After the boron-doped silicon oxide film 86 is formed, a non-doped silicon oxide film 85 is formed on the boron-doped silicon oxide film. At this time, the width of the opening 61a is L1, and the width of a part of the third interlayer insulating films 86 and 85 located between the openings 61a and 61b is W1.

  Next, as shown in FIG. 45, only the side surfaces of the boron-doped silicon oxide film 86 are removed by etching using vapor phase HF. For this reason, the width of the opening 61a is L2, and the width of a part of the third interlayer insulating film 86 located between the openings 61a and 61b is set to W2, which is smaller than the width W1 formed by the first etching. can do.

  Then, in the manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. 42, the same process as the process of forming capacitor lower electrodes 170a and 170b (see FIG. 42) and granular crystal 74 (see FIG. 42). Thus, as shown in FIG. 46, capacitor lower electrodes 170a and 170b and granular crystals 74 are formed in the openings 61a and 61b.

  Thereafter, a dielectric film 150 (see FIG. 43) and the like are formed to obtain a structure as shown in FIG.

  FIG. 47 is a cross sectional view showing a second modification of the DRAM according to the third embodiment of the present invention. Referring to FIG. 47, the second modification of the DRAM according to the third embodiment of the present invention basically has a structure similar to that of the DRAM according to the third embodiment of the present invention shown in FIG. Yes. However, in the second modification of the DRAM according to the third embodiment of the present invention shown in FIG. 47, the side surfaces of capacitor lower electrodes 170a and 170b have curved surfaces. For this reason, the surface area of the side surfaces of the capacitor lower electrodes 170a and 170b can be made larger than when the capacitor lower electrodes 170a and 170b are planar as shown in FIG. For this reason, it is possible to reduce the area occupied by the capacitor as compared with the prior art while securing a constant capacitor capacity, and as a result, it is possible to further miniaturize the semiconductor device.

  48 and 49 are cross-sectional views for illustrating a manufacturing process of the second modification of the DRAM according to the third embodiment of the present invention shown in FIG. Referring to FIGS. 48 and 49, the manufacturing process of the second modification of the DRAM according to the third embodiment of the present invention will be described below.

First, the first step of the manufacturing process of the DRAM according to the third embodiment of the present invention shown in FIG. 40 is performed. However, when the third interlayer insulating film 77 (see FIG. 48) is dry-etched, the atmospheric pressure of this etching is increased. Thus, as shown in FIG. 48, the side surface of the third interlayer insulating film 77 inside the openings 61a and 61b can be formed to have a curved surface. In this etching step, the amount of the etching gas mixed into the atmospheric gas for forming a film for protecting the side surface of the third interlayer insulating film 77 may be reduced. An etching gas used in this etching step may be a CHF ₃ / CF ₄ gas. In this case, increasing the flow rate of CF ₄ is effective for forming a curved surface, and mixing gas such as O ₂ is also effective.

  Next, as shown in FIG. 49, capacitor lower electrodes 170a and 170b and granular crystals 74 are formed in openings 61a and 61b, as in the manufacturing process shown in FIG. 42 of the DRAM according to the third embodiment of the present invention. And form.

  Thereafter, a dielectric film 150 (see FIG. 47) and the like are formed to obtain a configuration as shown in FIG. Forming the side surfaces of capacitor lower electrodes 170a and 170b so as to have curved surfaces as described above is also applied to the capacitor lower electrode of the DRAM according to the first embodiment of the present invention shown in FIGS. The same effect can be obtained when applied to another embodiment having a cylindrical capacitor lower electrode.

(Embodiment 4)
FIG. 50 is a sectional view of a DRAM according to the fourth embodiment of the present invention. Here, the cross section of the memory cell region shown in FIG. 50 is a cross section taken along line segment 500-500 in the schematic plan view of the memory cell of the DRAM shown in FIG. The DRAM according to the fourth embodiment of the present invention shown in FIG. 50 basically has the same structure as the DRAM according to the first embodiment of the present invention shown in FIG. However, in the DRAM according to the fourth embodiment, a gap is formed between capacitor lower electrode 170a and third interlayer insulating film 77 as shown in a manufacturing process described later, and dielectric film 150 and capacitor upper portion are formed in this gap. Electrode 151 is formed. Further, the upper surface of the third interlayer insulating film 77 is formed so as to be positioned at substantially the same height as the top surface of the capacitor lower electrode 170a. As described above, in the DRAM according to the fourth embodiment of the present invention, since a gap is formed between the capacitor lower electrode 170a and the third interlayer insulating film 77 in the manufacturing process described later, the side surface of the capacitor lower electrode 170a is connected to the capacitor. Available as Therefore, the capacitance of the capacitor can be increased without changing the shape of the capacitor lower electrode 170a.

  Further, since the third interlayer insulating film 77 is formed so as to extend from the memory cell region to the peripheral circuit region, the fourth interlayer insulating film is formed on the capacitor upper electrode 151 in the memory cell region and the peripheral circuit region. Even when the film is formed, it is possible to prevent the occurrence of a step on the upper surface of the fourth interlayer insulating film between the memory cell region and the peripheral circuit region. Further, as shown in the manufacturing process described later, since the gap is formed only on the side surface of the capacitor lower electrode 170a, the capacitor lower electrode 170a and the second interlayer insulating film 37 form the gap on the bottom surface of the capacitor lower electrode 170a. Even when formed, it is always in contact. For this reason, even in the process of cleaning the semiconductor substrate with the gap formed, the bottom surface of the capacitor lower electrode 170a is in contact with the second interlayer insulating film 37, so that the second interlayer insulating film is formed. The film 37 acts as a reinforcing member against physical impact. For this reason, it is possible to prevent the problem that the capacitor lower electrode 170a is broken due to physical vibration in the cleaning process as described above.

  51 to 55 are cross-sectional views for illustrating a manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIG. A manufacturing process of the DRAM according to the fourth embodiment of the present invention will be described with reference to FIGS.

  First, after performing the manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIGS. 3 to 9, the silicon nitride film 58 (see FIG. 51) and the second interlayer insulating film 37 (see FIG. 51) are formed. A third interlayer insulating film 77 (see FIG. 51) is formed. After a resist pattern (not shown) is formed on the third interlayer insulating film 77, a part of the third interlayer insulating film 77 is removed by anisotropic etching using this resist pattern as a mask. Thereby, an opening 61 (see FIG. 51) is formed. Then, the silicon nitride film 58 is removed by etching at the bottom of the opening 61. Here, as in the third embodiment of the present invention shown in FIG. 39, the width of the opening 61 may be widened by etching. By doing in this way, the same effect as Embodiment 3 is acquired further. Thereafter, a silicon nitride film 99 (see FIG. 51) is formed on the third interlayer insulating film 77 and inside the opening 61. In this way, a structure as shown in FIG. 51 is obtained. At this time, the silicon nitride film 99 may be formed on the third interlayer insulating film 77 and inside the opening 61 without removing the silicon nitride film 58 at the bottom of the opening 61.

  Next, a part of the silicon nitride film 99 is removed by anisotropic etching to form a sidewall 100 made of a silicon nitride film inside the opening 61, thereby obtaining a structure as shown in FIG. .

  Next, as shown in FIG. 53, a conductor film 101 such as polysilicon or amorphous silicon is formed on the third interlayer insulating film 77 and inside the opening 61.

  Next, as in the first embodiment, a part of the conductor film 101 located on the third interlayer insulating film 77 is removed by etching or the like. Thereby, a structure as shown in FIG. 54 is obtained. By this step, the capacitor lower electrode 170a for each bit is separated.

  Next, by selectively removing the sidewall 100 made of a silicon nitride film by etching, a gap is formed between the capacitor lower electrode 170a and the third interlayer insulating film 77. In this way, a structure as shown in FIG. 55 is obtained.

  Thereafter, a dielectric film 150 (see FIG. 50) and the like are formed to obtain a structure as shown in FIG. The peripheral circuit region is formed by the same manufacturing process as the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIGS.

  FIG. 56 is a cross sectional view showing a first modification of the DRAM according to the fourth embodiment of the present invention. Referring to FIG. 56, the first modification of the DRAM according to the fourth embodiment of the present invention basically has the same structure as the DRAM according to the fourth embodiment of the present invention shown in FIG. However, in this first modification, the capacitor is formed with a portion of the sidewall 100 made of a silicon nitride film located between the capacitor lower electrode 170a and the third interlayer insulating film 77 remaining. . As described above, since a part of the sidewall 100 is left, the surface area of the external side surface of the capacitor lower electrode 170a acting as a capacitor can be changed by changing the remaining amount of the sidewall 100. As a result, the capacitance of the capacitor can be changed without changing the structure of the capacitor lower electrode 170a. In addition, since a part of the remaining sidewall 100 also acts as a part of the reinforcing member against physical shock, it is possible to more effectively prevent the occurrence of problems such as breakage of the capacitor lower electrode 170a due to physical vibration in a cleaning process or the like. it can.

  FIG. 57 is a cross sectional view for illustrating a manufacturing step in the first modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. The manufacturing process of the first modification of the DRAM according to the fourth embodiment of the present invention will be described below with reference to FIG.

  First, after performing the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIGS. 51 to 54, a part of the sidewall 100 is left so that a part of the sidewall 100 remains as shown in FIG. Are removed by etching. At this time, when wet etching is used, only a part of the sidewall 100 can be removed by controlling the immersion time in the etching solution.

  Thereafter, a dielectric film 150 (see FIG. 56) and the like are formed to obtain a structure as shown in FIG.

  FIG. 58 is a cross sectional view showing a second modification of the DRAM according to the fourth embodiment of the present invention. Referring to FIG. 58, the second modification of the DRAM according to the fourth embodiment of the present invention basically has the same structure as the DRAM according to the fourth embodiment of the present invention shown in FIG. However, in the second modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 58, a gap located between capacitor lower electrode 170a and third interlayer insulating film 77 is formed in the manufacturing process described later. The capacitor lower electrode 170a is also formed so as to expose a part of the bottom surface. A part of the bottom surface of the capacitor lower electrode 170a also functions as a capacitor by forming the dielectric film 150 and the like thereon. By forming in this way, the capacitance of the capacitor can be further increased.

  FIG. 59 is a cross sectional view for illustrating a manufacturing process of the second variation of the DRAM according to the fourth embodiment of the present invention shown in FIG. Referring to FIG. 59, the manufacturing process of the second modification of the DRAM according to the fourth embodiment of the present invention will be described below.

  First, after performing the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIGS. 51 to 54, as shown in FIG. 59, it is located between the capacitor lower electrode 170a and the third interlayer insulating film 77. After performing the etching for removing the sidewall 100 (see FIG. 54) to be performed, the etching is performed so as to remove a part of the second interlayer insulating film 37 located under the sidewall 100. In this manner, the gap can be formed so as to expose the outer side surface and a part of the bottom surface of the capacitor lower electrode 170a. At this time, since the other part of the bottom surface of the capacitor lower electrode 170a is in contact with the second interlayer insulating film 37, even if the cleaning process or the like is performed after that, the physical impact in the cleaning process or the like is not caused. On the other hand, the second interlayer insulating film 37 functions as a reinforcing member that prevents the capacitor lower electrode 170a from being broken.

  Thereafter, a dielectric film 150 (see FIG. 58) is formed to obtain a structure as shown in FIG.

  FIG. 60 is a cross sectional view showing a third modification of the DRAM according to the fourth embodiment of the present invention. Referring to FIG. 60, the third modification of the DRAM according to the fourth embodiment of the present invention basically has the same structure as the DRAM according to the fourth embodiment of the present invention shown in FIG. However, in the third modification of the DRAM according to the fourth embodiment of the present invention, granular crystals 74 are formed on the inner surface of capacitor lower electrode 170a. Therefore, the surface area of the capacitor lower electrode 170a can be increased without increasing the area occupied by the capacitor lower electrode 170a. Thereby, the capacity of the capacitor can be increased. As a result, the area occupied by the capacitor lower electrode 170a can be reduced while securing a certain capacitor capacity. As a result, the semiconductor device can be miniaturized.

  61 to 63 are cross-sectional views for describing a manufacturing process of the third modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. A manufacturing process of the third modification of the DRAM according to the fourth embodiment of the present invention will be described below with reference to FIGS.

  First, after performing the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIGS. 51 to 53, the granular crystal 74 is formed on the conductive film 101 by the same process as that used in the first embodiment. Form. In this way, a structure as shown in FIG. 61 is obtained.

  Next, as shown in FIG. 62, the conductor film 101 and the granular crystal 74 located on the third interlayer insulating film 77 are removed by etching. Here, a CMP method may be used.

  Next, by removing the sidewall 100 inside the opening 61 by etching, a gap is formed between the capacitor lower electrode 170a and the third interlayer insulating film 77 as shown in FIG.

  Thereafter, a capacitor dielectric film 150 (see FIG. 60) and the like are formed to obtain a structure as shown in FIG.

  FIG. 64 is a cross sectional view showing a fourth modification of the DRAM according to the fourth embodiment of the present invention. Referring to FIG. 64, the fourth modification of the DRAM according to the fourth embodiment of the present invention basically has the same structure as the DRAM according to the fourth embodiment of the present invention shown in FIG. However, in the fourth modification of the DRAM according to the fourth embodiment of the present invention, granular crystal 74 is formed on the entire inner surface and outer side surface of capacitor lower electrode 170a. Therefore, the surface area of the capacitor lower electrode 170a can be increased without increasing the area occupied by the capacitor lower electrode 170a. As a result, the area occupied by the capacitor lower electrode 170a can be made smaller than before, while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized. Here, after the opening 61 is formed, the width of the opening 61 is increased by etching as in the third embodiment, whereby the first electrode positioned between the capacitor lower electrode 170a and another capacitor lower electrode is formed. The width of the third interlayer insulating film 77 may be made smaller than the final processing dimension that can be formed by photolithography. As a result, the semiconductor device can be more highly integrated.

  FIG. 65 is a cross sectional view for illustrating a manufacturing process of the fourth variation of the DRAM according to the fourth embodiment of the present invention shown in FIG. Referring to FIG. 65, the manufacturing process of the fourth modification of the DRAM according to the fourth embodiment of the present invention shown in FIG. 64 will be described.

  First, the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIGS. Thereafter, granular crystals 74 (see FIG. 65) are formed on the surface of capacitor lower electrode 170a by the same process as used in the first embodiment of the present invention. In this way, a structure as shown in FIG. 65 is obtained.

  Thereafter, a dielectric film 150 (see FIG. 64) and the like are formed to obtain a structure as shown in FIG.

(Embodiment 5)
FIG. 66 is a cross sectional view showing a DRAM according to the fifth embodiment of the present invention. Referring to FIG. 66, the DRAM according to the fifth embodiment of the present invention basically has the same structure as the DRAM according to the fourth embodiment of the present invention shown in FIG. However, the capacitor lower electrode 105 of the DRAM according to the fifth embodiment has a thick film shape. Thus, in the DRAM according to the fifth embodiment of the present invention, a gap is formed between the side surface of capacitor lower electrode 105 and third interlayer insulating film 77, and a dielectric film is formed on the side surface of capacitor lower electrode 105. Since the capacitor 150 and the capacitor upper electrode 151 are formed, the capacitance of the capacitor can be increased. In addition, since a gap is formed only in the manufacturing process described later only between the side surface of the capacitor lower electrode 105 and the third interlayer insulating film 77, the bottom surface of the capacitor lower electrode 105 The second interlayer insulating film 37 can be brought into contact with the second interlayer insulating film 37. For this reason, even if the step of cleaning the semiconductor substrate on which the semiconductor device is formed in the state where the gap is formed, the second interlayer in contact with the bottom surface of the capacitor lower electrode 105 is performed. The insulating film 37 acts as a reinforcing member, and it is possible to prevent a problem that a part of the capacitor lower electrode 105 is broken due to physical vibration in the cleaning process or the like.

  Further, since the capacitor lower electrode 105 is buried in the third interlayer insulating film 77, the fourth interlayer insulation in the memory cell region and the peripheral circuit region is caused by the capacitor lower electrode 105. Generation of a step on the upper surface of the film 205 can be prevented. Therefore, even when a wiring layer made of aluminum or the like is formed on the fourth interlayer insulating film 205 by photolithography, this wiring is caused by a step on the upper surface of the fourth interlayer insulating film 205. It is possible to prevent the layer pattern from becoming unclear. For this reason, it is possible to prevent problems such as disconnection and short circuit of the wiring layer due to the unclear pattern of the wiring layer. As a result, it is possible to obtain a semiconductor device having high reliability while ensuring the capacitance of the capacitor while achieving high integration.

  In the fifth embodiment, the width of the opening 61 is widened by etching, so that the width of a part of the third interlayer insulating film 77 located between the capacitor lower electrode 105 and another capacitor lower electrode is increased. It may be smaller than the minimum processing dimension that can be formed by photolithography. Thereby, the space | interval between the capacitor lower electrode 105 and another capacitor lower electrode can be made smaller than before. As a result, the semiconductor device can be more highly integrated.

  67 to 69 are cross-sectional views for illustrating a manufacturing process of the DRAM according to the fifth embodiment of the present invention shown in FIG. With reference to FIGS. 67 to 69, a manufacturing process of the DRAM according to the fifth embodiment of the present invention will be described below.

  First, after performing the manufacturing process of the DRAM according to the fourth embodiment of the present invention shown in FIGS. 51 and 52, amorphous silicon is formed on the third interlayer insulating film 77 and in the opening 61 as shown in FIG. A dielectric film 104 made of or the like is formed.

  Next, a part of the dielectric film 104 located on the third interlayer insulating film 77 is removed by dry etching or CMP to obtain a structure as shown in FIG. In this way, the capacitor lower electrode 105 is formed.

  Next, as shown in FIG. 69, the sidewall 100 (see FIG. 68) is removed by etching to form a gap between the capacitor lower electrode 105 and the third interlayer insulating film 77.

  Thereafter, a dielectric film 150 (see FIG. 66) or the like is formed on the surface of the capacitor lower electrode 105 and the third interlayer insulating film 77, thereby obtaining a structure as shown in FIG. The peripheral circuit region is formed by the same manufacturing process as the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIGS.

  FIG. 70 is a cross sectional view showing a modification of the DRAM according to the fifth embodiment of the present invention. Referring to FIG. 70, the modification of the DRAM according to the fifth embodiment of the present invention basically has the same structure as the DRAM according to the fifth embodiment of the present invention shown in FIG. However, in the modification of the DRAM according to the fifth embodiment of the present invention, granular crystals 74 are formed on the surface of capacitor lower electrode 105. Therefore, in addition to the effect of the fifth embodiment of the present invention shown in FIG. 66, the surface area of the capacitor lower electrode can be increased without increasing the area occupied by capacitor lower electrode 105. Thereby, the capacity of the capacitor can be increased. For this reason, the area occupied by the capacitor lower electrode 105 can be made smaller than before while securing a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  71 is a cross-sectional view for illustrating a manufacturing process of a variation of the DRAM according to the fifth embodiment of the present invention shown in FIG. Referring to FIG. 71, a manufacturing process of the DRAM according to the fifth embodiment of the present invention will be described below.

  First, after implementing the manufacturing process of the DRAM according to the fifth embodiment of the present invention shown in FIGS. 67 to 69, a granular crystal 74 is formed on the surface of the capacitor lower electrode 105 as shown in FIG. As the step of forming the granular crystal 74, the same step as the step of forming the granular crystal used in the first embodiment is used.

  Thereafter, a dielectric film 150 (see FIG. 70) or the like is formed on the third interlayer insulating film 77 and the surface of the capacitor lower electrode 105, thereby obtaining a structure as shown in FIG.

(Embodiment 6)
FIG. 72 is a cross sectional view showing a DRAM according to the sixth embodiment of the present invention. 72 is a cross-sectional view taken along line 700-700 in the schematic plan view of the memory cell of the DRAM shown in FIG.

  Referring to FIG. 72, in the memory cell region of the DRAM according to the sixth embodiment of the present invention, trench isolation oxide film 40 is formed on the main surface of semiconductor substrate 1 so as to surround active region 39. Source / drain regions 201 b and 201 c are formed on the main surface of the semiconductor substrate 1. On the main surface of the semiconductor substrate 1, a gate 43b is formed via a gate insulating film 42b. A silicon nitride film 44b is formed on the gate electrode 43b. Sidewalls 46c and 46d made of a silicon nitride film are formed on the side surfaces of the silicon nitride film 44b, the gate electrode 43b, and the gate insulating film 42b. A non-doped silicon oxide film 47 is formed on the silicon nitride film 44b, the sidewalls 46c and 46d, and the main surface of the semiconductor substrate 1. A first interlayer insulating film 48 is formed on the non-doped silicon oxide film 47. A bit line 174 made of a doped polysilicon film 52 and a refractory metal silicide film 53 is formed on the first interlayer insulating film 48. A silicon nitride film 54 is formed on the bit line 174. Side walls 55a and 55b made of a silicon nitride film are formed on the side surfaces of the silicon nitride film 54 and the bit line 174. A second interlayer insulating film 37 is formed on the silicon nitride film 54, the side walls 55 a and 55 b, and the first interlayer insulating film 48. By removing a part of the first and second interlayer insulating films 48 and 37 and the non-doped silicon oxide film 47, an opening 110 is formed. The second interlayer insulating film 37 is formed so as to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode 112 made of amorphous silicon or polysilicon is formed in the opening 110 so that a part thereof extends above the second interlayer insulating film 37. A dielectric film 150 is formed on the capacitor lower electrode 112 and the second interlayer insulating film 37. A capacitor upper electrode 151 is formed on the dielectric film 150. A third interlayer insulating film 205 is formed on the capacitor lower electrode 151. The structure of the DRAM according to the sixth embodiment in the peripheral circuit region is basically the same as that of the DRAM according to the first embodiment of the present invention shown in FIG.

  As described above, in the DRAM according to the sixth embodiment of the present invention, the capacitor lower electrode 112 is partially embedded in the second interlayer insulating film 37. Therefore, the step between the upper surface of the second interlayer insulating film 37 and the top surface of the capacitor lower electrode 112 in the memory cell region can be reduced as compared with the conventional case. As a result, even when the third interlayer insulating film 205 is formed in the memory cell region and the peripheral circuit region, the step between the memory cell region and the peripheral circuit region is formed on the upper surface of the third interlayer insulating film 205. Can be small. As a result, even when a wiring layer made of aluminum or the like is formed on the third interlayer insulating film 205 by photoengraving, the wiring layer is formed due to a step on the upper surface of the third interlayer insulating film 205. It is possible to prevent the pattern from becoming unclear. As a result, since the pattern of the wiring layer is unclear, it is possible to prevent problems such as disconnection and short circuit of the wiring layer. As a result, it is possible to obtain a highly reliable semiconductor device while ensuring high capacitance and ensuring the capacitance of the capacitor.

  72, since the capacitor lower electrode 112, the silicon nitride film 54, and the sidewall 55b are in contact with each other, the silicon nitride film is used in the etching for forming the opening 110 in the manufacturing process described later. 54 and the sidewall 55b can be used as a mask. Therefore, as in the prior art, a resist pattern patterning process is not required to form a contact hole for connecting the capacitor lower electrode and the source / drain region 201b on the main surface of the semiconductor substrate 1. . For this reason, the number of manufacturing steps can be reduced.

  73 to 77 are cross-sectional views for illustrating a manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIG. A manufacturing process of the DRAM according to the sixth embodiment of the present invention will be described below with reference to FIGS.

  First, a trench isolation oxide film 40 (see FIG. 73) is formed on the main surface of the semiconductor substrate 1 (see FIG. 73) so as to surround the active region 39. A silicon oxide film (not shown) serving as a gate insulating film is formed on the main surface of semiconductor substrate 1. A polysilicon film (not shown) to be a gate electrode is formed on the silicon oxide film. A silicon nitride film (not shown) is formed on the polysilicon film. A resist pattern (not shown) is formed on the silicon nitride film, and the silicon nitride film, the polysilicon film, and the silicon oxide film are partially removed by etching using the resist pattern as a mask. In this manner, the gate insulating film 42b (see FIG. 73), the gate electrode 43b (see FIG. 73), and the silicon nitride film 44b (see FIG. 73) are formed. Thereafter, the resist pattern is removed. Next, a silicon nitride film (not shown) is formed so as to cover the whole. By removing a part of the silicon nitride film by anisotropic etching, side walls 46c and 46d (see FIG. 73) are formed on the side surfaces of the gate insulating film 42b, the gate electrode 43b, and the silicon nitride film 44b. A non-doped silicon oxide film 47 (see FIG. 73) is formed so as to cover the whole. A first interlayer insulating film 48 (see FIG. 73) is formed on the non-doped silicon oxide film 47. A doped polysilicon film (not shown) is formed on the first interlayer insulating film 48. A refractory metal silicide film (not shown) is formed on the doped polysilicon film. A silicon nitride film (not shown) is formed on the refractory metal silicide film. After a resist pattern (not shown) is formed on the silicon nitride film, a part of the silicon nitride film, the refractory metal silicide film, and the doped polysilicon film is removed by using the resist pattern as a mask. A bit line 174 (see FIG. 73) and a silicon nitride film 54 (see FIG. 73) made of the top polysilicon film 52 (see FIG. 73) and the refractory metal silicide film 53 (see FIG. 73) are formed. After forming a silicon nitride film (not shown) so as to cover the whole, a part of this silicon nitride film is removed by anisotropic etching, thereby forming sidewalls 55a and 55b (see FIG. 73). A second interlayer insulating film 37 (see FIG. 73) is formed on the silicon nitride film. A boron-doped silicon oxide film 60 (see FIG. 73) is formed on the second interlayer insulating film 37. In this way, a structure as shown in FIG. 73 is obtained. The manufacturing process of the field effect transistor and the wiring in the peripheral circuit region is the same as the manufacturing process of the field effect transistor and the wiring in the peripheral circuit region of the DRAM according to the first embodiment of the present invention.

  Next, after forming a resist pattern (not shown) on the boron-doped silicon oxide film 60, using this resist pattern as a mask, the boron-doped silicon oxide film 60, the second interlayer insulating film 37, and the first By removing part of the one interlayer insulating film 48 and the non-doped silicon oxide film 47, an opening 110 (see FIG. 74) is formed. In the etching for forming the opening 110, the silicon nitride films 54 and 44b and the sidewalls 55b and 46c are used as a part of the mask, and the opening 110 is formed in a source / drain manner in a self-aligning manner. The region 201b can be reached. Thereafter, the resist pattern is removed to obtain a structure as shown in FIG.

  Here, the width of the opening 110 may be widened by using isotropic etching. As a result, the width of a part of the second interlayer insulating film 37 located between the opening 110 and the opening for the other capacitor lower electrode is made smaller than the minimum processing dimension that can be formed by photolithography. It becomes possible. As a result, even when the capacitor lower electrode 112 (see FIG. 72) is formed in the opening 110, the distance between the capacitor lower electrode 112 and the other capacitor lower electrode can be made smaller than in the prior art. As a result, the semiconductor device can be more highly integrated.

  Next, as shown in FIG. 75, a conductor film 111 made of amorphous silicon or the like is formed on the boron-doped silicon oxide film 60 and inside the opening 110.

  Next, as shown in FIG. 76, the capacitor lower electrode 112 is formed by removing the conductive film 111 (see FIG. 75) located on the boron-doped silicon oxide film 60 by dry etching or CMP. To do.

  Next, as shown in FIG. 77, the boron-doped silicon oxide film (see FIG. 76) is removed by etching.

  Thereafter, a dielectric film 150 (see FIG. 72) or the like is formed on the capacitor lower electrode 112 and the second interlayer insulating film 37, thereby obtaining a structure as shown in FIG.

  FIG. 78 is a cross sectional view showing a first modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 78, the first modification of the DRAM according to the sixth embodiment of the present invention basically has the same structure as the DRAM according to the sixth embodiment of the present invention shown in FIG. However, in the first modification of the DRAM according to the sixth embodiment of the present invention, granular crystal 74 is formed on the inner surface of capacitor lower electrode 112. Therefore, the surface area of the capacitor lower electrode 112 can be increased without increasing the area occupied by the capacitor lower electrode 112 on the semiconductor substrate 1. Thereby, the capacity of the capacitor can be increased. As a result, the area occupied by the capacitor lower electrode 112 can be reduced while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  As a manufacturing process of the first modification of the DRAM according to the sixth embodiment, the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS. 73 to 75 is performed, and then the present invention shown in FIG. A manufacturing process of the third modification of the DRAM according to the first embodiment is performed. Thereafter, the structure shown in FIG. 78 can be obtained by performing the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS.

  FIG. 79 is a cross sectional view showing a second modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 79, the second modification of the DRAM according to the sixth embodiment of the present invention basically has the same structure as the DRAM according to the sixth embodiment of the present invention shown in FIG. However, in the second modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 79, granular crystals 74 are also formed on the inner surface and the outer side surface of capacitor lower electrode 112. Therefore, the surface area of the capacitor lower electrode 112 can be increased without increasing the area occupied by the capacitor lower electrode 112. For this reason, it is possible to further reduce the area occupied by the capacitor lower electrode 112 while ensuring a certain capacitor capacity.

  FIG. 80 is a cross sectional view for illustrating a manufacturing step in the second modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. Referring to FIG. 80, the manufacturing process of the second modification of the DRAM according to the sixth embodiment of the present invention will be described below.

  First, after performing the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS. 73 to 77, granular crystals 74 (see FIG. 80) are formed on the surface of the capacitor lower electrode 112. As the step of forming the granular crystal 74, the step used for forming the granular crystal in the first embodiment of the present invention is used. In this way, a structure as shown in FIG. 80 is obtained.

  Thereafter, a dielectric film 150 (see FIG. 79) or the like is formed on the granular crystal 74 and the second interlayer insulating film 37, thereby obtaining a structure as shown in FIG.

  FIG. 81 is a cross sectional view showing a third modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 81, the third modification of the DRAM according to the sixth embodiment of the present invention basically has the same structure as the DRAM according to the sixth embodiment of the present invention shown in FIG. However, in the third modification of the DRAM according to the sixth embodiment of the present invention, capacitor lower electrode 92 is formed to be a thick film type. Also in the third modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 81, the same effect as that of the DRAM according to the sixth embodiment of the present invention shown in FIG. 72 is obtained.

  As a manufacturing process of the third modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 81, the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS. Then, the manufacturing process of the DRAM according to the second embodiment of the present invention shown in FIGS. 28 and 29 is performed. In this way, a structure as shown in FIG. 81 is obtained.

  FIG. 82 is a cross sectional view showing a fourth modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 82, the fourth modification of the DRAM according to the sixth embodiment of the present invention is basically the same as the third modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. The structure is provided. However, in the fourth modification shown in FIG. 82, sidewalls 96 and 97 are provided on the side surface of the capacitor lower electrode 92. The sidewalls 96 and 97 are formed such that at least a part of their surfaces are curved. For this reason, the surface area on the side surface of the capacitor lower electrode 92 can be made larger than when the sidewalls 96 and 97 are not formed on the capacitor lower electrode 92. As a result, the capacitor capacity can be increased. For this reason, it is possible to reduce the area occupied by the capacitor lower electrode as compared with the prior art while ensuring a certain capacitor capacity. As a result, the semiconductor device can be further miniaturized.

  As a manufacturing process of the fourth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 82, the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS. 28 and 29, the manufacturing process of the DRAM according to the second embodiment of the present invention is carried out. Thereafter, the manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention shown in FIGS. 31 and 32 is performed. In this way, a structure as shown in FIG. 82 is obtained.

  FIG. 83 is a cross sectional view showing a fifth modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 83, the fifth modification of the DRAM according to the sixth embodiment of the present invention is basically the same as the fourth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. However, a granular crystal 98 is further provided on the surfaces of the side walls 96 and 97 formed on the side surface of the capacitor lower electrode 92. For this reason, the fifth modification of the DRAM according to the sixth embodiment of the present invention includes granular crystal 98, so that the surface area of the capacitor lower electrode is further increased without increasing the area occupied by capacitor lower electrode 92. be able to. Thereby, the capacity of the capacitor can be increased. As a result, the area occupied by the capacitor lower electrode 92 can be reduced as compared with the prior art while ensuring a certain capacitor capacity, and the semiconductor device can be further miniaturized.

  As a manufacturing process of the fifth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 83, first, the manufacturing process of the DRAM according to the sixth embodiment of the present invention shown in FIGS. Thereafter, the manufacturing process of the DRAM according to the second embodiment of the present invention shown in FIGS. Then, after performing the manufacturing process of the first modification of the DRAM according to the second embodiment of the present invention shown in FIGS. 31 and 32, the third step of the DRAM according to the second embodiment of the present invention shown in FIG. The manufacturing process of the modified example is performed. In this way, a structure as shown in FIG. 83 is obtained.

  FIG. 84 is a cross sectional view showing a sixth modification of the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 84, the sixth modification of the DRAM according to the sixth embodiment of the present invention is basically the same as the fifth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. The structure is provided. However, in the sixth modification shown in FIG. 84, the granular crystal 98 is also formed on the upper surface of the capacitor lower electrode 92. Therefore, the surface area of the capacitor lower electrode 92 can be increased without increasing the area occupied by the capacitor lower electrode 92. Thereby, the same effect as in the fifth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 83 can be obtained.

  The manufacturing process of the sixth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. 84 is the same as the manufacturing process of the fifth modification of the DRAM according to the sixth embodiment of the present invention shown in FIG. After forming the sidewalls 96 and 97, the manufacturing process of the fourth modification example of the DRAM according to the second embodiment of the present invention shown in FIG. 38 is performed to obtain the structure shown in FIG.

(Embodiment 7)
FIG. 85 is a schematic plan view of a memory cell of a DRAM according to the seventh embodiment of the present invention. The memory cell of the DRAM according to the seventh embodiment basically has the same structure as the memory cell of the DRAM according to the first embodiment of the present invention shown in FIG. However, in the DRAM according to the seventh embodiment, the width of bit line 174 is smaller than the width of contact hole 49. And the cross section in line segment 500-500 is shown in FIG. Referring to FIG. 86, the DRAM according to the seventh embodiment of the present invention basically has the same structure as the first modification of the DRAM according to the first embodiment of the present invention shown in FIG. However, the DRAM according to the seventh embodiment of the present invention shown in FIG. 86 is formed such that the width of bit line 174 is smaller than the width of contact hole 49. Therefore, in addition to the effect of the first modification of the DRAM according to the first embodiment of the present invention shown in FIG. 16, the width of bit line 174 is made larger than the width of contact hole 49 as in the prior art. Compared with the semiconductor device, the semiconductor device can be further miniaturized. The bit line 174 is in direct contact with the second interlayer insulating film 37, and no wiring protection insulating film such as a silicon nitride film is formed between the bit line 174 and the second interlayer insulating film 37. For this reason, the number of layers formed in the memory cell region can be reduced as compared with the case where a wiring protective insulating film is formed on the bit line 174 as in the prior art. As a result, the height of the upper surface of the fourth interlayer insulating film 205 in the memory cell region can be lowered, and the height of the upper surface of the fourth interlayer insulating film 205 in the memory cell region and the height in the peripheral circuit region. It is possible to further reduce the step difference. Thus, even when a wiring layer made of aluminum or the like is formed on the fourth interlayer insulating film 205 by photolithography, this wiring layer is caused by the step on the upper surface of the fourth interlayer insulating film 205. The pattern can be prevented from becoming unclear. Thereby, it is possible to prevent the occurrence of defects such as disconnection or short circuit of the wiring layer, and to obtain a semiconductor device having high reliability while ensuring the capacitance of the capacitor while being highly integrated.

  The manufacturing process of the DRAM according to the seventh embodiment of the present invention shown in FIG. 86 is basically the same as the manufacturing process of the first modification of the DRAM according to the first embodiment of the present invention shown in FIG. However, in the manufacturing process shown in FIG. 7, a refractory metal film 127 such as titanium and a tungsten film 126 are formed inside the contact hole 49. Then, after forming a resist pattern on the tungsten film 126, by using this resist pattern as a mask, a part of the tungsten film 126 and the refractory metal film 127 is removed by etching, thereby forming a bit as shown in FIG. Line 174 is formed. Since no wiring protective insulating film such as a silicon nitride film is formed on the bit line 174, the surface of the second interlayer insulating film 37 is more easily planarized after the second interlayer insulating film 37 is formed.

  FIG. 87 is a cross sectional view showing a modification of the DRAM according to the seventh embodiment of the present invention. Referring to FIG. 87, the modification of the DRAM according to the seventh embodiment of the present invention basically has the same structure as the DRAM according to the seventh embodiment of the present invention shown in FIG. However, in the modification of the DRAM according to the seventh embodiment of the present invention shown in FIG. 87, plug 128 made of phosphorus-doped polysilicon is formed inside contact hole 49. A bit line 174 made of a refractory metal film 127 such as titanium and a tungsten film 126 is formed on the plug 128. The bit line 174 is formed to have a width smaller than that of the contact hole 49. By forming in this way, the same effect as the DRAM according to the seventh embodiment of the present invention shown in FIG. 86 can be obtained.

  The manufacturing process of the modification of the DRAM according to the seventh embodiment of the present invention shown in FIG. 87 is basically the same as that of the DRAM according to the seventh embodiment of the present invention shown in FIG. However, in the step of forming the bit line 174 of the modified example of the DRAM according to the seventh embodiment shown in FIG. 87, first, the plug 128 made of phosphorus-doped polysilicon is formed in the contact hole 49 and then the bit line 174 is formed. Is forming.

(Embodiment 8)
FIG. 88 is a cross sectional view of a DRAM according to the eighth embodiment of the present invention. The structure of the memory cell region of the DRAM according to the eighth embodiment is basically the same as the structure of the memory cell region of the DRAM according to the first embodiment of the present invention shown in FIG. The structure of the peripheral circuit region of the DRAM according to the eighth embodiment is basically the same as the structure of the peripheral circuit region of the DRAM according to the first embodiment of the present invention shown in FIG. However, in the DRAM according to the eighth embodiment of the present invention shown in FIG. 88, a contact hole for connecting a wiring formed on fourth interlayer insulating film 205 and capacitor upper electrode 151 in the peripheral circuit region. 135 is formed. A dummy wiring 138 for protecting peripheral circuit elements such as a field effect transistor in the peripheral circuit region is formed in a region located under the contact hole 135. As described above, since the dummy wiring 138 is provided, in the etching for forming the contact hole 135, the contact hole 135 penetrates the capacitor upper electrode 151 and the dielectric film 150 to the third interlayer insulating film 59 and the like located thereunder. Even when it reaches, the progress of the etching can be stopped in the dummy wiring 138 formed of the doped polysilicon film 52 and the refractory metal silicide film 53. As a result, it is possible to prevent the peripheral circuit element located under the dummy wiring 138 from being damaged by the etching. As a result, the semiconductor device can be prevented from malfunctioning due to damage to the peripheral circuit elements. As a result, a highly reliable semiconductor device can be obtained.

  The manufacturing process of the DRAM according to the eighth embodiment of the present invention shown in FIG. 88 is basically the same as the manufacturing process of the DRAM according to the first embodiment of the present invention shown in FIGS. However, the dummy wiring 138 is formed in the same process as the wiring 202 in the peripheral circuit region shown in FIG.

  FIG. 89 is a cross sectional view showing a first modification of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 89, the first modification of the DRAM according to the eighth embodiment of the present invention basically has the same structure as the DRAM according to the eighth embodiment of the present invention shown in FIG. However, in the first modification example of the DRAM according to the eighth embodiment of the present invention shown in FIG. 89, in the peripheral circuit region, the region located below contact hole 135 includes the wiring and field effect type in the peripheral circuit region. No peripheral circuit elements such as transistors are formed. Thus, in the etching process for forming the contact hole 135, even when the contact hole 135 penetrates the capacitor upper electrode 151 and the like and reaches the third interlayer insulating film 59 located under the capacitor upper electrode 151, the peripheral region is formed by the etching. Circuit elements are not damaged.

  The manufacturing process of the first modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. 89 is basically the same as the manufacturing process of the DRAM according to the eighth embodiment of the present invention shown in FIG. . However, the contact hole 135 and the peripheral circuit element are formed in regions that do not overlap each other in plan view.

  FIG. 90 is a cross sectional view showing a second modification of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 90, the memory cell region of the second modification of the DRAM according to the eighth embodiment of the present invention basically has the same structure as that of the DRAM according to the eighth embodiment of the present invention shown in FIG. Prepare. In the peripheral circuit region, an opening 303 is formed by removing part of the third interlayer insulating film 59 and the silicon nitride film 58. Inside the opening 303, a dummy capacitor lower electrode 140 made of the same material as that of the capacitor lower electrode 170a in the memory cell region is formed. A dielectric film 150 is formed on the third interlayer insulating film 59 and the dummy capacitor lower electrode 140. A capacitor upper electrode 151 is formed on the dielectric film 150. The contact hole 135 reaches the capacitor upper electrode 151 at the bottom of the dummy capacitor lower electrode 140. As described above, the dummy capacitor lower electrode 140 is formed and the contact hole 135 is formed in the region located above the dummy capacitor lower electrode 140. Therefore, the depth of the contact hole 135 is set according to the eighth embodiment of the present invention shown in FIG. It can be made deeper than the depth of the contact hole 135 in the DRAM. As a result, another contact hole (not shown) reaching the wiring layer 202 (see FIG. 2) in the peripheral circuit region and the contact hole 135 (see FIG. 90) of the DRAM according to the eighth embodiment of the present invention. The difference in depth can be shortened. As a result, the etching for forming the contact hole 135 can prevent the capacitor upper electrode 151 from being excessively etched at the bottom of the contact hole 135. As a result, the etching can be prevented from penetrating through the capacitor upper electrode 151 and reaching the second interlayer insulating film 37 therebelow.

  The manufacturing process of the second modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. 90 is basically the first modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. The dummy capacitor lower electrode 140 is formed at the same time as the capacitor lower electrode 170a in the step of forming the capacitor lower electrode 170a in the memory cell region.

  FIG. 91 is a cross sectional view showing a third modification of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 91, the third modification of the DRAM according to the eighth embodiment of the present invention is basically the same as the second modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. The structure is provided. However, in the third modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. 91, the horizontal width of dummy capacitor lower electrode 140 is reduced, and the capacitor upper portion inside dummy capacitor lower electrode 140 is reduced. The thickness of the electrode 151 in the vertical direction is larger than that of the second modification shown in FIG. A contact hole 135 is formed above the capacitor upper electrode 151 having a large thickness in the vertical direction. As described above, since the thickness of the capacitor upper electrode 151 positioned below the contact hole 135 is increased in the vertical direction, the contact hole 135 penetrates the capacitor upper electrode 151 during the etching for forming the contact hole 135. It is possible to prevent reaching the second interlayer insulating film 37. Further, by adjusting the width of the opening 303 and the film thickness of the capacitor upper electrode 151, the reaching depth of the contact hole 135 can be arbitrarily changed.

  The manufacturing process of the third modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. 91 is basically the same as that of the second modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. It is the same as the manufacturing process.

  Here, in order to obtain a semiconductor device that can be highly integrated while securing a certain capacitor capacity and has high reliability, the wiring used in the memory cell region and the peripheral circuit region also has lower resistance. Low-capacity wiring is required.

  FIG. 118 is a cross-sectional view showing a conventional wiring formed by using the damascene method. Referring to FIG. 118, in the conventional wiring, a silicon nitride film 1002 is formed on the main surface of semiconductor substrate 1001. A non-doped silicon oxide film 1143 is formed on the silicon nitride film 1002. An opening 1003 is formed by removing a part of the non-doped silicon oxide film 1143 and the silicon nitride film 1002. A wiring 1005 made of polysilicon is formed inside the opening 1003.

  119 and 120 are cross-sectional views for explaining the manufacturing process of the conventional wiring shown in FIG. With reference to FIGS. 119 and 120, a conventional wiring manufacturing process will be described below.

  First, a silicon nitride film 1002 (see FIG. 119) is formed on the main surface of the semiconductor substrate 1001 (see FIG. 119). The silicon nitride film 1002 may be a silicon oxynitride film or a film having a stacked structure of a silicon nitride film and a silicon oxynitride film. A non-doped silicon oxide film 1143 (see FIG. 119) is formed on the silicon nitride film 1002. The non-doped silicon oxide film 1143 may be a silicon oxide film doped with phosphorus or boron. After a resist pattern (not shown) is formed on the non-doped silicon oxide film 1143, a part of the non-doped silicon oxide film 1143 and the silicon nitride film 1002 is removed using the resist pattern as a mask, thereby opening the openings. A portion 1003 (see FIG. 119) is formed. In this way, a structure as shown in FIG. 119 is obtained.

  Next, as shown in FIG. 120, a polysilicon film 1004 is formed on the non-doped silicon oxide film 1143 and inside the opening 1003. The polysilicon film 1004 may be made of amorphous silicon. Further, phosphorus or arsenic may be doped or impurities may not be doped. Further, a refractory metal film such as tungsten or titanium may be used, or a silicide of the above refractory metal may be used. Further, a metal film such as copper or aluminum may be used, or a structure in which these are laminated may be used.

  Thereafter, the polysilicon film 1004 located on the non-doped silicon oxide film 1143 is removed by etching or CPM, thereby obtaining a structure as shown in FIG.

  Another example of the conventionally proposed wiring structure is as shown in FIG. Referring to FIG. 121, another conventionally proposed wiring forms a silicon nitride film 1002 on the main surface of a semiconductor substrate 1001. A non-doped silicon oxide film 1143 is formed on the silicon nitride film 1002. An opening 1003 is formed by removing a part of the non-doped silicon oxide film 1143 and the silicon nitride film 1002. A wiring 1015 made of polysilicon is formed inside the opening 1003. A granular crystal 1016 is formed on the surface of the wiring 1015. Thus, since the granular crystal 1016 is formed on the surface of the wiring 1015, the resistance of the wiring 1015 can be lowered.

  122 to 124 are cross-sectional views for explaining another conventional manufacturing process of the wiring shown in FIG. Hereinafter, another conventionally proposed wiring manufacturing process will be described with reference to FIGS.

  A silicon nitride film 1002 (see FIG. 122) is formed on the main surface of the semiconductor substrate 1001 (see FIG. 122). A non-doped silicon oxide film 1143 (see FIG. 122) is formed on the silicon nitride film 1002. After a resist pattern (not shown) is formed on the non-doped silicon oxide film 1143, a part of the non-doped silicon oxide film 1143 and the silicon nitride film 1002 is removed by etching using this resist pattern as a mask. An opening 1003 (see FIG. 122) is formed. Thereafter, the resist pattern is removed. In this way, a structure as shown in FIG. 122 is obtained.

  Next, as shown in FIG. 123, a conductor film 1014 made of polysilicon is formed inside the opening 1003 and on the non-doped silicon oxide film 1143.

  Next, a part of the conductor film 1014 located on the non-doped silicon oxide film 1143 is removed by etching, whereby a structure as shown in FIG. 124 is obtained. Thereafter, a granular crystal 1016 (see FIG. 121) is formed on the surface of the wiring 1015 by the same process as that used in the modification of the first embodiment of the present invention. In this way, a structure as shown in FIG. 121 is obtained.

  As described above, wiring with low resistance has been proposed in the past. However, miniaturization of semiconductor devices has progressed, and degradation of device characteristics such as access delay due to increase in wiring resistance is also a problem with conventional wiring. It has become. For this reason, further reduction in resistance and capacitance of the wiring is required. For the purpose of obtaining wiring satisfying such requirements, the structure applied to the shape of the capacitor lower electrode in the present invention can be applied. A modification of the wiring in the DRAM according to the eighth embodiment of the present invention based on such an idea will be described below.

  FIG. 92 is a cross sectional view showing a first modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 92, in the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention, silicon nitride film 2 is formed on the main surface of semiconductor substrate 1. A non-doped silicon oxide film 143 is formed on the silicon nitride film 2. A wiring 5 made of polysilicon is formed so as to be partially embedded in the non-doped silicon oxide film 143 and the silicon nitride film 2. Granular crystals 9 are formed on the inner surface and the outer side surface of the wiring 5. Thus, since the wiring 5 is formed so as to extend above the upper surface of the non-doped silicon oxide film 143, the cross-sectional area of the wiring 5 can be increased even if the occupation area of the wiring 5 is reduced. Thereby, the resistance of the wiring 5 can be reduced. Moreover, since the granular crystal 9 is formed on the surface of the wiring 5, a wiring with lower resistance can be obtained.

  93 to 96 are cross-sectional views for illustrating a manufacturing process of the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. A manufacturing process of the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention will be described below with reference to FIGS.

  First, a silicon nitride film 2 (see FIG. 93) is formed on the main surface of the semiconductor substrate 1 (see FIG. 93). A non-doped silicon oxide film 143 (see FIG. 93) is formed on the silicon nitride film 2. A boron-doped silicon oxide film 6 (see FIG. 93) is formed on the non-doped silicon oxide film 143. After a resist pattern (not shown) is formed on the boron-doped silicon oxide film 6, one of the boron-doped silicon oxide film 6, the non-doped silicon oxide film 143, and the silicon nitride film 2 is formed using this resist pattern as a mask. The part is removed by anisotropic etching. Thereby, the opening 3 (see FIG. 93) is formed. Thereafter, the resist pattern is removed to obtain a structure as shown in FIG.

  Next, as shown in FIG. 94, a polysilicon film 4 is formed on the boron-doped silicon oxide film 6 and inside the opening 3.

  Next, the polysilicon film 4 located on the boron-doped silicon oxide film 6 is removed by etching or CMP to obtain a structure as shown in FIG.

  Next, the boron-doped silicon oxide film 6 is removed by etching to obtain a structure as shown in FIG.

  Thereafter, by applying the process used in the modification of the first embodiment of the present invention, a granular crystal 9 (see FIG. 92) is formed on the surface of the wiring 5, thereby obtaining a structure as shown in FIG.

  97 to 100 are cross-sectional views for illustrating a modification of the process of the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. A modification of the manufacturing process of the first modification of the wiring of the DRAM according to the eighth embodiment of the present invention will be described below with reference to FIGS.

  A silicon nitride film 2 (see FIG. 97) is formed on the semiconductor substrate 1 (see FIG. 97). A non-doped silicon oxide film 143 (see FIG. 97) is formed on the silicon nitride film 2. After a resist pattern (not shown) is formed on the non-doped silicon oxide film 143, a part of the non-doped silicon oxide film 143 and the silicon nitride film 2 is removed by anisotropic etching using the resist pattern as a mask. . Thereby, the opening 3 (see FIG. 97) is formed. In this way, a structure as shown in FIG. 97 is obtained.

  Next, a polysilicon film 4 (see FIG. 98) is formed on the non-doped silicon oxide film 143 and inside the opening 3. In this way, a structure as shown in FIG. 98 is obtained.

  Next, the polysilicon film 4 located on the non-doped silicon oxide film 143 is removed by etching or CMP to obtain a structure as shown in FIG. Here, a wiring 5 is formed inside the opening 3.

  Next, as shown in FIG. 100, a part of the upper portion of the non-doped silicon oxide film 143 is removed by wet etching using an HF aqueous solution. At this time, the amount by which the non-doped silicon oxide film 143 is removed can be controlled by changing the immersion time in the HF aqueous solution.

  Thereafter, a granular crystal 9 is formed on the surface of the wiring 5 to obtain a structure as shown in FIG.

  FIG. 101 is a cross sectional view showing a second modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 101, in the second modification of the wiring of DRAM according to the eighth embodiment of the present invention, silicon nitride film 2 is formed on the main surface of semiconductor substrate 1. A non-doped silicon oxide film 143 is formed on the silicon nitride film 2. A wiring 15 made of polysilicon is formed so as to be partially embedded in the non-doped silicon oxide film 143 and the silicon nitride film 2. Sidewalls 23 are formed on the side surfaces of the wiring 15 made of polysilicon. Thus, since the wiring 15 includes the sidewall 23 made of polysilicon, the cross-sectional area of the wiring can be increased. For this reason, wiring can be made lower resistance.

  102 to 104 are cross-sectional views for illustrating a manufacturing process of the second modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. A manufacturing process of the second modified example of the DRAM wiring according to the eighth embodiment of the present invention will be described below with reference to FIGS.

  First, after performing the manufacturing process of the first modified example of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 93, the boron doped silicon oxide film 6 (see FIG. 102) and the opening 3 ( A polysilicon film (not shown) is formed on the inside (see FIG. 93). Thereafter, the polysilicon film located on the boron-doped silicon oxide film 6 is removed to form wiring 15 as shown in FIG.

  Next, the boron-doped silicon oxide film 6 is removed by etching to obtain a structure as shown in FIG. Thereby, a part 25 of the side surface of the wiring 15 can be exposed.

Next, as shown in FIG. 104, a polysilicon film 24 is formed so as to cover the whole.
Thereafter, a part of the polysilicon film 24 is removed by anisotropic etching to obtain a structure as shown in FIG.

  FIG. 105 is a cross sectional view showing a third modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 105, the third modification of the wiring of the DRAM according to the eighth embodiment of the present invention is basically the second modification of the DRAM according to the eighth embodiment of the present invention shown in FIG. With the same structure. However, in the third modification shown in FIG. 105, the wiring 304 is made of amorphous silicon. The side wall 23 is also made of amorphous silicon, and granular crystals 26 are formed on the surfaces of the wiring 304 and the side wall 23. As described above, since the surface of the wiring 304 and the sidewall 23 is provided with granular crystals, the resistance of the wiring can be further reduced.

  Further, as a manufacturing process of the third modification of the wiring of the DRAM according to the eighth embodiment of the present invention, after the manufacturing process shown in FIGS. 102 to 104 is performed, the modification of the first embodiment of the present invention is performed. A structure as shown in FIG. 105 can be obtained by carrying out the step of forming granular crystals performed in step (1).

  FIG. 106 is a cross sectional view showing a fourth modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 106, the fourth modification example of the wiring of the DRAM according to the eighth embodiment of the present invention basically has the same structure as the third modification example shown in FIG. However, in the fourth modified example shown in FIG. 106, the wiring 15 is made of polysilicon, and the granular crystal 26 is formed on the surface of the sidewall 23 made of amorphous silicon. A granular crystal 35 smaller than the granular crystal 26 is formed on the upper surface of the wiring 15. With this configuration, the same effect as that of the third modification of the DRAM wiring according to the eighth embodiment of the present invention can be obtained.

  FIG. 107 is a cross sectional view showing a fifth modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 107, in the fifth modification of the wiring of the DRAM according to the eighth embodiment of the present invention, silicon nitride film 2 is formed on the main surface of semiconductor substrate 1. A non-doped silicon oxide film 143 is formed on the silicon nitride film 2. A wiring 30 made of polysilicon is formed so as to be embedded in the non-doped silicon oxide film 143 and the silicon nitride film 2. A gap 33 is formed between the wiring 30 and the non-doped silicon oxide film 143 and the silicon nitride film 2. A silicon oxide film 32 is formed so as to cover the whole. As described above, since the gap 33 is provided on the side surface of the wiring 30, the parasitic capacitance in the wiring 30 can be reduced. Thereby, the delay of the access time of the semiconductor element due to the presence of the parasitic capacitance can be prevented, and the deterioration of the electrical characteristics of the device can be prevented.

  108 to 112 are cross-sectional views for illustrating a manufacturing process of the fifth modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. A manufacturing process of the fifth modification example of the wiring of the DRAM according to the eighth embodiment of the present invention will be described below with reference to FIGS.

  First, a silicon nitride film 2 (see FIG. 108) is formed on the main surface of the semiconductor substrate 1 (see FIG. 108). A non-doped silicon oxide film 143 (see FIG. 108) is formed on the silicon nitride film 2. After forming a resist pattern (not shown) on the non-doped silicon oxide film 143, using this resist pattern as a mask, a part of the non-doped silicon oxide film 143 and the silicon nitride film 2 is removed by etching. Opening 3 (see FIG. 108) is formed. In this way, a structure as shown in FIG. 108 is obtained.

  Next, an insulating film 27 (see FIG. 109) such as a silicon nitride film is formed on the non-doped silicon oxide film 143 and inside the opening 3. In this way, a structure as shown in FIG. 109 is obtained.

  Next, a sidewall 28 (see FIG. 110) is formed inside the opening 3 by removing a part of the insulating film 27 using anisotropic etching. Then, as shown in FIG. 110, a polysilicon film 29 is formed on the non-doped silicon oxide film 143 and inside the opening 3.

  Next, a part of the polysilicon film 29 located on the non-doped silicon oxide film 143 is removed by using anisotropic etching or CMP, thereby obtaining a structure as shown in FIG.

  Next, as shown in FIG. 112, the sidewall 28 (see FIG. 111) is selectively removed by etching. Thereby, a gap 33 is formed on the side surface of the wiring 30.

  Thereafter, a silicon oxide film 32 (see FIG. 107) with poor coverage is formed so as to cover the whole, thereby obtaining a structure as shown in FIG.

  FIG. 113 is a cross sectional view showing a sixth modification of the wiring of the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 113, the sixth modification of the DRAM wiring according to the eighth embodiment of the present invention is basically the fifth modification of the DRAM wiring according to the eighth embodiment of the present invention shown in FIG. It has the same structure as the modified example. However, in the sixth modified example shown in FIG. 113, a part of the sidewall 28 remains under the gap 33. Even with this configuration, the same effect as that of the fifth modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 107 can be obtained.

  The manufacturing process of the sixth modification of the wiring of the DRAM according to the eighth embodiment of the present invention shown in FIG. 113 is basically the DRAM according to the eighth embodiment of the present invention shown in FIGS. This is the same as the manufacturing process of the fifth modification of the wiring. However, in the process shown in FIG. 112, not all the sidewalls 28 on the side surfaces of the wiring 30 are removed, but a part thereof is left.

  In addition, the 1st-6th modification of this wiring is applicable also to Embodiment 1-7 of this invention.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2,44a-44e, 54,58,203 Silicon nitride film, 40 Trench isolation oxide film, 39 Active region, 42a-42e Gate insulating film, 43a-43e Gate electrode, 46a-46i, 45, 55a, 55b, 204a, 204b, 96, 97, 100, 23, 28 Side wall, 47, 85, 143 Non-doped silicon oxide film, 48, 37, 205, 59, 77 Interlayer insulating film, 38a, 38b, 49, 50, 51,144 Contact hole, 52, 56, 62, 91, 101, 104, 111, 141, 4, 29, 5, 15, 30, 24 Polysilicon film, 53 refractory metal silicide film, 201a to 201e Source / drain Area, 174, 202, 138 wiring, 57a, 57b, 128 plug, 61, 1 0, 3, 303 Opening, 170a, 170b, 92, 112, 120 Capacitor lower electrode, 150 Dielectric film, 151 Capacitor upper electrode, 60, 86, 6 Doped silicon oxide film, 70 Resist, 74, 98, 9 , 26, 35 Granular crystal, 95, 304 Amorphous silicon, 99 Insulating film, 126 Tungsten layer, 127 Refractory metal layer, 135 Capacitor upper electrode contact hole, 139 Trench isolation oxide film, 140 Dummy capacitor lower electrode, 142 Wrapping Space, part of 25 side surface, 27, 32 silicon oxide film, 33 gap, 301 top surface, 302 bottom surface.

Claims (13)

A semiconductor substrate having a field effect transistor provided on a main surface thereof, the bit line being electrically connected to one of a pair of source or drain regions of the field effect transistor; A first semiconductor substrate is provided, further comprising a conductor electrically connected to the other of the pair of source or drain regions, the upper surface of which is higher than the upper surface of the bit line as viewed from the main surface. Process,
After the first step, a second step of forming a silicon nitride film on the conductor;
A third step of forming a first insulating film in contact with the upper surface of the silicon nitride film;
A fourth step of forming a second insulating film in contact with the upper surface of the first insulating film;
After the fourth step, a fifth step of forming an opening through the silicon nitride film, the first insulating film, and the second insulating film to expose the conductor;
After the fifth step, the opening is etched in the opening under an etching condition in which the etching rate of the first insulating film is higher than that of the second insulating film and the silicon nitride film . The opening width of the opening is defined by the second portion defined by the second insulating film and the silicon nitride film, compared to the opening width at the first portion defined by the first insulating film. A sixth step of narrowing the opening width in the third portion to be performed ;
After the sixth step, a seventh step of forming a lower electrode of the capacitor that is electrically connected to the conductor along the inner surface of the opening without contacting the upper surface of the second insulating film. When,
After the seventh step, an eighth step of forming an upper electrode of the capacitor facing the lower electrode through a dielectric film;
A method for manufacturing a semiconductor device, comprising:   The seventh step includes a step of forming another conductor on the upper surface of the second insulating film and the inner surface of the opening, and the upper surface of the second insulating film among the other conductors. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing a portion. A semiconductor substrate having a field effect transistor provided on a main surface thereof, the bit line being electrically connected to one of a pair of source or drain regions of the field effect transistor; A first semiconductor substrate is provided, further comprising a conductor electrically connected to the other of the pair of source or drain regions, the upper surface of which is higher than the upper surface of the bit line as viewed from the main surface. Process,
A second step of forming a silicon nitride film on the conductor after the first step;
A third step of forming a first insulating film in contact with the upper surface of the silicon nitride film;
A fourth step of forming a second insulating film in contact with the upper surface of the first insulating film;
A fifth step of forming an opening exposing the conductor in the silicon nitride film, the first insulating film, and the second insulating film;
After the fifth step, a lower electrode of a capacitor electrically connected to the conductor is formed along the inner surface of the opening without contacting the upper surface of the second insulating film. Process,
After the sixth step, a seventh step of forming the upper electrode of the capacitor facing the lower electrode through a dielectric film;
With
In the fifth step, after forming a hole penetrating the first and second insulating films, the width of the hole in the first insulating film is made wider than the width of the hole in the second insulating film. We have a process,
In the opening formed by the fifth step, the opening width of the opening is larger than the opening width in the first portion where the opening width of the opening is defined by the first insulating film. the opening width of the third portion is that is narrower, a method of manufacturing a semiconductor device defined by the second portion and the silicon nitride film as defined in the insulating film.   The sixth step includes a step of forming another conductor on the upper surface of the second insulating film and the inner surface of the opening, and on the upper surface of the second insulating film among the other conductors. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of removing a certain portion.   The first and second insulating films contain silicon and oxygen, the first insulating film further contains impurities that are not silicon and oxide films, and the first insulating film has the second insulating film in relation to the concentration of the impurities. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration is higher than that of the film.   The method for manufacturing a semiconductor device according to claim 5, wherein the impurity is boron.   The method for manufacturing a semiconductor device according to claim 5, wherein the impurity is phosphorus. The method for manufacturing a semiconductor device according to claim 1, wherein an opening width of the second portion is wider than a width of a connection portion between the conductor and the lower electrode. A semiconductor substrate having a main surface;
A field effect transistor provided on the main surface of the semiconductor substrate;
A first insulating layer provided on the main surface of the semiconductor substrate so as to cover the field effect transistor;
A bit line provided in the first insulating layer and electrically connected to one of a pair of source or drain regions of the field effect transistor;
A conductive layer provided in the first insulating layer, electrically connected to the other source or drain region of the field effect transistor, and having an upper surface higher than the upper surface of the bit line as viewed from the main surface; Body,
A silicon nitride film provided on the first insulating layer;
A first insulating film provided in contact with the upper surface of the silicon nitride film;
A second insulating film provided in contact with the upper surface of the first insulating film and having an etching rate different from that of the first insulating film;
Provided along the inner surface of the opening provided in the silicon nitride film, the first insulating film, and the second insulating film without being in contact with the upper surface of the second insulating film; The lower electrode of the capacitor in contact,
An upper electrode of a capacitor disposed inside the opening and facing the lower electrode via a dielectric material, and extending over the upper surface of the second insulating film;
The opening has a first portion whose opening width is defined by the first insulating film, a second portion defined by the second insulating film, and a first portion defined by the silicon nitride film. and a third portion, said viewed from a section perpendicular to the back surface of the semiconductor substrate, the opening width of said second portion and said third portion is not narrower than the opening width of the first portion, Semiconductor device. The first and second insulating films contain silicon and oxygen, the first insulating film further contains impurities that are not silicon and oxide films, and the first insulating film has the second insulating film in relation to the concentration of the impurities. The semiconductor device according to claim 9 , wherein the concentration is higher than that of the film. The semiconductor device according to claim 10 , wherein the impurity is boron. The semiconductor device according to claim 10 , wherein the impurity is phosphorus. The semiconductor device according to claim 9, wherein an opening width of the second portion is wider than a width of a connection portion between the conductor and the lower electrode.

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