JP2003332464A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower increase of parasitic capacitance due to the formation of an electrode connection with a bit line in regard to a semiconductor memory device and a method of manufacturing the same. <P>SOLUTION: Overhang sections 3 which are led out in the shape of an overhang are provided in the areas deviated in a direction along a gate wiring from an active region 4, particularly at the area deviated by half-pitch to a contact electrode 2 for an upper layer from the active layer 4 within a memory array region including an accumulated capacitance in which at least a part thereof is located at the layer 1 higher than the bit line 1. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a structure for reducing a parasitic capacitance caused by a bit line contact of a DRAM (dynamic random access memory). The present invention relates to a characteristic semiconductor memory device and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor integrated circuit devices, SAC (Self-Alig) for forming a fine via hole by forming an insulating opening between wiring layers.
n Contact) method is known.

In a DRAM, it is difficult to resolve a complicated shape due to the progress of miniaturization. Therefore, the active region in which the memory cell is arranged is a simple rectangle, and the active region is arranged along the gate wiring. A structure in which a bit line contact is formed in a portion shifted by a half pitch is essential.

11 (a) and 11 (b). FIG. 11 (a) is a schematic plan view of a memory cell portion of a conventional DRAM, and FIG. 11 (b) is shown in FIG. 11 (a).
6 is a schematic cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG.
CH isolation method is used to form B by ion implantation into a simple rectangular region in which the element isolation insulating film 62 is formed.

Then, a gate insulating film (not shown) is formed by thermal oxidation using wet O ₂ and then WS
A gate electrode having an i ₂ / Si structure and a word line 64 continuous with the gate electrode are formed. Then, P is ion-implanted to form the n-type drain region 65 and the n-type source region 66.
To form. At this time, in other transistor parts such as logic transistors, n-type LDD (Light)
A ly doped drain region is formed at the same time.

Next, a SiN film 67 for forming a spacer is formed on the side wall of the gate electrode of another transistor portion, and then anisotropic etching is performed with the memory cell portion masked to form a spacer. After forming the n ⁺ type source / drain regions of the logic transistor portion by ion implantation, source / drain electrodes are formed.

Next, a SiN film 68 is provided on the entire surface, and then a BPSG film 69 to be an interlayer insulating film is deposited. Then, a rectangular resist pattern 79 shown by a broken line in FIG. 11A is formed from the p-type well region 63. The resist pattern 79 and the word line 6 are arranged with a shift of a half pitch.
Contact holes for the n-type drain region 65 and the n-type source region 66 are formed by using the SiN films 67 and 68 covering 4 as a mask.

At this time, the contact hole for the n-type drain region 65 needs to be formed in a shape enlarged by a half pitch in the direction along the word line 64 in order to form the contact portion 73 with the bit line.

Next, a doped polycrystalline silicon layer doped with P is thickly deposited on the entire surface, and then polished by CMP until the surface of the BPSG film 69 is exposed. The polycrystalline silicon layer is removed to form polycrystalline silicon plugs 70 and 71 buried in the contact holes.

Next, P-S is formed by using the plasma CVD method.
After forming the iO ₂ film 72, in order to form a contact portion with the bit line 75, a contact hole reaching the polycrystalline silicon plug 71 is formed and embedded with a doped polycrystalline silicon layer to form a plug 74.

Then, after depositing a conductive film having a Ti / TiN / W structure, a SiN film 76 is deposited, and then a bit line 75 is formed by etching in a line / space pattern.

Next, after depositing a SiN film on the entire surface, anisotropic etching is performed to form sidewalls 77. The sidewall 77 serves as a mask in a contact hole forming process for forming a plug connected to the storage capacitor 78.

Although not described below, the polycrystalline silicon plug 7 is connected to the n-type source region 66 via the plug.
By forming a storage capacitor 78 connected to 0, D
The basic structure of the RAM is completed.

As described above, a simple rectangular active region,
The connection to the active region can be opened in a self-aligning manner by the combination of the simple island-shaped mask patterns, and thus the polycrystalline silicon plug 71 drawn out along the word line 64 can be formed. .

[0015]

However, since the conventional polycrystalline silicon plug 71 has a shape extended long along the gate wiring, a large parasitic capacitance is generated between the plug and the adjacent gate wiring. However, this parasitic capacitance is unnecessary for connection with the bit line and is an extra parasitic capacitance.

In particular, the portion extending to the bit line is arranged along the word line 64 with a thin insulating film, that is, a sidewall formed of the remaining SiN films 67 and 68 formed when the contact hole is formed. Therefore, there is a problem that the high speed operation of the memory becomes difficult due to the increase of the bit line capacity.

Further, as described above, if the bit line capacity increases, it becomes necessary to increase the number of peripheral circuits, which is an obstacle to increasing the scale.

Therefore, it is an object of the present invention to reduce an increase in parasitic capacitance due to the formation of an electrode connection portion with a bit line.

[0019]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Here, the means for solving the problems in the present invention will be described with reference to FIG. In order to solve the above problems, the present invention is directed to a semiconductor memory device in which, in a memory cell array region having a storage capacitor, at least a part of which is located above a bit line 1, from an active region 4 to an upper layer. It is characterized in that the contact electrode 2 is provided with an eaves-shaped lead-out portion 3 drawn out in an eaves-like shape at a position displaced from the active region 4 in the direction along the gate wiring, particularly at a position displaced by a half pitch.

As described above, by providing the eave-shaped lead-out portion 3, the side area of the contact electrode 2 as a whole can be reduced, so that it is possible to reduce the parasitic capacitance between the adjacent gate wirings. Signal delay can also be reduced by.

In this case, it is desirable that the eave-shaped lead-out portion 3 is provided so that its bottom surface is located above the upper surface of the conductive layer forming the adjacent gate wiring, whereby the gate wiring and the eave-shaped lead-out portion 3 are formed. Since the distance can be increased, the parasitic capacitance can be further reduced.

When forming the eaves-shaped lead-out portion 3, first, the contact electrode material in which the recess formed first is filled is used as a mask, so that the sidewall and shoulder of the gate wiring are contact electrode material. Since it is covered with, it is possible to prevent thinning and disappearance of the insulating film covering the gate wiring due to the two etching steps.

In this case, the eave-shaped lead-out portion 3 may be formed after flattening the contact electrode material having the recess formed first and the contact electrode material having the recess filled with the eave-shaped emissive portion 3. After etching using the mask pattern for forming the lead-out portion 3, a recess for the eave-like lead-out portion may be formed using only the contact electrode material as a mask.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A DRAM according to a first embodiment of the present invention will be described with reference to FIGS. 2 to 7. First, referring to FIG. The configuration of the memory cell portion of the DRAM of the embodiment will be described. 2A. FIG. 2A is a plan view of the memory cell portion of the DRAM according to the first embodiment of the present invention, in which a simple rectangular active region, that is, the p-type well region 13 is The bit lines 35 are periodically arranged alternately, and the bit lines 35 are arranged at a position shifted by a half pitch from the p-type well region 13. Further, the bit lines 35 are stored so as to be connected to the polycrystalline silicon plug 27 connected to the n-type source region. The capacitor 41 is connected.

Refer to FIG. 2B. FIG. 2B is a cross-sectional view taken along the alternate long and short dash line connecting AA 'in FIG. 2 and shows the structure at the time when the bit line 35 is formed. As shown in the figure, the polycrystalline plug 28 connected to the n-type drain 19 is provided with a plug overhang portion 31, and the contact portion 3 provided with this plug overhang portion 31.
3 is connected to the bit line 35 via the plug 34.

Next, the manufacturing process of the DRAM of the first embodiment of the present invention will be described with reference to FIGS.
3 (a) to FIG. 4 (c), FIG. 5 (d), and FIG.
FIG. 4E is a cross-sectional view in each manufacturing process taken along the alternate long and short dash line connecting AA ′ in FIG. 2, and FIGS.
(F ') is a cross-sectional view in each manufacturing step taken along the alternate long and short dash line connecting BB' in FIG. 2, and FIG. 7 (f ") is
FIG. 9 is a cross-sectional view in each manufacturing process along the alternate long and short dash line connecting CC ′ of FIG. 2. It should be noted that the cross-sectional view taken along the alternate long and short dash line connecting BB ′ in FIG. 4C ′ and FIG.
Although the bit line is shown as a part of the cross section in (f '), it actually extends in the direction connecting BB'.

First, an element isolation insulating film 12 is formed on the n-type silicon substrate 11 by the STI method, and then the element isolation insulating film 12 is formed.
B is ion-implanted into a rectangular region surrounded by to form a p-type well region 13.

Next, as shown in FIG. 4 (c '), a gate insulating film 14 is formed by thermal oxidation using wet O _2, and then an amorphous Si layer, for example, with a thickness of 10 is formed.
The Si gate electrode layer 16 having a conductivity is obtained by depositing 0 nm and then ion-implanting As or P.

Then, for example, a WS having a thickness of 100 nm is used.
Using the i ₂ layer 17 and the plasma CVD method, for example,
After sequentially depositing a SiN film 18 having a thickness of 100 nm, the photolithography technique is used to, for example, a line / space of 0.1 μm /
By patterning and etching according to the design rule of 0.1 μm, the gate electrode and the word line 15 continuous with the gate electrode are formed.

Next, after ion-implanting P to form the n-type drain region 19 and the n-type source region 20, the thickness is, for example, 6 over the entire surface by the CVD method.
By depositing a 0 nm SiN film 21 and performing anisotropic etching with the memory cell portion masked with a resist, spacers are formed on the sidewalls of the gate electrodes of the other transistor portions, and then the spacers are used as a mask. A
After n ⁺ type source / drain regions (both not shown) are formed in other transistor parts by ion implantation of s, RTA (Rapid Thermal) is performed.
Annealing method is used to recover defects caused by ion implantation by performing heat treatment at 1000 ° C. for 10 seconds, for example.

Next, Co is applied to the entire surface and the thickness is, for example,
After depositing 50 nm, at 500 ° C. for 30 seconds
By performing heat treatment,
N ⁺CoSi only on the surface of the source / drain region₂
Forming a silicide electrode consisting of hydrogen peroxide
A mixture of water and ammonia water or sulfuric acid and hydrogen peroxide water
Unreacted C by etching with the mixed solution
remove o.

Then, again using the CVD method,
For example, a SiN film 22 having a thickness of 20 nm is deposited, a BPSG film 23 is deposited on the entire surface, and then a resist pattern 24 is formed, and then C ₄ F ₈ + CO + A.
The BPSG film 23 is etched by performing dual frequency RIE (reactive ion etching) using r + O ₂ , and then the SiN film 22 and the SiN film 21 are sequentially etched to form the n-type drain region 19 and the n-type source. The area 20 is exposed.

In this etching process, as shown in FIG.
As shown in (c ′), sidewalls 25 formed by the remaining portions of the SiN films 21 and 22 are provided on the sidewalls of the word line 15 facing each other.
Is formed, and the sidewall 25 prevents a short circuit between the polycrystalline silicon plugs 27 and 28 described later and the word line 15.

Next, referring to FIG. 3B, for example, a P-doped doped polycrystalline silicon layer is thickly deposited on the entire surface, and then polished by CMP until the surface of the BPSG film 23 is exposed. , The doped polycrystalline silicon layer deposited on the BPSG film 23 is removed to form polycrystalline silicon plugs 27 and 28 buried in the contact holes.

Next, referring to FIG. 4C, again, a resist pattern 29 having an opening for forming a plug eave portion is provided, and the same reactive ion etching as described above is performed using this resist pattern 29 as a mask. The contact hole 30 is formed. The contact hole 30 in this case has a depth such that its bottom is located above the word line 15.

At this time, since the sidewalls and shoulders of the word lines 15 are covered with the polycrystalline silicon plugs 28 at this time, the sidewalls 2 which cover the word lines 15 in this etching step.
5 or the SiN films 21 and 22 are not etched and the film thickness is not reduced or the etching damage is not caused.

Next, as shown in FIG. 5D, again, for example, a P-doped doped polycrystalline silicon layer is thickly deposited on the entire surface, and then polished by CMP until the surface of the BPSG film 23 is exposed. Thus, the polycrystalline silicon plug 28 and the doped polycrystalline silicon layer deposited on the BPSG film 23 are removed to form the plug eaves portion 31.

Next, the P-SiO ₂ film 32 having a thickness of, for example, 100 nm is formed on the entire surface by using the plasma CVD method.
Then, a contact hole for the polycrystalline silicon plug 28 is formed in the contact portion 33 for the bit line, and the contact hole is filled with doped polycrystalline silicon to form the plug 34.

Then, the entire surface has a thickness of, for example, 20 n.
A Ti film of m, a TiN film having a thickness of, for example, 50 nm, and a W film having a thickness of, for example, 100 nm are sequentially deposited to form a Ti / TiN / W structure, and then a Si film is formed thereon.
An N film 36 is formed and etched into a line / space pattern to form a bit line 35 having a Ti / TiN / W structure connected to the n-type drain region 19. Then, after forming a SiN film on the entire surface, anisotropic etching is performed to form the sidewalls 37.

Referring to FIG. 6 (f '), the HDP (Hi Density Plasma)
a) Using the -CVD method, after depositing the SiO ₂ film 38, a contact hole for the polycrystalline silicon plug 27 is formed, and then, for example, a P-doped doped polycrystalline silicon layer is deposited on the entire surface. After that, CMP
The polycrystalline silicon plug 39 is formed by polishing the surface of the SiO ₂ film 38 by the method until it is exposed. In the step of forming this contact hole, the sidewall 37 provided on the side of the bit line 35 functions as a mask.

Next, low pressure chemical vapor deposition (LPCVD
Method) is used to form an LP-SiN film 40, which will serve as an etching stopper in the subsequent steps, with a thickness of, for example, 10 nm, and then the BP with a thickness of, for example, 1 μm is formed on the entire surface.
An SG film (not shown) is deposited.

Next, the BPSG film and the LP-SiN film 4
0 is sequentially etched to form a wide opening reaching the polycrystalline silicon plug 39, and then a P-doped doped polycrystalline silicon layer having a thickness of, for example, 50 nm is deposited on the entire surface, and then CMP is performed. Is used to remove the doped polycrystalline silicon layer deposited on the BPSG film to form a storage node 42 having a double-sided cylinder structure.

Then, the LP-SiN film 40 is used as an etching stopper to selectively remove the BPSG film with an HF aqueous solution, and then the surface of the storage node 40 is formed on the surface of the storage node 40 by using the LPCVD method, for example, at 700 ° C.
For example, a SiN film having a thickness of 5 nm is deposited to form a dielectric film of a capacitor, and then a doped polycrystalline silicon layer doped with P having a thickness of 100 nm, for example, is deposited on the entire surface to form a plurality of storages. The storage capacitor 41 is formed by forming the cell plate 43 common to the nodes 42.

In this case, in the etching process for forming the plug eaves portion 31, since the contact hole formed previously is filled with the polycrystalline silicon plug 28 in advance, even if there is some misalignment in the mask alignment, FIG.
As shown in (c '), the sidewalls and shoulders of the word lines 15 are covered with the polycrystalline silicon plugs 28. In this etching step, the sidewalls 25 or the SiN films 21 and 22 covering the word lines 15 are formed. Since it is not etched, the parasitic capacitance does not increase due to the decrease in the film thickness of the sidewall 25.

Reference is made to FIG. 7 (f ″) FIG. 7 (f ″) shows C- at the same time as FIG. 6 (f ′).
FIG. 6 is a cross-sectional view taken along the alternate long and short dash line connecting C ′, and since the bottom of the plug eaves portion 31 is located above the word line 15,
Sidewall 25 and SiN2 covering the word line 15
The parasitic capacitance can be reduced since the first and second parts 22 are not damaged by etching and the distance between the word line 15 and the plug eave portion 31 is increased.

Here, when the plug eaves portion 31 is formed,
A problem in the case where the contact hole is not previously filled with the polycrystalline silicon plug 28 will be described with reference to FIG. 8A, first, similarly to the steps up to FIG. 3A, after forming a contact hole reaching the n-type drain region 19, a resist is applied to the entire surface, and the eaves-shaped portion is exposed and developed. Pattern 5 having an opening for forming
1 is formed, and a contact hole 52 for forming an eave-shaped portion is formed using the resist pattern 51 as a mask.

At this time, as shown in FIG. 8B, since the side surfaces of the word lines 15 are exposed in this etching step, the exposed sidewalls 25 are etched to form the sidewalls 53 whose film thickness is reduced, In an extreme case, it may disappear and cause a short circuit.

Further, when the positional displacement of the mask alignment is large, the shoulder portion of the word line 15 is also exposed, so that the SiNs 21 and 22 covering the shoulder portion are damaged by etching and the insulating property is deteriorated.

However, in the first embodiment of the present invention, since the contact hole is previously filled with the polycrystalline silicon plug, the parasitic capacitance is increased or the short circuit is caused due to the reduction of the film thickness or the etching damage as described above. There is nothing to do.

Next, with reference to FIGS. 9 and 10, a process of manufacturing the DRAM of the second embodiment of the present invention will be described. Referring to FIG. 9A, the contact hole 26 reaching the n-type drain region 19 is formed using the resist pattern 24 in exactly the same manner as the first embodiment.

Next, referring to FIG. 9B, for example, a P-doped polycrystalline silicon layer 44 is thickly deposited on the entire surface to completely fill the contact hole 26 with the polycrystalline silicon layer 44.

Next, referring to FIG. 10C, a resist pattern 45 having an opening for forming a plug eave portion is provided, and this resist pattern 45 is provided.
First, the exposed portion of the polycrystalline silicon layer 44 is removed with the mask as a mask, and then the remaining reactive polycrystalline silicon layer 44 is used as a mask to carry out the reactive ion etching in the same manner as in the first embodiment described above. To form. In this case as well, the contact hole 46 is
The depth is such that its bottom is located above the word line 15.

Next, as shown in FIG. 10D, again, for example, a doped polycrystalline silicon layer doped with P is thickly deposited on the entire surface, and then polished by CMP until the surface of the BPSG film 23 is exposed. As a result, the polycrystalline silicon plug 47 and the plug overhang portion 48 surrounded by the BPSG film 23 are formed. After that, the DRAM including the storage capacitor is configured in exactly the same manner as the first embodiment.

As described above, also in the second embodiment of the present invention, the insulating film covering the shoulders and the side portions of the word lines is covered with the polycrystalline silicon layer in the second etching step. The film thickness is not reduced and etching damage is not caused. It should be noted that compared with the first embodiment described above, an etching process for the polycrystalline silicon layer is required, but the polishing process can be performed only once.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the respective embodiments, and various modifications can be made. For example, in the description of the above embodiment, the plug is formed of doped polycrystalline silicon. However, after the plug is filled with non-doped polycrystalline silicon, the conductivity determining impurity is introduced by ion implantation or thermal diffusion, and the conductivity is determined. It is also possible to impart the property.

Further, such a plug is not limited to polycrystalline silicon, and any material having a high selection ratio with respect to the insulating film to be removed by anisotropic etching may be used.

Although not particularly mentioned in the above-mentioned respective embodiments, in the step of forming the buried plug, after forming the contact hole, cleaning by hydrofluoric acid treatment or the like is performed, and then the contact hole is plugged. The material is embedded.

Further, in each of the above-mentioned embodiments, the plug eaves are formed with a half pitch offset with respect to the active region. However, the plug eaves need not necessarily have a half pitch, and may be formed in the direction along the word line. It suffices if it is displaced to a position where it can be connected to the bit line.

Further, in each of the above embodiments, the polycrystalline silicon plug connected to the drain region is formed and then the plug eaves portion is formed. However, after the plug eaves portion is formed, it is connected to the drain region. It is also possible to form a polycrystalline silicon plug which is used.

Further, in each of the above embodiments, the plug 32 is provided in the contact portion 33,
If the insulating film provided on the polycrystalline silicon plug 28 is thin or the contact hole is shallow, the plug may not be provided and the contact hole may be buried during the bit line deposition.

[0061]

According to the present invention, since the bit line contact plug is provided with the eaves-shaped extending portion, it is possible to reduce the parasitic capacitance between the bit line contact plug and the adjacent gate wiring. The signal delay can be prevented.

Further, when the eave-shaped lead-out portion is formed in order to reduce the parasitic capacitance, the contact hole is previously filled with the plug material. Therefore, in the step of forming the eave-shaped lead-out portion, the shoulder portion and the side of the gate wiring are formed. The insulating film that covers the portion is not damaged, which can prevent an increase in parasitic capacitance and a short circuit between the gate wiring and the plug, thus improving the integration degree and reliability of the high-integration semiconductor memory device. Greatly contributes to the improvement of.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of the DRAM according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process up to the middle of the DRAM according to the first embodiment of the present invention.

FIG. 4 is an explanatory view of the manufacturing process of the DRAM according to the first embodiment of the present invention up to the middle of FIG.

FIG. 5 is an explanatory diagram of the manufacturing process of the DRAM according to the first embodiment of the present invention up to the middle of FIG.

FIG. 6 is an explanatory diagram of the manufacturing process of the DRAM according to the first embodiment of the present invention after FIG. 5;

FIG. 7 is an explanatory diagram of the manufacturing process of the DRAM according to the first embodiment of the present invention after FIG. 5;

FIG. 8 is an explanatory diagram of a problem when a plug eave portion is not embedded with a plug when forming the eaves portion.

FIG. 9 is an explanatory diagram of a manufacturing process up to the middle of the DRAM according to the second embodiment of the present invention.

FIG. 10 is a diagram of a DRAM according to a second embodiment of the present invention.
It is explanatory drawing of the subsequent manufacturing processes.

FIG. 11 is an explanatory diagram of a drain contact lead-out structure of a conventional DRAM.

[Explanation of symbols]

1 bit line 2 contact electrode 3 eaves-shaped extension 4 active region 11 n-type silicon substrate 12 element isolation insulating film 13 p-type well region 14 gate insulating film 15 word line 16 Si gate electrode layer 17 WSi ₂ layer 18 SiN film 19 n Type drain region 20 n type source region 21 SiN film 22 SiN film 23 BPSG film 24 resist pattern 25 sidewall 26 contact hole 27 polycrystal silicon plug 28 polycrystal silicon plug 29 resist pattern 30 contact hole 31 plug eaves 32 P-SiO ₂ film 33 contact portion 34 plugs 35 bit lines 36 SiN film 37 sidewall 38 SiO ₂ film 39 of polycrystalline silicon plug 40 LT-SiN film 41 storage capacitor 42 the storage node 43 cell plate 44 of polycrystalline silicon layer 45 a resist pattern 46 contact hole 47 polycrystalline silicon plug 48 plug eaves portion 51 resist pattern 52 contact hole 53 sidewall 61 n-type silicon substrate 62 element isolation insulating film 63 p-type well region 64 word line 65 n-type drain region 66 n-type source region 67 SiN film 68 SiN film 69 BPSG film 70 Polycrystalline silicon plug 71 Polycrystalline silicon plug 72 P-SiO ₂ film 73 Contact part 74 Plug 75 Bit line 76 SiN film 77 Sidewall 78 Storage capacitor 79 Resist pattern

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Claims (5)

[Claims] 1. A contact electrode extending from the active region to an upper layer in a memory cell array region having a storage capacitor, at least a portion of which is located above the bit line, and which is displaced from the active region in a direction along a gate line. A semiconductor memory device, wherein an eaves-shaped drawer portion that is drawn out in an eaves-like shape is provided. 2. The semiconductor memory device according to claim 1, wherein a bottom surface of the eave-shaped lead-out portion is located above an upper surface of a conductive layer forming an adjacent gate wiring. 3. When forming the contact electrode and the eaves-shaped lead-out portion of the semiconductor memory device according to claim 1, using two types of mask patterns, one of the two types of mask patterns is used to form a recess. And then burying it with a contact electrode material, and then forming a recess using the other mask pattern and the contact electrode material as a mask. 4. The contact pattern is formed by first using the mask pattern for forming a contact electrode on the active region of the two types of mask patterns, and the contact groove is filled with a contact electrode material. And removing the upper portion of the contact electrode material, and then forming a recess for the eaves-shaped lead-out portion using the mask pattern for forming the eaves-shaped lead-out portion and the contact electrode material as a mask. Item 4. A method of manufacturing a semiconductor memory device according to item 3. 5. The contact electrode material in which the recess is filled is etched using a mask pattern for forming the eaves-shaped extension, and then the recess for the eaves-shaped extension is formed using only the contact electrode material as a mask. The method of manufacturing a semiconductor memory device according to claim 3, wherein