JP5033479B2 - Reading device - Google Patents

Description

  The present invention relates to a readout device that reduces the current flowing through a transfer transistor by adiabatically changing the gate voltage of the transfer transistor.

  FIG. 18 shows a case where an SRAM is taken as an example of a circuit configuration for reading the potential of a bit line that changes due to a current flowing through a conventional transfer transistor. A conventional SRAM circuit uses two CMOS inverters composed of a pMOS transistor and an nMOS transistor, and uses a flip-flop connecting the output terminal of one CMOS inverter to the other input terminal as a memory element. The output signal of each CMOS inverter is connected to the bit line via the transfer transistor of the nMOS transistor, and one memory cell has a total of six transistors.

  In addition, a sense amplifier for reading a minute electric signal and pMOSFETs (P31, P32) and nMOSFETs (N31, N32) that charge and discharge the bit lines at high speed are connected to the bit lines.

  In the conventional reading method, first, the bit line is charged to VDD, and then the word line WL is set to High to turn on the transfer transistor. Of the two output terminals of the flip-flop, the potential of the bit line connected to the terminal at the GND level is slightly lowered from VDD.

  On the other hand, the potential of the other bit line remains fixed at VDD. The potentials of these two bit lines are taken into the sense amplifier, and signals having a slight drop in potential from VDD and VDD are output as High and Low, respectively.

FIG. 19 shows a specific circuit configuration of the sense amplifier. EN is an abbreviation for ENABLE signal for operating the sense amplifier. When EN is Low, the transfer transistors P13 and P14 are turned on, and the input signal is captured. When EN is High, the transistor N13 is turned on and the input signal is latched in the flip-flop (see Non-Patent Document 1).
Low power LSI technology white paper Challenge to 1 milliwatt, Nikkei BP Nikkei Microdevices, 1994, p. 175

  However, according to the conventional technique, when the miniaturization further progresses and becomes 45 nm or less, the threshold voltage of the element varies, and in order to increase the operation speed, the statistically considered maximum threshold voltage is exceeded. When the power supply voltage is increased, a very large current flows in a memory cell having a small threshold voltage.

  In addition, for this reason, phenomena such as electromigration and hot carriers have occurred.

  An object of the present invention has been made in view of the above, and a reading device that can reduce the current flowing through a transfer transistor and can read the potential of a bit line without causing electromigration or hot carrier problems. Is to provide.

In order to solve the above-mentioned problem, the present invention according to claim 1 is characterized in that after a bit line is charged to a predetermined voltage using a pMOSFET connected to a power supply line, a transfer transistor connected to the bit line is turned on. In the reading device for reading out the change in the potential of the bit line, the change in the potential of the bit line at the gate voltage of the desired transfer transistor while changing the gate voltage of the transfer transistor more slowly than the time constant of the circuit a first control circuit for repeatedly operating the sense amplifier to read the order to the GND by using a nMOSFET to the potential of the bit line connected to GND after reading a decrease from a predetermined voltage of said bit line A second control circuit.

According to the second aspect of the present invention, the potential of the bit line is changed to GND using an nMOSFET connected to GND, the transfer transistor connected to the bit line is turned ON, and the change of the potential of the bit line is detected. In a reading device for reading , the sense amplifier is repeatedly operated to read the change in the potential of the bit line at the gate voltage of the desired transfer transistor while changing the gate voltage of the transfer transistor more slowly than the time constant of the circuit . comprising a first control circuit, and a second control circuit for a VDD using the pMOSFET the potential of the bit line connected to VDD after reading increased from GND of the bit lines.

According to a third aspect of the present invention, in the SRAM according to the first or second aspect , the bit line is set to a predetermined voltage and the gate voltage of the transfer transistor in the memory cell is gradually changed. Then, the sense amplifier is operated repeatedly in order to read the change in the potential of the bit line at the gate voltage of the desired transfer transistor.

According to a fourth aspect of the present invention, in the DRAM according to the first or second aspect , the bit line is set to a predetermined voltage and the gate voltage of the transfer transistor in the memory cell is gradually changed. Then, the sense amplifier is operated repeatedly in order to read the change in the potential of the bit line at the gate voltage of the desired transfer transistor.

According to a fifth aspect of the present invention, in the DRAM according to the first aspect , after the potential of the bit line is charged to VDD / 2, the transfer transistor connected to the bit line is turned on, and the bit line is turned on. In a circuit for reading out the change in the potential of the line , a sense amplifier is used to read out the change in the potential of the bit line at the gate voltage of the desired transfer transistor while changing the gate voltage of the transfer transistor more slowly than the time constant of the circuit. It was repeated operation, and GND with a nMOSFET to the potential of the bit line connected to GND after reading decrease from VDD / 2 of the bit line, after reading increased from VDD / 2 of the bit line using a pMOSFET the potential of the bit line connected to VDD And DD.

Further, the invention according to claim 6, in any one of claims 1 to 5, stepwise varying the gate voltage of the transfer transistor.

  According to the present invention, it is possible to provide a read device that can reduce the current flowing through the transfer transistor and can read the potential of the bit line without causing electromigration or hot carrier problems.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of an adiabatic readout SRAM according to the first embodiment of the present invention. The configuration of the adiabatic readout SRAM in this embodiment is such that the control circuit C1 that controls the voltage of the word line WL and the voltage of the bit line (bit line) in the desired voltage of the word line WL are read by the sense amplifier 1 It has a circuit for setting the potential of the bit line by the control circuit C2 based on the result.

  Here, the bit line is precharged to VDD first. In the sense amplifier 1, the bit line voltage and the reference voltage Vref are input. As Vref, a voltage of about VDD-50 mV is used. As the sense amplifier 1, for example, an existing circuit as shown in FIG. 19 can be used.

  In FIG. 1, the voltage of the word line WL can be switched to GND, 1/4 · VDD, 2/4 · VDD, 3/4 · VDD, and VDD by a switch SW. Which voltage is selected can be selected using the control circuit C1.

  In the following WL voltage shown in FIG. 2, a specific method for applying the voltage of the word line WL will be described. In the WL voltage in FIG. 2, Vth (BL1) represents the threshold voltage of the selected transfer transistor connected to the bit line BL1.

  First, it is assumed that the transfer transistor is connected to the terminal on the GND side of the flip-flop. In the WL voltage of FIG. 2, when the word line WL voltage is ¼ · VDD, the transfer transistor connected to the bit line BL1 is not turned on, but is turned on at 2/4 · VDD. Similarly, the transfer transistor connected to the bit line BL2 is not turned on at 2/4 · VDD but turned on at 3/4 · VDD.

  Now, if the transfer transistor is connected to the VDD side terminal of the flip-flop, both the source and drain of the transfer transistor become VDD, and the transfer transistor does not change even if the word line WL voltage is changed in the range of 0 to VDD. It will not be ON.

  As described above, the transfer transistor can be turned on when the transfer transistor is connected to the GND-side terminal of the flip-flop.

  2 indicates a timing at which the sense amplifier 1 outputs an ENABLE signal (EN signal) for performing sensing. The High signal of the first EN signal is output after the setting of the voltage of the word line WL to 1/4 · VDD is completed. The High signal of the second EN signal is output after the setting of the voltage of the word line WL to 2/4 · VDD is completed. The same applies hereinafter.

  Voltage (BL1) and voltage (BL2) in FIG. 2 indicate temporal changes in the voltages of the bit lines BL1 and BL2. Here, a case is considered where the data of BL1 and BL2 is Low and the data of NBL1 and NBL2 is High. Of course, BL1 and NBL2 may be Low, and NBL1 and BL2 may be High.

  First, the bit line BL1 will be described. At t0, the bit line BL1 is precharged to VDD using the pMOSFET (P31). Since the transfer transistor connected to the bit line BL1 is turned ON at 2/4 · VDD, the voltage of the bit line BL1 starts to gradually decrease at t = t1. At this time, the other bit line NBL1 to be paired keeps the potential of VDD. After the voltage drop of the bit line BL1 is sensed by the sense amplifier 1, the nMOSFET (N31) is turned ON using the control circuit C2, and the voltage of the bit line BL1 is set to GND. In the voltage (BL1) of FIG. 2, the bit line BL1 becomes GND at t = tp.

  Next, the bit line BL2 will be described. Since the transfer transistor connected to the bit line BL2 is turned ON at 3/4 · VDD, the voltage of the bit line BL2 gradually decreases at t = t2. After this voltage drop is sensed by the sense amplifier, the control circuit C2 is used to turn on the nMOSFET (N31) and set the voltage of the bit line BL2 to GND. In the voltage (BL2) of FIG. 2, the bit line BL2 becomes GND at t = tq.

  This method eliminates sudden application of VDD to the word line WL to cause a large current to flow through the transfer transistor. According to the present invention, the voltage flowing through the transfer transistor can be reduced by boosting the voltage of the word line WL adiabatically, in other words, stepwise while checking the potential of the bit line.

  Here, the word “insulation” will be explained. Adiabatic is used in physics when the system changes very slowly. Accordingly, “adiabatically boosting” means a method of charging more slowly than the time constant of the circuit.

  The method for controlling the voltage of the word line WL is not limited to the WL voltage method shown in FIG. 2, but may be a method such as WL voltage shown in FIG. That is, the voltage of the word line WL may be controlled by a method of 1/4 · VDD → GND → 2/4 · VDD → GND → 3/4 · VDD → GND → VDD.

  The EN voltage in FIG. 3 shows one example of the output timing of the EN signal at this time. After the EN signal changes from High to Low, the voltage of the word line WL is immediately set to GND. According to this method, since the voltage of the word line WL is changed to GND after sensing by the sense amplifier, the current flowing from the bit line to the memory cell through the transfer transistor can be immediately cut off, so that the current flows through the transfer transistor. The amount of current can be reduced, which can contribute to the improvement of electromigration problems. The advantage of this method is that as the time for extracting the bit line charges (Ta in FIG. 3) by the nMOSFET (N31) is set longer, that is, the adiabatic charges are gradually extracted by the nMOSFET (N31). It becomes more effective when

  The method of controlling the voltage of the word line WL may be performed so that the voltage of the word line WL is increased in proportion to time as in WL voltage of FIG. 4 indicates the output timing of the EN signal at this time.

  The method of controlling the voltage of the word line WL may be a method that changes greatly at the beginning like the WL voltage of FIG. 5 and does not change with the passage of time. Specifically, the WL voltage waveform of FIG. 5 is obtained by charging using a high-resistance transistor. The EN voltage in FIG. 5 shows the output waveform of the EN signal at this time. Initially, the EN signal is output so that it becomes fine high with respect to time, so that it is sensed finely, and it is outputted so that it is coarsely high near the final state, so that it is sensed roughly. As a result, when viewed in the vertical direction of WL voltage in FIG. 5, that is, the voltage of the word line WL, it is possible to perform sensing at substantially the same voltage interval of the word line WL.

  FIG. 6 shows a flowchart of the word line WL voltage control of FIG. First, the bit line is precharged to VDD (S1). Next, the parameter i is set to 0 (S2). Next, the voltage of the word line WL is set to i / N · V (S3).

  At first, since all the voltage of the bit lines is High, the voltages of all the bit lines are sensed. Next, when the drop of the bit line voltage is confirmed by the sense circuit, only the bit line is set to GND using the nMOSFET (N31). If the bit line voltage drop cannot be confirmed, nothing is done and the state is set to Wait State. Next, the information of each bit is stored in the memory circuit. Next, it is determined whether or not the parameter i matches N, and if it matches, the process ends. However, if it does not match, i = i + 1 is set, and the voltage of the word line WL is set to i / N · V again.

  Next, it is identified whether the voltage of the bit line stored last time is VDD or GND (S4). If the bit line voltage stored last time is VDD, the bit line voltage may drop, so the bit line voltage is sensed (S5). If the voltage of the bit line is GND, nothing is done and the state is set to Wait State. When the bit line voltage is sensed and the drop of the bit line voltage is confirmed by the sense circuit (S6), only the bit line is set to GND using the nMOSFET (N31) (S7). If no drop in the bit line voltage can be confirmed, nothing is performed and the state is set to Wait State (S8).

  Next, the information of each bit is stored in the memory circuit (S9). Next, it is determined whether or not the parameter i matches N (S10). If the parameter i matches, all bit line states are output to the outside (S12), and the process ends (S13). As i + 1, the voltage of the word line WL is set to i / N · V again (S11). This is repeated below.

Specifically, as a method of sensing the voltage of the bit line, in the sense circuit as described above, one of the two input voltages is set as a reference voltage, and the value of the reference voltage is set to VDD-50 mV. At this time, when the voltage of the bit line is larger than VDD-50 mV, the output of the sense circuit becomes VDD. When the voltage of the bit line is smaller than VDD-50 mV, the output of the sense circuit is GND. (FIG. 19 and Non-Patent Document 1)
[Second Embodiment]
FIG. 7 is a circuit diagram of an adiabatic readout SRAM in the second embodiment of the present invention. Unlike the already described first embodiment, the circuit configuration does not precharge the bit line. The configuration of the adiabatic readout SRAM in the present embodiment is based on the control circuit C1 that controls the voltage of the word line WL and the sense amplifier 2 that reads the voltage of the bit line at the desired voltage of the word line WL and based on the output result. It has a circuit for setting the potential of the bit line by the control circuit C2.

  In the read operation, first, the bit line is set to GND. In the sense amplifier 2, the bit line voltage and the reference voltage Vref are input. A voltage of about 50 mV is used as Vref. When the bit line voltage is higher than 50 mV, the output of the sense circuit is VDD. When the voltage of the bit line is smaller than 50 mV, the output of the sense circuit is GND.

  Next, a specific circuit configuration of the sense amplifier 2 is shown in FIG. Since the bit line is set to GND and the input voltage is close to the GND level, nMOS is used instead of pMOS as the transfer transistors (N23, N24).

  FIG. 9 shows a flowchart of a method that does not perform precharging. First, the bit line is set to GND (S20). Next, the parameter i is set to 0 (S21). Next, the voltage of the word line WL is set to i / N · V (S22). At first, since all the voltage of the bit lines is GND, the voltages of all the bit lines are sensed. Next, when an increase in the bit line voltage is confirmed by the sense circuit, only the bit line is set to VDD using the pMOSFET (P31). If the increase in the bit line voltage cannot be confirmed, nothing is done and the state is set to Wait State. Next, the information of each bit is stored in the memory circuit. Next, it is determined whether or not the parameter i matches N, and if it matches, the process ends. However, if it does not match, i = i + 1 is set, and the voltage of the word line WL is set to i / N · V again.

  Next, it is identified whether the bit line voltage stored last time is VDD or GND (S23). If the previously stored bit line voltage is GND, the bit line voltage may rise, so the bit line voltage is sensed (S24). If the voltage of the bit line is VDD, nothing is done and the state is set to Wait State. When the bit line voltage is sensed, if the rise of the bit line voltage is confirmed by the sense circuit (S25), only the bit line is set to VDD using the pMOSFET (P31) (S26).

  If the increase in the bit line voltage cannot be confirmed, nothing is performed and the state is set to Wait State (S27). Next, the information of each bit is stored in the memory circuit (S28). Next, it is determined whether or not the parameter i matches N (S29). If the parameter i matches, all bit line states are output to the outside (S31), and the process ends (S32). As i + 1, the voltage of the word line WL is set to i / N · V again (S30). This is repeated below.

  Further, the readout circuit of the present invention is not limited to SRAM, but can be applied to DRAM. FIG. 10 shows an application example of the present invention to a DRAM. The DRAM is composed of a bit line BL, a transfer transistor N40 connected to the bit line, and a capacitor connected to the transfer transistor N40 (see CMOS VLSI design, supervised by Takuo Kanno, edited by Tetsuya Iizuka, Bafukan 1989, p. 158). ).

  Data 1 and 0 are identified depending on whether or not electric charge is accumulated in the capacitor Cc. In the method of precharging the bit line BL to VDD, the transfer transistor N40 is turned on to connect the bit line BL and the capacitor Cc, and when charge is accumulated in the capacitor Cc, Although the potential does not change, the potential of the bit line BL decreases when no charge is accumulated in the capacitor Cc.

  This decrease in potential is detected by the sense amplifier 1. The sense amplifier 1 receives the potential of the bit line BL and Vref = VDD−50 mV. In this case, the present invention can be realized by stepwise boosting the gate voltage of the transfer transistor and reading the bit line while checking the voltage of the transfer transistor as shown in FIG.

  FIG. 11 shows another application example of the present invention to a DRAM. In FIG. 11, the bit line BL is precharged to VDD / 2 instead of VDD. As the input of the sense amplifier 1, the voltage of the bit line BL and the voltage Vref = VDD / 2 are used. When charge is accumulated in the capacitor Cc, the potential of the bit line BL becomes slightly higher than VDD / 2, and is latched by the sense amplifier 1 to output VDD. When no charge is accumulated in the capacitor Cc, the potential of the bit line BL becomes slightly lower than VDD / 2, and is latched by the sense amplifier 1 to output GND.

  Compared with the circuit of FIG. 10, the bit line can be charged by VDD / 2, so that the bit line can be charged with low power consumption.

  The read circuit of the present invention can also be applied to a flash memory. Here, the flash memory will be described. A flash memory is a nonvolatile memory element that has a control gate and a floating gate and can electrically erase memory cell blocks at once. Tunnel current or hot electrons are used for charge injection into the floating gate. In “write”, electrons are injected into the floating gate to set the threshold voltage to a high value, and in “erasure”, electrons are emitted from the floating gate to set the threshold voltage to a low value. Is called.

  Further, instead of using a floating gate type flash memory, a SONOS (silicon-oxide-nitride-oxide-silicon) type flash memory may be used. In this case, electrons are injected into localized levels in the gate insulating film, Alternatively, the threshold voltage may be set by performing drawing.

  FIG. 12 shows a specific NAND type memory circuit of a flash memory. In this NAND type, data is simultaneously read from and written to memory cells connected to about 4000 bit lines BL1 to BL4000. The memory cell block is composed of 4000 strings. The selection signal line SG1 and the selection signal line SG2 are connected to the gates of the selection transistors T1 and T2 of each string, and the gates (controls) of the memory cells M1 to M4 of each string. Word lines WL1 to WL4 are connected to the gate. The “string” indicates a series connection circuit of the selection transistor T1, the selection transistor T2, and the memory cells M1 to M4.

  FIG. 13 shows a distribution of threshold voltages set in a normal binary memory cell. When the voltage of the word line WL is 0 V, if the threshold voltage is “1”, that is, the erase state, a current flows through the memory cell, and if it is “0”, that is, the write state, no current flows. Thus, the threshold voltage of “1” and “0” of the memory cell is determined depending on whether or not current flows. Therefore, one memory cell in this case stores 1-bit data.

  FIG. 14 shows a distribution of quaternary threshold voltages in which 2-bit data is stored in one memory cell. Here, the four peaks correspond to four threshold voltage distributions of data “11”, “10”, “01”, “00”. In these states, the threshold voltage is determined depending on whether or not a current flows with the voltage of the word line WL set to the position shown by the arrow in FIG.

  In terms of circuit, for example, in FIG. 12, in order to determine whether or not a current flows in the transistor M2, the word line is set so that the transistors T1, M1, M3, M4, and T2 are all turned on. The voltage of WL is set to VCC. Accordingly, if a current flows in the transistor M2, the potential of the bit line drops.

  In the contents shown in FIGS. 13 and 14 as well, the word line WL voltage is set only in the valley of the threshold voltage distribution. In the present invention, the voltage of the word line WL is divided more finely than the contents shown in FIG. 13 and FIG. 14, and the peak portion of the threshold voltage distribution is also set to determine whether or not current flows. .

  FIG. 15 shows an embodiment of the present invention in the case of binary memory cells. The voltage of the word line WL is set to VA1, VA2, and VA3. First, the voltage of the word line WL is set to VA1, and then set to VA2 and VA3. Consider a case where a bit line is precharged to a certain voltage. When the voltage of the word line WL is set to VA1, only a transistor having a threshold voltage in the region e1 flows and a voltage drop of the bit line occurs. This is detected by a sense amplifier, and the potential of the bit line is set to GND.

  Next, when the voltage of the word line WL is set to VA2, only a transistor having a threshold voltage in the region e2 flows and a voltage drop of the bit line occurs. Regarding the transistor having the threshold voltage in the region e1, since the potential of the bit line was set to GND last time, the transistor is turned on, but since the source and the drain are both GND, no current flows.

  Next, assuming that the voltage of the word line WL is VA3, only a transistor having a threshold voltage in the region e3 flows and a voltage drop of the bit line occurs. Regarding the transistors having threshold voltages in the regions e1 and e2, since the potential of the bit line has been set to GND until the previous time, the transistor is ON, but the current does not flow because both the source and the drain are GND. .

  With this method, the voltage of the word line WL is boosted while checking the potential of the bit line, in other words, the value of the threshold voltage, so that the current flowing through the string transistor can be reduced. Can solve migration problems.

  FIG. 16 shows an embodiment of the present invention in the case of a quaternary memory cell. The voltage of the word line WL is set to VB1 to VB7. Thereby, as in FIG. 2, the word line WL voltage is changed stepwise to identify whether electrons flow. When current flows, charge is extracted from the bit line using the nMOSFET (N31) of FIG. Therefore, thereafter, in the case shown in FIG. 12, no current flows from the bit line in the direction of T1, M1, M2, M3, M4, T2, and GND, the amount of current can be reduced, and the electromigration problem can be solved.

  The specific operation method is the same as that of the binary memory cell. Consider a case where a bit line is precharged to a certain voltage. When the voltage of the word line WL is set to VB1, only a transistor having a threshold value in the region f1 flows current and a voltage drop of the bit line occurs. This is detected by a sense amplifier, and the potential of the bit line is set to GND. Next, when the voltage of the word line WL is set to VB2, only a transistor having a threshold value in the region f2 flows and a voltage drop of the bit line occurs. As for the transistor having a threshold value in the region f1, since the potential of the bit line was set to GND last time, the transistor is turned on, but since the source and the drain are both GND, no current flows. Thereafter, the above operation is repeated as in the case of the binary memory cell to boost the word line WL voltage.

  Needless to say, the method of setting the word line WL voltage is not limited to the contents shown in FIGS. For example, in FIG. 15, the word line WL voltages VA1 and VA3 are set in the central portion of the states of “1” and “0”, but the regions of “1” and “0” are further refined as shown in FIG. The word line WL voltage may be set.

  With the method of FIG. 17, a more adiabatic read operation can be performed, and the problems of electromigration and hot carrier can be solved.

It is a circuit diagram of the heat insulation read-out memory of 1st Embodiment. It is a figure which shows the time change of the voltage of a word line, the timing of the ENABLE signal of a sense amplifier, and the time change of the voltage of bit lines BL1 and BL2. It is a figure which shows another time change of the voltage of a word line, and the timing of the ENABLE signal of a sense amplifier. It is a figure which shows another time change of the voltage of a word line, and the timing of the ENABLE signal of a sense amplifier. It is a figure which shows another time change of the voltage of a word line, and the timing of the ENABLE signal of a sense amplifier. It is a figure which shows the flowchart of 1st Embodiment. It is a circuit diagram of the heat insulation read-out memory of 2nd Embodiment. It is a figure which shows the sense amplifier used for 2nd Embodiment. It is a figure which shows the flowchart of 2nd Embodiment. FIG. 3 is a diagram showing a circuit when the present invention is applied to a DRAM and a precharge voltage is set to VDD. It is a figure which shows a circuit when the present invention is applied to DRAM and the precharge voltage is set to VDD / 2. It is a figure which shows the circuit which applied this invention to flash memory. It is a figure which shows threshold voltage distribution of 1 cell 1 bit of flash memory. It is a figure which shows the threshold voltage distribution of 1 cell 2 bits of a flash memory. In FIG. 13, it is a figure which shows the case where the voltage of a word line is set to VA1, VA2, VA3 using this invention. In FIG. 14, it is a figure which shows the case where the voltage of a word line is set to VB1, VB2, VB3, VB4, VB5, VB6, VB7 using this invention. In FIG. 13, it is a figure which shows the case where the voltage of a word line is set to VA1, VA2, VA3, VA4, VA5, VA6, VA7 using this invention. It is a figure which shows the read-out circuit of the conventional SRAM. It is a figure which shows the conventional sense amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Sense amplifier C1, C2 ... Control circuit Cell ... Cell BL, NBL ... Bit line FF ... Flip-flop circuit WL ... Word line SW ... Switch P1, P2, P31, P32 ... pMOS transistors N1-N4, N31, N32 , N40... NMOS transistors P11 to P14... PMOS transistors N11 to N13... NMOS transistors P21 to P22... PMOS transistors N21 to N25. CMOS inverter circuit Vref ... reference voltage VDD, VCC ... power supply voltage GND ... ground voltage IN, A, B ... input signal OUT ... output signal EN ... ENABLE signal Vth (BL1), Vth (BL2) ... threshold voltage Ta Time Wait state ... wait state to the word line voltage and GND

Claims (6)

In a reading device for reading a change in potential of the bit line by charging a bit line to a predetermined voltage using a pMOSFET connected to a power supply line and then turning on a transfer transistor connected to the bit line.
A first control circuit that repeatedly operates a sense amplifier to read a change in the potential of the bit line at a desired gate voltage of the transfer transistor while changing the gate voltage of the transfer transistor more slowly than a time constant of the circuit;
A second control circuit for a GND by using a nMOSFET to the potential of the bit line connected to GND after reading a decrease from a predetermined voltage of said bit line,
A reading device comprising: In a reading device for setting a bit line potential to GND using an nMOSFET connected to GND, turning on a transfer transistor connected to the bit line, and reading a change in the potential of the bit line,
A first control circuit that repeatedly operates a sense amplifier to read a change in the potential of the bit line at a desired gate voltage of the transfer transistor while changing the gate voltage of the transfer transistor more slowly than a time constant of the circuit;
A second control circuit for a VDD using the pMOSFET the potential of the bit line connected to VDD after reading increased from GND of the bit lines,
A reading device comprising: In SRAM, in order to read the change in the potential of the bit line at the desired gate voltage of the transfer transistor while setting the bit line to a predetermined voltage and gradually changing the gate voltage of the transfer transistor in the memory cell reading device according to claim 1 or 2, characterized in that repeatedly operate the sense amplifier. In DRAM, the bit line is set to a predetermined voltage, while gradually changing the gate voltage of the transfer transistor in the memory cell, to read the change in the potential of the bit line in the gate voltage of the desired transfer transistor reading device according to claim 1 or 2, characterized in that repeatedly operate the sense amplifier. In a DRAM, after charging the potential of the bit line to VDD / 2, turning on the transfer transistor connected to the bit line, and reading a change in the potential of the bit line,
While the gate voltage of the transfer transistor is changed more slowly than the time constant of the circuit , the sense amplifier is repeatedly operated to read the change in the potential of the bit line at the gate voltage of the desired transfer transistor,
And GND with a nMOSFET to the potential of the bit line connected to GND after reading decrease from VDD / 2 of the bit line,
Reading device according to claim 1, characterized in that the VDD using the pMOSFET the potential of the bit line connected to VDD after reading increased from VDD / 2 of the bit line. Reading device according to any one of claims 1 to 5, characterized in that stepwise changes the gate voltage of the transfer transistor.

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