JP5030656B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device for manufacturing a semiconductor memory device that stores information of 2 bits per field effect transistor.

Conventionally, as a non-volatile memory capable of storing 2-bit information with a single field effect transistor, there is a memory developed by Cyphan Semiconductors Limited (for example, Japanese Patent Application Laid-Open No. 2001-512290). reference.). As shown in FIG. 16, the memory includes a gate insulating film 904, 905, 906 having a three-layer structure formed on a P-type well region 901, a gate electrode 909 formed on the gate insulating film, The first N type diffusion layer region 902 and the second N type diffusion layer region 903 formed on the surface of the P type well region 901 are configured. The gate insulating film is a so-called ONO (Oxide Nitride Oxide) film in which a silicon nitride film 906 is sandwiched between silicon oxide films 904 and 905. In the silicon nitride film 906, memory holding portions 907 and 908 are formed near the ends of the first and second N-type diffusion layer regions 902 and 903, respectively. In operation, a predetermined voltage is applied to the P-type well region 901, the gate electrode 909, the first N-type diffusion layer region 902, and the second N-type diffusion layer region 903 to charge the memory holding portions 907 and 908, respectively. Information is written (or erased) by injecting (or extracting) and drain current (current between the regions 902 and 903) is detected in accordance with the amount of charge held in the respective memory holding portions 907 and 908. To read the information. In this way, 2 bits of information can be stored per field effect transistor.
JP-T-2001-512290

  However, in the above memory, since the gate insulating film has a three-layer structure (ONO film), there is a problem that it is difficult to reduce the thickness and it is difficult to miniaturize the element. That is, scaling with respect to the thickness of the gate insulating film is difficult, and an increase in the short channel effect is caused, thereby preventing miniaturization of the element. Further, as the channel length becomes shorter, it becomes difficult to separate the two memory storage portions 907 and 908 of one transistor, which prevents the element from being miniaturized.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device manufacturing method for manufacturing a semiconductor memory device that can store information of 2 bits per field effect transistor and can be easily miniaturized.

In order to solve the above problems, the present invention is a method of manufacturing a semiconductor memory device for manufacturing a semiconductor memory device,
The semiconductor memory device is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material, or crystal structure, and the nanodot is connected to the gate of the interface between the second insulator and the third insulator. Formed in a self-aligned manner in a plane substantially parallel to the surface of the insulating film,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. And
The above manufacturing method is
Forming the gate insulating film made of a silicon oxynitride film on the semiconductor substrate;
Forming the gate electrode having a substantially rectangular cross section on the gate insulating film;
A silicon oxide film serving as a material for the second insulator so as to cover the gate electrode and the semiconductor substrate corresponding to both sides of the gate electrode with a thickness reflecting the cross-sectional shape of the gate electrode on the surface side Forming by CVD or deposition by thermal oxidation,
Depositing a silicon nitride film as a material of the third insulator by a CVD method so as to cover the silicon oxide film with a thickness reflecting the cross-sectional shape of the gate electrode on the surface side;
Depositing a sacrificial silicon oxide film by a CVD method so as to cover the silicon nitride film at a thickness that fills the corners formed by the L-shaped cross section of the silicon nitride film on both sides of the gate electrode;
Etch back by anisotropic etching is performed to form a silicon oxide film serving as the second insulator material on both sides of the gate electrode and a silicon nitride film serving as the third insulator material in an L-shaped cross section. Forming a sidewall spacer on both sides of the gate electrode, leaving the sacrificial silicon oxide film at a corner portion formed by an L-shaped cross section of the silicon nitride film;
Ion implantation using the gate electrode and sidewall spacer as a mask to form the two diffusion layer regions laterally separated from the gate electrode,
Removing the sacrificial silicon oxide film forming the sidewall spacer by anisotropic etching under an etching condition in which the etching rate of the silicon nitride film is lower than the etching rate of the silicon oxide film, and exposing each of the silicon nitride films; ,
Introducing the first material to be the nanodot through each silicon nitride film by ion implantation;
And performing a heat treatment to form nanodots made of the first material.

According to the method for manufacturing a semiconductor memory device of the present invention, the semiconductor memory device of each aspect described below can be manufactured using a manufacturing apparatus used in a normal semiconductor process.

The semiconductor memory device of the first aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material, or crystal structure, and the nanodot is connected to the gate of the interface between the second insulator and the third insulator. Formed in a self-aligned manner in a plane substantially parallel to the surface of the insulating film,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. It is characterized by becoming.

  In the semiconductor memory device according to the first aspect, each of the two charge holding portions is formed laterally separated from the gate electrode, and is separated from the gate insulating film. Therefore, the memory function performed by the charge holding portion and the transistor operation function performed by the gate insulating film are separated. Therefore, it is easy to reduce the short channel effect by thinning the gate insulating film while having a sufficient memory function. In addition, since the two charge holding portions are formed on the opposite sides of the gate electrode, the interference between the two charge holding portions is effectively suppressed during rewriting. In other words, the distance between the two charge holding units can be reduced. Therefore, a semiconductor memory device capable of 2-bit operation and easy to be miniaturized is provided.

  Further, a nanodot made of a first material having a function of accumulating charges is sandwiched between a second insulator and a third insulator. Therefore, at the time of charge injection, the charge density in the first material can be increased and the charge density can be made uniform in a short time.

  The second insulator and the third insulator are different in material or crystal structure, and the second insulator and the third insulator have an interface. Accordingly, the nanodots can be formed on the interface in a self-aligning manner. In this semiconductor memory device, the nanodots are formed in a self-aligned manner in a plane substantially parallel to the surface of the gate insulating film in the interface between the second insulator and the third insulator. Has been.

  Further, since the nanodot is separated from the conductor portion (gate electrode, diffusion layer region, semiconductor substrate) by the second insulator, charge leakage is suppressed and sufficient holding time can be obtained. . Therefore, it is possible to rewrite the semiconductor memory device at high speed, improve reliability, and secure a sufficient holding time.

In the semiconductor memory device of one embodiment,
The first material is a metal or a semiconductor;
The second insulator is made of a silicon thermal oxide film,
The third insulator is made of a silicon oxide film deposited chemically or physically.

  In the semiconductor memory device of this embodiment, the first material forming the nanodot is a metal or a semiconductor and has a number of levels for trapping charges (electrons or holes). As a result, a large hysteresis characteristic can be obtained. Further, since the second insulator is made of a silicon thermal oxide film and the third insulator is made of a silicon oxide film deposited chemically or physically, the second insulator becomes a third insulator. The density is higher than that. Therefore, even if atoms that form nanodots try to diffuse through the second insulator, it is possible to effectively prevent the atoms from reaching the semiconductor substrate.

In the semiconductor memory device of one embodiment,
The first material is a metal or a semiconductor;
The second insulator is made of a silicon thermal oxide film,
The third insulator is made of a silicon nitride film.

  In the semiconductor memory device of this embodiment, since the third insulator is made of a silicon nitride film, the dielectric constant of the third insulator can be increased.

In the semiconductor memory device of one embodiment,
A thickness of a portion of the second insulator that separates the semiconductor substrate and the nanodot is 1.5 nm or more and 15 nm or less.

  In the semiconductor memory device according to this embodiment, it is possible to sufficiently inject charges into the nanodots while suppressing leakage of charges accumulated in the nanodots. Therefore, a semiconductor memory device that provides both a high-speed rewrite operation and a sufficient holding time is provided.

In the semiconductor memory device of one embodiment,
The size of the nanodot is 0.1 nm or more and 10 nm or less.

  In the semiconductor memory device according to this embodiment, the variation in the threshold value (or the change in read current) in the semiconductor memory device can be sufficient to suppress the variation between elements. In addition, it is possible to suppress a change in threshold value (or read current) due to charge transfer from the nanodots that are being stored.

In the semiconductor memory device of one embodiment,
The second insulator includes a film having an L-shaped cross section along the surface of the semiconductor substrate and the side wall of the gate electrode.
A thickness of a portion along the side wall of the gate electrode in the second insulator is smaller than a thickness of a portion along the surface of the semiconductor substrate.

  In the semiconductor memory device according to this embodiment, the thickness of the portion of the second insulator along the side wall of the gate electrode is smaller than the thickness of the portion along the surface of the semiconductor substrate. The injection of charge into the nanodot (or release of charge from the nanodot into the gate electrode) can be effectively suppressed. Therefore, a memory operation can be performed without exchanging charges between the semiconductor substrate and the nanodot. Therefore, it is possible to suppress the deterioration of the insulating film provided along the surface of the semiconductor substrate. Therefore, the rewrite characteristics of the semiconductor memory device are stabilized and the reliability is improved.

In the semiconductor memory device of one embodiment,
A plurality of the nanodots are provided on both sides of the gate electrode along the surface of the semiconductor substrate,
On both sides of the gate electrode, at least a part of the nanodot is formed so as to overlap a part of the diffusion layer region on the gate electrode side.

  In the semiconductor memory device of this embodiment, the read operation speed can be increased.

In the semiconductor memory device of one embodiment,
A plurality of the nanodots are provided on both sides of the gate electrode along the surface of the semiconductor substrate,
On both sides of the gate electrode, at least one set of the nanodots is arranged along a plane substantially parallel to the surface of the gate insulating film.

  In the semiconductor memory device of this embodiment, the memory effect according to the amount of charges accumulated in the nanodot can be effectively controlled, and the memory effect can be increased. Furthermore, the movement of charges in the upward direction of the nanodots is suppressed, and it is possible to suppress a change in characteristics due to the charge movement during storage.

The semiconductor memory device of the second aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material or crystal structure,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. And
The energy difference between the vacuum level in the first material and the lowest level of the conduction electron band is χ1, and the energy difference between the vacuum level in the second insulator and the lowest level of the conduction electron band is χ2. When the energy difference between the vacuum level and the lowest level of the conduction electron band in the third insulator is χ3, χ1> χ2 and χ1> χ3.

  The semiconductor memory device according to the second aspect can provide the same effects as the semiconductor memory device according to the first aspect. Furthermore, the electron affinity of the first material is greater than the electron affinity of the second and third insulators. Therefore, when the accumulated charge is an electron, the dissipation of the charge from the nanodot made of the first material is effectively suppressed, and the memory retention time becomes long. Furthermore, the efficiency of charge injection into the nanodot is increased, and the rewriting time is shortened. Therefore, the rewrite time of the semiconductor memory device can be shortened and high-speed operation can be realized.

The semiconductor memory device of the third aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material or crystal structure,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. And
The energy difference between the vacuum level and the highest level of the valence band in the first material is φ1, and the energy difference between the vacuum level and the highest level of the valence band in the second insulator is φ2. When the energy difference between the vacuum level and the highest level of the valence band in the third insulator is φ3, φ1 <φ2 and φ1 <φ3.

  The semiconductor memory device according to the third aspect can also provide the same operational effects as those of the semiconductor memory device according to the first aspect. Furthermore, the energy difference between the vacuum level in the first material and the highest level of the valence band is the energy between the vacuum level and the highest level of the valence band in the second and third insulators. Smaller than the difference. Therefore, when the accumulated charge is a hole, the dissipation of the charge from the nanodot is effectively suppressed, and the memory retention time is increased. Furthermore, the efficiency of charge injection into the nanodot is increased, and the rewriting time is shortened. Therefore, the rewrite time of the semiconductor memory device can be shortened and high-speed operation can be realized.

The semiconductor memory device of the fourth aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material or crystal structure,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. And
The energy difference between the vacuum level in the first material and the lowest level of the conduction electron band is χ1, and the energy difference between the vacuum level in the second insulator and the lowest level of the conduction electron band is χ2. The energy difference between the vacuum level of the third insulator and the lowest level of the conduction electron band is χ3, and the energy difference between the vacuum level of the first material and the highest level of the valence band is φ1 And the energy difference between the vacuum level and the highest level of the valence band in the second insulator is φ2, and the energy difference between the vacuum level and the highest level of the valence band in the third insulator Is characterized by satisfying all of χ1> χ2, χ1> χ3, φ1 <φ2, and φ1 <φ3.

  The semiconductor memory device according to the fourth aspect can also provide the same operational effects as the semiconductor memory device according to the first aspect. Furthermore, the electron affinity of the first material is larger than the electron affinity of the second and third insulators, and the vacuum level and the highest level of the valence band in the first material are The energy difference is smaller than the energy difference between the vacuum level and the highest level of the valence band in the second and third insulators. Therefore, both the electron injection efficiency and the hole injection efficiency are increased. For example, when writing electrons into the nanodots at the time of writing and injecting holes into the nanodots at the time of erasing to recombine with the accumulated electrons (even if the electrons and holes are exchanged), both writing and erasing operations are performed. The speed can be increased.

The semiconductor memory device of the fifth aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The first material is a metal or a semiconductor;
The second insulator is made of a silicon thermal oxide film,
The third insulator comprises a silicon oxide film deposited chemically or physically,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. It is characterized by becoming.

  In the semiconductor memory device according to the fifth aspect, the two charge holding portions are respectively formed laterally separated from the gate electrode and separated from the gate insulating film. Therefore, the memory function performed by the charge holding portion and the transistor operation function performed by the gate insulating film are separated. Therefore, it is easy to reduce the short channel effect by thinning the gate insulating film while having a sufficient memory function. In addition, since the two charge holding portions are formed on the opposite sides of the gate electrode, the interference between the two charge holding portions is effectively suppressed during rewriting. In other words, the distance between the two charge holding units can be reduced. Therefore, a semiconductor memory device capable of 2-bit operation and easy to be miniaturized is provided.

  Further, a nanodot made of a first material having a function of accumulating charges is sandwiched between a second insulator and a third insulator. Therefore, at the time of charge injection, the charge density in the first material can be increased and the charge density can be made uniform in a short time.

  Further, since the nanodot is separated from the conductor portion (gate electrode, diffusion layer region, semiconductor substrate) by the second insulator, charge leakage is suppressed and sufficient holding time can be obtained. . Therefore, it is possible to rewrite the semiconductor memory device at high speed, improve reliability, and secure a sufficient holding time.

  Moreover, the first material forming the nanodot is a metal or a semiconductor, and has many levels for trapping charges (electrons or holes). As a result, a large hysteresis characteristic can be obtained. Further, since the second insulator is made of a silicon thermal oxide film and the third insulator is made of a silicon oxide film deposited chemically or physically, the second insulator becomes a third insulator. The density is higher than that. Therefore, even if atoms that form nanodots try to diffuse through the second insulator, it is possible to effectively prevent the atoms from reaching the semiconductor substrate.

  In addition, since the second and third insulators are silicon oxide films, the electron affinity of the first material is larger than the electron affinity of the second and third insulators, and the first material The energy difference between the vacuum level in the material and the highest level of the valence band is smaller than the energy difference between the vacuum level and the highest level of the valence band in the second and third insulators. Therefore, both the write operation and the erase operation can be speeded up. Furthermore, since the silicon oxide film and the metal or semiconductor or silicon nitride are both materials used in the LSI process, the manufacturing process is simplified.

  In one embodiment of the semiconductor memory device, a thickness of a portion of the second insulator that separates the semiconductor substrate and the nanodot is 1.5 nm or more and 15 nm or less.

  In the semiconductor memory device according to this embodiment, it is possible to sufficiently inject charges into the nanodots while suppressing leakage of charges accumulated in the nanodots. Therefore, a semiconductor memory device that provides both a high-speed rewrite operation and a sufficient holding time is provided.

  In one embodiment, the size of the nanodot is 2 nm or more and 15 nm or less, more preferably 0.1 nm or more and 10 nm or less.

  In the semiconductor memory device according to this embodiment, the variation in the threshold value (or the change in read current) in the semiconductor memory device can be sufficient to suppress the variation between elements. In addition, it is possible to suppress a change in threshold value (or read current) due to charge transfer from the nanodots that are being stored.

The semiconductor memory device of the sixth aspect is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator includes a film having an L-shaped cross section along the surface of the semiconductor substrate and the side wall of the gate electrode.
Of the second insulator, the thickness of the portion along the side wall of the gate electrode is thinner than the thickness of the portion along the surface of the semiconductor substrate,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. It is characterized by becoming.

  In the semiconductor memory device according to the sixth aspect, the two charge holding portions are formed laterally separated from the gate electrode, and are separated from the gate insulating film. Therefore, the memory function performed by the charge holding portion and the transistor operation function performed by the gate insulating film are separated. Therefore, it is easy to reduce the short channel effect by thinning the gate insulating film while having a sufficient memory function. In addition, since the two charge holding portions are formed on the opposite sides of the gate electrode, the interference between the two charge holding portions is effectively suppressed during rewriting. In other words, the distance between the two charge holding units can be reduced. Therefore, a semiconductor memory device capable of 2-bit operation and easy to be miniaturized is provided.

  Further, a nanodot made of a first material having a function of accumulating charges is sandwiched between a second insulator and a third insulator. Therefore, at the time of charge injection, the charge density in the first material can be increased and the charge density can be made uniform in a short time.

  Further, since the nanodot is separated from the conductor portion (gate electrode, diffusion layer region, semiconductor substrate) by the second insulator, charge leakage is suppressed and sufficient holding time can be obtained. . Therefore, it is possible to rewrite the semiconductor memory device at high speed, improve reliability, and secure a sufficient holding time.

  In addition, since the thickness of the portion of the second insulator along the side wall of the gate electrode is thinner than the thickness of the portion along the surface of the semiconductor substrate, charge injection from the gate electrode to the nanodots is performed. (Or release of charges from the nanodots to the gate electrode) can be performed. Therefore, a memory operation can be performed without exchanging charges between the semiconductor substrate and the nanodot. Therefore, it is possible to suppress the deterioration of the insulating film provided along the surface of the semiconductor substrate. Therefore, the rewrite characteristics of the semiconductor memory device are stabilized and the reliability is improved.

  In one embodiment, the thickness of the second insulator along the surface of the semiconductor substrate is thinner than the gate insulating film and 0.8 nm or more. Features.

  According to the semiconductor memory device of this embodiment, it is possible to maintain a certain level of uniformity and film quality by the manufacturing process. In addition, the voltage of the write operation and the erase operation can be reduced without reducing the withstand voltage performance of the memory whose retention characteristics are not extremely deteriorated. Alternatively, it is possible to increase the memory effect by speeding up the write operation and the erase operation.

  In one embodiment of the semiconductor memory device, the thickness of a portion of the second insulator along the surface of the semiconductor substrate is greater than the thickness of the gate insulating film and not more than 20 nm. To do.

  According to the semiconductor memory device of this embodiment, it is possible to improve the retention characteristics without significantly reducing the rewrite speed and without deteriorating the short channel effect of the memory.

In the semiconductor memory device of one embodiment,
A plurality of the nanodots are provided on both sides of the gate electrode along the surface of the semiconductor substrate,
On both sides of the gate electrode, at least a part of the nanodot is formed so as to overlap a part of the diffusion layer region on the gate electrode side.

  In the semiconductor memory device of this embodiment, the read operation speed can be increased.

In the semiconductor memory device of one embodiment,
A plurality of the nanodots are provided on both sides of the gate electrode along the surface of the semiconductor substrate,
On both sides of the gate electrode, at least one set of the nanodots is arranged along a plane substantially parallel to the surface of the gate insulating film.

  In the semiconductor memory device of this embodiment, the memory effect according to the amount of charges accumulated in the nanodot can be effectively controlled, and the memory effect can be increased. Furthermore, the movement of charges in the upward direction of the nanodots is suppressed, and it is possible to suppress a change in characteristics due to the charge movement during storage.

Thus , according to the method for manufacturing a semiconductor memory device of the present invention, the semiconductor memory device according to each aspect described above can be manufactured using a manufacturing apparatus used in a normal semiconductor process.

In one embodiment of a method of manufacturing a semiconductor memory device,
The method includes the step of introducing the first material to be the nanodots through the silicon nitride films and then removing the silicon nitride films to deposit a silicon oxide film to be an interlayer insulating film.

  According to the method of manufacturing a semiconductor memory device of this embodiment, the nitride film that has been subjected to the implantation damage can be removed.

In the semiconductor memory device of one embodiment,
In the step of forming the nanodots by performing the heat treatment, the heat treatment is performed in an atmosphere containing oxygen.

  According to the semiconductor memory device manufacturing method of this embodiment, oxygen vacancies can be reduced.

  Hereinafter, the present invention will be described in detail by embodiments.

The semiconductor memory device manufactured by the manufacturing method of the present invention mainly includes a gate insulating film, a gate electrode formed on the gate insulating film, and two charges formed laterally apart on both sides of the gate electrode. The holding unit, source / drain regions (diffusion layer regions), and a channel region disposed under the gate electrode.

  This semiconductor memory device functions as a memory element that stores four or more information by storing binary or more information in one charge holding portion.

The semiconductor memory device manufactured by the manufacturing method of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type well region formed in the semiconductor substrate.

  The semiconductor substrate is not particularly limited as long as it is used in a semiconductor device. For example, a substrate made of an elemental semiconductor such as silicon or germanium, a compound semiconductor such as GaAs, InGaAs, or ZnSe, an SOI substrate, or a multilayer SOI. Various substrates such as a substrate can be used. Among these, a silicon substrate or an SOI substrate on which a silicon layer is formed as a surface semiconductor layer is preferable. An element isolation region is preferably formed on this semiconductor substrate, and further, elements such as transistors, capacitors, resistors, etc., circuits using these, semiconductor devices, and interlayer insulating films are combined to form a single or multi-layer structure. It may be formed. The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and at least one first conductivity type (P-type or N-type) well region is preferably formed in the semiconductor substrate. . The impurity concentration in the semiconductor substrate and well region can be within the range known in the art. When an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, but a body region may be provided under the channel region.

  The gate insulating film is not particularly limited as long as it is normally used in a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, or a tantalum oxide film. A single-layer film or a laminated film of a high dielectric film such as a hafnium oxide film can be used. Of these, a silicon oxide film is preferable.

  The gate electrode is formed on the gate insulating film in a shape that is usually used in a semiconductor device. The gate electrode is not particularly limited unless otherwise specified in the embodiment. The conductive film, for example, polysilicon: metal such as copper and aluminum: refractory metal such as tungsten, titanium and tantalum: high Examples thereof include a single layer film or a laminated film such as silicide with a melting point metal. The gate electrode is suitably formed to a thickness of about 50 nm to 400 nm, for example. Note that a channel region is formed under the gate electrode, but the channel region may be formed not only under the gate electrode but also under the region including the gate electrode and the outside of the gate end in the gate length direction. preferable. Thus, when there is a channel region that is not covered with the gate electrode, the channel region is preferably covered with a gate insulating film or a charge holding portion described later.

  The charge holding unit preferably has a sandwich structure in which nanodots made of a first material that accumulates charges are sandwiched between a film made of a second insulator and a film made of a third insulator. Since the first material for accumulating charges is a nanodot, the charge density in the first material can be increased in a short time by injecting charges, and the amount of charge required can be reduced. If the charge distribution in the first material that accumulates the charge is non-uniform, the charge may move in the first material during holding, and the reliability of the memory element may be reduced. Further, since the first material for accumulating charges is separated from the conductor portion (gate electrode, diffusion layer region, semiconductor substrate) by another insulating film, leakage of charges is suppressed and sufficient holding time is obtained. Can be obtained. Therefore, in the case of having the sandwich structure, it is possible to rewrite the semiconductor memory device at high speed, improve reliability, and ensure a sufficient holding time.

  Furthermore, when the accumulated charge is electrons, it is preferable that the electron affinity of the first material is larger than the electron affinity of the second and third insulators. Here, the electron affinity is an energy difference between the vacuum level and the lowest level of the conduction electron body. Alternatively, when the accumulated charge is a hole (hole), the energy difference between the vacuum level of the first material and the highest level of the valence band is the vacuum level of the second and third insulators. It is preferable that the energy difference between the potential and the highest level of the valence band is smaller. When the above conditions are satisfied, the dissipation of charges from the nanodots made of the first material that accumulates charges is effectively suppressed, and the memory retention time becomes longer. Furthermore, the charge injection efficiency into the first material for accumulating charges is increased, and the rewriting time is shortened. As the charge holding portion that satisfies the above conditions, it is particularly preferable that the first material is a metal, a semiconductor, or silicon nitride, and the second and third insulators are silicon oxide films. Nanodots made of metal, semiconductor, or silicon nitride retain a large number of charges, and thus can provide a large hysteresis characteristic. In addition, both silicon oxide film and silicon nitride are preferable because they are very standard materials used in the LSI process. In addition to metal, semiconductor, or silicon nitride, hafnium oxide, tantalum oxide, yttrium oxide, or the like can be used as the first material. Furthermore, aluminum oxide or the like can be used as the second and third insulators in addition to silicon oxide. Note that the second and third insulators may be different materials or the same material.

  The charge holding portions are formed on both sides of the gate electrode so as to be laterally separated, and are disposed on the semiconductor substrate (well region, body region, source / drain region or diffusion layer region).

  The source / drain regions are arranged on the opposite side of the gate electrode of the charge holding portion as diffusion layer regions having a conductivity type opposite to that of the semiconductor substrate or well region. The junction between the source / drain region and the semiconductor substrate or well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. When an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the film thickness of the surface semiconductor layer, but approximately the same as the film thickness of the surface semiconductor layer. It is preferable to have the following junction depth.

  The source / drain regions may be arranged on the surface of the semiconductor substrate so as to overlap with the gate electrode end, or may be arranged offset with respect to the gate electrode end. In particular, when offset is applied, the ease of inversion of the offset region under the charge retention film when a voltage is applied to the gate electrode varies greatly depending on the amount of charge accumulated in the charge retention portion, and the memory effect increases. In addition, the short channel effect is reduced, which is preferable. However, if the offset is too great, the drive current between the source and drain becomes remarkably small. Therefore, the offset amount may be determined so that both the memory effect and the drive current have appropriate values.

  A part of the source / drain region may be extended to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-described metals, refractory metals, and the like. Of these, polysilicon is preferable. This is because polysilicon has a very large impurity diffusion rate compared to a semiconductor substrate, so that it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate and to easily suppress the short channel effect. . In this case, it is preferable that a part of the source / drain region is arranged so as to sandwich at least a part of the charge holding film together with the gate electrode.

The semiconductor memory device manufactured by the manufacturing method of the present invention has a gate electrode, a source region, a drain region, and a semiconductor substrate formed on a gate insulating film as four terminals, and each of the four terminals has a predetermined value. By applying a potential, writing, erasing and reading operations are performed. Examples of specific operating principles and operating voltages will be described later. When the semiconductor memory device manufactured by the manufacturing method of the present invention is arranged in an array to constitute a memory cell array, each memory cell can be controlled by a single control gate, so that the number of word lines can be reduced. .

The charge holding portion of the semiconductor memory device manufactured by the manufacturing method of the present invention is performed by a normal semiconductor process, for example, a method substantially similar to the method of forming a well-known side wall spacer on the side wall of the gate electrode or some steps. It can be formed by adding. Specifically, after forming the gate electrode, a laminated film of an insulating film (second insulator) / charge storage film (first material) / insulating film (third insulator) is formed, and an appropriate film is formed. A method of etching back under conditions to leave these films as sidewall spacers of a laminated structure can be mentioned.

When the memory cell array is configured by arranging the semiconductor memory devices manufactured by the manufacturing method of the present invention, the best mode of the semiconductor memory device is, for example, (1) gate electrodes of a plurality of semiconductor memory devices are integrated. (2) A charge holding portion is formed on both sides of the word line. (3) It is a trap in a metal, semiconductor or insulator that holds a charge in the charge holding portion. (4) The charge holding portion is composed of nanodots, and at least one set of nanodots has a surface substantially parallel to the surface of the gate insulating film. (5) Word line and channel region in the charge holding portion (6) Nanodots in the charge holding portion and the diffusion region overlap, (7) Nanodots having a surface substantially parallel to the surface of the gate insulating film The thickness of the insulating film separating at least one set from the channel region or the semiconductor layer is different from the thickness of the gate insulating film. (8) Writing and erasing operations of one semiconductor memory device are performed by a single word line. (9) There is no electrode (word line) having a function of assisting writing and erasing operations on the charge holding portion. (10) Opposite to the conductivity type of the diffusion region in the portion in contact with the diffusion region immediately below the charge holding portion All the requirements for having a region with a high impurity concentration of the conductivity type are satisfied. However, what is necessary is just to satisfy | fill one of these requirements.

  Particularly preferable combinations of the above-mentioned requirements are, for example, (3) a metal or semiconductor, particularly nanodots, that holds charges in the charge holding portion, and (6) at least a part of the metal or semiconductor in the charge holding portion and the diffusion region. (9) The case where there is no electrode (word line) having a function of assisting writing and erasing operations on the charge holding portion.

  When the requirement (3) and the requirement (9) are satisfied, it is very useful as follows.

  First, the bit line contact can be arranged closer to the charge holding unit arranged on the side of the word line. Alternatively, even when the distance between the semiconductor memory devices is close, the plurality of charge holding units do not interfere with each other and the stored information can be held. Therefore, miniaturization of the semiconductor memory device is facilitated. When the charge holding region in the charge holding unit is a continuous body, interference occurs between the charge holding regions as the semiconductor storage devices come closer due to capacitive coupling, and the stored information cannot be held.

  In addition, when the charge holding region in the charge holding part is discrete (for example, nanodots), it is not necessary to make the charge holding part independent for each memory cell. For example, the charge holding portions formed on both sides of one word line shared by a plurality of memory cells need not be separated for each memory cell, and the charge holding portions formed on both sides of one word line Can be shared by a plurality of memory cells sharing a word line. This eliminates the need for a photolithography process and an etching process for separating the charge holding portion, thereby simplifying the manufacturing process. Further, since the alignment margin of the photolithography process and the etching film reduction margin are not required, the margin between the memory cells can be reduced. Therefore, compared with the case where the charge holding region in the charge holding portion is a continuum of conductors (for example, a polycrystalline silicon film), the area occupied by the memory cell can be reduced even if formed at the same fine processing level. Can do. When the charge holding region in the charge holding portion is a continuum of conductors, a photo and etching process for separating the charge holding portion for each memory cell is required, and an alignment margin in the photolithography process and an etching film reduction margin are required. Is required.

  Further, since there is no electrode having a function of assisting writing and erasing operations on the charge holding portion and the element structure is simple, the number of steps can be reduced and the yield can be improved. Therefore, it is possible to easily mount the logic circuit and the transistors constituting the analog circuit, and to obtain an inexpensive semiconductor memory device.

  Further, it is more useful when the requirements (3) and (9) are satisfied and the requirement (6) is satisfied.

  That is, writing and erasing can be performed at a very low voltage by overlapping the charge holding region and the diffusion region in the charge holding portion. Specifically, write and erase operations can be performed with a low voltage of 5 V or less. This action is a very significant effect in circuit design. Since it is not necessary to produce a high voltage in the chip like a flash memory, it is possible to omit or reduce the scale of a charge pumping circuit that requires a huge occupation area. In particular, when a small-capacity memory is incorporated in a logic LSI for adjustment, the area occupied by the peripheral circuit that drives the memory cell is more dominant than the memory cell. Omitting the booster circuit or reducing the scale is most effective for reducing the chip size.

  On the other hand, when the requirement (3) is not satisfied, that is, when it is a conductor continuum that holds charges in the charge holding portion, the requirement (6) is not satisfied, that is, the conductor in the charge holding portion Even if the diffusion regions do not overlap, the write operation can be performed. This is because the conductor in the charge holding portion assists writing by capacitive coupling with the gate electrode.

  Further, when the requirement (9) is not satisfied, that is, when there is an electrode having a function of assisting writing and erasing operations on the charge holding portion, the requirement (6) is not satisfied, that is, the discrete in the charge holding portion. Even if the static charge trap and the diffusion region do not overlap, the write operation can be performed.

In the semiconductor memory device manufactured by the manufacturing method of the present invention, the transistor may be connected in series to one or both of the semiconductor memory devices, or the logic transistor and the logic transistor may be mounted on the same chip. May be. In such a case, a semiconductor device manufactured by the manufacturing method of the present invention, particularly a semiconductor memory device, can be formed by a process having high affinity with a process for forming a normal transistor such as a transistor and a logic transistor. Can be formed simultaneously. Therefore, the process of mounting the semiconductor memory device and the transistor or the logic transistor is simple, and an inexpensive mixed device can be obtained.

In the semiconductor memory device manufactured by the manufacturing method of the present invention, the semiconductor memory device can store binary information or more information in one charge holding portion, whereby quaternary information or more information can be stored. The semiconductor memory device can function as a memory. Note that the semiconductor memory device may store only binary information. In addition, the semiconductor memory device can be made to function as a memory cell having both the function of the selection transistor and the memory transistor by the variable resistance effect by the charge holding portion.

The semiconductor memory device manufactured by the manufacturing method of the present invention can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.

Hereinafter, a manufacturing method of the present invention and a semiconductor memory device manufactured by the manufacturing method will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1A shows a cross section along the channel length direction of the nonvolatile memory element as the semiconductor memory device of the first embodiment. This memory element is configured as a field effect transistor capable of storing 2 bits.

  As shown in FIG. 1A, a gate insulating film 12 is formed on a surface 11a of a semiconductor substrate 11, and a gate length similar to that of a normal transistor, for example, about 0.015 μm to 0.5 μm is formed on the gate insulating film 12. A gate electrode 13 having a substantially rectangular cross section is formed. Discrete charge holding portions 61 and 62 are formed at positions corresponding to both sides of the gate electrode 13 above the semiconductor substrate 11 and spaced apart from the gate electrode 13 laterally. Further, the first diffusion layer region 17 and the second diffusion layer region 18 (source / drain regions) are formed so as to occupy portions corresponding to both sides of the gate electrode 13 in the surface 11a of the semiconductor substrate 11. . A region corresponding to a portion between the first diffusion layer region 17 and the second diffusion layer region 18 in the surface 11a of the semiconductor substrate 11 is a channel region. In this example, the source / drain regions 17 and 18 are laterally separated (offset) from the side walls 13 b and 13 b of the gate electrode 13. That is, offset regions 42 and 42 that are not covered by the gate electrode 13 are provided between the region 41 corresponding to the region immediately below the gate electrode 13 and the source / drain regions 17 and 18 in the surface 11 a of the semiconductor substrate 11. ing.

  The charge holding portions 61 and 62 of the memory element are formed independently of the gate insulating film 12. Therefore, the memory function performed by the charge holding units 61 and 62 and the transistor operation function performed by the gate insulating film 12 are separated. In addition, since the two charge holding portions 61 and 62 formed on both sides of the gate electrode 13 are formed on the opposite sides with respect to the gate electrode 13, interference during rewriting is effectively suppressed. The Therefore, this memory element can store 2 bits and can be easily miniaturized.

  Further, since the source / drain regions 17 and 18 are offset from the gate electrode 13, the ease of inversion of the offset region 42 below the charge holding portion when a voltage is applied to the gate electrode 13 is determined. The amount of charge accumulated in 62 can be changed greatly, and the memory effect can be increased. Further, compared with a normal logic transistor, the short channel effect can be strongly prevented, and the gate length can be further miniaturized. In addition, since it is structurally suitable for suppressing the short channel effect, it is possible to employ a gate insulating film that is thicker than a logic transistor, and it is possible to improve reliability.

  The discrete charge holding portions 61 and 62 are nanodots (indicated by ● marks in the figure) 15 as an example of a discrete charge trap made of the first material, as an example of a film made of the second insulator. And a silicon oxide film (interlayer insulating film) 16 as an upper layer as an example of a film made of a third insulator. That is, in this embodiment, the second and third insulators are silicon oxide. The nanodot 15 has a function of trapping and storing charges (electrons or holes). As described above, since the charge holding units 61 and 62 have a structure in which the nanodot 15 is sandwiched between the silicon oxide films 14 and 16, the charge injection efficiency into the charge holding units 61 and 62 is improved, and the rewriting operation (writing and erasing operation) is performed. ) Is realized.

  It is preferable that at least a part of the nanodot 15 is formed so as to overlap a part of the first diffusion layer region 17 or the second diffusion layer region 18.

  In addition, the nanodots 15 are preferably arranged in a plane substantially parallel to the surface of the gate insulating film 12 (the surface in contact with the bottom surface of the gate electrode 13).

  2A is an enlarged view of the vicinity of the left charge holding portion 61 of the memory element illustrated in FIG. 1A (the vicinity of the right charge holding portion 62 is configured symmetrically with FIG. 2A). Since it is the nanodot 15 that mainly accumulates charges, the thickness T1 of the silicon oxide film 14 and the size T2 of the nanodot 15 on the offset region 42 have a great influence on the memory characteristics.

  The thickness T1 of the silicon oxide film 14 on the offset region 42 is preferably set as follows. When the thickness T1 of the silicon oxide film 14 is 1.5 nm or less, the charges accumulated in the nanodots 15 can easily escape through the silicon oxide film 14, and the holding time is remarkably shortened. On the other hand, when T1 is 15 nm or more, the charge injection efficiency into the nanodot 15 is deteriorated, and an increase in the writing time cannot be ignored. Therefore, if the thickness T1 of the silicon oxide film 14 is 1.5 nm to 15 nm, it is preferable because sufficient holding time and high-speed rewriting are compatible. T1 is more preferably 5 nm to 12 nm.

  The size T2 of the nanodot 15 on the offset region 42 is preferably set as follows. When the size T2 of the nanodot 15 is 0.1 nm or less, it is difficult to inject charges into the nanodot 15, and thus the threshold value change (or read current change) of the memory element becomes insufficient. Furthermore, the inter-element variation caused by the size variation of the nanodots cannot be ignored. On the other hand, when the size T2 of the nanodot 15 is 10 nm or more, it is difficult to uniformly inject charges into the nanodot during rewriting, or a longer time is required. In addition, when the charges are not uniformly injected into the nanodots, the charges move between the nanodots during storage and the threshold value (or read current) changes. Therefore, if the size T2 of the nanodot 15 is 0.1 nm to 10 nm, it is preferable because the memory element has sufficient reliability. T2 is more preferably set to 1 nm to 5 nm.

  FIG. 3 shows an energy diagram (energy band diagram) for electrons at the section line A-A ′ in FIG. 2A. For simplicity, the bands are all flat (the vacuum level VL is constant regardless of the position). In FIG. 3, ECs is the lowest level of the conduction electron band of the semiconductor (semiconductor substrate 11), EVs is the highest level of the valence band of the semiconductor, Efs is the Fermi level of the semiconductor, and EC1 is the first material (nanodot 15). EV1 is the lowest level of the valence band of the first material, EC2 is the lowest level of the conduction electron band of the second insulator (silicon oxide film 14), and EV2 is the second level. The highest level of the valence band of the insulator, EC3 is the lowest level of the conduction electron band of the third insulator (silicon oxide film 16 or silicon nitride film 52 described later), and EV3 is the value of the third insulator. It is the highest level of the electronic band. Therefore, χ1 is the energy difference (electron affinity) between the vacuum level of the first material and the lowest level of the conduction electron band, and φ1 is the energy between the vacuum level of the first material and the highest level of the valence band. The difference, χ2 is the energy difference (electron affinity) between the vacuum level and the lowest level of the conduction electron band in the second insulator, and φ2 is the vacuum level and the highest level of the valence band in the second insulator. Χ3 is the energy difference (electron affinity) between the vacuum level of the third insulator and the lowest level of the conduction electron band, and φ3 is the highest level of the vacuum level and valence band of the third insulator. The energy difference from the position is shown.

  When electrons accumulate in the first material that accumulates charges, it is preferable that χ1> χ2 and χ1> χ3. In this case, when electrons are injected into the first material (nanodots 15), the third insulator (silicon oxide film 16 or silicon nitride film 52 described later) serves as a barrier, and the electron injection efficiency increases. . In addition, it is possible to efficiently prevent electrons accumulated in the first material from leaking to the semiconductor substrate 11. Therefore, high-speed writing operation and good holding characteristics are realized.

  When holes are accumulated in the first material that accumulates charges, it is preferable that φ1 <φ2 and φ1 <φ3. In this case, when holes are injected into the first material (nanodots 15), the third insulator (silicon oxide film 16 or silicon nitride film 52 described later) serves as a barrier, and the hole injection efficiency is improved. Get higher. In addition, holes accumulated in the first material can be efficiently prevented from leaking to the semiconductor substrate 11. Therefore, high-speed writing operation and good holding characteristics are realized.

  It is more preferable that the above four conditions (χ1> χ2, χ1> χ3, φ1 <φ2, φ1 <φ3) are all satisfied. For example, even when electrons are accumulated in the first material for accumulating charges, when holes are injected to remove the accumulated electrons, the hole injection efficiency is increased, and the erase operation is performed. Can also be speeded up.

  In this embodiment, the first material is a metal or semiconductor, the second insulator is a silicon oxide film, and the third insulator is a silicon oxide film or a silicon nitride film, but this is not restrictive. For example, the first material and the second and third insulators can be high dielectric materials such as hafnium oxide, tantalum oxide, yttrium oxide, and zirconium oxide, or aluminum oxide.

  Next, returning to FIG. 1A, the write operation principle of the memory element will be described.

Here, writing refers to injecting electrons into the charge holding units 61 and 62.
In order to inject (write) electrons into the second charge holding portion 62, the first diffusion layer region 17 is used as a source electrode, and the second diffusion layer region 18 is used as a drain electrode. For example, 0 V may be applied to the first diffusion layer region 17 and the semiconductor substrate 11, +5 V may be applied to the second diffusion layer region 18, and +2 V may be applied to the gate electrode 13. Under such a voltage condition, the inversion layer extends from the first diffusion layer region 17 (source electrode), but a pinch-off point is generated without reaching the second diffusion layer region 18 (drain electrode). The electrons are accelerated by a high electric field from the pinch-off point to the second diffusion layer region 18 (drain electrode), and become so-called hot electrons (high energy conduction electrons). Writing is performed by injecting the hot electrons into the second charge holding portion 62 (more precisely, the nanodot 15). In the vicinity of the first charge holding portion 61, no hot electrons are generated, so that writing is not performed.

  In this way, writing can be performed by injecting electrons into the second charge holding portion 62.

  On the other hand, in order to inject (write) electrons into the first charge holding portion 61, the second diffusion layer region 18 is used as a source electrode, and the first diffusion layer region 17 is used as a drain electrode. For example, 0 V may be applied to the second diffusion layer region 18 and the semiconductor substrate 11, +5 V may be applied to the first diffusion layer region 17, and +2 V may be applied to the gate electrode 13. As described above, when electrons are injected into the second charge holding portion 62, writing can be performed by injecting electrons into the first charge holding portion 61 by switching the source / drain regions.

  Next, the principle of reading operation of the memory element will be described.

  When the information stored in the first charge holding unit 61 is read, the transistor is operated in a saturation region by using the first diffusion layer region 17 as a source electrode and the second diffusion layer region 18 as a drain electrode. For example, 0 V may be applied to the first diffusion layer region 17 and the semiconductor substrate 11, +2 V may be applied to the second diffusion layer region 18, and +1 V may be applied to the gate electrode 13. At this time, if electrons are not accumulated in the first charge holding portion 61, the drain current tends to flow. On the other hand, when electrons are accumulated in the first charge holding unit 61, the inversion layer is not easily formed in the vicinity of the first charge holding unit 61, so that the drain current hardly flows. Accordingly, the storage information of the first charge holding unit 61 can be read by detecting the drain current. At this time, the presence or absence of charge accumulation in the second charge holding portion 62 does not affect the drain current because the vicinity of the drain is pinched off.

  When the information stored in the second charge holding portion 62 is read, the second diffusion layer region 18 is used as a source electrode, the first diffusion layer region 17 is a drain electrode, and the transistor is operated in a saturation region. For example, 0 V may be applied to the second diffusion layer region 18 and the semiconductor substrate 11, +2 V may be applied to the first diffusion layer region 17, and +1 V may be applied to the gate electrode 13. As described above, when the information stored in the first charge holding unit 61 is read out, the information stored in the second charge holding unit 62 can be read out by switching the source / drain regions. .

  As is clear from the above description, when attention is paid to the charge holding portion on one side, the source and the drain are switched between the case where writing is performed and the case where the reading operation is performed. In other words, the magnitude relationship between the voltages applied to the first diffusion layer region and the second diffusion layer region is reversed between the read operation and the write operation. Therefore, the information stored in each of the two charge holding units can be detected with high sensitivity.

  In addition, when a portion (offset region 42) that is not covered with the gate electrode 13 remains as the channel regions 41 and 42, the inversion layer disappears in the offset region 42 depending on the presence or absence of surplus electrons in the charge holding portions 61 and 62. Or formed, resulting in a large hysteresis (threshold change). However, if the width of the offset region 42 is too large, the drain current is greatly reduced, and the reading speed is greatly reduced. Therefore, it is preferable to determine the width of the offset region 42 so that sufficient hysteresis and reading speed can be obtained.

  When the first and second diffusion layer regions 17 and 18 reach the end of the gate electrode 13, that is, when the first and second diffusion layer regions 17 and 18 and the gate electrode 13 overlap. Even in such a case, the threshold value of the transistor was hardly changed by the write operation, but the parasitic resistance at the source / drain ends was greatly changed, and the drain current was greatly decreased (one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the first and second diffusion layer regions 17 and 18 and the gate electrode 13 do not overlap (the offset region 42 exists).

  Further, the erase operation principle of the memory element will be described.

  First, as a first method, when erasing information stored in the first charge holding unit 61, a positive voltage (for example, +6 V) is applied to the first diffusion layer region 17 and 0 V is applied to the semiconductor substrate 11. A reverse bias may be applied to the PN junction between the first diffusion layer region 17 and the semiconductor substrate 11 and a negative voltage (for example, −5 V) may be applied to the gate electrode 13. At this time, in the vicinity of the gate electrode 13 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, hot holes (high energy holes) are generated on the side of the semiconductor substrate 11 of the PN junction due to the band-to-band tunnel. This hot hole is drawn in the direction of the gate electrode 13 having a negative potential. As a result, hole injection is performed in the first charge holding portion 61. In this way, the first charge holding unit 61 is erased. At this time, 0 V may be applied to the second diffusion layer region 18. When erasing the information stored in the second charge holding portion 62, the potentials of the first diffusion layer region and the second diffusion layer region may be switched in the above.

  Next, as a second method, when erasing information stored in the first charge holding unit 61, a positive voltage (for example, +5 V) is applied to the first diffusion layer region 17, and a second diffusion layer region 18 is applied to the second diffusion layer region 18. A negative voltage (for example, −4 V) may be applied to the gate electrode 13 and a positive voltage (for example, +0.8 V) may be applied to the semiconductor substrate 11. At this time, a forward voltage is applied between the semiconductor substrate 11 and the second diffusion layer region 18, and electrons are injected into the semiconductor substrate 11. The injected electrons are diffused to the PN junction between the semiconductor substrate 11 and the first diffusion layer region 17, where they are accelerated by a strong electric field and become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. That is, by applying a forward voltage between the semiconductor substrate 11 and the second diffusion layer region 18, electrons injected into the semiconductor substrate 11 become a trigger, and a hot hole is formed at the PN junction located on the opposite side. Will occur. Hot holes generated at the PN junction are attracted toward the gate electrode 13 having a negative potential, and as a result, holes are injected into the first charge holding portion 61. When erasing the information stored in the second charge holding portion 62, the potentials of the first diffusion layer region and the second diffusion layer region may be switched in the above.

  According to the second method, even when only a voltage sufficient to generate hot holes due to the band-to-band tunnel is applied to the PN junction between the semiconductor substrate 11 and the first diffusion layer region 17, the second diffusion is performed. The electrons injected from the layer region 18 serve as a trigger for generating electron-hole pairs at the PN junction, and can generate hot holes. Therefore, the voltage during the erase operation can be reduced. In particular, when the offset region 42 exists, there is little effect that the PN junction is sharpened by the gate electrode to which a negative potential is applied. For this reason, although it is difficult to generate hot holes due to a band-to-band tunnel, the second method can compensate for the disadvantage and realize an erasing operation at a low voltage.

  In the case of erasing information stored in the first charge holding portion 61, in the first erasing method, +6 V must be applied to the first diffusion layer region 17, but the second erasing method Then, + 5V was enough. Thus, according to the second method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the memory element due to hot carriers can be suppressed.

  With the above operation method, 2-bit writing and erasing can be selectively performed per transistor.

  In the above operation method, writing and erasing of 2 bits per transistor are performed by switching the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed to operate as a 1-bit memory. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be halved.

  FIG. 1B shows a modification of the memory element of FIG. 1A.

  In the memory element of FIG. 1A, the silicon oxide film (interlayer insulating film) 16 is used as the third insulator of the charge holding portions 61 and 62. On the other hand, the memory element of FIG. 1B is different only in that the silicon nitride film 52 is used as the third insulator of the charge holding portions 61 and 62. The silicon nitride film 52 is a film having an L-shaped cross section including a portion 52 a along the surface 11 a of the semiconductor substrate 11 and a portion 52 b along the side wall 13 b of the gate electrode 13. Accordingly, the silicon oxide film 14 as the second insulator is a film having an L-shaped cross section including a portion along the surface 11 a of the semiconductor substrate 11 and a portion along the side wall 13 b of the gate electrode 13. Yes. The nanodot 15 is provided along the interface between the portion 52a along the surface 11a of the semiconductor substrate 11 of the silicon nitride film 52 as the third insulator and the silicon oxide film 14 as the second insulator in contact therewith. Yes. The silicon oxide film (interlayer insulating film) 16 covers the upper surface 13a of the gate electrode 13 and the silicon nitride film 52 thickly.

  2B is an enlarged view of the vicinity of the charge holding unit 61 on the left side of the memory element illustrated in FIG. 1B. In the memory element of FIG. 1B, the thickness T1 of the silicon oxide film 14 and the size T2 of the nanodot 15 on the offset region 42 are set in the same manner as in the memory element of FIG. 1A.

  As mentioned with respect to FIG. 3, the memory element of FIG. 1B has an energy diagram (energy band diagram) similar to that of the memory element of FIG. 1A. Therefore, writing, erasing, and reading operations can be performed in exactly the same manner as the memory element of FIG. 1A, and similar effects can be obtained. In addition, since the third insulator is made of the silicon nitride film 52, the dielectric constant of the third insulator can be increased.

The memory element of FIG. 1B can be formed as follows by a manufacturing method including manufacturing steps almost the same as those of a normal logic transistor.

  First, as shown in FIG. 4A, a gate insulating film 12 made of a silicon oxynitride film having a thickness of about 1 nm to 6 nm is formed on the surface 11a of the semiconductor substrate 11, and polysilicon having a thickness of about 50 nm to 400 nm. A gate electrode material film made of a laminated film of polysilicon and refractory metal silicide or a laminated film of polysilicon and metal was formed, and the gate electrode 13 was formed by patterning these films into a desired shape. The gate electrode 13 has a substantially rectangular cross section having an upper surface 13 a, side walls 13 b and 13 b, and a bottom surface in contact with the gate insulating film 12. Note that, as described above, the material for the gate insulating film and the gate electrode may be a material used in a logic process in accordance with the scaling law of that era, and is not limited to the above materials.

  Subsequently, as shown in FIG. 4B, the gate is formed on the surface side so as to cover the entire surface of the obtained semiconductor substrate 11, more specifically, the semiconductor substrate 11 corresponding to both sides of the gate electrode 13 and the gate electrode 13. A silicon oxide film 14 having a thickness reflecting the cross-sectional shape of the electrode 13, in this example, a film thickness of 1.5 nm to 15 nm, more preferably a film thickness of 5 nm to 12 nm, was deposited by a CVD (Chemical Vapor Deposition) method. The silicon oxide film 14 may be formed by thermal oxidation. Next, a thickness reflecting the cross-sectional shape of the gate electrode 13 on the surface side so as to cover the silicon oxide film over the entire surface of the silicon oxide film 14, in this example, a film thickness of 2 nm to 15 nm, more preferably 3 nm to 7 nm. The silicon nitride film 52 was deposited by the CVD method. Further, the entire surface of the silicon nitride film 52 is covered with the corner 52c formed by the L-shaped cross section of the silicon nitride film 52 on both sides of the gate electrode 13 so as to cover the silicon nitride film 52. A silicon oxide film 53 as a sacrificial silicon oxide film having a thickness of 20 nm to 70 nm was deposited by the CVD method.

  Subsequently, as shown in FIG. 4C, the silicon oxide films 53 and 51 and the silicon nitride film 52 are etched back by anisotropic etching, whereby the silicon oxide film 14 and the silicon nitride film 52 are respectively formed on both sides of the gate electrode 13. Sidewall spacers 76 and 76 were formed on both sides of the gate electrode 13 while leaving the silicon oxide film 53 at the corner portion 52 c formed by the L-shaped cross section of the silicon nitride film 52 while leaving the cross section in the L shape.

  Thereafter, ion implantation is performed using the gate electrode 13 and the sidewall spacers 76 and 76 as a mask, thereby forming the source / drain regions 17 and 18.

  Further, as shown in FIG. 4D, photolithography is performed to provide photoresists 71 and 71 in regions corresponding to the outside of the side wall spacers 76 and 76 with respect to the gate electrode 13. At this time, in order to protect the surfaces of the source / drain regions 17 and 18 with an alignment margin, the photoresists 71 and 71 are overlapped with the end portions of the side wall spacers 76 and 76. Then, at least portions of the silicon oxide films 53 and 53 forming the side wall spacers 76 and 76 near the side walls 13b and 13b of the gate electrode 13 are removed by anisotropic etching. At this time, it is possible to use an etching condition in which the etching rate of the silicon nitride film is lower than the etching rate of the silicon oxide film. For example, the silicon nitride film is used as an etching stopper by performing anisotropic etching under conditions such that the silicon oxide film is etched but the silicon nitride film is hardly etched. By this method, etching can be accurately stopped with the silicon nitride film, so that excessive etching is performed by the element, for example, damage to the substrate, or conversely, etching is insufficient and, for example, etching residue is prevented from occurring. be able to. Therefore, variation in element characteristics and occurrence of defects can be suppressed.

  Subsequently, as shown in FIG. 4E, a material 72 for producing nanodots is introduced into the insulating films 52 and 14 by ion implantation, for example, from above. At the same time, the material 72 is also introduced into the upper surface 13a of the gate electrode 13 and the surfaces of the photoresists 71 and 71 (the implanted region is indicated by a dotted line 73). As the material 72, for example, a semiconductor such as Si or Ge or a metal such as Ag, Au, Cu, Ti, Cr, Mn, Zr, Hf, Ta, W, or Pt can be used. In particular, it is preferable to use a material having a high melting point, since deterioration of device characteristics due to diffusion due to heat or aging can be avoided.

  After removing the photoresists 71, 71, a heat treatment step is performed as necessary. As a result, as shown in FIG. 4F, nanodots 15 were formed at the interface between the silicon nitride film 52 and the silicon oxide film 14. Depending on the implantation conditions, nanodots can be formed without a heat treatment step. Preferably, a heat treatment step is performed. As a result, defects present in the insulating film can be reduced. The heat treatment can be selected from an inert gas such as argon, an oxidizing atmosphere such as oxygen, a hydrogen atmosphere, or a nitriding atmosphere. In particular, when an oxide insulator is used as the insulator, heat treatment is preferably performed in an atmosphere containing a small amount of oxygen. Thereby, oxygen deficiency can be reduced.

  In this example, the nanodot 15 is formed at the interface between the silicon nitride film 52 and the silicon oxide film 14. It is possible to form.

  Thereafter, an interlayer insulating film 16 for separating the gate electrode 13 from an upper wiring (not shown) is deposited thicker than the gate electrode 13 by CVD. In this example, a silicon oxide film is used as the material of the interlayer insulating film 16.

  The memory element of FIG. 1A can be formed as follows by a process obtained by slightly modifying the above manufacturing process for manufacturing the memory element of FIG. 1B.

  As shown in FIG. 5A, at least a portion near the side walls 13b and 13b of the gate electrode 13 of the silicon oxide films 53 and 53 forming the side wall spacers 76 and 76 is anisotropically etched. The above-described manufacturing process proceeds in the same manner until the removal step).

  Next, in this example, as shown in FIG. 5B, a portion of the silicon nitride film 52 exposed between the resists 71 and 72 is removed. At this time, a dry etching method can be used as a method of removing the silicon nitride film 52. For example, an etching condition in which the etching rate of the silicon oxide film is smaller than the etching rate of the silicon nitride film can be used. For example, the silicon oxide film is used as an etching stopper by performing anisotropic etching under conditions such that the silicon nitride film is etched but the silicon oxide film is hardly etched. By this method, etching can be accurately stopped with a silicon oxide film, and it is possible to prevent excessive etching by the element, for example, damage to the substrate, or conversely, insufficient etching to cause, for example, etching residue. be able to. Therefore, variation in element characteristics and occurrence of defects can be suppressed. As another method for removing the silicon nitride film, for example, a wet etching method using phosphoric acid or the like can be used.

  Subsequently, as shown in FIG. 5C, a material 72 for forming nanodots is introduced into the silicon oxide film 14 by ion implantation, for example, from above.

  It is preferable to remove the silicon nitride film 52 after injecting the material 72 for forming nanodots, because the surface damage layer caused by the implantation can be removed together with the silicon nitride film 52.

  After removing the photoresists 71, 71, a heat treatment step is performed as necessary. As a result, nanodots 15 are formed in the silicon oxide film 14 as shown in FIG. 5D.

  Thereafter, the interlayer insulating film 16 is deposited thicker than the gate electrode 13 by CVD. In this example, a silicon oxide film is used as the material for the interlayer insulating film 16.

  In the memory element of FIGS. 1A and 1B, the two charge holding portions 61 and 62 are formed to be separated from the gate electrode 13 laterally and are separated from the gate insulating film 12. Therefore, the memory function performed by the charge holding units 61 and 62 and the transistor operation function performed by the gate insulating film 12 are separated. Therefore, it is easy to reduce the short channel effect by thinning the gate insulating film 12 while having a sufficient memory function. Further, since the two charge holding portions 61 and 62 are formed on the opposite sides with respect to the gate electrode 13, interference between the two charge holding portions 61 and 62 is effectively suppressed during rewriting. The In other words, the distance between the two charge holding portions 61 and 62 can be reduced. Therefore, 2-bit operation is possible and miniaturization is easy.

  Further, in the memory elements of FIGS. 1A and 1B, the nanodots 15 made of the first material having a function of accumulating charges are formed by the silicon oxide film 14 as the second insulator and the silicon oxide as the third insulator. The structure is sandwiched between the oxide film 16 or the silicon nitride film 52. Therefore, at the time of charge injection, the charge density in the first material can be increased and the charge density can be made uniform in a short time.

  1A and 1B, the silicon oxide film 14 as the second insulator and the silicon oxide film 16 as the third insulator have different densities. In the memory element of FIG. 1B, the silicon oxide film 14 as the second insulator and the silicon nitride film 52 as the third insulator are made of different materials. The silicon oxide film 14 as the second insulator and the silicon oxide film 16 or the silicon nitride film 52 as the third insulator have an interface. Therefore, the nanodot 15 can be formed in a self-aligned manner on the interface.

  In particular, in the memory element of FIG. 1A, the second insulator is made of a silicon thermal oxide film 14, and the third insulator is made of a silicon oxide film 16 deposited chemically or physically. 14 has a higher density than the third insulator 16. Therefore, even if the atoms forming the nanodot 15 try to diffuse through the second insulator 14, it can be effectively prevented from reaching the semiconductor substrate 111.

  Further, since the nanodot 15 is separated from the conductor portion (gate electrode, diffusion layer region, semiconductor substrate) by the silicon oxide film 14 as the second insulator, charge leakage is suppressed and sufficient. Retention time can be obtained. Therefore, high-speed rewriting of the memory element, improvement of reliability, and securing of sufficient holding time can be achieved.

(Second Embodiment)
6A and 6B show cross sections in the vicinity of the charge holding portion 61 of the nonvolatile memory element as the semiconductor memory device of the second embodiment. The structure of the remaining part is the same as that in the memory element of FIGS. 1A and 1B.

  The memory element of FIG. 6A has a distance T1B between the sidewall 13b of the gate electrode 13 and the nanodot 15 located closest to the side wall 13b of the memory element of FIG. It is characterized by being larger than the distance between. In other words, the thickness T1B of the silicon oxide film 14 along the side wall 13b of the gate electrode 13 is thicker than the thickness T1A of the silicon oxide film 14 on the surface 11a of the semiconductor substrate 11. Yes.

  Similarly, in FIG. 6B, the distance T1B between the side wall 13b of the gate electrode 13 and the nanodot 15 located closest to the side wall 13b of the memory element of FIG. It is characterized by being larger than the distance between. In other words, the total thickness T1B of the portion of the silicon oxide film 14 along the side wall 13b of the gate electrode 13 and the portion of the silicon nitride film 52 along the side wall 13b of the gate electrode 13 is It is characterized by being thicker than the thickness T1A of the silicon oxide film 14 on the surface 11a.

  Therefore, in the memory elements of FIGS. 6A and 6B, injection of charges from the gate electrode 13 to the nanodots 15 (or discharge of charges from the nanodots 15 to the gate electrode 13) can be effectively suppressed. Therefore, a memory operation can be performed without exchanging charges between the semiconductor substrate 111 and the nanodots 15. Therefore, the deterioration of the insulating film provided along the surface 11a of the semiconductor substrate 11 can be suppressed. Therefore, the rewrite characteristics of the memory element are stabilized and the reliability is improved.

A procedure of a manufacturing method for manufacturing the memory element of FIGS. 6A and 6B will be described. Hereinafter, a case where the semiconductor substrate 11 is a single crystal silicon substrate and the gate electrode 13 is made of polycrystalline silicon will be described.

  6A, first, the gate insulating film 12 and the gate electrode 13 were formed on the semiconductor (single crystal silicon) substrate 11 by the same method as described with reference to FIG. 4A. Next, a silicon oxide film 14 was formed on the surface of the gate electrode 13 and the surface of the silicon substrate 11 corresponding to both sides of the gate electrode 13 by thermal oxidation. At this time, the thickness of the silicon oxide film 14 is thicker at the portion T1B along the side wall 13b of the gate electrode 13 than at the thickness T1A of the silicon oxide film 14 on the surface 11a of the silicon substrate 11. became. This is because the thermal oxidation rate of polycrystalline silicon is higher than that of single crystal silicon. Thereafter, the process proceeds in the same manner as described for the memory element of FIG. 1A. Thereby, the memory element of FIG. 6A can be completed.

  6B, first, the gate insulating film 12 and the gate electrode 13 were formed on the semiconductor (single crystal silicon) substrate 11 by the same method as described with reference to FIG. 4A. Next, a silicon oxide film 14 was formed on the surface of the gate electrode 13 and the surface of the silicon substrate 11 corresponding to both sides of the gate electrode 13 by thermal oxidation. At this time, the thickness of the silicon oxide film 14 is thicker at the portion T1B along the side wall 13b of the gate electrode 13 than at the thickness T1A of the silicon oxide film 14 on the surface 11a of the silicon substrate 11. became. This is because the thermal oxidation rate of polycrystalline silicon is higher than that of single crystal silicon. Thereafter, the process proceeds in the same manner as described for the memory element of FIG. 1B. Thereby, the memory element of FIG. 6B can be completed.

  According to the above procedure, by using the difference in the oxidation rate due to the difference in crystallinity, the film thickness of the portion along the side wall 13b of the gate electrode 13 in the silicon oxide film 14 can be selectively selected without increasing the number of processes. Can be thickened. Therefore, a memory element having stable rewriting characteristics and high reliability can be formed by a simple process.

(Third embodiment)
7A and 7B show cross sections along the channel length direction of the nonvolatile memory cell as the semiconductor memory device of the third embodiment.

  As shown in FIG. 7A, a gate insulating film 114 is formed on a surface 111a of a semiconductor substrate 111, and a gate length similar to that of a normal transistor, for example, about 0.015 μm to 0.5 μm is formed on the gate insulating film 114. A gate electrode 117 having a substantially rectangular cross section is formed. Discrete charge holding portions 161 and 162 are formed at positions corresponding to both sides of the gate electrode 117 above the semiconductor substrate 111 and spaced apart from the gate electrode 117 laterally. The first diffusion layer region 112 and the second diffusion layer region 113 (source / drain regions) are formed so as to occupy portions corresponding to both sides of the gate electrode 117 in the surface 111a of the semiconductor substrate 111. . A region corresponding to a portion between the first diffusion layer region 112 and the second diffusion layer region 113 in the surface 111a of the semiconductor substrate 111 is a channel region. In this example, the source / drain regions 112 and 113 are laterally separated (offset) from the side walls 117b and 117b of the gate electrode 117. That is, offset regions 171 and 171 that are not covered with the gate electrode 117 are provided between the region 170 corresponding to the surface 111 a of the semiconductor substrate 111 immediately below the gate electrode 117 and the source / drain regions 17 and 18, respectively. ing.

  In the memory element of FIG. 7A, the charge holding portions 161 and 162 hold a charge (a charge storage area and may be an object having a charge holding function) 142 and a charge prevention area. (It may be a film having a function of making it difficult to escape charges) 141 and 143. For example, the memory element has an ODO structure. That is, an example of the nanodot made of the first material between the silicon oxide film 141 as an example of the film made of the second insulator and the silicon oxide film 143 as an example of the film made of the third insulator. The nanodots 142 are sandwiched between the charge holding portions 161 and 162. Here, the nanodot 142 functions to retain electric charge. In addition, the silicon oxide films 141 and 143 serve as films having a function of making it difficult for the charges stored in the nanodots 142 to escape.

  In addition, the regions (nanodots) 142 for holding charges in the charge holding units 161 and 162 overlap with the diffusion layer regions 112 and 113, respectively. Here, the term “overlap” means that at least a part of the region (nanodot 142) that retains the charge exists on at least a part of the diffusion layer regions 112 and 113.

  FIG. 8A is an enlarged view of the vicinity of the charge holding portion 162 on the right side of the memory element shown in FIG. 7A. Next, the effect of overlapping the charge holding regions 161 and 162 in the charge holding portions 161 and 162 (nanodots 142) and the diffusion layer regions 112 and 113 will be described with reference to FIG. 8A.

  W1 in FIG. 8A indicates an offset amount between the gate electrode 114 and the diffusion layer region 113. W2 represents the width of the charge holding portion 162 at the cut surface of the gate electrode 114 in the channel length direction. In addition, since the end of the nanodot 142 far from the gate electrode 117 in the charge holding portion 162 coincides with the end of the charge holding portion 162 far from the gate electrode 117, the width of the charge holding portion 162 is set to W2. Defined. The amount of overlap between the charge holding portion 162 and the diffusion layer region 113 is represented by W2-W1. In this embodiment, what is particularly important is that the nanodots 142 in the charge holding portion 162 overlap with the diffusion layer region 113, that is, satisfy the relationship of W2> W1.

  In the structure of FIG. 8A, the drain current when the width W2 of the charge holding portion 162 is fixed to 100 nm and the offset amount W1 is changed was examined. Here, the drain current was simulated with the charge holding portion 162 in an erased state (holes accumulated). As a result, when W1 is 100 nm or more (that is, the nanodots 142 and the diffusion layer region 112 do not overlap), the drain current rapidly decreases. Since the drain current value is substantially proportional to the read operation speed, the memory performance deteriorates rapidly when W1 is 100 nm or more. On the other hand, in the range where the nanodot 142 and the diffusion layer region overlap, the decrease in the drain current is moderate. Therefore, it is preferable that at least a part of the nanodots 142 having a function of holding charges overlap with the source / drain regions (diffusion layer regions). Similarly, in the charge holding unit 161, it is preferable that at least a part of the nanodots 142 having a function of holding charges overlap with the source / drain regions (diffusion layer regions).

  As in the first embodiment, the information stored in the charge holding unit 161 shown in FIG. 7A is read out using the diffusion layer region 112 as a source electrode, the diffusion layer region 113 as a drain region, and the drain region 113 in the channel region. It is preferable to form a pinch-off point on the side close to. That is, when reading the information stored in one of the two charge holding portions 161 and 162, it is preferable to form the pinch-off point in the channel region and in the region close to the other charge holding portion. This makes it possible to detect the stored information of the charge holding unit 161 with high sensitivity regardless of the storage state of the charge holding unit 162, which is a major factor enabling 2-bit operation.

  On the other hand, when information is stored only on one side of the two charge holding units or when the two charge holding units are used in the same storage state, the pinch-off point does not necessarily have to be formed at the time of reading.

  Note that a well region (a P-type well in the case of an N-channel element) is preferably formed on the surface 111a of the semiconductor substrate 111. By forming the well region, it is easy to control other electrical characteristics (breakdown voltage, junction capacitance, short channel effect) while making the impurity concentration of the channel region optimal for memory operation (rewrite operation and read operation). become.

  As described above, the charge holding units 161 and 162 preferably include nanodots 142 having a function of holding charges and an insulating film from the viewpoint of improving the holding characteristics of the memory. In the memory element of FIG. 7A, nanodots 142 having a level for trapping charges are used as the charge holding film, and silicon oxide films 141 and 143 having a function of preventing the dissipation of charges accumulated in the charge holding film are used as the insulating film. . By including the nanodots 142 and the insulating film in the charge holding portion, charge dissipation can be prevented and the holding characteristics can be improved. Furthermore, the volume of the nanodots can be appropriately reduced as compared with the case where the charge holding portion is composed only of the nanodots 142. By appropriately reducing the volume of the nanodots 142, it is possible to limit the movement of charges between the nanodots 142, and to suppress the characteristic change caused by the movement of charges during storage.

  In addition, the charge holding portions 161 and 162 include nanodots arranged substantially parallel to the surface of the gate insulating film 114, in other words, the nanodots 142 of the charge holding portion 162 are substantially parallel to the surface of the gate insulating film 114. It is preferable that they are arranged on a flat surface. More specifically, the lower surfaces of the plurality of nanodots 142 in the charge holding portions 161 and 162 are preferably arranged so as to have the same height difference with respect to the upper surface of the gate insulating film 114. The presence of the nanodots 142 substantially parallel to the surface of the gate insulating film 114 in the charge holding portion 162 effectively controls the ease with which the inversion layer is formed in the offset region 171 by the amount of charges accumulated in the nanodots 142. This can increase the memory effect. Further, by making the nanodots 142 substantially parallel to the surface of the gate insulating film 114, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and variations in the memory effect can be suppressed. Can do. In addition, the movement of charges upward of the nanodots 142 is suppressed, and it is possible to suppress changes in characteristics due to the charge movement during storage.

  Further, the charge holding portion 162 is an insulating film (for example, a portion of the silicon oxide film 141 on the offset region 171) that separates the nanodot 142 substantially parallel to the surface of the gate insulating film 114 and the channel region (or well region). It is preferable to include. With this insulating film, dissipation of charges accumulated in the nanodots is suppressed, and a memory element with better holding characteristics can be obtained.

  The semiconductor substrate is controlled by controlling the particle size, distribution, and film thickness of the nanodots 142 and by controlling the film thickness of the insulating film below the nanodots 142 (the portion of the silicon oxide film 141 above the offset region 171) to be constant. It becomes possible to keep the distance from the surface 111a of 111 to the electric charge stored in the nanodot 142 substantially constant. That is, the distance from the semiconductor substrate surface 111a to the charge stored in the nanodots 142 is determined from the minimum film thickness value of the insulating film under the nanodot 142, the maximum film thickness value of the insulating film under the nanodot 142, and the particle size value of the nanodot 142. Can be controlled until the sum of As a result, the density of the lines of electric force generated by the charges stored in the nanodots 142 can be generally controlled, and the size variation of the memory effect of the memory element can be extremely reduced.

  The charge is injected into the nanodots 142 during the rewrite operation because the generated charges are drawn by the electric field in the offset region 171. Therefore, by including the nanodots 142 arranged on the offset region 171, the charge injected into the charge holding unit 162 during the rewrite operation increases, and the rewrite speed increases.

  When the silicon oxide film 143 is a silicon nitride film, that is, when the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 114, the upward charge of the silicon nitride film Movement becomes remarkable, and the holding characteristics deteriorate.

  Furthermore, the charge holding portions 161 and 162 further provide an insulating film (a portion of the silicon oxide film 141 on the offset region 171) that separates the nanodots substantially parallel to the surface of the gate insulating film 114 and the channel region (or well region). It is preferable to include. With this insulating film, dissipation of charges accumulated in the nanodots 142 is suppressed, and retention characteristics can be further improved.

  FIG. 7B shows a modification of the memory element of FIG. 7A. FIG. 8B is an enlarged view of the vicinity of the charge holding portion 162 on the right side of the memory element shown in FIG. 7B.

  In the memory element of FIG. 7A, a silicon oxide film (interlayer insulating film) 143 is used as the third insulator of the charge holding portions 161 and 162. On the other hand, the memory element of FIG. 7B is different only in that the silicon nitride film 152 is used as the third insulator of the charge holding portions 161 and 162. The silicon nitride film 152 is a film having an L-shaped cross section including a portion 152 a along the surface 111 a of the semiconductor substrate 111 and a portion 152 b along the side wall 117 b of the gate electrode 117. Accordingly, the silicon oxide film 141 as the second insulator is an L-shaped film including a portion along the surface 111 a of the semiconductor substrate 111 and a portion along the side wall 117 b of the gate electrode 117. Yes. The nanodots 142 are provided along the interface between the portion 152a along the surface 111a of the semiconductor substrate 111 of the silicon nitride film 152 as the third insulator and the silicon oxide film 141 as the second insulator in contact therewith. Yes. The silicon oxide film (interlayer insulating film) 143 covers the upper surface 13a of the gate electrode 117 and the silicon nitride film 152 thickly.

  The memory element of FIG. 7B has the same effect as that of the memory element of FIG. 7A.

(Fourth embodiment)
The optimization of the arrangement in the channel length direction of the gate electrode 117, the charge holding portions 161 and 162, and the source / drain regions 112 and 113 will be described with reference to FIGS. 9A and 9B. The memory elements themselves shown in FIGS. 9A and 9B are the same as the memory elements (third embodiment) in FIGS. 7A and 7B, respectively.

  9A and 9B, A indicates the dimension (gate electrode length) of the gate electrode 117 at the cut surface in the channel length direction, and B indicates the distance (channel length) between the source / drain regions 112 and 113. FIG. C is the distance between the end of one charge holding portion 161 far from the gate electrode and the end of the other charge holding portion 162 far from the gate electrode, that is, one of the cut surfaces in the channel length direction. The outer end of the nanodot 142 farthest from the gate electrode in the charge holding portion 161 (the end far from the gate electrode) and the outer end of the nanodot 142 farthest from the gate electrode of the other charge holding portion 162 (the side far from the gate electrode) The distance to the end of ().

  In these memory elements, first, it is preferable that B <C. An offset region 171 exists between a portion of the channel region immediately below the gate electrode 117 and the source / drain regions 112 and 113. By B <C, the ease of inversion effectively varies in the entire region of the offset region 171 due to the charges accumulated in the charge holding portions 161 and 162 (nanodots 142). Therefore, the memory effect is increased, and in particular, the reading operation is speeded up.

  Further, when the gate electrode 117 and the source / drain regions 112 and 113 are offset, that is, when A <B is established, the ease of inversion of the offset region when a voltage is applied to the gate electrode. This greatly changes depending on the amount of charge accumulated in the charge holding portion, and the memory effect increases and the short channel effect can be reduced. However, as long as the memory effect appears, the offset region 171 does not necessarily exist. Even in the absence of the offset region 171, if the impurity concentration of the source / drain regions 112 and 113 is sufficiently low, the memory effect can be exhibited in the charge holding portions 161 and 162 (nanodots 142).

  Therefore, it is most preferable that A <B <C.

(Fifth embodiment)
FIG. 10 shows a cross section along the channel length direction of the nonvolatile memory element as the semiconductor memory device of the fifth embodiment.

  As shown in FIG. 10, a gate insulating film 2301 is formed on a surface 2300a of a semiconductor substrate 2300, and a gate length similar to that of a normal transistor, for example, about 0.015 μm to 0.5 μm is formed on the gate insulating film 2301. A gate electrode 2303 having a substantially rectangular cross section is formed. Discrete charge holding portions 2361 and 2362 are formed at positions corresponding to both sides of the gate electrode 2303 above the semiconductor substrate 2300 and spaced laterally with respect to the gate electrode 2303, respectively. Further, a first diffusion layer region 2304 and a second diffusion layer region 2305 (source / drain regions) are formed so as to occupy portions corresponding to both sides of the gate electrode 2303 in the surface 2300a of the semiconductor substrate 2300. . A region corresponding to a portion between the first diffusion layer region 2304 and the second diffusion layer region 2305 in the surface 2300a of the semiconductor substrate 2300 is a channel region. In this example, the source / drain regions 2304 and 2305 are laterally separated (offset) from the side walls 2303b and 2303b of the gate electrode 2303. That is, offset regions 2371 and 2371 that are not covered with the gate electrode 2303 are provided between the region 2370 and the source / drain regions 2304 and 2305 in the surface 2300a of the semiconductor substrate 2300, which are directly below the gate electrode 2303, respectively. ing.

  In this memory element, the discrete charge holding portions 2361 and 2362 are formed of a silicon dot formed by a nanodot 2306 as an example of a discrete charge trap made of a first material and a lower layer as an example of a film made of a second insulator. It has a structure sandwiched between an oxide film 2302 and an upper silicon oxide film (interlayer insulating film) 2316 as an example of a film made of a third insulator. That is, in this embodiment, the second and third insulators are silicon oxide. Each nanodot 2306 is made of a material capable of accumulating charges such as metal or semiconductor. The silicon oxide film 2302 includes a film having an L-shaped cross section along the surface 2300a of the semiconductor substrate 2300 and the side wall 2303b of the gate electrode 2303. A silicon oxide film (interlayer insulating film) 2316 covers the upper surface 2303a and the like of the gate electrode 2303 thickly.

  This memory element can perform characteristic operations different from those of a memory using normal nanodots as a floating gate electrode and a memory having a charge storage portion of polysilicon or silicon nitride on the side of the gate electrode. Next, for example, an operation of injecting and writing electrons as charges in the nanodot 2306 which is a charge holding unit will be described.

  In a normal memory, electrons are injected from the channel portion between the source / drain 2304 and 2305 by FN (Fowler-Nordeheim) tunnel or hot electron injection. On the other hand, in this memory element, electrons are sequentially tunneled from the source 2304 to the plurality of nanodots 2306 by setting the source region 2304 to the ground potential and the gate electrode 2203 to the positive potential.

  FIG. 11 is a schematic enlarged view of the vicinity of the charge holding portion 2361 on the left side of the memory element of FIG. Each nanodot 2306a, 2306b, 2306c (generically referred to as 2306) constituting the charge holding portion 2361 is represented in a square shape. The operation of the memory element will be specifically described with reference to FIG.

  When reading is performed first, for example, a P-type semiconductor substrate is used as the substrate 2300, and a ground potential is applied to the source region 2304 and a positive potential is applied to the gate electrode 2303. At this time, if no charge is accumulated in each nanodot 2306, the channel region is inverted, and a current flows between the source region 2304 and the drain region 2305. On the other hand, if electrons are sufficiently accumulated in the nanodot 2306, the inversion layer is hardly formed in the channel region near the source region 2034 due to the strong influence of the negative potential of the nanodot 2306. Therefore, by applying the same voltage to the gate electrode 2303 and detecting the magnitude of the current, a reading operation can be performed according to the amount of charges accumulated in the nanodot 2306. The design is such that electrons do not enter and exit the nanodot 2306 under the condition of voltage application to the source region 2034, the drain region 2305, and the gate electrode 2303 at the time of reading. Specifically, the distance T11 between the nanodot 2306 and the source region 2304 and the distance T12 between the nanodot 2306 and the gate electrode 2303 are set to such a distance that electrons do not enter and exit under the bias application condition at the time of reading. Keep it.

  On the other hand, when writing is performed, a ground potential is applied to the source region 2304, a positive potential is applied to the gate electrode 2303, and a potential difference between the source region 2304 and the gate electrode 2303 is increased. As a result, electrons are tunneled from the source 2304 to the nanodot 2306 a disposed at the closest position to the source 2304. Electrons injected into the nanodots 2306a arranged closest to the source 2304 can be sequentially tunneled to the nanodots 2306b and 2303c arranged closer to the gate electrode 2303. In this way, electrons are accumulated in the plurality of nanodots 2306a, 2306b, and 2306c.

  When erasing is performed, the potential is reversed from that during writing. Thereby, electrons are expelled from each nanodot 2306. At this time, the potential of the semiconductor substrate 2300 can be set to the same potential as that of the source region 2304, for example, and electrons can be expelled from each nanodot 2306 to the semiconductor substrate 2300. Note that in this embodiment, since the source region 2304 is N-type and the semiconductor substrate 2300 is P-type, the potential of the semiconductor substrate 2300 is preferably not set lower than the potential of the source region 2304. This is to prevent a PN forward current from flowing between the semiconductor substrate 2300 and the source region 2304.

  In the modification, the thickness T12 of the portion along the side wall 2303b of the gate electrode 2303 in the silicon oxide film 2302 as the second insulator is set to be smaller than the thickness of the portion along the surface 2300a of the semiconductor substrate 2300. Is done. In this case, charge injection from the gate electrode 2303 to the nanodot 2306 (or discharge of charge from the nanodot 2306 to the gate electrode 2303) can be performed. Accordingly, a memory operation can be performed without charge exchange between the semiconductor substrate 2300 and the nanodot 2306. Therefore, deterioration of the insulating film provided along the surface 2300a of the semiconductor substrate 2300 can be suppressed. Therefore, the rewrite characteristics of the memory element are stabilized and the reliability is improved.

  In the above description, FIG. 11 is used to focus attention on the vicinity of the charge holding portion 2361 on the left side of FIG. 10. However, as shown in FIG. The portions 2361 and 2362 preferably include a plurality of nanodots 2306a, 2306b, and 2306c, respectively. Even if there are charge holding portions 2361 and 2362 on both sides of the gate electrode 2303, the operation is basically the same as that described with reference to FIG. When there are the charge holding portions 2361 and 2362 on both sides of the gate electrode 2303, the operation condition may be set so that the charge holding state of the other charge holding portion does not change during the rewriting or erasing operation of one charge holding portion. preferable.

  As a material of the nanodot 2306, it is preferable to use a metal or a semiconductor. If the material of the nanodot 2306 is a metal or a semiconductor, the defects in which electrons and holes are trapped are different from those in the case where charges are trapped in defects such as silicon nitride. That is, it is possible to avoid complicated operation due to different holding forces.

  In the modification, the nanodot 2306 can be provided in a two-dimensional plane. In such a case, controllability is better than that of a storage device that traps charges in defects in which traps are three-dimensionally distributed.

As described above, the nanodot 2306 is used in the memory element described above. In particular, when the size of the nanodot 2306 becomes smaller than 10 nm, the Coulomb blockade effect gradually becomes apparent. In this case, for example, the source region 2304, the drain region 2305, the gate electrode 2303, or the semiconductor substrate 2300, which can be an electrode for injecting charges into the nanodot 2306, and the nanodot 2306 are separated by a thin insulating film that can directly tunnel the charge. Even if it is only, the entry and exit of charges is limited. Therefore, a memory operation is possible. If such a thin film is used in a conventional storage device that does not use such a nanodot 2306 in the memory holding unit, the charge leaks and the memory cannot be held, or the charge enters and exits during memory operation such as reading. Malfunctions such as erroneous erasure occurred. Therefore, in the memory device manufactured by the manufacturing method of the present invention, since the insulating film of the charge holding portion can be made thinner than in the conventional memory device, the element can be downsized and further miniaturized. Further, when the nano dot 2306 as small as less than 10 nm is used, it is possible to store in units of one electron at a minimum, so that the amount of charge to be charged / discharged in the memory operation can be extremely reduced. Therefore, power consumption can be extremely reduced.

  This phenomenon will be described by taking as an example the case where one charge holding portion 2361 and the other charge holding portion 2362 include three nanodots 2306a, 2306b, and 2306c (6 in total) as shown in FIG. . When the source region 2304 or the drain 2305 is the first electrode and the gate electrode is the second electrode, the first nanodots closer to the first electrode between the first electrode and the second electrode It has at least two nanodots of the second nanodot closer to the second electrode, the first electrode is an electrode that is relatively easy to put in and out the charge to the nanodot, and the second electrode has a charge to the nanodot. The electrode is difficult to put in and out. That is, electric charges pass through the barrier between the first electrode and the first nanodot (first barrier) more than the barrier between the second electrode and the second nanodot (second barrier). It should be easy. When both barriers are made of the same material, the first barrier is thinner than the second barrier. Further, by applying different voltages to the first electrode and the second electrode, a potential difference can be applied between the first electrode and the second electrode.

  Therefore, the charge injected from the first electrode to the first nanodot can be further moved to the second nanodot by the electric field resulting from the potential difference between the first electrode and the second electrode. Here, even if the potential difference between the first electrode and the second electrode disappears, the barrier between the first nanodot and the second nanodot (the first nanodot) in order to leak the charge to the first electrode. 3 barriers) and the first barrier. For this reason, leak can be further suppressed. Further, by increasing the number of nanodots between the first electrode and the second electrode, it is possible to increase the number of barriers against the leak as described above, and to further suppress the leak.

(Sixth embodiment)
The memory device of the sixth embodiment has substantially the same configuration except that the semiconductor substrate 111 in the memory device (third embodiment) of FIGS. 7A and 7B is an SOI substrate.

  In this case, in the memory element, a buried oxide film is formed on a semiconductor substrate (not shown), and an SOI layer (silicon layer) is further formed thereon. Diffusion layer regions 112 and 113 are formed in the SOI layer, and regions other than the diffusion layer regions 112 and 113 in the SOI layer are so-called body regions.

  This memory element also has the same operational effects as the memory element of the third embodiment. Furthermore, since the junction capacitance between the diffusion layer regions 112 and 113 and the body region can be remarkably reduced, the device can be increased in speed and power consumption can be reduced.

(Seventh embodiment)
13A and 13B show cross sections along the channel length direction of the nonvolatile memory element as the semiconductor memory device of the seventh embodiment, respectively.

  13A and 13B are the P-type high-concentration regions adjacent to the channel side of the N-type source / drain regions 112 and 113 in the memory device of FIG. 7A and FIG. 7B, respectively (third embodiment). 191 and 191 are added. The other configuration is substantially the same as that of the third embodiment.

The P-type impurity concentration (for example, boron) concentration in the P-type high concentration region 191 is set higher than the impurity concentration in other regions 192 in the channel region. An appropriate P-type impurity concentration in the P-type high concentration region 191 is, for example, approximately 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The P-type impurity concentration in the region 192 can be set to, for example, 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

  As described above, by providing the P-type high concentration region 191, the junction between the diffusion layer regions 112 and 113 and the semiconductor substrate 111 becomes steep immediately below the charge holding portions 161 and 162. For this reason, hot carriers are likely to be generated during writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the writing and erasing operations can be performed at high speed. Further, since the impurity concentration in the region 192 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current is large. Therefore, the reading speed is improved. Therefore, it is possible to obtain a memory element having a low rewrite voltage or a high rewrite speed and a high read speed.

  Further, P on the surface 111a of the semiconductor substrate 111 is adjacent to the end portions of the source / drain regions 112 and 113 and is located immediately below the charge holding portions 161 and 162 (that is, not directly below the gate electrode 117). By providing the mold high-concentration regions 191 and 191, the threshold value of the entire transistor is remarkably increased. The degree of this increase is significantly greater than when the P-type high concentration region 191 is provided immediately below the gate electrode 117. When write charges (electrons when the transistor is an N channel type) are accumulated in the nanodots 142 of the charge holding portions 161 and 162, this difference becomes even larger. On the other hand, when sufficient erasing charges (holes when the transistor is an N channel type) are accumulated in the nanodots 142 of the charge holding portion, the threshold value of the entire transistor is the channel region (region 192) under the gate electrode. Decreases to a threshold determined by the impurity concentration. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the P-type high concentration region 191, while the threshold value at the time of writing is greatly influenced. Therefore, P on the surface 111 a of the semiconductor substrate 111 is adjacent to the ends of the source / drain regions 112 and 113 and is located immediately below the charge holding portions 161 and 162 (that is, not directly below the gate electrode 117). By providing the mold high-concentration regions 191 and 191, only the threshold value at the time of writing varies greatly, and the memory effect (the difference between the threshold value at the time of writing and the erasing time) can be remarkably increased.

(Eighth embodiment)
14A and 14B show cross sections along the channel length direction of the nonvolatile memory element as the semiconductor memory device of the eighth embodiment, respectively.

  14A and 14B are the same as the memory elements (third embodiment) of FIGS. 7A and 7B, respectively, and the nanodots 142 of the charge holding portions 161 and 162 and the semiconductor in the silicon oxide film 141 as the second insulator. The thickness (T3) of the portion separating the surface 111a (channel region or well region) of the substrate 111 is set to be thinner than the thickness (T4) of the gate insulating film 114. The other configuration is substantially the same as that of the third embodiment.

  The gate insulating film 114 has a lower limit value in the thickness T4 due to a demand for withstand voltage during the rewrite operation of the memory element. However, since the thickness T3 of the silicon oxide film 141 does not receive a request for withstand voltage to the gate insulating film 114, it can be made thinner than the thickness T4 of the gate insulating film 114. By reducing the thickness T3 of the silicon oxide film 141 as the second insulator, it becomes easy to inject charges into the nanodots 142 of the charge holding portions 161 and 162, and the voltage for the write operation and the erase operation is reduced. Alternatively, the write operation and the erase operation can be performed at high speed. In addition, since the amount of charge induced in the channel region or the well region when charges are accumulated in the nanodots 142 increases, the memory effect can be increased.

  Therefore, by setting T3 <T4, the voltage of the write operation and the erase operation can be lowered or the write operation and the erase operation can be speeded up and the memory effect can be further increased without reducing the withstand voltage performance of the memory element. It becomes possible.

  Note that the thickness T3 of the silicon oxide film 141 as the second insulator is a limit that allows the uniformity and film quality of the manufacturing process to be maintained at a constant level and that the holding characteristics are not extremely deteriorated. More preferably, it is 8 nm or more.

(Ninth embodiment)
15A and 15B show cross sections along the channel length direction of the nonvolatile memory element as the semiconductor memory device of the ninth embodiment, respectively.

  15A and 15B are the same as those in FIGS. 7A and 7B (third embodiment), and the nanodots 142 of the charge holding portions 161 and 162 and the semiconductor in the silicon oxide film 141 as the second insulator. The thickness (T3) of the portion separating the surface 111a (channel region or well region) of the substrate 111 is set to be thicker than the thickness (T4) of the gate insulating film 114. The other configuration is substantially the same as that of the third embodiment.

  The gate insulating film 114 has an upper limit on the thickness T4 due to the demand for preventing the short channel effect of the memory element. However, since the thickness T3 of the silicon oxide film 141 is irrelevant to the request for preventing the short channel effect, it can be made thicker than the thickness T4 of the gate insulating film 114. By increasing the thickness T3 of the silicon oxide film 141 as the second insulator, it is possible to prevent the charge accumulated in the nanodots 142 of the charge holding portions 161 and 162 from being dissipated and to improve the holding characteristics of the memory element. It becomes.

  Therefore, by setting T3> T4, the retention characteristics can be improved without deteriorating the short channel effect of the memory element.

  Note that the thickness T3 of the silicon oxide film 141 as the second insulator is preferably 20 nm or less in consideration of a decrease in the rewrite speed.

It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 1st Embodiment produced with the manufacturing method of this invention. It is a figure which shows the modification of the memory element of FIG. 1A. FIG. 1B is an enlarged view of the vicinity of a charge holding unit on the left side of the memory element shown in FIG. 1A. FIG. 3 is an enlarged view of the vicinity of a charge holding unit on the left side of the memory element shown in FIG. 1B. It is a figure which shows the energy diagram with respect to the electron in the cut surface line A-A 'in FIG. 2A. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. FIG. 1B is a diagram showing a manufacturing process of the memory element shown in FIG. 1B. It is a figure which shows the manufacturing process of the memory element shown to FIG. 1A. It is a figure which shows the manufacturing process of the memory element shown to FIG. 1A. It is a figure which shows the manufacturing process of the memory element shown to FIG. 1A. It is a figure which shows the manufacturing process of the memory element shown to FIG. 1A. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 2nd Embodiment produced with the manufacturing method of this invention. FIG. 6B is a diagram showing a modification of the memory element in FIG. 6A. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 3rd Embodiment produced by the manufacturing method of this invention. It is a figure which shows the modification of the memory element of FIG. 7A. FIG. 7B is an enlarged view of the vicinity of the charge holding unit on the right side of the memory element shown in FIG. 7A. FIG. 7B is an enlarged view of the vicinity of the charge holding unit on the right side of the memory element shown in FIG. 7B. FIG. 7B is a diagram illustrating optimization of the arrangement in the channel length direction of the gate electrode, the charge holding unit, and the source / drain region in the memory element of FIG. 7A. FIG. 7B is a diagram illustrating optimization of the arrangement in the channel length direction of the gate electrode, the charge holding unit, and the source / drain region in the memory element of FIG. 7B. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 5th Embodiment of this invention. FIG. 11 is a schematic enlarged view of the vicinity of a charge holding unit on the left side of the memory element of FIG. 10. FIG. 11 is a diagram schematically showing charge holding portions on both sides of the memory element of FIG. 10. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 7th Embodiment produced by the manufacturing method of this invention. It is a figure which shows the modification of the memory element of FIG. 13A. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 8th Embodiment produced by the manufacturing method of this invention. FIG. 14B is a diagram showing a modification of the memory element in FIG. 14A. It is a figure which shows the cross section along the channel length direction of the non-volatile memory element as a semiconductor memory device of 9th Embodiment produced by the manufacturing method of this invention. It is a figure which shows the modification of the memory element of FIG. 15A. It is a figure which shows the structure of the conventional non-volatile memory.

11, 111, 2300 Semiconductor substrate 13, 117, 2303 Gate electrode 61, 62, 161, 162, 2361, 2362 Charge holding unit 15, 142, 2306, 2306a, 2306b, 2306c Nanodot

Claims (3)

A method of manufacturing a semiconductor memory device for producing a semi-conductor memory device,
The semiconductor memory device is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a substantially rectangular cross section formed on the gate insulating film;
Two charge holding portions formed at positions corresponding to both sides of the gate electrode above the semiconductor substrate and spaced apart from the gate electrode laterally;
Two diffusion layer regions formed separately from the gate electrode and the two charge holding portions so as to occupy at least portions corresponding to both sides of the gate electrode on the surface of the semiconductor substrate;
A channel region disposed under the gate electrode,
The charge holding unit includes a second insulating layer in which nanodots made of a first material having a function of accumulating charges are disposed closer to the surface of the semiconductor substrate and / or the side wall of the gate electrode than the nanodots. Having a structure sandwiched between a body and a third insulator disposed on the opposite side of the second insulator with respect to the nanodot,
The second insulator and the third insulator are different from each other in density, material, or crystal structure, and the nanodot is connected to the gate of the interface between the second insulator and the third insulator. Formed in a self-aligned manner in a plane substantially parallel to the surface of the insulating film,
The amount of current flowing from the one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode is changed according to the amount of charges held in the nanodots of the charge holding units. And
The above manufacturing method is
Forming the gate insulating film made of a silicon oxynitride film on the semiconductor substrate;
Forming the gate electrode having a substantially rectangular cross section on the gate insulating film;
A silicon oxide film serving as a material for the second insulator so as to cover the gate electrode and the semiconductor substrate corresponding to both sides of the gate electrode with a thickness reflecting the cross-sectional shape of the gate electrode on the surface side Forming by CVD or deposition by thermal oxidation,
Depositing a silicon nitride film as a material of the third insulator by a CVD method so as to cover the silicon oxide film with a thickness reflecting the cross-sectional shape of the gate electrode on the surface side;
Depositing a sacrificial silicon oxide film by a CVD method so as to cover the silicon nitride film at a thickness that fills the corners formed by the L-shaped cross section of the silicon nitride film on both sides of the gate electrode;
Etch back by anisotropic etching is performed to form a silicon oxide film serving as the second insulator material on both sides of the gate electrode and a silicon nitride film serving as the third insulator material in an L-shaped cross section. Forming a sidewall spacer on both sides of the gate electrode, leaving the sacrificial silicon oxide film at a corner portion formed by an L-shaped cross section of the silicon nitride film;
Ion implantation using the gate electrode and sidewall spacer as a mask to form the two diffusion layer regions laterally separated from the gate electrode,
Removing the sacrificial silicon oxide film forming the sidewall spacer by anisotropic etching under an etching condition in which the etching rate of the silicon nitride film is lower than the etching rate of the silicon oxide film, and exposing each of the silicon nitride films; ,
Introducing the first material to be the nanodot through each silicon nitride film by ion implantation;
A method for manufacturing a semiconductor memory device, comprising: performing at least heat treatment to form nanodots made of the first material. The method of manufacturing a semiconductor memory device according to claim 1 ,
A semiconductor memory comprising: introducing the first material to be the nanodots through the silicon nitride films; and removing the silicon nitride films to deposit a silicon oxide film to be an interlayer insulating film. Device manufacturing method. The method of manufacturing a semiconductor memory device according to claim 1 ,
A method for manufacturing a semiconductor memory device, characterized in that in the step of forming the nanodots by performing the heat treatment, the heat treatment is performed in an atmosphere containing oxygen.

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