JP5028044B2 - Manufacturing method of semiconductor thin film - Google Patents

Manufacturing method of semiconductor thin film Download PDF

Info

Publication number
JP5028044B2
JP5028044B2 JP2006203478A JP2006203478A JP5028044B2 JP 5028044 B2 JP5028044 B2 JP 5028044B2 JP 2006203478 A JP2006203478 A JP 2006203478A JP 2006203478 A JP2006203478 A JP 2006203478A JP 5028044 B2 JP5028044 B2 JP 5028044B2
Authority
JP
Japan
Prior art keywords
substrate
electrode
thin film
semiconductor thin
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006203478A
Other languages
Japanese (ja)
Other versions
JP2008034469A (en
Inventor
栄史 栗部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaneka Corp
Original Assignee
Kaneka Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaneka Corp filed Critical Kaneka Corp
Priority to JP2006203478A priority Critical patent/JP5028044B2/en
Publication of JP2008034469A publication Critical patent/JP2008034469A/en
Application granted granted Critical
Publication of JP5028044B2 publication Critical patent/JP5028044B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は半導体薄膜の製造方法に関し、さらに詳細には、大面積の基板表面に均一な半導体薄膜を成膜するために好ましく用いられるプラズマCVD方法を用いた半導体薄膜の製造方法に関する。 The present invention relates to the production how the semiconductor thin film, and more particularly relates to the production how the semiconductor thin film using the preferred plasma CVD method used for forming a uniform semiconductor thin film on a substrate surface having a large area .

液晶表示パネルの透明基板上に形成されるTFT(薄膜トランジスタ)アレイ、薄膜太陽電池、複写機の感光ドラム上の感光層などにおける種々の半導体薄膜の形成のために、プラズマCVD方法による薄膜の成膜技術が利用されている。近年、液晶表示パネルにおいては画面の大型化が望まれており、薄膜太陽電池においても大きな発電能力と生産効率の向上のために大面積化が求められている。そのため、大面積の半導体薄膜を形成することができるプラズマCVD方法やプラズマCVD装置が求められている。   Thin film deposition by plasma CVD method for the formation of various semiconductor thin films on TFT (thin film transistor) arrays, thin film solar cells, photosensitive layers on photocopier drums, etc. formed on transparent substrates of liquid crystal display panels Technology is being used. In recent years, a liquid crystal display panel has been desired to have a large screen, and a thin film solar cell is also required to have a large area in order to improve a large power generation capacity and production efficiency. Therefore, a plasma CVD method and a plasma CVD apparatus capable of forming a large-area semiconductor thin film are required.

図15は従来のプラズマCVD装置の構成を模式的に表す縦断面図である。図15のプラズマCVD装置(半導体薄膜製造装置)61は大面積の半導体薄膜の製造に対応可能な縦型プラズマCVD装置であり、基本的に、真空チャンバー(成膜室)62内に電極65及び温調パネル(ヒータ)66が備えられたものである。そして、使用時において、半導体薄膜を成膜すべき基板(基体)80が装着された支持部材68を真空チャンバー62の上部から挿入し、電極65と基板80とが対向する位置に支持部材68を配置する。   FIG. 15 is a longitudinal sectional view schematically showing the configuration of a conventional plasma CVD apparatus. A plasma CVD apparatus (semiconductor thin film manufacturing apparatus) 61 shown in FIG. 15 is a vertical plasma CVD apparatus that can be used for manufacturing a semiconductor thin film having a large area. A temperature control panel (heater) 66 is provided. In use, a support member 68 on which a substrate (substrate) 80 on which a semiconductor thin film is to be formed is inserted from above the vacuum chamber 62, and the support member 68 is placed at a position where the electrode 65 and the substrate 80 face each other. Deploy.

真空チャンバー62はステンレススチールやアルミニウム合金等からなる直方体状の箱である。真空チャンバー62には、図示しない排気真空ポンプ、配管、及び圧力調整弁等が接続され、真空チャンバー62内を所定の圧力に減圧することが可能である。一方、電極65はカソード電極として機能するものであり、図示しない高周波電力供給装置が接続されている。電極65には、半導体薄膜を成膜するための原料ガスを供給するためのガス供給装置および配管(図示せず)が接続され、電極65の電極面に開口形成されたガス流出孔から原料ガスが排出される。   The vacuum chamber 62 is a rectangular parallelepiped box made of stainless steel, aluminum alloy, or the like. The vacuum chamber 62 is connected to an unillustrated exhaust vacuum pump, piping, a pressure control valve, and the like, and the inside of the vacuum chamber 62 can be depressurized to a predetermined pressure. On the other hand, the electrode 65 functions as a cathode electrode and is connected to a high-frequency power supply device (not shown). A gas supply device and piping (not shown) for supplying a source gas for forming a semiconductor thin film are connected to the electrode 65, and the source gas is supplied from a gas outflow hole formed in the electrode surface of the electrode 65. Is discharged.

図16は基板80と支持部材68の要部の拡大断面図である。支持部材68は中央に開口76を有する矩形枠状をなし、開口76の端部には段部78が形成されている。基板80の装着時において、段部78に基板80の一方の面(成膜面)の周辺部が係合し、さらに、基板80の他方の面(裏面)には背板81が配置される。背板81は、支持部材68の背面取付面開口部92の周辺部に設けられたクランプ79によって支持部材68に着脱可能に固定されている。それによって、基板80は支持部材68に対して位置決めされ、かつ支持部材68の開口76から基板80の一部が露出した状態で保持および固定される。基板80の露出面82は、支持部材68の面状部85によって包囲されている。面状部85は基板80の露出面82とともに放電面を形成している。一般に、面状部85は平坦で1つの平面からなる。
上記のように基板80が支持部材68に装着された状態において、基板80と支持部材68とが一体となって基板支持電極91を構成し、電極65に対向するように配置される。
FIG. 16 is an enlarged cross-sectional view of the main parts of the substrate 80 and the support member 68. The support member 68 has a rectangular frame shape having an opening 76 in the center, and a step 78 is formed at the end of the opening 76. When the substrate 80 is mounted, the peripheral portion of one surface (film formation surface) of the substrate 80 is engaged with the stepped portion 78, and the back plate 81 is disposed on the other surface (back surface) of the substrate 80. . The back plate 81 is detachably fixed to the support member 68 by a clamp 79 provided at the periphery of the back surface mounting surface opening 92 of the support member 68. Accordingly, the substrate 80 is positioned with respect to the support member 68 and is held and fixed in a state where a part of the substrate 80 is exposed from the opening 76 of the support member 68. The exposed surface 82 of the substrate 80 is surrounded by the planar portion 85 of the support member 68. The planar portion 85 forms a discharge surface together with the exposed surface 82 of the substrate 80. In general, the planar portion 85 is flat and has one plane.
In the state where the substrate 80 is mounted on the support member 68 as described above, the substrate 80 and the support member 68 are integrated to form the substrate support electrode 91 and are disposed so as to face the electrode 65.

図17に示すように、支持部材68に段部78を設けずに基板80と背板81を保持および固定することもできる。図17の基板80は、支持部材68の開口76を裏面から覆うように配置され、さらに基板80の裏面から背板81が配置され、背面取付面開口部92の周辺部に設けられた複数のクリップ77によって支持部材68に固定されている。   As shown in FIG. 17, the substrate 80 and the back plate 81 can be held and fixed without providing the support member 68 with the stepped portion 78. 17 is disposed so as to cover the opening 76 of the support member 68 from the back surface, and further, a back plate 81 is disposed from the back surface of the substrate 80, and a plurality of portions provided in the peripheral portion of the back mounting surface opening 92 are provided. The clip 77 is fixed to the support member 68.

支持部材68は、例えばSUS304やSUS430等のステンレススチールやアルミニウム合金等、場合によってはアルミニウム合金表面に別途コーティングされた耐熱性および剛性を有する材質によって形成されている。一方、背板81は耐熱性と熱伝導の優れたカーボン等によって形成されている。また真空チャンバー62内の温調パネル66により、基板80は背板81を経由して一定温度に調整される。   The support member 68 is made of, for example, stainless steel such as SUS304 or SUS430, an aluminum alloy, or the like, or a material having heat resistance and rigidity that is separately coated on the surface of the aluminum alloy in some cases. On the other hand, the back plate 81 is formed of carbon having excellent heat resistance and heat conduction. Further, the substrate 80 is adjusted to a constant temperature via the back plate 81 by the temperature control panel 66 in the vacuum chamber 62.

基板80の露出面82に薄膜を成膜する手順は以下のとおりである。まず、図15に示すように、基板80の露出面82が電極65に対向する位置に、基板支持電極91(基板80が装着された支持部材68)を配置する。このとき、電極65と基板支持電極91との間にプラズマ発生空間が形成される。次に、原料ガスを電極65表面のガス流出孔(図示せず)からプラズマ発生空間に供給すると共に、真空チャンバー62内がある一定圧力になるよう原料ガスの排気を実施する。次に、電極65に高周波電力を印加し、電極65と基板支持電極91との間(プラズマ発生空間)にプラズマを発生させ、基板80の露出面82に半導体薄膜を成膜する。   The procedure for forming a thin film on the exposed surface 82 of the substrate 80 is as follows. First, as shown in FIG. 15, the substrate support electrode 91 (the support member 68 to which the substrate 80 is mounted) is disposed at a position where the exposed surface 82 of the substrate 80 faces the electrode 65. At this time, a plasma generation space is formed between the electrode 65 and the substrate support electrode 91. Next, the source gas is supplied from the gas outflow hole (not shown) on the surface of the electrode 65 to the plasma generation space, and the source gas is exhausted so that the inside of the vacuum chamber 62 has a certain pressure. Next, high-frequency power is applied to the electrode 65 to generate plasma between the electrode 65 and the substrate support electrode 91 (plasma generation space), and a semiconductor thin film is formed on the exposed surface 82 of the substrate 80.

なお、図15に示すプラズマCVD装置では、基板80の露出面82が外側を向いて設置されるが、図18に示すような露出面82が内側を向いて設置される「1電極両面放電タイプ」のプラズマCVD装置もある。本プラズマCVD装置の場合には、基板80が装着された支持部材68は真空チャンバー62の上部からではなく正面から水平方向に挿入されるのが通常である。   In the plasma CVD apparatus shown in FIG. 15, the exposed surface 82 of the substrate 80 is installed facing outward, but the exposed surface 82 as shown in FIG. There is also a plasma CVD apparatus. In the case of this plasma CVD apparatus, the support member 68 on which the substrate 80 is mounted is usually inserted horizontally from the front rather than from the upper part of the vacuum chamber 62.

一般に、プラズマCVD方法及びプラズマCVD装置においては、成膜領域(プラズマ発生空間の一部であって、基板露出面を覆う領域)に生成するプラズマの均一性が、基板上に成膜される半導体薄膜の膜厚の均一性および均質性に大きな影響を与える。そのため、成膜領域におけるプラズマをより均一化するための工夫が行われている。例えば、特許文献1に記載の発明では、水平型CVD装置において、カソード電極に給電される高周波電力の周波数がVHF帯にある場合に、大面積平行平板型成膜装置において周辺部でのプラズマ電界強度が減少するために、基板支持電極(アノード電極)と対向するカソード電極の周辺部電極間距離を周辺部で局所的に狭くすることで、周辺部のプラズマ電界強度を強め、成膜領域におけるプラズマの均一化を図っている。   Generally, in a plasma CVD method and a plasma CVD apparatus, the uniformity of plasma generated in a film formation region (a part of a plasma generation space and covering an exposed surface of a substrate) is a semiconductor film formed on a substrate. It has a great influence on the uniformity and uniformity of the film thickness. Therefore, a device for making the plasma in the film formation region more uniform has been devised. For example, in the invention described in Patent Document 1, in the horizontal CVD apparatus, when the frequency of the high-frequency power supplied to the cathode electrode is in the VHF band, the plasma electric field at the peripheral portion in the large area parallel plate type film forming apparatus. In order to reduce the strength, the distance between the peripheral electrodes of the cathode electrode facing the substrate support electrode (anode electrode) is locally narrowed in the peripheral portion, thereby increasing the plasma electric field strength in the peripheral portion and The plasma is made uniform.

一方、プラズマの均一性を大きく支配するのは電極間距離であり、特に大面積基板への成膜を行う際には、大型化された各電極間の平行度が重要となる。更に、生産性の向上を目的として成膜速度を向上させるために、電極に投入する高周波電力の投入パワーを大きくする、投入する電力の周波数を大きくする(高高周波数化)、またはチャンバー内の圧力を大きくし基板支持電極とカソード電極との間の電極間距離を小さくする、といったことが行なわれている。ところが、これらの場合には更に高精度な電極間の平行度が要求される。   On the other hand, it is the distance between the electrodes that largely controls the uniformity of the plasma. Particularly, when forming a film on a large-area substrate, the parallelism between the enlarged electrodes becomes important. Furthermore, in order to improve the deposition rate for the purpose of improving productivity, the input power of the high frequency power input to the electrode is increased, the frequency of the input power is increased (high frequency), or the inside of the chamber For example, the pressure is increased to reduce the distance between the substrate support electrode and the cathode electrode. However, in these cases, a higher degree of parallelism between the electrodes is required.

特許文献2に記載の発明では、大面積の平行平板型高周波プラズマCVD装置において、基板の成膜面とカソード電極面との平行度を測定するための基準面を設定し、基板電極(成膜面)とカソード電極との電極間距離が12mm以下の所定値で、基板電極とカソード電極の平行度を1mm以内に調整し、基板に成膜される半導体薄膜の膜厚分布のばらつきを所定範囲内に収めている。
特開平9−312268号公報 特開2002−270527号公報
In the invention described in Patent Document 2, in a parallel plate high-frequency plasma CVD apparatus having a large area, a reference plane for measuring the parallelism between the film formation surface of the substrate and the cathode electrode surface is set, and the substrate electrode (film formation) is determined. The distance between the surface) and the cathode electrode is a predetermined value of 12 mm or less, the parallelism of the substrate electrode and the cathode electrode is adjusted to within 1 mm, and the variation in the film thickness distribution of the semiconductor thin film formed on the substrate is within the predetermined range. It is housed in.
JP-A-9-31268 JP 2002-270527 A

前述のように、大面積化および成膜速度の向上のために、大面積のカソード電極および基板を用い、電極間距離をできるだけ小さくし、高パワー・高周波数の電力を投入し、半導体薄膜の成膜が行われている。その際に問題となるのが、成膜領域におけるプラズマの安定・均一化である。すなわち、成膜時において基板上のプラズマが不均一であると、基板上の半導体薄膜の膜厚や膜質の分布が不均一となり、その局所的なバラツキにより、半導体薄膜全体の性能を低下させる大きな原因となる。そして、基板面積が大きくなるに従い、また成膜速度の向上を実現するための高周波電力のパワー増大や高高周波数化につれて、プラズマの均一性を保つことはより難しくなる。その際、重要となるのが、カソード電極の電極面の平面度、基板支持電極の平面度、及び、これらの電極間の平行度である。   As described above, in order to increase the area and improve the deposition rate, a large area cathode electrode and substrate are used, the distance between the electrodes is made as small as possible, high power and high frequency power is input, and the semiconductor thin film A film is being formed. At that time, the problem is the stabilization and homogenization of plasma in the film formation region. That is, if the plasma on the substrate is non-uniform during film formation, the film thickness and film quality distribution of the semiconductor thin film on the substrate become non-uniform, and the local variation greatly reduces the performance of the entire semiconductor thin film. Cause. As the substrate area increases, it becomes more difficult to maintain the uniformity of the plasma as the power of the high-frequency power is increased or the frequency is increased to improve the deposition rate. At that time, what is important is the flatness of the electrode surface of the cathode electrode, the flatness of the substrate support electrode, and the parallelism between these electrodes.

しかしながら、1m□程度やそれ以上の大面積基板に半導体薄膜を成膜するときは、カソード電極と基板支持電極のサイズがいずれも1m□を越えることとなり、これらの平面度を保つこと、並びに、カソード電極と基板支持電極の平行度を保つことは、機械加工精度上、組み立て精度上あるいは真空時や加熱時の変形等により困難である。また、同じ1mmの電極平面度の悪化や電極間の平行度の悪化であっても、電極間距離が20mmから10mmに小さくなった場合には、そのバラツキの割合としては5%から10%と、その影響が大きくなる。その結果、電極間距離がより小さい場合には、成膜された半導体薄膜の膜厚・膜質のバラツキが大きくなり、半導体薄膜全体の性能は格段に低下する。   However, when a semiconductor thin film is formed on a large area substrate of about 1 m □ or more, the size of the cathode electrode and the substrate support electrode both exceeds 1 m □, and maintaining these flatnesses, It is difficult to maintain the parallelism between the cathode electrode and the substrate support electrode due to machining accuracy, assembly accuracy, or deformation during vacuum or heating. Further, even if the electrode flatness of the same 1 mm is deteriorated or the parallelism between the electrodes is deteriorated, when the distance between the electrodes is reduced from 20 mm to 10 mm, the variation ratio is 5% to 10%. , The effect will be greater. As a result, when the distance between the electrodes is smaller, the variation in film thickness and film quality of the formed semiconductor thin film becomes large, and the performance of the entire semiconductor thin film is remarkably lowered.

図15に示す従来のプラズマCVD装置においては、電極65の平面度、基板支持電極91の平面度、及び、電極65と基板支持電極91との間(電極間)の平行度が理想的に保たれている場合には、図19(a)に示すように、プラズマ発生空間内の成膜領域にプラズマ95がうまく閉じ込められ、基板の周辺部までに均一な半導体薄膜が成膜される。しかしながら、電極間の平行度が保たれていない場合には、成膜領域におけるプラズマの均一性が低下し、基板の成膜面に成膜される半導体薄膜の均一性および均質性が低下する。   In the conventional plasma CVD apparatus shown in FIG. 15, the flatness of the electrode 65, the flatness of the substrate support electrode 91, and the parallelism between the electrode 65 and the substrate support electrode 91 (between the electrodes) are ideally maintained. In the case where it is leaned, as shown in FIG. 19A, the plasma 95 is well confined in the film formation region in the plasma generation space, and a uniform semiconductor thin film is formed up to the periphery of the substrate. However, when the parallelism between the electrodes is not maintained, the uniformity of the plasma in the film formation region decreases, and the uniformity and homogeneity of the semiconductor thin film formed on the film formation surface of the substrate decreases.

例えば、圧力領域や高周波電力の大きさによりその挙動は逆にもなり得るが、電極間距離が小さい場合には、成膜領域に閉じ込められるべきプラズマ95が支持部材68の面状部85付近にまで広がってしまう。プラズマ95の広がり具合はその電極間距離に依存し、その度合いが小さければ図19(b)の様な状態、大きければ図19(c)の様な状態となる。プラズマの広がりが小さい図19(b)の場合は、成膜領域におけるプラズマ95の均一性低下が許容範囲に収まることもあるが、図19(c)の様にプラズマ95の広がりが大きい場合には、支持部材68の面状部85でのプラズマ95に全体のプラズマエネルギーを消耗され、その結果、基板80の露出面82上のプラズマ強度が弱くなり、露出面82上に成膜される半導体薄膜の膜質が変化してしまうことがある。   For example, the behavior may be reversed depending on the pressure region and the magnitude of the high-frequency power, but when the interelectrode distance is small, the plasma 95 to be confined in the film formation region is near the planar portion 85 of the support member 68. Will spread. The degree of spread of the plasma 95 depends on the distance between the electrodes. If the degree is small, the state shown in FIG. 19B is obtained, and if the degree is large, the state shown in FIG. 19C is obtained. In the case of FIG. 19B in which the plasma spread is small, the uniformity degradation of the plasma 95 in the film formation region may fall within an allowable range, but when the plasma 95 spread is large as shown in FIG. The entire plasma energy is consumed by the plasma 95 in the planar portion 85 of the support member 68, and as a result, the plasma intensity on the exposed surface 82 of the substrate 80 becomes weak, and the semiconductor film is formed on the exposed surface 82. The film quality of the thin film may change.

また同じく、圧力領域や高周波電力の大きさによりその挙動は逆にもなり得るが、電極間距離が大きくなった場合には、図19(d)のように生成したプラズマ95が収縮し、基板80の露出面82上にプラズマ95が広がりきれず、露出面82の周辺部で半導体薄膜の膜厚が薄くなったりし、膜質が変化してしまう。   Similarly, the behavior may be reversed depending on the pressure region and the magnitude of the high frequency power, but when the distance between the electrodes increases, the generated plasma 95 contracts as shown in FIG. The plasma 95 cannot be spread on the exposed surface 82 of the 80, and the film thickness of the semiconductor thin film becomes thin at the periphery of the exposed surface 82, and the film quality changes.

特許文献2に記載のように、電極間距離の調整を緻密に実施することで、電極間の平行度はある程度改善される。しかしながら、基板支持電極およびカソード電極の製作精度や組立精度、更には真空や熱による変形により、それらの平面度を安定して確保することは難しい。   As described in Patent Document 2, the parallelism between the electrodes is improved to some extent by precisely adjusting the distance between the electrodes. However, it is difficult to stably ensure the flatness of the substrate support electrode and the cathode electrode due to the manufacturing accuracy and assembly accuracy, as well as deformation due to vacuum or heat.

さらに、特許文献1に記載のように、水平型CVD装置においても電極外縁部で電界強度が減少し、半導体薄膜の膜厚が薄くなる問題に対しては、カソード電極を外縁部にかけて除々に厚くなるテーパ状として電極間距離を小さくして、外縁部での電界分布の改善を実施している。しかしながら、電極間の平行度がよくない場合には、外縁部の電界強度が強くなり過ぎ、プラズマが不均一となり、半導体薄膜への悪影響が懸念される。また、カソード電極をテーパ状とするとカソード電極が汚れやすくなり、メンテナンス性が極度に落ちる。さらに、カソード電極の電極面に設けられたガス流出孔の付近をテーパ状とすると、ガス流出孔の長さが変化し、各ガス流出孔の圧力損失に差が生じることで、ガス供給量の不均一性が発生し、半導体薄膜の膜厚および膜質の均一性が損なわれるおそれがある。   Further, as described in Patent Document 1, in the horizontal CVD apparatus, the problem that the electric field strength decreases at the outer edge of the electrode and the film thickness of the semiconductor thin film becomes thin is gradually increased from the cathode electrode to the outer edge. As a taper shape, the distance between the electrodes is reduced to improve the electric field distribution at the outer edge. However, when the parallelism between the electrodes is not good, the electric field strength at the outer edge becomes too strong, the plasma becomes non-uniform, and there is a concern about adverse effects on the semiconductor thin film. Further, when the cathode electrode is tapered, the cathode electrode is easily soiled, and maintenance performance is extremely lowered. Furthermore, when the vicinity of the gas outflow hole provided on the electrode surface of the cathode electrode is tapered, the length of the gas outflow hole changes, and the difference in pressure loss of each gas outflow hole causes a difference in gas supply amount. Inhomogeneity may occur, and the uniformity of the film thickness and film quality of the semiconductor thin film may be impaired.

本発明の目的は、プラズマを安定・均一化でき、大面積で均一な半導体薄膜を成膜することができるプラズマCVD方法を用いた半導体薄膜の製造方法を提供することにある。 An object of the present invention, the plasma can be stabilized, equalized, to provide a preparation how the semiconductor thin film using a plasma CVD method capable of depositing a uniform semiconductor thin film in a large area.

上記した課題を解決するための請求項1に記載の発明は、 半導体薄膜を成膜すべき基体を支持部材に装着して該基体の一部又は全部を該支持部材から露出させ、電極を備えた成膜室内において基体露出面が電極面に対向するように前記支持部材を配置して、基体が装着された支持部材と電極との間にプラズマ発生空間を形成させ、前記電極に高周波電力を供給して放電を発生させ、基体露出面に半導体薄膜を成膜するプラズマCVD工程を含む半導体薄膜の製造方法であって、前記プラズマ発生空間にプラズマを遮蔽する壁を設けるものであり、前記支持部材は、基体露出面の外縁に位置し且つ前記電極面に対向する面状部を有し、前記面状部に前記壁を設け、前記面状部と前記基体露出面とは段部を形成しており、電極面と面状部との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下であり、前記段部は、面状部から基体露出面に向かって高さが小さくなるテーパ状に形成されていることを特徴とする半導体薄膜の製造方法ある。 An invention according to claim 1 for solving the above-described problem is provided with an electrode, wherein a substrate on which a semiconductor thin film is to be formed is mounted on a support member, and a part or all of the substrate is exposed from the support member. The support member is disposed in the film forming chamber so that the substrate exposed surface faces the electrode surface, a plasma generation space is formed between the support member on which the substrate is mounted and the electrode, and high-frequency power is applied to the electrode. A method of manufacturing a semiconductor thin film including a plasma CVD process for forming a semiconductor thin film on an exposed surface of a substrate by supplying a discharge to form a semiconductor thin film, wherein a wall for shielding plasma is provided in the plasma generation space, and the support The member has a planar portion located on the outer edge of the substrate exposed surface and opposed to the electrode surface, the wall is provided on the planar portion, and the planar portion and the substrate exposed surface form a stepped portion. The distance between the electrode surface and the planar portion Is smaller than the distance between the electrode surface and the substrate exposed surface, and the height of the stepped portion is 0.5 mm or more and 4.0 mm or less, and the stepped portion has a height from the planar portion toward the substrate exposed surface. There is a method for manufacturing a semiconductor thin film characterized by being formed in a taper shape in which is reduced .

本発明の半導体薄膜の製造方法は、プラズマCVD工程により半導体薄膜を成膜するものである。すなわち、本発明の半導体薄膜の製造方法は、支持部材に装着された基体に薄膜を成膜するものであり、基体が装着された支持部材と電極との間のプラズマ発生空間にプラズマを遮蔽する壁を設ける。本発明の半導体薄膜の製造方法では、プラズマ発生空間にプラズマを遮蔽する壁を設けるので、基体露出面を覆う領域(成膜領域)に生じたプラズマが成膜領域からプラズマ発生空間外に向かって広がろうとしても、壁に衝突し、プラズマが成膜領域に閉じ込められる。そのため、成膜領域においてプラズマがより均一化される。その結果、基体露出面に成膜される半導体薄膜の膜厚がより均一化され、膜質もより均質化されたものとなる。   The method for producing a semiconductor thin film of the present invention forms a semiconductor thin film by a plasma CVD process. That is, the method for producing a semiconductor thin film according to the present invention forms a thin film on a substrate mounted on a support member, and shields plasma in a plasma generation space between the support member mounted on the substrate and the electrode. Establish walls. In the method for producing a semiconductor thin film according to the present invention, since a wall for shielding plasma is provided in the plasma generation space, the plasma generated in the region (film formation region) covering the substrate exposed surface is directed from the film formation region to the outside of the plasma generation space. Even if it tries to spread, it collides with the wall and the plasma is confined in the film formation region. Therefore, the plasma is made more uniform in the film formation region. As a result, the film thickness of the semiconductor thin film formed on the substrate exposed surface is made more uniform, and the film quality becomes more uniform.

また、本発明のプラズマCVD方法では、壁によりプラズマを成膜領域に閉じ込める構成を採用したので、電極の電極面の平面度、基板支持電極の平面度、電極間の平行度、といった他の要素の影響を吸収することができ、安定的に成膜領域のプラズマを均一化することができる。   Further, in the plasma CVD method of the present invention, since the structure in which the plasma is confined in the film formation region by the wall is adopted, other factors such as the flatness of the electrode surface of the electrode, the flatness of the substrate supporting electrode, and the parallelism between the electrodes Can be absorbed, and the plasma in the film formation region can be made uniform in a stable manner.

また本発明の半導体薄膜の製造方法では、用いる支持部材の形状に特徴がある。すなわち、従来のプラズマCVD方法を用いる半導体薄膜の製造方法では、用いる支持部材の面状部は平坦で1つの平面からなるが、本発明の半導体薄膜の製造方法では、用いる支持部材の面状部にプラズマを遮蔽する壁を設ける。本発明の半導体薄膜の製造方法では、基体の支持部材として面状部に壁を設けたものを使用するので、成膜領域に生じたプラズマが、基体露出面から支持部材の面状部外に向かって広がろうとしても、面状部に設けられた壁に衝突し、プラズマが成膜領域に閉じ込められる。そのため、成膜領域においてプラズマがより均一化される。その結果、基体露出面に成膜される半導体薄膜の膜厚がより均一化され、膜質もより均質化されたものとなる。   Further, the method for producing a semiconductor thin film according to the present invention is characterized by the shape of the supporting member used. That is, in the manufacturing method of the semiconductor thin film using the conventional plasma CVD method, the planar portion of the supporting member to be used is flat and has one plane. However, in the manufacturing method of the semiconductor thin film of the present invention, the planar portion of the supporting member to be used is used. A wall for shielding plasma is provided. In the method for producing a semiconductor thin film according to the present invention, the support member for the substrate is provided with a wall on the planar portion, so that the plasma generated in the film forming region is exposed from the substrate exposed surface to the outside of the planar portion of the support member. Even if it is going to spread, it collides with a wall provided in the planar portion, and the plasma is confined in the film formation region. Therefore, the plasma is made more uniform in the film formation region. As a result, the film thickness of the semiconductor thin film formed on the substrate exposed surface is made more uniform, and the film quality becomes more uniform.

また本発明の半導体薄膜の製造方法では、前記面状部と前記基体露出面とは段部を形成しており、電極面と面状部との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下である。かかる構成により、基体露出面から支持部材の面状部へのプラズマの変動が小さくなり、プラズマがより均一化される。 In the method for producing a semiconductor thin film of the present invention, the planar portion and the substrate exposed surface form a stepped portion, and the distance between the electrode surface and the planar portion is greater than the distance between the electrode surface and the substrate exposed surface. And the height of the step is 0.5 mm or more and 4.0 mm or less. With this configuration, plasma fluctuation from the substrate exposed surface to the planar portion of the support member is reduced, and the plasma is made more uniform.

また本発明の半導体薄膜の製造方法では、前記段部は、面状部から基体露出面に向かって高さが小さくなるテーパ状に形成されている。かかる構成により、基体露出面から基体側電極対向面へのプラズマの変動が極めて小さくなり、プラズマがより均一化される。 In the method for producing a semiconductor thin film of the present invention, the stepped portion is formed in a tapered shape whose height decreases from the planar portion toward the substrate exposed surface. With this configuration, plasma fluctuation from the substrate exposed surface to the substrate-side electrode facing surface becomes extremely small, and the plasma is made more uniform.

請求項に記載の発明は、半導体薄膜を成膜すべき基体を支持部材に装着して該基体の一部又は全部を該支持部材から露出させ、電極を備えた成膜室内において基体露出面が電極面に対向するように前記支持部材を配置して、基体が装着された支持部材と電極との間にプラズマ発生空間を形成させ、前記電極に高周波電力を供給して放電を発生させ、基体露出面に半導体薄膜を成膜するプラズマCVD工程を含む半導体薄膜の製造方法であって、前記プラズマ発生空間にプラズマを遮蔽する壁を設けるものであり、前記支持部材は、基体露出面の外縁に位置し且つ前記電極面に対向する面状部を有し、前記面状部に前記壁を設け、前記面状部は、基体露出面に隣接する基体側電極対向面と、該基体側電極対向面の基体露出面側とは反対側に隣接する端部側電極対向面とを有し、該基体側電極対向面と該端部側電極対向面とは、端部側電極対向面と電極面との距離が基体側電極対向面と電極面との距離よりも小さくなる段差を形成しており、前記壁は当該段差により形成されており、前記基体側電極対向面と前記基体露出面とは段部を形成しており、電極面と基体側電極対向面との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下であり、前記段部は、基体側電極対向面から基体露出面に向かって高さが小さくなるテーパ状に形成されていることを特徴とする半導体薄膜の製造方法である。 According to a second aspect of the present invention, a substrate on which a semiconductor thin film is to be formed is mounted on a support member, and a part or all of the substrate is exposed from the support member. The support member is disposed so as to face the electrode surface, a plasma generation space is formed between the support member on which the base is mounted and the electrode, high frequency power is supplied to the electrode to generate discharge, A method of manufacturing a semiconductor thin film including a plasma CVD process for forming a semiconductor thin film on a substrate exposed surface, wherein a wall for shielding plasma is provided in the plasma generation space, and the support member is an outer edge of the substrate exposed surface. A planar portion facing the electrode surface, wherein the wall is provided on the planar portion, and the planar portion includes a substrate-side electrode facing surface adjacent to a substrate exposed surface, and the substrate-side electrode. Adjacent to the opposite side of the opposite side of the substrate exposed surface And the base-side electrode-facing surface and the end-side electrode-facing surface have a distance between the base-side electrode-facing surface and the electrode surface. The wall is formed by the step, and the base-side electrode facing surface and the base-exposed surface form a step, and the electrode surface and the base The distance from the side electrode facing surface is smaller than the distance between the electrode surface and the substrate exposed surface, and the height of the stepped portion is 0.5 mm or more and 4.0 mm or less. from a process for manufacturing semi-conductive thin film you characterized in that it is formed in a tapered shape in which the height becomes smaller toward the substrate exposed surface.

本発明の半導体薄膜の製造方法では、用いる支持部材の面状部に段差が設けられており、当該段差がプラズマを遮蔽する壁として機能する。すなわち、当該段差において、端部側電極対向面と電極面との距離は、基体側電極対向面と電極面との距離よりも小さい。換言すれば、当該段差は電極に向かって凸形状となるもので、かつ端部側電極対向面が基体側電極対向面に対して電極側に突出している。本発明の半導体薄膜の製造方法では、段差によりプラズマを遮蔽する壁が形成されているので、成膜領域に生じたプラズマが、基体露出面から支持部材の面状部に向かって広がろうとしても、面状部に設けられた段差(壁)に当たり、プラズマが成膜領域に閉じ込められる。そのため、成膜領域においてプラズマがより均一化される。その結果、基体露出面に成膜される半導体薄膜の膜厚がより均一化され、膜質もより均質化されたものとなる。   In the method for producing a semiconductor thin film of the present invention, a step is provided in the planar portion of the supporting member to be used, and the step functions as a wall that shields plasma. That is, in the step, the distance between the end-side electrode facing surface and the electrode surface is smaller than the distance between the base-side electrode facing surface and the electrode surface. In other words, the step is convex toward the electrode, and the end-side electrode facing surface protrudes toward the electrode side with respect to the base-side electrode facing surface. In the method for producing a semiconductor thin film of the present invention, the wall that shields the plasma is formed by the step, so that the plasma generated in the film formation region tends to spread from the substrate exposed surface toward the planar portion of the support member. However, the plasma hits the step (wall) provided in the planar portion and is confined in the film formation region. Therefore, the plasma is made more uniform in the film formation region. As a result, the film thickness of the semiconductor thin film formed on the substrate exposed surface is made more uniform, and the film quality becomes more uniform.

また本発明の半導体薄膜の製造方法では、前記基体側電極対向面と前記基体露出面とは段部を形成しており、電極面と基体側電極対向面との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下である。かかる構成により、基体露出面から支持部材の基体側電極対向面へのプラズマの変動が小さくなり、プラズマがより均一化される。 In the method for producing a semiconductor thin film of the present invention, the base-side electrode facing surface and the base-exposed surface form a step, and the distance between the electrode surface and the base-side electrode facing surface is the electrode surface and the base-exposed surface. And the height of the stepped portion is 0.5 mm or more and 4.0 mm or less. With this configuration, the variation in plasma from the substrate exposed surface to the substrate-side electrode facing surface of the support member is reduced, and the plasma is made more uniform.

また本発明の半導体薄膜の製造方法では、前記段部は、基体側電極対向面から基体露出面に向かって高さが小さくなるテーパ状に形成されている。かかる構成により、基体露出面から基体側電極対向面へのプラズマの変動が極めて小さくなり、プラズマがより均一化される。 In the method for producing a semiconductor thin film of the present invention, the stepped portion is formed in a tapered shape whose height decreases from the substrate-side electrode facing surface toward the substrate exposed surface. With this configuration, plasma fluctuation from the substrate exposed surface to the substrate-side electrode facing surface becomes extremely small, and the plasma is made more uniform.

請求項に記載の発明は、前記段差の高さは、前記電極面と前記基体露出面との距離の1/20以上かつ1/3以下であることを特徴とする請求項に記載の半導体薄膜の製造方法である。 According to a third aspect of the invention, the height of the step is set forth in claim 2, wherein the electrode surface and the at most 1/20 or more and 1/3 of the distance between the substrate exposed surface It is a manufacturing method of a semiconductor thin film.

本発明の半導体薄膜の製造方法では、段差の高さが所定の範囲に限定されている。かかる構成により、端部側電極対向面と電極面との距離をプラズマの発生に悪影響を及ぼさない程度に保ちながら、成膜領域に生じたプラズマが確実に閉じ込められる。   In the method for producing a semiconductor thin film of the present invention, the height of the step is limited to a predetermined range. With this configuration, the plasma generated in the film formation region is reliably confined while maintaining the distance between the end-side electrode facing surface and the electrode surface to an extent that does not adversely affect the generation of plasma.

前記支持部材は開口を有する枠体からなり、前記基体の一部又は全部を該開口から露出させる構成が推奨される(請求項)。また、前記基体は板体であり、基体露出面は該板体の一方の面の一部又は全部である構成も推奨される(請求項)。 Said support member is made of a frame body having an opening, configured to expose a portion or all of the base from the opening is recommended (claim 4). In addition, a configuration in which the base is a plate and the base exposed surface is a part or all of one surface of the plate is also recommended (Claim 5 ).

前記支持部材に複数の基体を並べて装着し、各々の基体の一部又は全部を支持部材から露出させ、複数の基体に対して半導体薄膜を成膜する構成が採用できる(請求項)。 The support member side by side a plurality of substrates mounted, some or all of each of the substrate is exposed from the support member, configured to be deposited may be employed a semiconductor thin film on a plurality of substrates (claim 6).

関連の発明は、上記した半導体薄膜の製造方法を行うための半導体薄膜製造装置であって、電極を備えた成膜室を有し、基体が保持された前記支持部材が前記成膜室に対して出し入れ可能であり、該支持部材が成膜室内で電極に対向して配置されることを特徴とする半導体薄膜製造装置である。 A related invention is a semiconductor thin film manufacturing apparatus for performing the above-described method for manufacturing a semiconductor thin film, the film forming chamber having an electrode, and the support member on which a base is held is located with respect to the film forming chamber The semiconductor thin film manufacturing apparatus is characterized in that the support member is disposed to face the electrode in the deposition chamber.

この発明は半導体薄膜製造装置にかかるものである。この半導体薄膜製造装置は本発明の半導体薄膜の製造方法を行うためのものであり、電極を備えた成膜室を有し、基体が保持された支持部材が成膜室に対して出し入れ可能であり、該支持部材が成膜室内で電極に対向して配置される。この半導体薄膜製造装置によれば、成膜領域に生じたプラズマがより均一化される。その結果、基体露出面に成膜される半導体薄膜の膜厚がより均一化され、膜質もより均質化されたものとなる。 The present invention relates to a semiconductor thin film manufacturing apparatus. This semiconductor thin film manufacturing apparatus is for carrying out the semiconductor thin film manufacturing method of the present invention, has a film forming chamber equipped with electrodes, and a support member holding a substrate can be taken in and out of the film forming chamber. And the support member is arranged to face the electrode in the film forming chamber. According to this semiconductor thin film manufacturing apparatus, the plasma generated in the film forming region is made more uniform. As a result, the film thickness of the semiconductor thin film formed on the substrate exposed surface is made more uniform, and the film quality becomes more uniform.

複数の支持部材が配置可能である構成、前記成膜室が複数の電極を備える構成、及び、前記成膜室を複数備えた構成が採用できる。 Configuration plurality of support members can be arranged, the deposition chamber is configuration comprising a plurality of electrodes, and the film forming chamber can configure adopted including a plurality of.

本発明の半導体薄膜の製造方法によれば、成膜領域においてプラズマがより均一化される。その結果、基体露出面に成膜される薄膜の膜厚がより均一化され、膜質もより均質化されたものとなる。   According to the method for producing a semiconductor thin film of the present invention, the plasma is made more uniform in the film formation region. As a result, the film thickness of the thin film formed on the substrate exposed surface is made more uniform, and the film quality is made more uniform.

図1は本発明の第一実施形態のプラズマCVD装置が備える成膜室の斜視図である。図2は図1のA−A断面図である。図3は図1の成膜室に収納される基体キャリアの斜視図である。図4は図3の基体キャリアの分解斜視図である。図5は成膜室内における基体キャリアと電極との位置関係を示す一部破断斜視図である。図6は基体キャリアの内側の状態を示す一部破断斜視図である。図7は図6のB−B断面斜視図である。図8は成膜領域におけるプラズマの状態を模式的に表す断面図である。図9(a)はプラズマが収縮した場合のプラズマの状態を模式的に示す断面図、図9(b)はプラズマが外周面上にはみ出た場合のプラズマの状態を模式的に示す断面図である。図10は参考例のプラズマCVD装置の要部を示す断面図である。図11は参考例のプラズマCVD装置の要部を示す断面図である。図12は第実施形態のプラズマCVD装置の要部を示す断面図である。図13は第一実施形態における枠体の一例を示す断面図である。図14は本発明の第実施形態における基体キャリアの斜視図である。 FIG. 1 is a perspective view of a film forming chamber provided in the plasma CVD apparatus according to the first embodiment of the present invention. 2 is a cross-sectional view taken along the line AA in FIG. FIG. 3 is a perspective view of the substrate carrier housed in the film forming chamber of FIG. 4 is an exploded perspective view of the base carrier of FIG. FIG. 5 is a partially broken perspective view showing the positional relationship between the substrate carrier and the electrode in the film forming chamber. FIG. 6 is a partially broken perspective view showing a state inside the base carrier. FIG. 7 is a cross-sectional perspective view taken along the line BB of FIG. FIG. 8 is a cross-sectional view schematically showing the state of plasma in the film formation region. 9A is a cross-sectional view schematically showing the state of the plasma when the plasma contracts, and FIG. 9B is a cross-sectional view schematically showing the state of the plasma when the plasma protrudes on the outer peripheral surface. is there. FIG. 10 is a cross-sectional view showing a main part of a plasma CVD apparatus of a reference example . FIG. 11 is a cross-sectional view showing a main part of a plasma CVD apparatus of a reference example. FIG. 12 is a cross-sectional view showing the main part of the plasma CVD apparatus of the second embodiment. FIG. 13 is a cross-sectional view showing an example of a frame body in the first embodiment. FIG. 14 is a perspective view of a base carrier in the third embodiment of the present invention.

図1に示すプラズマCVD装置(半導体薄膜製造装置)1は、基板(基体)の成膜面が内側を向いて設置される「1電極両面放電タイプ」のものである。図1に示すように、本実施形態(第一実施形態)のプラズマCVD装置1は成膜室2を中心として構成されるものであり、成膜室2において所望の基体に半導体薄膜を成膜する。成膜室2は直方体状の箱体であり、その正面には成膜室出入口3が設けられている。成膜室出入口3には気密性を備えたシャッターが設けられており、シャッターを開閉することで成膜室2内に基体を出し入れすることができる。成膜室2には、排気真空ポンプ、配管、及び圧力調整弁等(いずれも図示せず)が接続されており、成膜室2の内部は所定の圧力に減圧可能である。   A plasma CVD apparatus (semiconductor thin film manufacturing apparatus) 1 shown in FIG. 1 is of a “one-electrode double-sided discharge type” in which a film-forming surface of a substrate (base) is placed inward. As shown in FIG. 1, the plasma CVD apparatus 1 of the present embodiment (first embodiment) is configured with a film forming chamber 2 as a center, and a semiconductor thin film is formed on a desired substrate in the film forming chamber 2. To do. The film forming chamber 2 is a rectangular parallelepiped box, and a film forming chamber entrance 3 is provided in front of it. The film formation chamber entrance / exit 3 is provided with an airtight shutter, and the substrate can be taken in and out of the film formation chamber 2 by opening and closing the shutter. The film forming chamber 2 is connected to an exhaust vacuum pump, piping, a pressure control valve and the like (all not shown), and the inside of the film forming chamber 2 can be depressurized to a predetermined pressure.

図2に示すように、成膜室2はその内部に電極5とヒータ6a,6bを備える。
電極5は細長い直方体状であり、成膜室2の天面から垂下され、成膜室2の略中央に縦置きされている。電極5と成膜室2の底面との間、および電極5とヒータ6a,6bとの間にはいずれも隙間がある。電極5の表面(電極面)にはガス流入孔(図示せず)が設けられており、該ガス流入孔には原料ガス供給装置(図示せず)が接続されている。さらに、電極5には高周波電量供給装置(図示せず)が接続されている。電極5はカソード電極として機能する。
ヒータ6a,6bは細長い直方体状であり、成膜室2の内壁に取り付けられている。すなわち、ヒータ6a,6bは電極5を挟んで平行に位置している。
As shown in FIG. 2, the film forming chamber 2 includes an electrode 5 and heaters 6a and 6b.
The electrode 5 has an elongated rectangular parallelepiped shape, is suspended from the top surface of the film formation chamber 2, and is placed vertically at the approximate center of the film formation chamber 2. There are gaps between the electrode 5 and the bottom surface of the film forming chamber 2 and between the electrode 5 and the heaters 6a and 6b. A gas inflow hole (not shown) is provided on the surface (electrode surface) of the electrode 5, and a raw material gas supply device (not shown) is connected to the gas inflow hole. Further, a high-frequency electricity supply device (not shown) is connected to the electrode 5. The electrode 5 functions as a cathode electrode.
The heaters 6 a and 6 b have an elongated rectangular parallelepiped shape and are attached to the inner wall of the film forming chamber 2. That is, the heaters 6a and 6b are positioned in parallel with the electrode 5 interposed therebetween.

本実施形態における成膜室2、電極5、及びヒータ6a,6bは、それぞれ、図15,19に示した従来のプラズマCVD装置における真空チャンバー62、電極65、及び温調パネル66と基本的に同じものである。   The film formation chamber 2, the electrode 5, and the heaters 6a and 6b in this embodiment are basically the same as the vacuum chamber 62, the electrode 65, and the temperature control panel 66 in the conventional plasma CVD apparatus shown in FIGS. The same thing.

電極5とヒータ6aとの隙間、および電極5とヒータ6bとの隙間には、基体キャリア7の一部が挿入されている。ここで、基体キャリア7の構成について説明する。なお図2においては、基体キャリア7の詳細な形状は省略して示している。図3に示すように、基体キャリア7は細長い台車に2枚の枠体(支持部材)8を対向して立設したような形状を有する。すなわち、基体キャリア7は、直方体状のキャリアベース10を有し、その両側に合計4個の車輪11が設けられている。また、キャリアベース10の底面には、ラック12が取り付けられている。   A part of the base carrier 7 is inserted into the gap between the electrode 5 and the heater 6a and the gap between the electrode 5 and the heater 6b. Here, the configuration of the base carrier 7 will be described. In FIG. 2, the detailed shape of the base carrier 7 is omitted. As shown in FIG. 3, the base carrier 7 has a shape in which two frames (support members) 8 are erected on an elongated cart so as to face each other. That is, the base carrier 7 has a rectangular parallelepiped carrier base 10 and a total of four wheels 11 are provided on both sides thereof. A rack 12 is attached to the bottom surface of the carrier base 10.

キャリアベース10の上面側の長辺部には、2枚の枠体(支持部材)8が平行に対向して設けられている。枠体8どうしの間は空隙15となっている。すなわち、キャリアベース10と2枚の枠体8によって上向きの「コ」の字形状をなしている。
図3,4に示すように、枠体8には正方形の開口16が設けられている。そして、開口16の周囲にはクリップ17が多数設けられている。すなわち、基体キャリア7には合計2個の開口16が設けられている。
Two frame bodies (support members) 8 are provided in parallel to face each other on the long side portion on the upper surface side of the carrier base 10. There is a gap 15 between the frames 8. That is, the carrier base 10 and the two frames 8 form an upward “U” shape.
As shown in FIGS. 3 and 4, the frame body 8 is provided with a square opening 16. A large number of clips 17 are provided around the opening 16. That is, the substrate carrier 7 is provided with a total of two openings 16.

基体キャリア7の枠体8には、図3,4に示すようにガラス基板(基体)20と背板21とが取り付けられており、これらをクリップ17が押さえている。すなわち、基体キャリア7には計2枚のガラス基板(基体)20が装着されている。そして、枠体8に装着されたガラス基板(基体)20はその一部を開口16から露出しており、かつ当該露出面(基体露出面)22は対向する枠体8の内側を向いている。なお、図3ではガラス基板20を省略している。   As shown in FIGS. 3 and 4, a glass substrate (base body) 20 and a back plate 21 are attached to the frame body 8 of the base carrier 7, and the clip 17 presses them. That is, a total of two glass substrates (bases) 20 are mounted on the base carrier 7. A part of the glass substrate (base body) 20 mounted on the frame body 8 is exposed from the opening 16, and the exposed surface (base body exposed surface) 22 faces the inside of the opposing frame body 8. . In FIG. 3, the glass substrate 20 is omitted.

本実施形態のプラズマCVD装置1の成膜室2における、基体キャリア7と電極5との位置関係は、図5に示すものとなる。すなわち、電極5の両面を2枚の枠体8が挟んで位置し、枠体8に装着されたガラス基板20の露出面(基体露出面)22がそれぞれ電極5に対向する。電極5とガラス基板20の露出面22とは、互いに平行に位置している。さらに、基体キャリア7の2個の枠体8の外側にヒータ6a,6bが位置する(図2)。   The positional relationship between the substrate carrier 7 and the electrode 5 in the film forming chamber 2 of the plasma CVD apparatus 1 of this embodiment is as shown in FIG. That is, both surfaces of the electrode 5 are positioned between the two frame bodies 8, and the exposed surfaces (substrate exposed surfaces) 22 of the glass substrate 20 mounted on the frame body 8 face the electrodes 5. The electrode 5 and the exposed surface 22 of the glass substrate 20 are located in parallel to each other. Furthermore, heaters 6a and 6b are located outside the two frames 8 of the base carrier 7 (FIG. 2).

本実施形態のプラズマCVD装置(半導体薄膜製造装置)1では、ガラス基板(基体)20が装着される枠体(支持部材)8の形状に特徴がある。図6,7に示すように、枠体8にはガラス基板20が装着されており、ガラス基板20の一部が開口16から露出し、露出面22を形成している。そして、枠体8は露出面22の周囲に面状部25を有する。従来のプラズマCVD装置では枠体8の面状部25が一平面からなり且つ平坦である。しかし、本実施形態のプラズマCVD装置1では、面状部25が内周面(基体側電極対向面)26と外周面(端部側電極対向面)27とで構成されており、さらに、内周面26と外周面27とが段差(壁)28を形成している。そして、外周面27が内周面26に対して内側(電極5側)に突出している。
またさらに、内周部26と露出面22との間には段部30が設けられており、内周面26が露出面22に対して内側(電極5側)に突出している。さらに、段部30は内周部26から露出面22に向かってその高さが小さくなるテーパ状に形成されている。
なお、図7では背板21を省略している。
The plasma CVD apparatus (semiconductor thin film manufacturing apparatus) 1 according to this embodiment is characterized by the shape of the frame (support member) 8 on which the glass substrate (base body) 20 is mounted. As shown in FIGS. 6 and 7, a glass substrate 20 is mounted on the frame 8, and a part of the glass substrate 20 is exposed from the opening 16 to form an exposed surface 22. The frame body 8 has a planar portion 25 around the exposed surface 22. In the conventional plasma CVD apparatus, the planar portion 25 of the frame 8 is a flat surface and is flat. However, in the plasma CVD apparatus 1 of the present embodiment, the planar portion 25 is composed of an inner peripheral surface (substrate-side electrode facing surface) 26 and an outer peripheral surface (end-side electrode facing surface) 27. The peripheral surface 26 and the outer peripheral surface 27 form a step (wall) 28. The outer peripheral surface 27 protrudes inward (electrode 5 side) with respect to the inner peripheral surface 26.
Furthermore, a step portion 30 is provided between the inner peripheral portion 26 and the exposed surface 22, and the inner peripheral surface 26 protrudes inward (electrode 5 side) with respect to the exposed surface 22. Further, the step portion 30 is formed in a tapered shape whose height decreases from the inner peripheral portion 26 toward the exposed surface 22.
In FIG. 7, the back plate 21 is omitted.

次に、本実施形態のプラズマCVD装置(半導体薄膜製造装置)を使用したプラズマCVD方法による半導体薄膜の製造方法について、プラズマCVD装置の作用とともに説明する。
本実施形態のプラズマCVD装置1によりガラス基板(基体)20に薄膜を成膜する場合には、まず、基体キャリア7を成膜室2から取り出しておき、ガラス基板(基体)20を背板21と共に装着する。一方、成膜室2の成膜室出入口30に設けられたシャッターを閉め、成膜室2内の空気を排気し、減圧する。さらに、ヒータ6a,6bを運転し、所定温度に昇温しておく。次に、ガラス基板20が装着された基体キャリア7を成膜室出入口30から挿入し、図2,5に示すような位置関係となるように固定する。このとき、成膜室2内の減圧が解除されないように、密閉系を保ったままで基体キャリア7を挿入する。例えば、成膜室出入口30と密閉状態で接合できる移動用チャンバーに基体キャリア7をセットしておき、移動用チャンバーを成膜室出入口30と接合し、シャッターを開け、基体キャリア7を成膜室出入口30から挿入することができる。この際、移動用チャンバーにヒータを設けておき、移動用チャンバー内で基体キャリア7に装着されたガラス基板20を予め加熱しておいてもよい。
次に、電極5に設けられたガス流入孔から原料ガスを供給すると共に、電極5に高周波電力を供給する。そして、電極5と基体キャリア7の枠体8との間(プラズマ発生空間)にグロー放電を発生させて原料ガスのプラズマを発生させ、ガラス基板20の露出面22に半導体薄膜を成膜する。なおこの際、ガラス基板20と枠体8とが一体となって1つの電極(基板支持電極31)を構成する。換言すれば、ガラス基板20が装着された枠体8が基板支持電極31である。そして、電極5と基板支持電極31との間がプラズマ発生空間となり、プラズマ発生空間のうちガラス基板20の露出面22を覆う領域が成膜領域となる。基板支持電極31はアノード電極として機能する。
Next, a method for manufacturing a semiconductor thin film by a plasma CVD method using the plasma CVD apparatus (semiconductor thin film manufacturing apparatus) of this embodiment will be described together with the action of the plasma CVD apparatus.
When a thin film is formed on the glass substrate (base) 20 by the plasma CVD apparatus 1 of the present embodiment, first, the base carrier 7 is taken out from the film formation chamber 2 and the glass substrate (base) 20 is moved to the back plate 21. Wear with. On the other hand, the shutter provided in the film formation chamber entrance / exit 30 of the film formation chamber 2 is closed, and the air in the film formation chamber 2 is exhausted and decompressed. Further, the heaters 6a and 6b are operated to raise the temperature to a predetermined temperature. Next, the base carrier 7 on which the glass substrate 20 is mounted is inserted from the film formation chamber entrance 30 and fixed so as to have a positional relationship as shown in FIGS. At this time, the substrate carrier 7 is inserted while keeping the sealed system so that the decompression in the film forming chamber 2 is not released. For example, the substrate carrier 7 is set in a transfer chamber that can be sealed with the film formation chamber entrance / exit 30, the transfer chamber is connected to the film formation chamber entrance 30, a shutter is opened, and the substrate carrier 7 is attached to the film formation chamber It can be inserted from the doorway 30. At this time, a heater may be provided in the movement chamber, and the glass substrate 20 mounted on the substrate carrier 7 may be heated in advance in the movement chamber.
Next, source gas is supplied from a gas inflow hole provided in the electrode 5, and high-frequency power is supplied to the electrode 5. Then, glow discharge is generated between the electrode 5 and the frame 8 of the substrate carrier 7 (plasma generation space) to generate plasma of source gas, and a semiconductor thin film is formed on the exposed surface 22 of the glass substrate 20. At this time, the glass substrate 20 and the frame body 8 are integrated to form one electrode (substrate support electrode 31). In other words, the frame body 8 on which the glass substrate 20 is mounted is the substrate support electrode 31. A space between the electrode 5 and the substrate support electrode 31 is a plasma generation space, and a region covering the exposed surface 22 of the glass substrate 20 in the plasma generation space is a film formation region. The substrate support electrode 31 functions as an anode electrode.

図8は成膜領域におけるプラズマの状態を模式的に表す断面図である。図8に示すように、本実施形態においては、内周面26と外周面27とにより形成されている段差(壁)28によって成膜領域に発生したプラズマ35の不必要な広がりが阻害され、成膜領域にプラズマ35が閉じ込められる形となる。すなわち、段差28がプラズマ35を遮蔽する壁として機能する。その結果、成膜領域においてプラズマ35が均一化し、ガラス基板20の露出面22に成膜される半導体薄膜は、その膜厚と膜質が均一なものとなる。   FIG. 8 is a cross-sectional view schematically showing the state of plasma in the film formation region. As shown in FIG. 8, in this embodiment, unnecessary spread of the plasma 35 generated in the film formation region is inhibited by the step (wall) 28 formed by the inner peripheral surface 26 and the outer peripheral surface 27, The plasma 35 is confined in the film formation region. That is, the step 28 functions as a wall that shields the plasma 35. As a result, the plasma 35 becomes uniform in the film formation region, and the semiconductor thin film formed on the exposed surface 22 of the glass substrate 20 has a uniform film thickness and film quality.

ここで、電極5と基体支持電極31との距離(電極間距離)がより大きくなった場合について考察する。圧力領域や高周波電力の大きさによりその挙動は逆にもなり得るが、電極間距離が大きくなると、プラズマが収縮した状態となりやすい。しかし、本実施形態ではその収縮は面状部25の内周面26上で起こるのみであり、プラズマ35の状態は図9(a)に示すようなものとなり、ガラス基板20の露出面22上ではプラズマの均一性が保たれる。すなわち、本実施形態においては、成膜領域のプラズマ35が図19(d)に示すような状態とはならない。
一方、電極間距離がより小さくなった場合について考察する。圧力領域や高周波電力の大きさによりその挙動は逆にもなり得るが、電極間距離が小さくなるとプラズマの広がりが大きくなる。しかし、本実施形態では段差(壁)28があるので、図8に示すように、プラズマ35が外周面27上にはみ出ることなく成膜領域に閉じ込められる。また、プラズマの広がりが極めて大きい場合には、発生したプラズマ35が面状部25の内周面26上を超えて外周面27上にはみ出ることもある。しかし、この場合でも段差(壁)28があるのではみ出るプラズマ35の量は少なく、プラズマ35の状態は図9(b)に示すようなものとなり、結果的にガラス基板20の露出面22上ではプラズマ35の均一性が保たれる。つまり、本実施形態においては、成膜領域のプラズマ35が図19(c)に示すような状態とはならない。
このように、本実施形態のプラズマCVD装置1によれば、成膜領域におけるプラズマの均一性が電極間距離により大きな影響を受けることはない。
Here, the case where the distance (distance between electrodes) between the electrode 5 and the substrate support electrode 31 becomes larger will be considered. The behavior may be reversed depending on the pressure region and the magnitude of the high-frequency power, but if the distance between the electrodes increases, the plasma tends to contract. However, in the present embodiment, the contraction only occurs on the inner peripheral surface 26 of the planar portion 25, and the state of the plasma 35 is as shown in FIG. 9A, and on the exposed surface 22 of the glass substrate 20. Then, the uniformity of plasma is maintained. That is, in the present embodiment, the plasma 35 in the film formation region does not become in the state as shown in FIG.
On the other hand, the case where the distance between electrodes becomes smaller will be considered. The behavior may be reversed depending on the pressure region and the magnitude of the high frequency power, but the spread of the plasma increases as the distance between the electrodes decreases. However, since there is a step (wall) 28 in this embodiment, the plasma 35 is confined in the film formation region without protruding onto the outer peripheral surface 27 as shown in FIG. In addition, when the spread of plasma is extremely large, the generated plasma 35 may protrude from the outer peripheral surface 27 beyond the inner peripheral surface 26 of the planar portion 25. However, even in this case, if there is a step (wall) 28, the amount of the plasma 35 that protrudes is small, and the state of the plasma 35 is as shown in FIG. 9B. As a result, on the exposed surface 22 of the glass substrate 20 The uniformity of the plasma 35 is maintained. That is, in the present embodiment, the plasma 35 in the film forming region does not become in a state as shown in FIG.
As described above, according to the plasma CVD apparatus 1 of the present embodiment, the uniformity of plasma in the film formation region is not greatly affected by the distance between the electrodes.

なお、段差28の高さとしては、電極間距離、電極5に投入される電力のパワー及び周波数、成膜室2内の圧力等によって適当な高さを選択すればよいが、例えば、電極5と露出面22との間の距離の1/20以上かつ1/3以下の範囲とすることができる。すなわち、電極間に発生したプラズマを効率よく閉じ込めるためには、段差28の高さはできるだけ大きい方がよいが、外周面27が電極5に近づきすぎると、外周面27と電極5との間に異常放電が起こり、プラズマの発生に大きな支障が出る。一方、段差の高さが低すぎると、成膜領域にプラズマを効率よく閉じ込められない。そこで、段差28の高さを電極5と露出面22との間の距離の1/20以上かつ1/3以下の範囲にすることで、外周面27と電極5との間に異常放電が起こらず且つ電極間に発生したプラズマが成膜領域に効率よく閉じ込められる。   As the height of the step 28, an appropriate height may be selected depending on the distance between the electrodes, the power and frequency of power input to the electrode 5, the pressure in the film forming chamber 2, and the like. And a range of 1/20 or more and 1/3 or less of the distance between the exposed surface 22 and the exposed surface 22. That is, in order to efficiently confine the plasma generated between the electrodes, the height of the step 28 is preferably as large as possible. However, if the outer peripheral surface 27 is too close to the electrode 5, the gap between the outer peripheral surface 27 and the electrode 5 is good. Abnormal discharge occurs, causing a major hindrance to plasma generation. On the other hand, if the height of the step is too low, the plasma cannot be confined efficiently in the film formation region. Therefore, abnormal discharge occurs between the outer peripheral surface 27 and the electrode 5 by setting the height of the step 28 to a range of 1/20 or more and 1/3 or less of the distance between the electrode 5 and the exposed surface 22. In addition, the plasma generated between the electrodes is efficiently confined in the film formation region.

また本実施形態では、内周部26と露出面22との間には段部30が設けられており、内周面26が露出面22に対して内側(電極5側)に突出している。さらに、段部30は、その高さが内周部26から露出面22に向かって小さくなるテーパ状に形成されている。これにより、露出面22から内周面26に至る過程でプラズマの変動がより小さく抑えられる。
段部30の高さはできるだけ小さい方が好ましいが、例えば、0.5mm以上かつ4.0mm以下の範囲とすればよい。すなわち、0.5mm未満とすることは、枠体8の機械加工精度、加工の難易度、及び枠体8のガラス基板20を保持する際の強度等の面で困難である。一方、4.0mmを越えると面状部25上のプラズマの状態に影響を与え、成膜領域におけるプラズマの均一性に悪影響が出るおそれがある。
In the present embodiment, a step portion 30 is provided between the inner peripheral portion 26 and the exposed surface 22, and the inner peripheral surface 26 protrudes inward (electrode 5 side) with respect to the exposed surface 22. Further, the step portion 30 is formed in a tapered shape whose height decreases from the inner peripheral portion 26 toward the exposed surface 22. As a result, plasma fluctuations are further reduced in the process from the exposed surface 22 to the inner peripheral surface 26.
The height of the stepped portion 30 is preferably as small as possible, but may be in the range of 0.5 mm or more and 4.0 mm or less, for example. That is, it is difficult to make it less than 0.5 mm in terms of the machining accuracy of the frame 8, the difficulty of processing, and the strength when holding the glass substrate 20 of the frame 8. On the other hand, if the thickness exceeds 4.0 mm, the plasma state on the planar portion 25 is affected, and the uniformity of the plasma in the film formation region may be adversely affected.

なお、本発明のプラズマCVD方法およびプラズマCVD装置においては、より高いプラズマの閉じ込め効果が得られるのは電極間距離が20mm以下の場合であるが、これに限定されるものではない。なお、電極間距離を6mm以下とすると、一般に段差の形成が難しくなるので、現実的な電極間距離は6mm〜20mmであり、この場合には、例えば、生産性を考慮した200mW/cm2以上の投入パワーにて、成膜時のガス圧の範囲を100Pa〜2000Paとすると、成膜領域に発生するプラズマは均一なものとなる。 In the plasma CVD method and plasma CVD apparatus of the present invention, a higher plasma confinement effect can be obtained when the distance between the electrodes is 20 mm or less, but is not limited thereto. If the distance between the electrodes is 6 mm or less, it is generally difficult to form a step. Therefore, the actual distance between the electrodes is 6 mm to 20 mm. In this case, for example, 200 mW / cm 2 or more in consideration of productivity. When the gas pressure during film formation is set to 100 Pa to 2000 Pa with the input power of 1, the plasma generated in the film formation region becomes uniform.

上記した第一実施形態のプラズマCVD装置1では、枠体(支持部材)8に設けられた段部30がテーパ状に形成されていたが、段部30がテーパ状に形成されていない例を示す。図10は参考例のプラズマCVD装置の要部を示す断面図である。図10のプラズマCVD装置(半導体薄膜製造装置)においては、枠体(支持部材)42の段部43はテーパ状に形成されていないが、段差28によるプラズマの閉じ込め効果により成膜領域のプラズマは十分均一なものとなる。段部43の高さは、例えば、第一実施形態と同様に0.5mm以上かつ4.0mm以下の範囲とすればよい。 In the plasma CVD apparatus 1 of the first embodiment described above, although a stepped portion 30 provided on the frame (supporting member) 8 is formed in the tapered shape, an example in which the step portion 30 is not formed in a tapered shape Show. FIG. 10 is a cross-sectional view showing a main part of a plasma CVD apparatus of a reference example . In the plasma CVD apparatus (semiconductor thin film manufacturing apparatus) of FIG. 10, the stepped portion 43 of the frame (supporting member) 42 is not formed in a taper shape. It will be sufficiently uniform. The height of the stepped portion 43 may be, for example, in the range of 0.5 mm or more and 4.0 mm or less as in the first embodiment.

上記した実施形態では枠体の面状部に段差を設けることで、成膜領域にプラズマを閉じ込めたが、段差以外の手段で成膜領域にプラズマを閉じ込めることもできる。図11は参考例のプラズマCVD装置の要部を示す断面図である。図11のプラズマCVD装置(半導体薄膜製造装置)では、枠体46の面状部47が従来のプラズマCVD装置と同様に平坦かつ一平面からなる。そして、プラズマ発生空間に枠体46とは別の部材からなる壁48を設けることにより、成膜領域にプラズマを閉じ込めている。なお、壁48を構成する部材は、例えば成膜室の内壁に設けられており、当該部材が面状部47の一部を覆うことにより、壁48が形成されている。 In the above embodiments by providing the stepped planar portions of the frame body has been confined plasma deposition region, it is also possible to confine the plasma in the deposition region by means other than stepped. FIG. 11 is a cross-sectional view showing a main part of a plasma CVD apparatus of a reference example. In the plasma CVD apparatus (semiconductor thin film manufacturing apparatus) of FIG. 11, the planar portion 47 of the frame 46 is flat and flat as in the conventional plasma CVD apparatus. The plasma is confined in the film formation region by providing a wall 48 made of a member different from the frame 46 in the plasma generation space. The member constituting the wall 48 is provided, for example, on the inner wall of the film forming chamber, and the wall 48 is formed by covering the part of the planar portion 47 with the member.

壁48を枠体の面状部に直接設けることもできる。図12は第実施形態のプラズマCVD装置の要部を示す断面図である。図12のプラズマCVD装置(半導体薄膜製造装置)では、枠体(支持部材)52の面状部53に壁54を設け、成膜領域にプラズマを閉じ込めている。
なお、図8〜12ではいずれもクリップ17と背板21を省略している。
The wall 48 can also be provided directly on the planar portion of the frame. FIG. 12 is a cross-sectional view showing the main part of the plasma CVD apparatus of the second embodiment. In the plasma CVD apparatus (semiconductor thin film manufacturing apparatus) of FIG. 12, a wall 54 is provided on the planar portion 53 of the frame (supporting member) 52 to confine plasma in the film formation region.
8 to 12, the clip 17 and the back plate 21 are omitted.

上記した実施形態のうち、枠体の面状部に段差または壁を設ける場合には、面状部を削り出すことで段差または壁を形成してもよいし、平坦な面状部に段差または壁に相当するする部材を貼り付けて形成させてもよい。図13は第一実施形態における枠体の一例を示す断面図である。図13の枠体8は、外周面27を構成する第一の部材55と、内周面26を構成する第二の部材56とを組み合わせることにより形成されている。そして、段差28は、第一の部材55と第二の部材56とにより形成されている。テーパ状の段部30は第二の部材56の一部からなる。   In the above-described embodiment, when a step or a wall is provided in the planar portion of the frame, the step or wall may be formed by cutting out the planar portion, or the step or wall may be formed in the flat planar portion. A member corresponding to the wall may be attached and formed. FIG. 13 is a cross-sectional view showing an example of a frame body in the first embodiment. The frame body 8 in FIG. 13 is formed by combining a first member 55 that constitutes the outer peripheral surface 27 and a second member 56 that constitutes the inner peripheral surface 26. The step 28 is formed by the first member 55 and the second member 56. The tapered step portion 30 is composed of a part of the second member 56.

上記したいずれの実施形態においても、段差28と壁48,54についてはガラス基板20の露出面22の四辺全てに設けてもよいし、一部の辺に設けてもよい。   In any of the above-described embodiments, the step 28 and the walls 48 and 54 may be provided on all four sides of the exposed surface 22 of the glass substrate 20 or may be provided on some sides.

本実施形態ではガラス基板20の成膜面が内側を向いて設置される「1電極両面放電タイプ」の例を示したが、図15に示すようなガラス基板の成膜面(露出面)が外側を向いて配置されるタイプのプラズマCVD装置にも本実施形態の構成が全く同様に適用できる。図14は本発明の第実施形態における基体キャリアの斜視図である。図14に示す実施形態では、成膜室内において基体キャリア57の枠体8がヒータ6を挟むような位置関係になる。
すなわち、本実施形態における基体キャリア57は、成膜室の上部から出し入れするものであり、下向きの「コ」の字形状をなす。そして、基体キャリア57は2枚の枠体8を有し、枠体8は面状部25が外側を向くように互いに平行に設けられている。すなわち、第一実施形態の基体キャリア7と本実施形態の基体キャリア57とでは、枠体8の取り付け方向が逆である。そして、成膜室内における基体キャリア57とヒータ6との位置関係は、図14に示すようになる。すなわち、2枚の枠体8が1個のヒータ6を挟むように位置することとなり、ガラス基板(基体)20の露出面22が電極(図示せず)に対向する。本実施形態のプラズマCVD装置の作用は、第一実施形態のプラズマCVD装置1の作用と基本的に同じである。
In the present embodiment, an example of the “one-electrode double-sided discharge type” in which the film formation surface of the glass substrate 20 is installed facing inward is shown. However, the film formation surface (exposed surface) of the glass substrate as shown in FIG. The configuration of the present embodiment can be applied to a plasma CVD apparatus of the type arranged facing outwards in exactly the same manner. FIG. 14 is a perspective view of a base carrier in the third embodiment of the present invention. In the embodiment shown in FIG. 14, the frame carrier 8 of the substrate carrier 57 has a positional relationship such that the heater 6 is sandwiched in the film forming chamber.
That is, the substrate carrier 57 in this embodiment is taken in and out from the upper part of the film forming chamber, and has a downward “U” shape. The base carrier 57 has two frame bodies 8, and the frame bodies 8 are provided in parallel to each other so that the planar portion 25 faces outward. That is, the mounting direction of the frame body 8 is opposite between the base carrier 7 of the first embodiment and the base carrier 57 of the present embodiment. The positional relationship between the substrate carrier 57 and the heater 6 in the film forming chamber is as shown in FIG. That is, the two frame bodies 8 are positioned so as to sandwich one heater 6, and the exposed surface 22 of the glass substrate (base body) 20 faces an electrode (not shown). The operation of the plasma CVD apparatus of this embodiment is basically the same as that of the plasma CVD apparatus 1 of the first embodiment.

上記した実施形態では、いずれもガラス基板(基体)と電極を垂直方向に配置して対向させているが、垂直方向以外の方向にこれらを配置してもよい。例えば、ガラス基板(基体)と電極を水平方向に配置して対向させてもよい。この場合、電極面を下面、基体露出面を上面としてもよいし、基体露出面を下面、電極面を上面としてもよい。すなわち、本発明の半導体薄膜の製造方法および半導体薄膜製造装置は、基体と電極の配置方向に関わらず、その作用効果を発揮する。   In each of the above-described embodiments, the glass substrate (base) and the electrode are arranged in the vertical direction to face each other, but they may be arranged in a direction other than the vertical direction. For example, the glass substrate (base) and the electrode may be arranged in the horizontal direction to face each other. In this case, the electrode surface may be the lower surface, the substrate exposed surface may be the upper surface, the substrate exposed surface may be the lower surface, and the electrode surface may be the upper surface. That is, the semiconductor thin film manufacturing method and the semiconductor thin film manufacturing apparatus of the present invention exert their effects regardless of the arrangement direction of the base and the electrode.

上記した実施形態では、基体キャリアに設けられた枠体1枚につきガラス基板(基体)が1枚装着されていたが、複数のガラス基板が装着される実施形態も可能である。また、上記した実施形態では、成膜室内に設置される基体キャリアの数が1個であったが、複数の基体キャリアが設置できる実施形態も可能である。さらに、上記した実施形態のプラズマCVD装置は1個の成膜室を有するものであったが、複数の成膜室を有する実施形態も可能である。   In the embodiment described above, one glass substrate (substrate) is mounted on one frame provided on the substrate carrier, but an embodiment in which a plurality of glass substrates are mounted is also possible. In the embodiment described above, the number of substrate carriers to be installed in the film forming chamber is one, but an embodiment in which a plurality of substrate carriers can be installed is also possible. Furthermore, although the plasma CVD apparatus of the above-described embodiment has one film formation chamber, an embodiment having a plurality of film formation chambers is also possible.

また、上記した実施形態では電極5をカソード電極、基板支持電極31をアノード電極としたが、逆でも全く同一の効果が得られる。すなわち、段差28や壁48,54が設けられている限り、成膜領域におけるプラズマは均一なものとなる。   In the embodiment described above, the electrode 5 is a cathode electrode and the substrate support electrode 31 is an anode electrode. However, the opposite effect can be obtained. That is, as long as the step 28 and the walls 48 and 54 are provided, the plasma in the film formation region is uniform.

また、上記した実施形態では電極5が平行平板電極であったが、電極5はラダー電極であってもよい。   In the above embodiment, the electrode 5 is a parallel plate electrode, but the electrode 5 may be a ladder electrode.

本発明の半導体薄膜の製造方法は、例えば、薄膜太陽電池の製造に使用することができる。すなわち、本発明の半導体薄膜の製造方法によってシリコン系光電変換層を形成させることにより、シリコン系光電変換層を有する薄膜太陽電池を製造することができる。 Producing how the semiconductor thin film of the present invention, for example, may be used in the manufacture of thin-film solar cell. That is, by forming the thus silicon-based photoelectric conversion layer in the manufacture how the semiconductor thin film of the present invention, it is possible to manufacture a thin-film solar cell having a silicon-based photoelectric conversion layer.

以下に実施例をもって本発明を具体的に説明するが、本発明は実施例に限定されるものではない。   EXAMPLES The present invention will be specifically described below with reference to examples, but the present invention is not limited to the examples.

図1〜9に示した第一実施形態のプラズマCVD装置を用い、種々の条件で、ガラス基板に半導体薄膜の成膜を行った。すなわち、縦950mm、横980mmのガラス基板20を基体キャリア57の枠体8に装着し、基体支持電極31とした。この基体支持電極31を成膜室に導入し、基体支持電極31を電極5に対向させて配置した。電極間距離(電極5の表面とガラス基板20の露出面22との距離)は9mmとした。なお、電極5と基板支持電極31については、それらの平面度がいずれも0.3mm以内となるように製作および組立てを行った。成膜条件として、電極5と基板支持電極31との平行度を3種類、段差28(枠体8の内周面26と外周面27とで形成される)の高さを5種類に振り、計15種類の条件で成膜を行った。ここで、電極5と基板支持電極31との平行度は、電極間距離の−5%〜+5%、同−10%〜+10%、同−15%〜+15%の3種類とした。また段差28の高さは、段差28の高さの電極間距離に対する比をkとして、k=0(電極間距離の0倍。段差なし。)、k=1/20(電極間距離の1/20倍)、k=1/10(電極間距離の1/10倍)、k=1/5(電極間距離の1/5倍)、及び、k=1/3(電極間距離の1/3倍)の5種類とした。なお、段部30の高さは2mmの固定値とし、かつテーパ状に形成した。これらの条件で半導体薄膜の成膜を行い、成膜された半導体薄膜の膜厚分布(%)を測定した。   Using the plasma CVD apparatus of the first embodiment shown in FIGS. 1 to 9, a semiconductor thin film was formed on a glass substrate under various conditions. That is, a glass substrate 20 having a length of 950 mm and a width of 980 mm was mounted on the frame body 8 of the base carrier 57 to form the base support electrode 31. The substrate support electrode 31 was introduced into the film forming chamber, and the substrate support electrode 31 was arranged to face the electrode 5. The distance between the electrodes (the distance between the surface of the electrode 5 and the exposed surface 22 of the glass substrate 20) was 9 mm. In addition, about the electrode 5 and the board | substrate support electrode 31, manufacture and assembly were performed so that those flatness might be all within 0.3 mm. As film formation conditions, the parallelism between the electrode 5 and the substrate support electrode 31 is changed to three types, and the height of the step 28 (formed by the inner peripheral surface 26 and the outer peripheral surface 27 of the frame body 8) is changed to five types. Film formation was performed under a total of 15 conditions. Here, the parallelism between the electrode 5 and the substrate support electrode 31 was set to three types of −5% to + 5%, −10% to + 10%, and −15% to + 15% of the distance between the electrodes. The height of the step 28 is k = 0 (0 times the inter-electrode distance, no step), and k = 1/20 (1 of the inter-electrode distance), where k is the ratio of the height of the step 28 to the inter-electrode distance. / 20 times), k = 1/10 (1/10 times the distance between electrodes), k = 1/5 (1/5 times the distance between electrodes), and k = 1/3 (1 times the distance between electrodes). / 3 times). In addition, the height of the step part 30 was set to a fixed value of 2 mm and formed in a tapered shape. A semiconductor thin film was formed under these conditions, and the film thickness distribution (%) of the formed semiconductor thin film was measured.

結果を第1表に示す。すなわち、電極間の平行度が−5%〜+5%のとき、段差28を設けない場合(k=0)には膜厚分布が「±19%」であったが、段差28を設けた場合(k=1/20、1/10、1/5、1/3)はいずれも膜厚分布が「±10%以下」と良好であった。   The results are shown in Table 1. That is, when the parallelism between the electrodes is −5% to + 5%, the film thickness distribution is “± 19%” when the step 28 is not provided (k = 0), but the step 28 is provided. (K = 1/20, 1/10, 1/5, 1/3) all had good film thickness distributions of “± 10% or less”.

また、電極間の平行度を−10%〜+10%とやや悪化させたとき、段差28を設けない場合(k=0)には膜厚分布が「±38%」と急激に悪化した。しかし、段差28を設けた場合でk=1/5とk=1/3のときはいずれも膜厚分布が「±10%以下」と良好な値を保っていた。また、k=1/20とk=1/10のときは、膜厚分布はやや悪化したが、段差28を設けない場合(k=0)に比べてその悪化度は小さかった。   Further, when the parallelism between the electrodes was slightly deteriorated to −10% to + 10%, the film thickness distribution rapidly deteriorated to “± 38%” when the step 28 was not provided (k = 0). However, when k = 1/5 and k = 1/3 in the case where the step 28 was provided, the film thickness distribution maintained a good value of “± 10% or less”. Further, when k = 1/20 and k = 1/10, the film thickness distribution was slightly deteriorated, but the degree of deterioration was small as compared with the case where the step 28 was not provided (k = 0).

また、電極間の平行度を−15%〜+15%とさらに悪化させたとき、段差28を設けない場合(k=0)には膜厚分布が「±50%以上」とさらに悪化した。しかし、段差28を設けた場合でk=1/3のときは膜厚分布が「±10%以下」と良好な値を保っていた。また、k=1/20、k=1/10、及びk=1/5のときはいずれも膜厚分布がやや悪化したが、段差28を設けない場合(k=0)に比べてその悪化度は小さかった。   Further, when the parallelism between the electrodes was further deteriorated to −15% to + 15%, the film thickness distribution was further deteriorated to “± 50% or more” when the step 28 was not provided (k = 0). However, when the step 28 is provided and when k = 1/3, the film thickness distribution is “± 10% or less” and maintains a good value. In addition, when k = 1/20, k = 1/10, and k = 1/5, the film thickness distribution is slightly deteriorated, but the deterioration is worse than when the step 28 is not provided (k = 0). The degree was small.

以上より、基体キャリア7の枠体8に段差28を設けることにより、ガラス基板20の露出面22に成膜される半導体薄膜の膜厚を均一化することができた。これは、段差28によって発生したプラズマが閉じ込められ、成膜領域においてプラズマが均一化されたことによると考えられた。   As described above, by providing the step 28 on the frame 8 of the base carrier 7, the thickness of the semiconductor thin film formed on the exposed surface 22 of the glass substrate 20 can be made uniform. This was considered to be because the plasma generated by the step 28 was confined and the plasma was made uniform in the film formation region.

Figure 0005028044
Figure 0005028044

本発明の第一実施形態のプラズマCVD装置が備える成膜室の斜視図である。It is a perspective view of the film-forming chamber with which the plasma CVD apparatus of 1st embodiment of this invention is provided. 図1のA−A断面図である。It is AA sectional drawing of FIG. 図1の成膜室に収納される基体キャリアの斜視図である。It is a perspective view of the base | substrate carrier accommodated in the film-forming chamber of FIG. 図3の基体キャリアの分解斜視図である。It is a disassembled perspective view of the base | substrate carrier of FIG. 成膜室内における基体キャリアと電極との位置関係を示す一部破断斜視図である。It is a partially broken perspective view which shows the positional relationship of the base | substrate carrier and electrode in a film-forming chamber. 基体キャリアの内側の状態を示す一部破断斜視図である。It is a partially broken perspective view which shows the state inside a base carrier. 図6のB−B断面斜視図である。It is a BB cross-sectional perspective view of FIG. 成膜領域におけるプラズマの状態を模式的に表す断面図である。It is sectional drawing which represents typically the state of the plasma in a film-forming area | region. (a)はプラズマが収縮した場合のプラズマの状態を模式的に示す断面図、(b)はプラズマが外周面上にはみ出た場合のプラズマの状態を模式的に示す断面図である。(A) is sectional drawing which shows typically the state of the plasma when a plasma shrinks, (b) is sectional drawing which shows typically the state of the plasma when a plasma protrudes on an outer peripheral surface. 参考例のプラズマCVD装置の要部を示す断面図である。It is sectional drawing which shows the principal part of the plasma CVD apparatus of a reference example . 参考例のプラズマCVD装置の要部を示す断面図である。It is sectional drawing which shows the principal part of the plasma CVD apparatus of a reference example. 実施形態のプラズマCVD装置の要部を示す断面図である。It is sectional drawing which shows the principal part of the plasma CVD apparatus of 2nd embodiment. 第一実施形態における枠体の一例を示す断面図である。It is sectional drawing which shows an example of the frame in 1st embodiment. 本発明の第実施形態における基体キャリアの斜視図である。It is a perspective view of the base | substrate carrier in 3rd embodiment of this invention. 従来のプラズマCVD装置の構成を模式的に表す縦断面図である。It is a longitudinal cross-sectional view which represents typically the structure of the conventional plasma CVD apparatus. 従来のプラズマCVD装置における基板と支持部材の要部の拡大断面図である。It is an expanded sectional view of the principal part of the board | substrate and support member in the conventional plasma CVD apparatus. 従来の別のプラズマCVD装置における基板と支持部材の要部の拡大断面図である。It is an expanded sectional view of the principal part of the board | substrate and support member in another conventional plasma CVD apparatus. 1電極両面放電タイプのプラズマCVD装置の構成を模式的に表す縦断面図である。It is a longitudinal cross-sectional view which represents typically the structure of a 1-electrode double-sided discharge type plasma CVD apparatus. 従来のプラズマCVD装置におけるプラズマの状態を模式的に示す断面図であり、(a)は理想的な状態、(b)はプラズマの広がり具合が小さい場合の状態、(c)はプラズマの広がり具合が大きい場合の状態、(d)はプラズマが収縮した場合の状態を示す。It is sectional drawing which shows typically the state of the plasma in the conventional plasma CVD apparatus, (a) is an ideal state, (b) is a state in case the spread of plasma is small, (c) is the spread of plasma. (D) shows the state when the plasma contracts.

1 プラズマCVD装置(半導体薄膜製造装置)
2 製膜室
5 電極
8 枠体(支持部材)
16 開口
20 ガラス基板(基体)
22 露出面(基体露出面)
25 面状部
26 内周面(基体側電極対向面)
27 外周面(端部側電極対向面)
28 段差(壁)
30 段部
42 枠体(支持部材)
46 枠体(支持部材)
47 面状部
52 枠体(支持部材)
53 面状部
54 壁
1 Plasma CVD equipment (semiconductor thin film production equipment)
2 Film forming chamber 5 Electrode 8 Frame (supporting member)
16 opening 20 glass substrate (base)
22 Exposed surface (Substrate exposed surface)
25 Planar part 26 Inner peripheral surface (substrate-side electrode facing surface)
27 Peripheral surface (surface facing the electrode on the end side)
28 steps (walls)
30 steps 42 frame (support member)
46 Frame (supporting member)
47 Planar part 52 Frame (support member)
53 Surface 54 Wall

Claims (6)

半導体薄膜を成膜すべき基体を支持部材に装着して該基体の一部又は全部を該支持部材から露出させ、電極を備えた成膜室内において基体露出面が電極面に対向するように前記支持部材を配置して、基体が装着された支持部材と電極との間にプラズマ発生空間を形成させ、前記電極に高周波電力を供給して放電を発生させ、基体露出面に半導体薄膜を成膜するプラズマCVD工程を含む半導体薄膜の製造方法であって、前記プラズマ発生空間にプラズマを遮蔽する壁を設けるものであり、前記支持部材は、基体露出面の外縁に位置し且つ前記電極面に対向する面状部を有し、前記面状部に前記壁を設け、前記面状部と前記基体露出面とは段部を形成しており、電極面と面状部との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下であり、前記段部は、面状部から基体露出面に向かって高さが小さくなるテーパ状に形成されていることを特徴とする半導体薄膜の製造方法。 A substrate on which a semiconductor thin film is to be formed is mounted on a support member, and a part or all of the substrate is exposed from the support member, and the substrate exposed surface is opposed to the electrode surface in a film forming chamber provided with electrodes. A support member is arranged to form a plasma generation space between the support member on which the substrate is mounted and the electrode, and a high frequency power is supplied to the electrode to generate discharge, and a semiconductor thin film is formed on the substrate exposed surface A method of manufacturing a semiconductor thin film including a plasma CVD step, wherein a wall for shielding plasma is provided in the plasma generation space, and the support member is located at an outer edge of a substrate exposed surface and faces the electrode surface The planar portion is provided with the wall, the planar portion and the substrate exposed surface form a stepped portion, and the distance between the electrode surface and the planar portion is the electrode surface Smaller than the distance to the substrate exposed surface, Saga and at 0.5mm or more and 4.0mm or less, the step portion, fabrication of the semiconductor thin film characterized by being formed in a tapered shape in which the height decreases toward the planar portion on the substrate exposed surface Method. 半導体薄膜を成膜すべき基体を支持部材に装着して該基体の一部又は全部を該支持部材から露出させ、電極を備えた成膜室内において基体露出面が電極面に対向するように前記支持部材を配置して、基体が装着された支持部材と電極との間にプラズマ発生空間を形成させ、前記電極に高周波電力を供給して放電を発生させ、基体露出面に半導体薄膜を成膜するプラズマCVD工程を含む半導体薄膜の製造方法であって、前記プラズマ発生空間にプラズマを遮蔽する壁を設けるものであり、前記支持部材は、基体露出面の外縁に位置し且つ前記電極面に対向する面状部を有し、前記面状部に前記壁を設け、前記面状部は、基体露出面に隣接する基体側電極対向面と、該基体側電極対向面の基体露出面側とは反対側に隣接する端部側電極対向面とを有し、該基体側電極対向面と該端部側電極対向面とは、端部側電極対向面と電極面との距離が基体側電極対向面と電極面との距離よりも小さくなる段差を形成しており、前記壁は当該段差により形成されており、前記基体側電極対向面と前記基体露出面とは段部を形成しており、電極面と基体側電極対向面との距離は電極面と基体露出面との距離よりも小さく、前記段部の高さが0.5mm以上かつ4.0mm以下であり、前記段部は、基体側電極対向面から基体露出面に向かって高さが小さくなるテーパ状に形成されていることを特徴とする半導体薄膜の製造方法。 A substrate on which a semiconductor thin film is to be formed is mounted on a support member, and a part or all of the substrate is exposed from the support member, and the substrate exposed surface is opposed to the electrode surface in a film forming chamber provided with electrodes. A support member is arranged to form a plasma generation space between the support member on which the substrate is mounted and the electrode, and a high frequency power is supplied to the electrode to generate discharge, and a semiconductor thin film is formed on the substrate exposed surface A method of manufacturing a semiconductor thin film including a plasma CVD step, wherein a wall for shielding plasma is provided in the plasma generation space, and the support member is located at an outer edge of a substrate exposed surface and faces the electrode surface The surface portion is provided with the wall, and the surface portion includes a substrate side electrode facing surface adjacent to the substrate exposed surface, and a substrate exposed surface side of the substrate side electrode facing surface. An end-side electrode facing surface adjacent to the opposite side; The base-side electrode facing surface and the end-side electrode facing surface have a step where the distance between the end-side electrode facing surface and the electrode surface is smaller than the distance between the base-side electrode facing surface and the electrode surface. The wall is formed by the step , the base-side electrode facing surface and the base-exposed surface form a step, and the distance between the electrode surface and the base-side electrode facing surface is the electrode The height of the step portion is 0.5 mm or more and 4.0 mm or less, and the step portion has a height from the substrate-side electrode facing surface toward the substrate exposure surface. method of manufacturing a semi-conductor film you characterized in that it is formed in a tapered shape which becomes smaller. 前記段差の高さは、前記電極面と前記基体露出面との距離の1/20以上かつ1/3以下であることを特徴とする請求項に記載の半導体薄膜の製造方法。 3. The method of manufacturing a semiconductor thin film according to claim 2 , wherein the height of the step is 1/20 or more and 1/3 or less of a distance between the electrode surface and the substrate exposed surface. 前記支持部材は開口を有する枠体からなり、前記基体の一部又は全部を該開口から露出させることを特徴とする請求項1乃至3のいずれか1項に記載の半導体薄膜の製造方法。 It said support member is made of a frame body having an opening, the method for manufacturing a semiconductor thin film according to any one of claims 1 to 3, characterized in that to expose a portion or all of the base from the opening. 前記基体は板体であり、基体露出面は該板体の一方の面の一部又は全部であることを特徴とする請求項1乃至4のいずれか1項に記載の半導体薄膜の製造方法。 It said substrate is a plate member, a method of manufacturing a semiconductor thin film according to any one of claims 1 to 4, wherein the substrate exposed surface is a part or all of one surface of the plate member. 前記支持部材に複数の基体を並べて装着し、各々の基体の一部又は全部を支持部材から露出させ、複数の基体に対して半導体薄膜を成膜することを特徴とする請求項1乃至5のいずれか1項に記載の半導体薄膜の製造方法。 The support member side by side a plurality of substrates mounted, to expose part or all of each of the substrate from the support member, according to claim 1 to 5, characterized in that for forming a semiconductor thin film to a plurality of base A manufacturing method of a semiconductor thin film given in any 1 paragraph.
JP2006203478A 2006-07-26 2006-07-26 Manufacturing method of semiconductor thin film Expired - Fee Related JP5028044B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006203478A JP5028044B2 (en) 2006-07-26 2006-07-26 Manufacturing method of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006203478A JP5028044B2 (en) 2006-07-26 2006-07-26 Manufacturing method of semiconductor thin film

Publications (2)

Publication Number Publication Date
JP2008034469A JP2008034469A (en) 2008-02-14
JP5028044B2 true JP5028044B2 (en) 2012-09-19

Family

ID=39123609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006203478A Expired - Fee Related JP5028044B2 (en) 2006-07-26 2006-07-26 Manufacturing method of semiconductor thin film

Country Status (1)

Country Link
JP (1) JP5028044B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101210555B1 (en) * 2008-06-06 2012-12-10 가부시키가이샤 아루박 Apparatus for manufacturing thin film solar cell
CN101999173B (en) * 2008-06-06 2013-02-13 株式会社爱发科 Apparatus for manufacturing thin film solar cell
CN111690911B (en) * 2020-06-30 2023-07-25 通威太阳能(金堂)有限公司 Bearing device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05160039A (en) * 1991-12-02 1993-06-25 Canon Inc Semiconductor film forming device
JPH06120153A (en) * 1992-10-06 1994-04-28 Canon Inc Film-forming apparatus
JP3723003B2 (en) * 1998-12-18 2005-12-07 三菱重工業株式会社 Vacuum processing system
JP2001127048A (en) * 1999-10-29 2001-05-11 Nihon Ceratec Co Ltd Member for semiconductor wafer treatment
JP4676074B2 (en) * 2001-02-15 2011-04-27 東京エレクトロン株式会社 Focus ring and plasma processing apparatus
JP3820197B2 (en) * 2002-08-23 2006-09-13 三菱重工業株式会社 Vacuum processing equipment

Also Published As

Publication number Publication date
JP2008034469A (en) 2008-02-14

Similar Documents

Publication Publication Date Title
KR100253134B1 (en) Substrate process apparatus
TWI425109B (en) Apparatus for chemical vapor deposition
JP3179605U (en) Heating and cooling the substrate support
JP4646609B2 (en) Plasma CVD equipment
TWI405261B (en) Dry etching apparatus
US20060054090A1 (en) PECVD susceptor support construction
TW200908361A (en) An apparatus for depositing a uniform silicon film and methods for manufacturing the same
JP5517392B2 (en) Substrate support assembly, process chamber and method for maintaining the temperature of a substrate in the process chamber
JP5028044B2 (en) Manufacturing method of semiconductor thin film
US20130040414A1 (en) Method for manufacturing a thin-film solar cell
KR20130102577A (en) Substrate heating device
KR101046910B1 (en) Vacuum processing equipment
JPH08260158A (en) Substrate treating device
JP5748858B2 (en) Plasma film forming apparatus and plasma film forming method
TWI455653B (en) Plasma reactor for treating a substrate
US20130004681A1 (en) Mini blocker plate with standoff spacers
CN110241382A (en) The manufacturing method of the one-piece type mask of frame
JP2013187318A (en) In-line type plasma cvd apparatus
JP2007327097A (en) Plasma treatment apparatus
KR101464662B1 (en) Improved Boat, and Heat Treatment Chamber and Apparatus of Substrate Having the Same
KR20200044747A (en) Producing method of mask and producing method of mask integrated frame
KR20100094696A (en) Boat
KR101800915B1 (en) Chemical Vapor Deposition Apparatus for Flat Panel Display
KR20200004115A (en) Producing method of mask integrated frame
JPH01232717A (en) Device for manufacture of thin film of amorphous silicon solar battery

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090525

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110608

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110616

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120321

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120518

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120604

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120625

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150629

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5028044

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150629

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees