JP5010352B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an extremely shallow impurity diffusion region in which a diffusion region in a depth direction is extremely shallow.

  With the increase in performance and functionality of semiconductor devices, the number of elements mounted on the devices has been increasing dramatically in recent years. In order to mount such an increasing number of elements in an apparatus of the same scale or a reduced scale, a fine processing technique is required.

  When miniaturizing an element, it is necessary not only to reduce the area of the impurity diffusion region but also to make the diffusion region in the depth direction shallow. For this purpose, when forming the impurity diffusion region, an impurity implantation process and an annealing process (heat treatment) for activation are performed under such conditions that the diffusion region is not formed deep in the depth direction from the substrate surface. There is a need to do. Therefore, it is important to optimize the setting conditions when performing the impurity implantation process and the annealing process.

  In the past, heat treatment by furnace annealing has been performed as the annealing treatment. However, in the case of furnace annealing, the implanted impurities can be sufficiently activated by high-temperature heat treatment for a long time, but the junction depth increases due to thermal diffusion. Therefore, even if an impurity implantation process (ultra shallow implantation process) is performed to form a shallow diffusion region in order to miniaturize the element, a desired impurity concentration distribution can be obtained by performing an annealing process by furnace annealing. There was a problem that I could not. In response to this, an annealing process that suppresses diffusion in the depth direction while activating the ultra-shallow implanted impurities by high-temperature short-time heat treatment of about several μs to several s has been studied in recent years. Typical technologies include spike annealing that rapidly heats the substrate with the high heat output of the heating lamp, and flash lamp annealing that enables high-temperature heat treatment for a shorter time using a flash lamp. It is attracting attention as an annealing technique necessary for junction formation.

  Further, when performing the spike annealing process, as a technique for further suppressing the diffusion of the impurity diffusion region in the depth direction, as shown in FIG. 5, a high speed is reached until the temperature reaches 1000 ° C. (annealing arrival temperature). Patent Document 1 below describes a method in which the temperature is lowered at a high speed to 900 ° C. and then lowered at a high speed.

  When the temperature of the semiconductor substrate raised to the annealing temperature is lowered, the solid solubility of the implanted impurity is also lowered, so that the bond between the implanted impurity and the semiconductor substrate is easily broken. However, according to Patent Document 1 described below, by lowering the temperature lowering rate of the semiconductor substrate from the middle, the stress on the bonding can be alleviated and damage or peeling can be prevented. Further, since the temperature lowering rate is high halfway, sufficient thermal energy does not act on the bond with the semiconductor substrate for the impurities whose solid solubility is lowered. For this reason, it is possible to suppress unnecessary diffusion of the ion-implanted impurity without breaking the bond between the impurity and the semiconductor substrate.

  As another method, as shown in FIG. 6, a semiconductor substrate is heated to a preheating temperature T1 (400 to 600 ° C.) with a halogen lamp, and then Xe (xenon) flash is taken over a short time of about 0.1 to 10 ms. Patent Document 2 below describes a method of raising the temperature of a semiconductor substrate preheated by a halogen lamp to an annealing temperature T2 (1000 to 1100 ° C.) by irradiating the lamp.

  Under heating at about T1 ° C., the implanted impurities are not further diffused, and the temperature of the impurity diffusion region can be increased in a short time by raising the temperature to about T2 ° C. required for processing in a very short time. Can be realized. In particular, by preheating to the extent that impurities do not diffuse, the temperature required for activation can be reached quickly.

JP 2001-297996 A JP 2003-173983 A

  However, the annealing methods described in the above patent documents have the following problems.

  High-temperature short-time annealing used for ultra-shallow impurity bonding is a short-time temperature rise / fall heat treatment, and it is extremely difficult to control the heat treatment. For this reason, it is difficult to suppress variations in heat treatment between apparatuses, between lots, between wafers, between wafer in-plane coordinates, and the like. Moreover, in order to suppress these, a complicated processing mechanism is required.

  Then, when the variation in the heat treatment as described above occurs, the junction depth of the impurity diffusion region varies, resulting in a variation in the electrical characteristics of the device.

  In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor device having an extremely shallow impurity diffusion region that can suppress variation in characteristics due to junction depth.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a first step of implanting impurities into a semiconductor substrate surface to form a very shallow impurity diffusion region, and after the completion of the first step, A second step of forming a semiconductor material film having an impurity diffusion coefficient equal to or higher than the impurity diffusion coefficient of the semiconductor substrate on the impurity diffusion region; and after the second step, annealing is performed to perform the ultra-shallow impurity diffusion region. And a third step of forming a very shallow junction by activating the first feature.

  According to the first feature of the method of manufacturing a semiconductor device according to the present invention, the semiconductor material film having an impurity diffusion coefficient greater than or equal to the impurity diffusion coefficient of the semiconductor substrate is formed on the extremely shallow impurity diffusion region. Annealing treatment is performed. The impurities in the ultra-shallow impurity diffusion region are further diffused by applying energy (thermal energy, light energy, etc.) by heating during the annealing process. At this time, the semiconductor material film and the ultra-shallow impurity diffusion region As the semiconductor material film has a larger impurity diffusion coefficient than the semiconductor substrate, impurities in the ultra-shallow impurity diffusion region diffuse in the direction of the semiconductor material film formation. Will be.

  Therefore, compared with the case where the semiconductor material film is not formed, it is possible to suppress the diffusion of the implanted impurities during the annealing process in the depth direction of the semiconductor substrate. For this reason, since the activation process can be executed while suppressing the diffusion of impurities to the semiconductor substrate side, a semiconductor device having an extremely shallow junction can be manufactured. In forming such an ultra-shallow junction, it is only necessary to perform an annealing process after forming a semiconductor material film, and precise temperature control during the annealing process is not required as in the prior art. Accordingly, a complicated control mechanism for performing temperature control is not required, and there is no problem of variations in heat treatment between apparatuses, lots, wafers, wafer surface coordinates, and the like. Accordingly, it is possible to form an extremely shallow junction while suppressing variation in characteristics due to the junction depth.

  In addition to the first feature, the semiconductor device manufacturing method according to the present invention has a second feature that the semiconductor material film is a material film made of polysilicon or amorphous silicon.

  In addition to the first feature, the semiconductor device manufacturing method according to the present invention is a material film in which the semiconductor material film is formed of any one of a silicon compound containing germanium and a silicon compound containing carbon. This is the third feature.

  According to the second or third feature of the method of manufacturing a semiconductor device according to the present invention, the polysilicon is in a polycrystalline state, and the amorphous silicon is in an incomplete crystal state. The impurity diffusion coefficient is larger than that of the substrate (silicon single crystal). Therefore, by using these materials as the semiconductor material film, during the annealing process, the implanted impurities are more diffused to the semiconductor material film side than the depth direction of the semiconductor substrate, and diffusion in the depth direction is performed. Further suppression can be achieved.

  According to the semiconductor device manufacturing method of the present invention, in addition to any one of the first to third features, the third step is performed using a flash lamp filled with a rare gas. A fourth feature is that the annealing process is performed by annealing.

  According to the fourth feature of the method for manufacturing a semiconductor device according to the present invention, since the annealing process is performed in a short time, the diffusion of the implanted impurities can be suppressed as much as possible. In particular, as described in the third feature, when a material film of a silicon compound containing germanium or a silicon compound containing carbon is used as the semiconductor material film, the optical band gap is widened. It is easy to adjust the sensitivity. Therefore, the sensitivity of light irradiation is adjusted by executing the annealing process by the flash lamp annealing in a state in which the semiconductor material film composed of these material films is formed, so that the ultrashallow impurity diffusion region can be adjusted. The active state can be adjusted to a desired state.

  Further, in the semiconductor device manufacturing method according to the present invention, in addition to any one of the first to fourth features, the first step is a region above a depth position of 50 nm from the semiconductor substrate surface. The fifth feature is that it is a step of forming the ultra-shallow impurity diffusion region therein.

  According to the fifth feature of the method of manufacturing a semiconductor device according to the present invention, the ultra-shallow impurity diffusion region is formed in the ultra-narrow region from the semiconductor substrate surface to the depth position of 50 nm. Variation in thermal diffusion during annealing in the region is greatly suppressed.

  Further, in addition to any one of the first to fifth features, the method for manufacturing a semiconductor device according to the present invention includes reacting the semiconductor material film and the metal film after the third step. A sixth feature is that it includes a fourth step of forming a silicide layer on the semiconductor material film.

  According to the sixth feature of the method of manufacturing a semiconductor device according to the present invention, when the contact plug for forming an electrical connection between the wiring layer and the ultra-shallow impurity diffusion region is formed in a later step, Contact resistance can be reduced. In addition, since the silicide layer is formed by reacting the semiconductor material film and the metal film, it is not necessary to react the semiconductor substrate surface on which the ultra-shallow impurity diffusion region is formed with the metal film to form the silicide layer. Therefore, it is possible to suppress the influence on the electrical characteristics of the extremely shallow impurity diffusion region when the silicide layer is formed.

  In the semiconductor device manufacturing method according to the present invention, in addition to the sixth feature, the second step forms the semiconductor material film having a thickness of 20 nm or more on the ultra-shallow impurity diffusion region. This is the seventh feature.

  According to the seventh feature of the method of manufacturing a semiconductor device according to the present invention, since the semiconductor material film has a sufficient thickness, the semiconductor material film and the metal film are formed by reaction. The silicide layer does not reach the semiconductor substrate surface, and the silicide layer does not come into contact with the extremely shallow impurity diffusion region. For this reason, the influence with respect to the electrical property of the ultra-shallow impurity diffusion area | region at the time of silicide layer formation can be suppressed.

  According to the present invention, since the activation process can be performed while suppressing the diffusion of impurities to the semiconductor substrate side, a semiconductor device having an extremely shallow junction can be manufactured. When forming such an ultra-shallow junction, it is only necessary to perform a flash lamp annealing process after forming a semiconductor material film with a predetermined film thickness. Is unnecessary. Accordingly, a complicated control mechanism for performing temperature control is not required, and there is no problem of variations in heat treatment between apparatuses, lots, wafers, wafer surface coordinates, and the like. Accordingly, it is possible to form an extremely shallow junction while suppressing variation in characteristics due to the junction depth.

  In the following, an embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “method of the present invention” as appropriate) will be described with reference to FIGS.

  FIG. 1 schematically shows a schematic cross-sectional structure diagram in each process when a semiconductor device is manufactured by using the method of the present invention. The process is divided into FIGS. 1A to 1E for each process. Show. Note that these schematic configuration diagrams are merely schematically illustrated, and the scale of the actual structure does not necessarily match the scale of the drawing.

First, as shown in FIG. 1A, a gate oxide film 12, a gate electrode 13, and a protective insulating film 14 are sequentially formed on a semiconductor substrate 11 (here, a P-type substrate), and then the gate electrode 13 is masked. As a result, ion implantation is performed under conditions of an implantation energy of about 2 keV and an implantation amount of about 1 × 10 ¹¹ ions / cm ^2, thereby forming a low concentration ultra-shallow impurity diffusion region 15. The low-concentration ultra-shallow impurity diffusion region 15 has a lower concentration than the ion concentration implanted for forming the source / drain regions in a later step, and forms an extension region.

Next, as shown in FIG. 1B, after the sidewall insulating film 17 is formed on the outer wall of the gate electrode 3, the implantation energy is about 2 keV and the implantation amount is 5 × 10 ¹⁵ ions / cm ^{2 using the} gate electrode 13 as a mask. Ion implantation is performed under conditions of about a degree to form a high concentration ultra-shallow impurity diffusion region (hereinafter referred to as “source / drain region”) 18.

Next, as shown in FIG. 1C, after the semiconductor material film 21 is deposited on the entire surface of the substrate to a thickness of about 250 nm, the film formation surface of the semiconductor material film 21 is flattened and subjected to an etching process. The semiconductor material film 21 is left on the region 18 with a thickness of about 20 nm. At this time, as the semiconductor material film 21, a polysilicon film having a concentration of impurities that can be carriers in the doped semiconductor is 1 × 10 ¹⁵ ions / cm ³ or less is used.

  Next, flash lamp annealing using a rare gas such as Xe is performed so that heat treatment at 1100 ° C. or higher is performed for a short time of 10 ms or less, and the depth of the ultrashallow impurity diffusion regions (15, 18) is increased. The activation process is performed while suppressing diffusion as much as possible. At this time, since the semiconductor material film 21 is composed of a polysilicon film, the impurity diffusion coefficient is larger than that of the semiconductor substrate 11, and there is a very large concentration difference between the semiconductor material film 21 and the source / drain regions 18. Therefore, the impurities in the source / drain regions 18 diffuse not only in the depth direction (downward direction in the drawing) of the semiconductor substrate 11 but also in the semiconductor material film 21 side (upward direction in the drawing). That is, the ultra-shallow impurity diffusion regions 15 and 18 can be activated while suppressing the absolute amount of impurity diffusion in the depth direction (inner junction direction).

  In the following, experimental results on the degree of impurity diffusion when annealing is performed in a state where a predetermined deposition film is formed on a semiconductor substrate surface or an extremely shallow impurity diffusion region formed in the substrate. It demonstrates with reference to the graph which shows.

  FIG. 2 is a cross-sectional structure diagram of a semiconductor substrate to be annealed. That is, the deposited film 20 is formed on the extremely shallow impurity diffusion region 18 formed by ion-implanting arsenic (As) into the P-type semiconductor substrate (silicon substrate) 11 at an implantation energy of 2 keV (description of the explanation) For convenience, the deposited film 20 has a different sign from the semiconductor material film 21). FIG. 3 shows a comparison result in the case where a silicon oxide film and polysilicon are employed as the deposited film 20 with respect to the impurity concentration distribution when annealing is performed at a heat treatment temperature of 1050 ° C. for 2 to 32 seconds under this state. . The experimental results shown in FIG. 3 are obtained by calculating the impurity (As) concentration distribution at each position after the annealing treatment by calculating an impurity concentration profile using a device simulator.

  FIG. 3 is a graph showing the relationship between the depth position and the impurity (As) concentration when the depth position of the substrate surface is 0 (reference) and the semiconductor substrate direction is the positive direction. 3A shows a case where silicon oxide (insulating film) is used as the deposited film 20, and FIG. 3B shows a case where polysilicon (semiconductor material film) is used. In any case, the experimental results in three patterns of (1) 2 seconds, (2) 8 seconds, and (3) 32 seconds are shown as the annealing treatment time.

According to FIG. 3A, As ions are not detected at a position where the substrate depth is negative, that is, on the deposited film 20 side (silicon oxide film side). On the other hand, according to FIG. 3B, the substrate depth is at a negative position, that is, about 1 × 10 ¹⁹ ions / cm ³ to 1 × 10 ²⁰ ions / cm ³ on the deposited film 20 side (polysilicon film side). An As concentration of about ³ is measured. This indicates that As ions hardly diffuse toward the silicon oxide film by annealing, but As ions diffuse into the polysilicon film.

  Further, referring to both graphs in FIG. 3, it can be seen that the longer the annealing time, the deeper the diffusion to the semiconductor substrate 11 side. However, in the case of FIG. 3B, it can be seen that the diffusion in the substrate direction is greatly suppressed as compared to FIG. 3A (see graphs (2) and (3)). In FIG. 3B, the longer the annealing time, the higher the As concentration in the polysilicon film. Therefore, the As diffused toward the semiconductor substrate 11 in FIG. It can be seen that the diffusion to the side of the polysilicon film suppresses the diffusion toward the semiconductor substrate 11 side.

  In the case of FIG. 3A, the diffusion coefficient of As of silicon oxide is remarkably low with respect to the semiconductor substrate 11. Therefore, As is not diffused to the silicon oxide film side and most is diffused to the semiconductor substrate 21 side by the annealing process. is doing. On the other hand, in the case of FIG. 3B, polysilicon has an impurity diffusion coefficient larger than that in a single crystal because the element is silicon and is incomplete crystal like the semiconductor substrate 11, and As is thus obtained by annealing. It can be said that this is because it can be easily diffused to the polysilicon film side.

  FIG. 4 is a graph showing the relationship when the annealing time is on the horizontal axis and the junction depth Xj (see FIG. 2) is on the vertical axis. The case where silicon oxide is adopted as the deposited film 20 is indicated by a broken line (1), and the case where polysilicon is adopted is indicated by a solid line (2).

  As can be seen from FIG. 4, under the same annealing time, the junction depth is shallower when the deposited film 20 is made of polysilicon than when silicon oxide is used. Therefore, based on this graph and the results of FIG. 3, it can be seen that the junction depth Xj can be reduced by diffusing impurities in the deposited film 20.

  Therefore, by performing the flash lamp annealing process for a short time under the state of FIG. 1C, the ultra-shallow impurity diffusion regions 15 and 18 can be activated while suppressing the diffusion of impurities in the depth direction. it can. Furthermore, since diffusion of impurities in the depth direction is suppressed, the formation of the ultra-shallow impurity diffusion region is kept within a predetermined region from the semiconductor substrate surface, thereby suppressing variations in the degree of thermal diffusion during annealing. Can do. In particular, during the impurity implantation, the impurity implantation is performed so that the ultra-shallow impurity diffusion regions 15 and 18 are formed in a region above the position of a depth of 50 nm from the surface of the semiconductor substrate, thereby suppressing variation in thermal diffusion. The effect can be enhanced.

  After the annealing process, as shown in FIG. 1 (d), after removing the protective insulating film 14, after depositing a metal film, the metal film, the lower gate electrode 13 and the semiconductor material film 21 constituting the semiconductor material film 21 are formed. By reacting the silicon film, a silicide layer (for example, cobalt silicide) 23 for reducing the resistance is formed on the surfaces of the gate electrode 13 and the semiconductor material film 21. In the state shown in FIG. 1C, by leaving the semiconductor material film 21 to a thickness of 20 nm or more, the influence of the silicide layer 23 reaching the source / drain region 18 on the electrical characteristics of the device is affected. It also has the effect of preventing.

  Thereafter, as shown in FIG. 1E, an interlayer insulating film 25 is formed on the entire surface, and then patterned by photolithography to open the gate electrode 13 and the upper portion of the source / drain region 18 to form a contact hole. After the formation, a Ti film 26 as a barrier metal layer and a TiN film 27 are formed on the inner wall of the hole, and then a W film 28 is filled in the hole as a contact material film to form a contact plug. Then, a well-known wiring process is performed. In the case of multilayer wiring, this plug formation process and wiring process are appropriately performed a plurality of times.

  According to the above-described method of the present invention, the activation process can be performed while suppressing the diffusion of impurities to the semiconductor substrate side, so that a semiconductor device having an extremely shallow junction can be manufactured. When forming such an ultra-shallow junction, it is only necessary to perform a short flash lamp annealing process after forming a semiconductor material film with a predetermined film thickness. No temperature control is required. Accordingly, a complicated control mechanism for performing temperature control is not required, and there is no problem of variations in heat treatment between apparatuses, lots, wafers, wafer surface coordinates, and the like. Accordingly, it is possible to form an extremely shallow junction while suppressing variation in characteristics due to the junction depth.

In the above embodiment, a polysilicon film is used as the semiconductor material film 21.
Even when the amorphous silicon film is formed, the same effect as that of the polysilicon film can be obtained. Since amorphous silicon can be formed by a low temperature process, the film forming conditions can be relaxed compared to the case of polysilicon. Further, since amorphous silicon has a random crystal structure, the impurity diffusion coefficient is larger than that of single crystal silicon constituting the semiconductor substrate 11.

  According to Fick's diffusion equation, the concentration difference as well as the diffusion coefficient is an important factor for impurity diffusion. Even if the concentration is uneven in crystals having the same diffusion coefficient, impurities diffuse from a high concentration to a low concentration. Therefore, if the semiconductor material film 21 is not a material having a remarkably low impurity diffusion coefficient such as a silicon oxide film but a silicon-based material having an impurity diffusion coefficient equal to or higher than that of the substrate semiconductor, the ultra-shallow impurity diffusion region may be reduced due to the difference in impurity concentration. Impurities can be diffused toward the semiconductor material film 21.

Further, even when a silicon compound film containing germanium or a silicon compound film containing carbon is used as the material of the semiconductor material film 21, an optical band for a crystal made only of silicon due to germanium or carbon contained in silicon. The gap changes. For this reason, in the process of forming the semiconductor material film 21, a silicon film forming gas such as silane (SiH ₄ ) and a gas containing germanium or carbon are simultaneously introduced, and the gas flow rate is adjusted to be contained in the semiconductor material film 21. By adjusting the germanium concentration or carbon concentration, the active state for the ultra-shallow impurity diffusion regions 15 and 18 can be adjusted.

  In the above-described embodiment, only the case where the flash lamp annealing process using a rare gas is performed as the annealing process has been described. However, the present invention can be similarly used even when the spike annealing process or the laser spike annealing process is used.

A schematic cross-sectional structure diagram in each process when a semiconductor device is manufactured using the method of the present invention. Cross-sectional structure diagram of semiconductor substrate to be annealed A graph showing the relationship between the depth position and the impurity concentration by annealing treatment A graph of the relationship between depth position and junction depth by annealing treatment Diagram showing the relationship between annealing time and heat treatment temperature when using conventional spike annealing Figure showing the relationship between annealing time and heat treatment temperature when using conventional flash lamp annealing treatment

Explanation of symbols

11: Semiconductor substrate 12: Gate oxide film 13: Gate electrode 14: Protective insulating film 15: Lightly doped ultra-shallow impurity diffusion region (extension region)
17: Side wall insulating film 18: High concentration ultra-shallow impurity diffusion region (source / drain region)
20: Deposited film 21: Semiconductor material film 23: Silicide layer 25: Interlayer insulating film 26: Ti film 27: TiN film 28: W film

Claims (7)

A first step of implanting impurities into the semiconductor substrate surface to form an extremely shallow impurity diffusion region;
After completion of the first step, a second semiconductor material film having an impurity concentration lower than that of the ultra-shallow impurity diffusion region and having an impurity diffusion coefficient equal to or higher than that of the semiconductor substrate is formed on the ultra-shallow impurity diffusion region . Process,
Immediately after the end of the second step, annealing is performed by any one of a flash lamp annealing process, a spike annealing process, and a laser spike process using a rare gas to activate the ultra-shallow impurity diffusion region to form an ultra-shallow junction. And a third step of forming the semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor material film is a material film made of polysilicon or amorphous silicon. The semiconductor material film is
2. The method of manufacturing a semiconductor device according to claim 1, wherein the material film is formed of any one of a silicon compound containing germanium and a silicon compound containing carbon. The third step is
4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is annealed by flash lamp annealing performed using a flash lamp in which a rare gas is sealed. 5. The first step includes
5. The semiconductor device according to claim 1, wherein the ultra shallow impurity diffusion region is formed in a region above a depth position of 50 nm from the semiconductor substrate surface. Manufacturing method.   6. The method according to claim 1, further comprising a fourth step of forming a silicide layer on the semiconductor material film by reacting the semiconductor material film with the metal film after the third step. Manufacturing method of semiconductor device as described in paragraph The second step includes
The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor material film is formed with a thickness of 20 nm or more on the ultra-shallow impurity diffusion region.

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