JP5004270B2 - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a group III nitride semiconductor device used for a high voltage device or a high frequency device and a manufacturing method thereof.

In a semiconductor device using a group III nitride semiconductor, a layer formed on the surface of a group III nitride semiconductor layer containing a p-type impurity (hereinafter sometimes referred to as a p-type group III nitride semiconductor layer) is etched. In some cases, at least a part of the surface of the p-type group III nitride semiconductor layer is exposed, and a metal electrode is formed on the exposed surface of the p-type group III nitride semiconductor layer. In addition, a group III nitride semiconductor layer containing n-type impurities (hereinafter sometimes referred to as an n-type group III nitride semiconductor layer) or a layer formed on the surface of an i-type group III nitride semiconductor layer is etched. In some cases, at least part of the surface of the n-type or i-type group III nitride semiconductor layer is exposed, and a metal electrode is formed on the exposed surface of the n-type or i-type group III semiconductor layer.
In the group III nitride semiconductor device of Patent Document 1, an n-type or i-type group III nitride semiconductor layer is formed by forming an n-type or i-type group III nitride semiconductor layer on the surface of the p-type group III nitride semiconductor layer. A gate insulating film is formed on the surface of the layer. The gate insulating film is etched to expose part of the surface of the n-type or i-type group III nitride semiconductor layer, and the n-type or i-type group III nitride semiconductor layer is further etched to form a p-type group III A part of the surface of the nitride semiconductor layer is exposed. Thereafter, a metal electrode is formed on each of the exposed surface of the p-type group III nitride semiconductor layer and the exposed surface of the n-type or i-type group III nitride semiconductor layer.
When a metal electrode is formed on the surface of the p-type group III nitride semiconductor layer, the potential of the p-type group III nitride semiconductor layer can be stabilized. As a result, a stable depletion layer can be formed between the p-type group III nitride semiconductor layer and the n-type or i-type group III nitride semiconductor layer, and a normally-off characteristic can be realized. When a metal electrode is formed on the surface of the n-type or i-type group III nitride semiconductor layer, a current can flow through the semiconductor device.

In the technique of Patent Document 1, the surface of the p-type group III nitride semiconductor layer is exposed by etching the surface layer formed on the surface of the p-type group III nitride semiconductor layer. At this time, energy for etching the surface layer acts on the surface of the p-type group III nitride semiconductor layer, and nitrogen (N) may escape from the crystal structure of the surface of the p-type group III nitride semiconductor layer. is there. In group III nitride semiconductor layers, it is widely known that N vacancies from which nitrogen has been released act as donors. For this reason, a phenomenon may occur in which the surface conductivity type is inverted from p-type to n-type. Even if a metal electrode is formed on the surface of the p-type group III nitride semiconductor layer whose surface is inverted to n-type, good ohmic contact characteristics cannot be obtained between the p-type group III nitride semiconductor layer and the metal electrode.
Non-Patent Document 1 discloses that the surface of the p-type group III nitride semiconductor layer is irradiated with nitrogen plasma on the surface of the p-type group III nitride semiconductor layer from which nitrogen has escaped from the surface crystal structure. A technique for recovering the amount of nitrogen to the same level as the amount of nitrogen in the crystal structure other than the surface of the p-type group III nitride semiconductor layer is disclosed. According to the technique of Non-Patent Document 1, since the surface of the p-type group III nitride semiconductor layer is not inverted to n-type, the p-type group III nitride semiconductor layer and the metal electrode can be connected well.

JP 2004-260140 A JOURNAL OF APPLIED PHYSICS VOLUME94, NUMBER1, 1 July 2003, P431〜438

  In the conventional technique, nitrogen escapes not only from the p-type group III nitride semiconductor layer but also from the crystal structure of the surface of the n-type or i-type group III nitride semiconductor layer. When nitrogen escapes from the n-type or i-type group III nitride semiconductor layer, the amount of electrons in the n-type or i-type group III nitride semiconductor layer increases, and the n-type or i-type group III nitride semiconductor layer The contact resistance between the metal electrode and the metal electrode is reduced. That is, when a metal electrode is formed on the surface of an n-type or i-type group III nitride semiconductor layer, it is advantageous that nitrogen escapes from the surface of the n-type or i-type group III nitride semiconductor layer. Works. However, in the conventional technique, when nitrogen is supplied (compensated) to the surface of the p-type group III nitride semiconductor layer, nitrogen is also supplied to the n-type or i-type group III nitride semiconductor layer at the same time.

  In the present invention, the amount of nitrogen in the crystal structure of the surface of the p-type group III nitride semiconductor layer is the same level as the amount of nitrogen in the crystal structure other than the surface of the p-type group III nitride semiconductor layer, and n-type Or a semiconductor device having both characteristics that the amount of nitrogen in a part of the crystal structure on the surface of the i-type group III nitride semiconductor layer is smaller than the amount of nitrogen in the crystal structure other than part of the surface. Realize.

In the group III nitride semiconductor layer, in order to form a metal electrode in a predetermined region on the surface of the semiconductor layer, a protective layer is formed on the entire surface of the semiconductor layer, and the predetermined region of the protective layer is removed by etching. In many cases, the surface of the semiconductor layer is exposed in the predetermined region. It is known that when the surface protective layer is etched to expose the surface of the group III nitride semiconductor layer, nitrogen is released from the crystal structure of the surface of the group III nitride semiconductor layer. If nitrogen escapes from the crystal structure on the surface of the group III nitride semiconductor layer, the semiconductor device may not operate as intended. In order to cope with this problem, the conventional common sense compensates for the loss of nitrogen from the surface of the group III nitride semiconductor layer. Nitrogen is supplied into the crystal structure, and the amount of nitrogen in the crystal structure on the surface of the group III nitride semiconductor layer is recovered to the amount of nitrogen before etching. The prior art does not consider that nitrogen works favorably when nitrogen escapes from the surface of the n-type or i-type group III nitride semiconductor layer, and kills the beneficial effects by supplying nitrogen. Yes.
Therefore, in one system of the present invention, the surface of the p-type group III nitride semiconductor layer is compensated for nitrogen in the crystal structure from which nitrogen is eliminated, and the surface of the n-type or i-type group III nitride semiconductor layer is compensated. Does not compensate for nitrogen in the crystal structure from which nitrogen is lost.
In another method of the present invention, when etching the surface layer of the p-type group III nitride semiconductor layer, etching is performed so that nitrogen does not escape from the p-type group III nitride semiconductor layer. When the surface layer of the group III nitride semiconductor layer is etched, etching is performed so that nitrogen is released from the n-type or i-type group III nitride semiconductor layer.
In the present invention, the fact that the characteristics are improved by the removal of nitrogen from the surface of the n-type or i-type group III nitride semiconductor layer is positively utilized. On the other hand, measures are taken to prevent the characteristics from deteriorating due to nitrogen desorption from the surface of the p-type group III nitride semiconductor layer.

  In the method for manufacturing a group III nitride semiconductor device of the present invention, by etching a layer formed on the surface of the first group III nitride semiconductor layer containing a p-type impurity with a gas not containing nitrogen element, A step of exposing at least a part of the surface of the first group III nitride semiconductor layer, and a layer containing an n-type impurity or formed on the surface of the i-type second group III nitride semiconductor layer, A step of exposing at least a part of the surface of the second group III nitride semiconductor layer by etching with a gas containing no nitrogen element is provided. Further, there is a selective supply step of supplying nitrogen to the exposed surface of the first group III nitride semiconductor layer without supplying nitrogen to the exposed surface of the second group III nitride semiconductor layer.

According to the above manufacturing method, the nitrogen removed through the etching is supplied to the first group III nitride semiconductor layer containing the p-type impurity. The amount of nitrogen in the crystal structure of the exposed surface of the first group III nitride semiconductor layer can be recovered to the same extent as the amount of nitrogen in the crystal structure other than the exposed surface of the first group III nitride semiconductor layer. . When a metal electrode is formed on the exposed surface of the first group III nitride semiconductor layer containing the p-type impurity compensated for the nitrogen that has escaped, a good ohmic contact is provided between the first group III nitride semiconductor layer and the metal electrode. Characteristics are obtained. The degree to which the lost nitrogen is recovered should be adjusted according to the required ohmic contact characteristics. It may be necessary to compensate for a part of the missing nitrogen, or it may be preferable to compensate more than the missing nitrogen.
On the other hand, on the exposed surface of the i-type second group III nitride semiconductor layer containing n-type impurities or nitrogen, nitrogen is released from the crystal structure, and the amount of electrons present is increased. When the metal electrode is formed on the exposed surface of the second group III nitride semiconductor layer, the contact resistance between the second group III nitride semiconductor layer and the metal electrode is reduced.
According to the present manufacturing method, it is possible to positively utilize the elimination of nitrogen in the n-type or i-type group III nitride semiconductor layer, and to eliminate the nitrogen in the p-type group III nitride semiconductor layer. Countermeasures can be taken and the characteristics of the semiconductor device can be improved.

In the manufacturing method of the present invention, the exposed surface of the second group III nitride semiconductor layer is covered with a protective film, and the exposed surface of the first group III nitride semiconductor layer is not covered with the protective film. It is preferable to irradiate the whole semiconductor layer with nitrogen plasma.
According to the above manufacturing method, nitrogen is compensated for the exposed surface of the first group III nitride semiconductor layer. On the other hand, nitrogen is not compensated for the exposed surface of the second group III nitride semiconductor layer. Further, an advanced technique of irradiating nitrogen plasma only on a narrow area of the surface of the group III nitride semiconductor layer is not required. The manufacturing cost of the semiconductor device can be reduced.

  The present invention also provides manufacturing methods other than those described above. In the manufacturing method, the layer formed on the surface of the first group III nitride semiconductor layer containing the p-type impurity is etched with a gas containing nitrogen element, whereby the first group III nitride semiconductor layer is etched. A step of exposing at least a part of the surface, and etching a layer containing n-type impurities or formed on the surface of the i-type second group III nitride semiconductor layer with a gas not containing nitrogen element To expose at least part of the surface of the second group III nitride semiconductor layer.

According to the above manufacturing method, in the step of etching the layer formed on the surface of the p-type group III nitride semiconductor layer to expose the surface of the p-type group III nitride semiconductor layer, the p-type group III Nitrogen does not escape from the crystal structure of the surface of the nitride semiconductor layer. Strictly speaking, a phenomenon in which nitrogen escapes from the surface crystal structure and a phenomenon in which nitrogen is compensated for in the surface crystal structure occur simultaneously. Good ohmic contact characteristics are obtained between the p-type group III nitride semiconductor layer and the metal electrode. According to the above manufacturing method, the p-type III-nitride semiconductor layer is exposed at the stage where the layer formed on the surface of the p-type III-nitride semiconductor layer is etched to expose the surface of the p-type III-nitride semiconductor layer. The extent to which nitrogen escapes from the surface of the group nitride semiconductor layer can be reduced. The step of exposing the surface of the semiconductor layer and the step of compensating nitrogen on the exposed surface can be performed simultaneously. Since the selective supply process of nitrogen is unnecessary, the manufacturing cost of the semiconductor device can be reduced.
In the step of etching a layer formed on the surface of the n-type or i-type group III nitride semiconductor layer to expose a part of the surface of the n-type or i-type group III nitride semiconductor layer, n Nitrogen escapes from the crystal structure of the surface of the type- or i-type group III nitride semiconductor layer. The amount of electrons increases on the exposed surface of the n-type or i-type group III nitride semiconductor layer. The contact resistance between the exposed surface of the n-type or i-type group III nitride semiconductor layer and the metal electrode can be reduced.

  The semiconductor device of the present invention is formed on a part of the first group III nitride semiconductor layer containing the p-type impurity and on the surface side of the first group III nitride semiconductor layer, and contains the n-type impurity. Or an i-type second group III nitride semiconductor layer. The amount of nitrogen in the crystal structure of the surface of the first group III nitride semiconductor layer in the region where the second group III nitride semiconductor layer is not formed is approximately the same as the amount of nitrogen in the crystal structure outside the region. In addition, the nitrogen amount in the crystal structure in a partial region of the surface of the second group III nitride semiconductor layer is smaller than the nitrogen amount in the crystal structure other than the partial region.

According to the semiconductor device described above, the metal electrode can be formed on the surface of the p-type group III nitride semiconductor layer in the region where the n-type or i-type group III nitride semiconductor layer is not formed. The surface of the p-type group III nitride semiconductor layer contains sufficient nitrogen, and good ohmic contact characteristics can be obtained between the first group III nitride semiconductor layer and the metal electrode.
In addition, a metal electrode can be formed on part of the surface of the n-type or i-type group III nitride semiconductor layer. Nitrogen is released from the surface of the n-type or i-type group III nitride semiconductor layer, and the contact resistance between the second group III nitride semiconductor layer and the metal electrode can be reduced.

In the semiconductor device of the present invention, the metal electrode formed on the surface of the first group III nitride semiconductor layer in the region where the second group III nitride semiconductor layer is not formed, and the second group III nitride A metal electrode formed on the surface of the second group III nitride semiconductor layer is preferably formed in the partial region of the semiconductor layer, and the pair of metal electrodes are preferably separated.
According to the above semiconductor device, the metal electrode formed on the surface of the first group III nitride semiconductor layer and the metal electrode formed on the surface of the second group III nitride semiconductor layer as necessary The composition of can be different. A metal electrode having a composition suitable for each can be selected.

The present invention can provide a semiconductor device in which the band gap of the second group III nitride semiconductor layer is larger than the band gap of the first group III nitride semiconductor layer.
According to the above semiconductor device, the first group III nitride semiconductor layer and the second group III nitride semiconductor layer form a heterojunction. By forming the heterojunction, a two-dimensional electron gas region is formed between the first group III nitride semiconductor layer and the second group III nitride semiconductor layer. Electrons can move in the two-dimensional electron gas region.

  In the present invention, a part of the surface of the first group III nitride semiconductor layer includes an n-type impurity or an i-type third group III nitride semiconductor layer is formed. The second group III nitride semiconductor layer is formed on the surface of the semiconductor semiconductor layer, and the band gap of the second group III nitride semiconductor layer is greater than the band gap of the third group III nitride semiconductor layer. A large semiconductor device can be provided.

  According to the above semiconductor device, a hetero bond is formed by the third group III nitride semiconductor layer and the second group III nitride semiconductor layer. By forming the heterojunction, a two-dimensional electron gas region is formed between the second group III nitride semiconductor layer and the third group III nitride semiconductor layer. Since the two-dimensional electron gas region is formed in the n-type or i-type semiconductor region, the electron transfer resistance is reduced, and the on-resistance of the semiconductor device can be reduced.

  According to the present invention, good ohmic characteristics are ensured between the p-type group III nitride semiconductor layer and the metal electrode, and the contact resistance between the n-type or i-type group III nitride semiconductor layer and the metal electrode. It is possible to provide a semiconductor device with low resistance.

The main features of the examples are listed.
First Embodiment A plurality of p ⁺ -type group III nitride semiconductor regions 28 are formed in an island shape on the surface of an n ⁻ -type group III nitride semiconductor layer 26.
(Second Embodiment) n ^- on the surface of the mold of the group III nitride semiconductor region 34, n ^- type Group III nitride ^- type n having a larger band gap than the band gap of the III nitride semiconductor region 34 of the A semiconductor region 36 is formed.
(Third Embodiment) n ^- -type III nitride semiconductor region 34 and the n ^- both ends of the type III nitride semiconductor region 36, n ⁺ -type III nitride semiconductor region 34a, 36a are formed ing.
Fourth Embodiment A source electrode 56 connected to the n ⁺ -type group III nitride semiconductor regions 34a and 36a is formed.
Fifth Embodiment A body electrode 54 connected to the p ⁺ type group III semiconductor region 28 is formed.
Sixth Embodiment A gate electrode 44 is formed on the surface of the group III nitride semiconductor region 36 via a gate insulating film 86. The gate electrode 44 is formed at a position facing at least the p ⁺ -type group III nitride semiconductor region 28.

Embodiments will be described in detail below with reference to the drawings.
(First embodiment)
FIG. 1 schematically shows a cross-sectional view of an essential part of a vertical group III nitride semiconductor device 10 having a heterojunction. FIG. 1 shows a unit structure of the semiconductor device 10, and this unit structure is actually repeated in the left-right direction on the paper.
A drain electrode 22 in which titanium (Ti) and aluminum (Al) are stacked is formed on the back surface of the semiconductor device 10. On the surface of the drain electrode 22, an n ⁺ -type group III nitride semiconductor layer 24 mainly composed of gallium nitride (GaN) is formed. Silicon (Si) or oxygen (O) is used as an impurity of the group III nitride semiconductor layer 24, and its carrier concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ .
On the surface of the group III nitride semiconductor layer 24, an n ⁻ type low concentration group III nitride semiconductor layer 26 mainly composed of gallium nitride is formed. Silicon is used as an impurity of the group III nitride semiconductor layer 26, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .
A p ⁺ -type group III nitride semiconductor region (first group III nitride semiconductor region) 28 mainly composed of gallium nitride is formed in an island shape on the group III nitride semiconductor layer 26. Yes. Magnesium (Mg) is used as an impurity in the group III nitride semiconductor region 28, and its carrier concentration is adjusted to about 1 × 10 ¹⁸ cm ⁻³ . A plurality of group III nitride semiconductor regions 28 are formed dispersedly on the group III nitride semiconductor layer 26, and the group III nitride semiconductor layer 26 provides a gap between adjacent group III nitride semiconductor regions 28. It is separated. As shown in FIG. 1, in this embodiment, two group III nitride semiconductor regions 28 are formed on the left and right sides of the paper. When viewed in plan, the group III nitride semiconductor region 28 extends long in the depth direction of the drawing, and a plurality of group III nitride semiconductor regions 28 are arranged in a stripe pattern.

An n ⁻ -type group III nitride semiconductor region (third group III nitride) mainly composed of gallium nitride is formed on the surface of group III nitride semiconductor layer 26 and a part of surfaces of group III nitride semiconductor regions 28, 28. A physical semiconductor layer) 34 is formed. Silicon is used as an impurity in the group III nitride semiconductor region 34, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .
On the group III nitride semiconductor region 34, an n ⁻ type group III nitride semiconductor region (second group III nitride semiconductor region) containing gallium nitride / aluminum (Al _0.3 Ga _0.7 N) as a main material. ) 36 is formed. Silicon is used as an impurity of the group III nitride semiconductor region 36, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ . The crystal structure of group III nitride semiconductor region 36 includes aluminum, and group III nitride semiconductor region 36 has a larger band gap than the band gap of group III nitride semiconductor region 34. The group III nitride semiconductor region 34 and the group III nitride semiconductor region 36 form a heterojunction.

N ⁺ -type source regions 34 a and 36 a mainly made of gallium nitride are formed at both ends of the group III nitride semiconductor region 34 and the group III nitride semiconductor region 36 in the horizontal direction of the drawing. The source regions 34a and 36a have a group III nitride semiconductor region 34 and a group III nitride in a range where the low concentration group III nitride semiconductor layer 26 is in contact with the group III nitride semiconductor region 34 (center side in the drawing) when viewed in plan. It does not contact the physical semiconductor region 36. Silicon is used as an impurity in the source regions 34a and 36a, and the carrier concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ . Further, the surface of the source region 36a in contact with the source electrode 56 described later has less nitrogen in the crystal structure of gallium nitride than the region where the source electrode 56 is not in contact. A source electrode 56 made of a laminate of titanium and aluminum is formed on the surfaces of the source regions 34a and 36a.

  A gate insulating film 86 made mainly of aluminum nitride (AlN) is formed on the surface of the group III nitride semiconductor region 36. A gate electrode 44 containing nickel (Ni) as a main material is formed on the surface of the gate insulating film 86. In this embodiment, the gate insulating film 86 and the gate electrode 44 are formed so as to face almost the entire range of the group III nitride semiconductor region 34 and the group III nitride semiconductor region 36. The gate electrode 44 only needs to be formed at a position facing the group III nitride semiconductor region 28. That is, the gate insulating film 86 and the gate electrode 44 may be formed only in a portion where the group III nitride semiconductor region 28, the group III nitride semiconductor region 34, and the group III nitride semiconductor region 36 are stacked. .

  On the surface of group III nitride semiconductor region 28 where group III nitride semiconductor regions 34 and 36 and source regions 34a and 36a are not formed, body electrode 54 made mainly of nickel is formed. The body electrode 54, the source regions 34a and 36a, and the source electrode 56 are formed separately from each other by an insulating film 86a mainly made of aluminum nitride.

Next, the operation of the semiconductor device 10 will be described.
The p-type group III nitride semiconductor region 28 is in contact with the n-type group III nitride semiconductor region 34. In a state where no voltage is applied to the gate electrode 44, a depletion layer is formed from the group III nitride semiconductor region 28 toward the group III nitride semiconductor regions 34 and 36. At this time, by applying a predetermined voltage to the body electrode 54, the potential of the group III semiconductor region 28 can be stabilized, and a stable depletion layer can be formed. That is, the depletion layer is formed to extend to the heterojunction surface of the group III nitride semiconductor region 34 and the group III nitride semiconductor region 36. The energy level of the conduction band of the heterojunction surface exists above the Fermi level, and the two-dimensional electron gas layer cannot exist on the heterojunction surface. That is, in a state where no voltage is applied to the gate electrode 44, the electron travel is stopped and the semiconductor device 10 is turned off. The semiconductor device 10 performs a normally-off operation.

In a state where a positive voltage is applied to the gate electrode 44, the depletion layer formed from the group III nitride semiconductor region 28 toward the group III nitride semiconductor regions 34 and 36 disappears, and the group III nitride semiconductor is lost. A two-dimensional electron gas layer is formed at the heterojunction surface of region 34 and group III nitride semiconductor region 36. Therefore, the energy level of the conduction band of the two-dimensional electron gas layer exists below the Fermi level, and a state in which the two-dimensional electron gas layer exists in the potential well of the heterojunction plane is created. As a result, electrons run in the two-dimensional electron gas layer, and the semiconductor device 10 is turned on.
The electrons that have traveled laterally along the two-dimensional electron gas layer at the heterojunction surface of the group III nitride semiconductor region 34 and the group III nitride semiconductor region 36 from the source regions 34a, 36a are transferred to the group III nitride semiconductor layer 26. In the vertical direction (portion where the group III nitride semiconductor layer 26 is in contact with the group III nitride semiconductor region 34), and the drain electrode via the group III nitride semiconductor layer 26 and the group III nitride semiconductor layer 24 It flows to 22. The source electrode 56 and the drain electrode 22 are electrically connected.

  As described above, the on / off control of the semiconductor device 10 is performed in a portion where the group III nitride semiconductor region 28, the group III nitride semiconductor region 34, and the group III nitride semiconductor region 36 are stacked. Yes. That is, by controlling the thickness of the depletion layer formed in the group III nitride semiconductor region 34 by the voltage applied to the gate electrode 44, the on / off of the semiconductor device 10 is controlled. Since body electrode 54 and group III nitride semiconductor region 28 exhibit good ohmic contact characteristics, the thickness of the depletion layer is stabilized. By applying a predetermined gate voltage, the semiconductor device 10 is reliably turned on, and when the gate voltage is not applied, the semiconductor device 10 is reliably turned off. Further, since the contact resistance between the source electrode 56 and the source region is small, the on-resistance of the semiconductor device 10 is small.

A method for manufacturing the semiconductor device 10 will be described.
(First Manufacturing Method) A method for manufacturing the semiconductor device 10 will be described with reference to FIGS. In addition, about each structure in a figure, the reduced scale of actual size is not represented correctly. Changes have been made as appropriate for the sake of clarity.
First, as shown in FIG. 2, a group III nitride semiconductor substrate 24 containing n ⁺ -type gallium nitride as a main material is prepared. Group III nitride semiconductor substrate 24 has a thickness of about 200 μm.
Next, as shown in FIG. 3, an n ⁻ type group III nitride semiconductor region 26 is grown on the group III nitride semiconductor substrate 24 by using MOCVD (Metal Organic Chemical Vapor Deposition). The thickness of the group III nitride semiconductor region 26 is 6 μm. Further, the p ⁺ -type first group III nitride semiconductor region 28 is grown on the group III nitride semiconductor region 26 using MOCVD. Next, the first mask layer 32 is formed on the group III nitride semiconductor region 28. The thickness of the first mask layer 32 is about 0.5 μm. The first mask layer 32 is formed of silicon oxide.

Next, as shown in FIG. 4, after forming a hole by etching a part of the first mask layer 32, the group III nitride is formed from the hole of the first mask layer 32 by RIE (Reactive Ion Etching) method. The semiconductor region 28 is etched to form a groove 72 that penetrates a part of the group III nitride semiconductor region 28 and reaches the group III nitride semiconductor region 26.
Next, as shown in FIG. 5, gallium nitride is crystal-grown from the group III nitride semiconductor region 26 where the bottom surface of the groove 72 is exposed, using the MOCVD method. The crystal growth of gallium nitride is continued until the portion where the group III nitride semiconductor region 28 is etched is filled. Next, after removing the first mask layer 32, the surface of the group III nitride semiconductor region 28 and a part of the group III nitride semiconductor region 26 are grown by crystal growth of gallium nitride using the MOCVD method. A gallium nitride layer 34 is uniformly formed on the surface. The amount of impurities in the gallium nitride layer for crystal growth is adjusted to be the same as that of the low concentration semiconductor region 26. That is, the crystal-grown gallium nitride layer 34 and the group III nitride semiconductor region 26 can be evaluated as one continuous region. The thickness of the semiconductor region deposited on the surface of the group III nitride semiconductor region 28 is about 100 nm.
Although the gallium nitride layer crystal-grown between the group III nitride semiconductor regions 28 and 28 and the gallium nitride layer crystal-grown on the surface of the group III nitride semiconductor region 28 are continuous, the semiconductor shown in FIG. In order to match with the device 10, in the following description, the former is described as a part of the group III nitride semiconductor region 26, and the latter is described as the third group III nitride semiconductor region 34.

Next, as shown in FIG. 6, a group III nitride semiconductor region (second group III nitride semiconductor layer) 36 is crystal-grown on the group III nitride semiconductor region 34 using the MOCVD method. The thickness of the group III nitride semiconductor region 36 is 25 nm. At this stage, a heterojunction is formed.
Next, a second mask layer 82 is formed by depositing silicon dioxide on the surface of the group III nitride semiconductor region 36 using the CVD method. After the second mask layer 82 is formed on the entire surface of the group III nitride semiconductor layer 36, a portion for forming the source region is removed by using a lithography technique and an etching technique.
Next, ion implantation is performed to form source regions 34a and 36a (see FIG. 7). In the ion implantation, silicon is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 65 eV. In addition, the arrow in a figure has shown the range where ion implantation is implemented.
Next, silicon dioxide is deposited again on the portion where the second mask layer 82 has been removed to form a third mask layer 83 (see FIG. 7). That is, the third mask layer 83 is formed on the entire surface of the group III nitride semiconductor layer 36. Next, annealing is performed at 1300 ° C. for 5 minutes in a nitrogen atmosphere. By annealing, the ion-implanted impurity (silicon) is activated. Source regions 34a and 36a are completed.

Next, as shown in FIG. 7, the third mask layer 83 in the region for forming the source electrode and the body electrode is removed by dry etching. At this stage, a part of the surface of the source region 36a is exposed to the etching gas, and nitrogen is released from the crystal structure. In the drawing, x indicates that nitrogen has been removed from the crystal structure of the surface of the source region 36a by dry etching.
Next, silicon dioxide is formed again on the portion where the third mask layer 83 has been removed to form a fourth mask layer 84 (see FIG. 8). That is, a mask layer is formed on the surface of the group III nitride semiconductor layer 36 and the surfaces of the source regions 34a and 36a.

  Next, as shown in FIG. 8, after the fourth mask layer 84 where the body electrode is to be formed is removed by etching, a part of the source regions 34a and 36a is etched using the RIE method, A portion of the surface of group III nitride semiconductor layer 28 is exposed. At this stage, a part of the surface of the group III nitride semiconductor layer 28 is exposed to the etching gas, and nitrogen is released from the crystal structure. In the drawing, “X” indicates that nitrogen was released from the crystal structure of the surface of the group III nitride semiconductor layer 28 by etching.

  Next, the fourth mask layer 84 is removed using an aqueous hydrogen fluoride solution. Next, as shown in FIG. 9, a gate insulating film 86 is formed on the surface of the group III nitride semiconductor layer 36, the surface of the source region 36 a, and the exposed surface of the group III nitride semiconductor layer 28. The thickness of the gate insulating film 86 on the surface of the group III nitride semiconductor layer 36 is adjusted to 50 nm.

Next, as shown in FIG. 10, the gate insulating film 86 is removed by etching in the region where the source electrode is formed and the region where the body electrode is formed using the RIE method. Also at this time, nitrogen escapes from the crystal structure of the surface of the source region 36a exposed by etching and the crystal structure of the surface of the group III nitride semiconductor layer 28 exposed by etching. At this stage, a gate insulating film 86 (see FIG. 1) is formed on the surface of the group III nitride semiconductor layer 36, and an insulating film 86a is formed on the surface of the group III nitride semiconductor layer 28.
Next, as shown in FIG. 11, a resist 32 is applied on the exposed surface of the source region 36a. At this time, a resist is not applied on the exposed surface of the group III nitride semiconductor layer 28. Instead of applying the resist 32, the source electrode 56 may be formed directly on the exposed surface of the source region 36a.
Next, the exposed surface of the group III nitride semiconductor layer 28 is irradiated with nitrogen plasma using an ECR (Electron Cyclotron Resonance) method. The arrow in the figure indicates that the nitrogen plasma treatment is being performed. At this stage, nitrogen is compensated for in the crystal structure of the exposed surface of the group III nitride semiconductor layer 28. The amount of nitrogen in the crystal structure of the exposed surface of group III nitride semiconductor layer 28 is recovered to the same level as the amount of nitrogen in the crystal structure of group III nitride semiconductor layer 28 in other regions. On the other hand, since the exposed surface of the source region 36a is covered with the resist 32, nitrogen in the crystal structure is still removed. That is, the amount of nitrogen remains smaller in the crystal structure of the exposed surface of the source region 36a than in the crystal structure other than the exposed surface of the source region 36a.

Next, as shown in FIG. 1, the resist 32 is removed with a resist stripping material. Next, titanium and aluminum are vapor-deposited to form the source electrode 56 on the surface of the source region 36a. Next, nickel is deposited to form a body electrode 54 on the exposed surface of the group III nitride semiconductor layer 28. Next, titanium and aluminum are vapor-deposited to form the drain electrode 22 on the back surface of the group III nitride semiconductor layer 24. Next, annealing is performed at 500 ° C. for 2 minutes in a nitrogen atmosphere. The contact resistance of the source electrode 56 and the source region 36a, the body electrode 54 and the group III nitride semiconductor layer 28, and the drain electrode 22 and the group III nitride semiconductor layer 24 is reduced by annealing. Next, nickel is deposited on the surface of the gate insulating film 86 to form the gate electrode 44.
Through the above steps, the semiconductor device 10 shown in FIG. 1 can be obtained.

(Second Manufacturing Method) Another method for manufacturing the semiconductor device 10 will be described with reference to FIGS. Here, only parts different from the first manufacturing method will be described.
In the second manufacturing method, after the state of FIG. 9 is obtained, as shown in FIG. 12, the gate insulating film 86 at the position where the body electrode is formed is removed by dry etching. At this time, nitrogen gas is mixed in the etching gas. At this stage, nitrogen is compensated for in the crystal structure of the surface of the group III nitride semiconductor layer 28.
Next, as shown in FIG. 13, the portion where the source electrode is formed is removed by dry etching. At this time, nitrogen gas is not mixed in the etching gas.
Next, as described in the first manufacturing method, the semiconductor device 10 can be obtained by forming the source electrode, the body electrode, the drain electrode, and the gate electrode.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the above embodiment, the source electrode and the body electrode are formed separately. However, the source electrode may be formed so as to be connected to both the source region and the p ⁺ -type group III nitride semiconductor layer. In that case, after covering the source region and the p ⁺ -type group III nitride semiconductor layer with a mask layer such as silicon dioxide, the amount of nitrogen in the crystal structure of the surface of the source region where the source electrode is formed is The state in which the amount of nitrogen in the crystal structure of the surface of the source region of the p ⁺ -type group III nitride semiconductor layer is formed is less than the amount of nitrogen in the crystal structure of the source region where no source is formed. A state in which the amount of nitrogen in the crystal structure of the p ⁺ -type group III nitride semiconductor layer in which no is formed is the same is completed. Next, the source electrode may be formed after removing the mask layer using an aqueous hydrogen fluoride solution.
In the above embodiment, gallium nitride is crystal-grown from the n ⁻ type group III nitride semiconductor region until the etched portion of the p ⁺ type group III nitride semiconductor region is filled, and then the mask layer is removed, and then p Gallium nitride is uniformly grown on the entire surface of the ⁺ -type group III nitride semiconductor region. However, gallium nitride may be grown from the n ⁻ type group III nitride semiconductor region until the surface of the p ⁺ type group III nitride semiconductor region is covered without removing the mask layer.
In the above embodiment, the source electrode is formed, then the body electrode is formed, and then the drain electrode is formed. However, the order of forming the metal electrodes is not limited to the order of the examples. The desired metal electrode should just be formed reliably.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. A process of manufacturing a semiconductor device of the first embodiment (second manufacturing method) is shown. A process of manufacturing a semiconductor device of the first embodiment (second manufacturing method) is shown.

Explanation of symbols

22: Drain electrode 24: n ⁺ type group III nitride semiconductor region 26: n ⁻ type low concentration group III nitride semiconductor layer 28: first group III nitride semiconductor region 34: third group III nitride Semiconductor region 36: second group III nitride semiconductor region 44: gate electrode 54: body electrode 56: source electrode 86: gate insulating film

Claims (7)

By etching the layer formed on the surface of the first group III nitride semiconductor layer containing the p-type impurity with a gas not containing nitrogen element, at least one of the surfaces of the first group III nitride semiconductor layer is etched. Exposing the part,
A second group III nitride semiconductor layer is formed by etching a layer containing an n-type impurity or formed on the surface of an i-type second group III nitride semiconductor layer with a gas not containing a nitrogen element. Exposing at least a portion of the surface of
A selective supply step of supplying nitrogen to the exposed surface of the first group III nitride semiconductor layer without supplying nitrogen to the exposed surface of the second group III nitride semiconductor layer;
A method of manufacturing a group III nitride semiconductor device comprising:   In the selective supply step, the exposed surface of the second group III nitride semiconductor layer is covered with a protective film, and the exposed surface of the first group III nitride semiconductor layer is not covered with the protective film, 2. The manufacturing method according to claim 1, wherein the entire semiconductor layer is irradiated with nitrogen plasma. At least part of the surface of the first group III nitride semiconductor layer is formed by etching a layer formed on the surface of the first group III nitride semiconductor layer containing the p-type impurity with a gas containing nitrogen element. A step of exposing
A second group III nitride semiconductor layer is formed by etching a layer containing an n-type impurity or formed on the surface of an i-type second group III nitride semiconductor layer with a gas not containing a nitrogen element. Exposing at least a portion of the surface of
A method of manufacturing a group III nitride semiconductor device comprising: a first group III nitride semiconductor layer containing a p-type impurity;
The first group III nitride semiconductor layer is formed on a part of the surface side of the first group III nitride semiconductor layer and includes an n-type impurity or i-type second group III nitride semiconductor layer,
The amount of nitrogen in the crystal structure of the surface of the first group III nitride semiconductor layer in the region where the second group III nitride semiconductor layer is not formed is approximately the same as the amount of nitrogen in the crystal structure outside the region. Yes,
The group III nitride characterized in that the nitrogen amount in the crystal structure in a partial region of the surface of the second group III nitride semiconductor layer is smaller than the nitrogen amount in the crystal structure other than the partial region Semiconductor device. A metal electrode formed on the surface of the first group III nitride semiconductor layer in a region where the second group III nitride semiconductor layer is not formed;
A metal electrode formed on the surface of the second group III nitride semiconductor layer in the partial region of the second group III nitride semiconductor layer;
5. The semiconductor device according to claim 4, wherein the pair of metal electrodes are separated from each other.   6. The semiconductor device according to claim 4, wherein the band gap of the second group III nitride semiconductor layer is larger than the band gap of the first group III nitride semiconductor layer. A part of the surface of the first group III nitride semiconductor layer includes an n-type impurity or an i-type third group III nitride semiconductor layer,
A second group III nitride semiconductor layer is formed on the surface of the third group III nitride semiconductor layer,
6. The semiconductor device according to claim 4, wherein the band gap of the second group III nitride semiconductor layer is larger than the band gap of the third group III nitride semiconductor layer.

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