JP5002844B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that stores tune information for adjusting circuit characteristics and the like, redundant address information for relieving defective cells, and the like in a nonvolatile manner.

  In a semiconductor device such as a semiconductor integrated circuit device, characteristics of transistor elements vary due to a pattern shift in a manufacturing process and variations in process parameters, and operation characteristics of an internal circuit vary. In order to compensate for such variations in the characteristics of the transistor elements / internal circuits and obtain desired operation characteristics, an operation called tuning or trimming is usually performed.

  An example of a configuration for adjusting circuit operation characteristics using such tuning information for adjusting operation characteristics is disclosed in Japanese Patent Application Laid-Open No. 2004-118921. In Patent Document 1, an MRAM (Magnetic Random Access Memory) cell is used as a trimming information storage element in order to solve the problem of area increase when a fuse element is used for storing trimming / tuning information. To do. An MRAM cell that stores trimming information is arranged in a different area from the memory cell array that stores normal data.

  Patent Document 1 uses an MRAM cell as a trimming / tuning information storage element, so that tuning information can be programmed even after packaging, and the tuning information can be rewritten even after packaging. To make it. Further, even when a circuit for writing / reading normal data and a control circuit are in an unstable state after power-on, a tuning information storage area provided in a separate area from the memory array for storing normal data is stored. In accordance with the information, the operation characteristics of each circuit are adjusted to compensate for the circuit operation characteristics.

  In Patent Document 1, in order to accurately read tuning information even after power is turned on, MRAM cells are connected in series, complementary data is stored in each of the serial cells, and 1-bit tuning information is stored. The configuration is shown.

  Further, in a flash memory, a configuration in which a PROM area for storing redundant information (including tuning information) is arranged adjacent to a normal memory array block for storing data is disclosed in JP-A-2005-92962. Is shown in

  In the configuration shown in Patent Document 2, writing / erasing data to / from the PROM area storing redundant information is performed through the same path as normal data erasing / writing, and data reading from this PROM area is normally performed. This is executed from a different route from the reading from the memory array block area. The write / erase circuit is used in common for the redundant information storage area and the normal data storage area to suppress an increase in layout area, and read out redundant information from another path, resulting in instability after power-on. Even in such a state, it is intended to stably read redundant information.

Patent Document 2 shows a configuration in which twin cell information is read to each pair of bit lines by a folded bit line configuration when reading redundant information. The twin cell is composed of first and second memory cells that store complementary data. Accordingly, 1-bit redundant information (tuning information) is stored by four memory cells (two twin cells). In Patent Document 2, in such a mode that should be called a double twin cell, by storing redundant information, a read margin is ensured and the redundant / tuning information is stably read.
JP 2004-118921 A JP 2005-92962 A

  In the configuration shown in Patent Document 1, an MRAM cell is arranged instead of a fuse element, and a differential amplifier is provided for each trimming / tuning information bit (see FIG. 9). Therefore, when storing 1-bit tuning / trimming information using two twin cells, there arises a problem that the layout area of the trimming / tuning information storage area increases.

  In the configuration disclosed in Patent Document 1, the size of the trimming / tuning information storing MRAM cell is made larger than that of the normal MRAM storing normal data. By increasing this size, the trimming information read margin is increased, and the trimming information can be stably written / read even when the trimming information read / write circuit is not tuned. In this case, a normal MRAM cell that stores normal data and an MRAM cell that stores trimming / tuning information are arranged in different areas. Therefore, it becomes difficult to arrange memory cells having different sizes in a common memory array region, and there arises a problem that it becomes impossible to arrange MRAM cells that store trimming / tuning information efficiently.

  In the configuration disclosed in Patent Document 2, a memory array is divided into a plurality of memory blocks, and one memory block is used for storing redundancy / tuning (trimming) information. In this case, the main bit line is arranged in common to each memory block, and a row decoder for selecting a word line is arranged for each memory block. Therefore, in the case of the configuration of Patent Document 2, the row decoder cannot be shared between the memory block for storing redundancy / tuning information and the normal memory block for storing normal data. This increases the circuit layout area.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reliably read and set tuning information while avoiding an increase in chip layout area.

  Another object of the present invention is to securely write / read tuning information by arranging a tuning information storage area in the same array as normal memory cells storing normal data while suppressing an increase in the array layout area. It is an object to provide a semiconductor device that can be taken out.

  In the semiconductor device according to the present invention, in the second operation mode, more word lines are driven to the selected state in parallel than in the first operation mode, and the storage information of the plurality of twin cells is read in parallel. The twin cell has first and second memory cells that store complementary data. The first memory cells of the plurality of twin cells are connected in common to the first bit line, and the second memory cell is connected to the first memory cell. Are commonly connected to the bit lines.

  In one embodiment, a semiconductor device according to the present invention includes a plurality of memory cells arranged in a matrix and a plurality of words arranged corresponding to each memory cell row and connected to the memory cells in the corresponding row. A plurality of bit lines arranged corresponding to each memory cell column and connected to the memory cells in the corresponding column and a word line addressed from a plurality of word lines according to a row address signal are selected. A row selection drive circuit for driving is provided. The plurality of memory cells are grouped into a plurality of twin cells each having first and second memory cells that store complementary data. The row selection drive circuit selects a first number of word lines from the plurality of word lines so that the first and second memory cells of the twin cell are selected in parallel in the first operation mode, In the second operation mode, more second word lines than the first number are selected, and more twin cells are selected in parallel than in the first operation mode. These twin cells selected in parallel store the same data.

  The semiconductor memory device according to the embodiment further includes a column selection circuit that selects a bit line corresponding to an addressed column according to a column address signal, and a bit line signal selected by the column selection circuit, An internal read circuit is provided that detects stored information of the selected twin cell and generates internal read data. The first memory cell of the selected twin cell is connected to the first bit line, and the second memory cell is connected to the second bit line. The column selection circuit selects the first and second bit lines in parallel.

  In the second operation mode, a number of twin cells are selected in parallel to read out stored data. Therefore, the amount of signal change corresponding to the stored data can be increased, and the stored data can be read accurately with a sufficient margin. Therefore, when the stored information of the twin cell is, for example, tuning information, the stored information can be accurately read and the state of the circuit to be tuned can be set even if the internal circuit is in an untuned state.

  Also, the number of selected word lines is changed according to the operation mode. When this twin cell is arranged in a normal memory cell array for storing normal data, the row decoder can be shared, and the layout of the peripheral circuit An increase in area can be avoided.

[Embodiment 1]
1 schematically shows a structure of a main portion of the semiconductor device according to the first embodiment of the present invention. In FIG. In FIG. 1, this semiconductor device is a semiconductor memory device that stores tune information for adjusting the operating characteristics of another circuit (not shown).

  In FIG. 1, the semiconductor device includes two memory arrays 1a and 1b and row selection drive circuits 2a and 2b provided corresponding to these memory arrays 1a and 1b, respectively. In memory array 1a, memory cells MC are arranged in a matrix, word lines WLA are arranged corresponding to the respective memory cell rows, and bit lines (first bit lines) BLA corresponding to the memory cell columns. Is placed. In memory array 1b, memory cells MC are arranged in a matrix, word lines WLB are arranged corresponding to the memory cell rows, and bit lines (second bit lines) BLB are arranged corresponding to the memory cell columns. Be placed.

  Memory cell MC may be a memory cell in which reading of stored information is performed by detecting the amount of current flowing through the memory cell and storing information in a nonvolatile manner. The memory cell MC is an MRAM cell as an example. When an MRAM cell is used as a memory cell MC for storing tune information, writing tune information does not require a high voltage like a flash memory, and tune information can be easily rewritten even after packaging. Can do. However, when the tune information is information for setting the operating characteristics of the internal circuit of the flash memory, the memory cell MC may be a flash memory cell. When a nonvolatile semiconductor memory device is formed on the same chip as a semiconductor device that stores tune information, a memory cell having the same configuration as that of the nonvolatile semiconductor memory device integrated on the same chip is used as a memory for storing tune information. What is necessary is just to be used as a cell.

  Row selection drive circuits 2a and 2b respectively drive word lines corresponding to the addressed row in corresponding memory arrays 1a and 1b to a selected state in accordance with a row address (not shown). A plurality (two in this embodiment) of row selection drive circuits 2a and 2b are provided in each of corresponding memory arrays 1a and 1b when tune information read instruction signal PRME is activated (in the second operation mode). ) Are driven to the selected state in parallel, and when the tune information read instruction signal PRME is inactivated (in the first operation mode), the number is less than in the second operation mode (1 in this embodiment). Drive the word line to the selected state.

  A column selection signal generation circuit 3a and a column selection gate circuit 4a are further provided for the memory array 1a, and a column selection signal generation circuit 3b and a column selection gate circuit 4b are further provided for the memory array 1b. It is done.

  Column selection signal generating circuits 3a and 3b each decode a column address signal (not shown) to generate a column selection signal for designating an addressed column in corresponding memory arrays 1a and 1b. Column selection gate circuits 4a and 4b select bit lines BLA and BLB corresponding to the addressed columns of corresponding memory arrays 1a and 1b in accordance with column selection signals from corresponding column selection signal generating circuits 3a and 3b. . Column selection signal generating circuits 3a and 3b operate in parallel, and bit lines are selected in parallel in memory arrays 1a and 1b.

  Bit lines BLA and BLB selected by column select gate circuits 4a and 4b are coupled to read circuit 5 through internal read data lines RD and RDN. Read circuit 5 includes a current detection type sense amplifier circuit for supplying a read current, and generates internal read data Q according to the current flowing through internal read data lines RD and RDN when sense activation signal SAE is activated. . Internal read data Q from the read circuit 5 is supplied to a tuning circuit that adjusts the operating characteristics of other circuits (not shown).

  A control circuit 6 is provided to control the internal operation of the semiconductor device. Control circuit 6 activates sense activation signal SAE and tune information read instruction signal PRME at a predetermined timing in accordance with power-on detection signal POR from a power-on detection circuit (not shown).

  The semiconductor device that stores the tune information shown in FIG. 1 reads the tune information when the power-on detection signal POR is activated after the power is turned on and the power supply voltage is stabilized, and the tune information read to the tuning circuit of another circuit. Supply. In accordance with the tune information, adjustment of circuit operation timing, operation power supply voltage level, reference voltage level, and the like is performed in other circuits. This allows other circuits to operate with the specified operating characteristics. In a semiconductor device that stores tune information (hereinafter referred to as a tune information storage device), the operation characteristics of each circuit such as the read circuit 5 are not adjusted by the tune information when the tune information is read. Therefore, it is necessary to read the stored tune information with a sufficient margin. In particular, when data is read by detecting the memory cell current, the memory cell current decreases as the size of the memory cell is reduced. Therefore, it is necessary to ensure a sufficient margin for reading the tune information.

  FIG. 2 shows an arrangement of selected memory cells at the time of reading tune information in the semiconductor device according to the first embodiment of the present invention. At the time of reading the tune information, a plurality of word lines may be selected in each memory array. Hereinafter, a mode in which two word lines are selected in parallel in each memory array will be described. In FIG. 2, when tune information read instruction signal PRME is activated, word lines WLAo and WLAe are selected in parallel in memory array 1a by row selection drive circuits 2a and 2b, and word line WLAo is also selected in memory array 1b. Lines WLBo and WLBe are selected in parallel, respectively.

  Memory cells MCA1 and MCB1 in the same column connected to even word lines WLAe and WLBe constitute one twin cell TW1, and memory cells MCA2 and MCB2 in the same column connected to odd word lines WLAo and WLBo are different from each other. The twin cell TW2 is configured. The first memory cells MCA1 and MCA2 of the twin cells TW1 and TW2 are connected to the bit line BLA, and the other memory cells (second memory cells) MCB1 and MCB2 of the twin cells TW1 and TW2 are connected to the bit line BLB. Is done. Memory cells MCA and MCB constituting one twin cell TW store complementary data, and the twin cells selected in parallel when the tuning information read instruction signal PRME is activated store the same data.

  That is, data of the same logic level is stored in the memory cells (first memory cells) MCA1 and MCA2 connected to the bit lines (first bit lines) in the same column of the twin cells TW1 and TW2, and the twin cells TW1 And memory cells (second memory cells) MCB1 and MCB2 connected to another common bit line (second bit line BLB) of TW2 store logic data complementary to the first memory cell. FIG. 2 shows an example in which H (logic high) data is stored in memory cells MCA1 and MCA2, and L (logic low) data is stored in memory cells MCB1 and MCB2.

  Bit lines BLA and BLB are electrically connected to internal read data lines RD and RDN when selected. Read circuit 5 differentially amplifies the current flowing through internal read data lines RD and RDN to generate internal read data Q. That is, data is read by the “open bit line” method. In the “open bit line system”, when the tune information read instruction signal PRME is in an inactive state, one word line is selected in each of the memory arrays 1a and 1b, and the current flowing through the memory cell connected to each selected word line Are differentially amplified. This memory cell selection mode is hereinafter referred to as “twin cell mode”. On the other hand, when tune information read instruction signal PRME is activated, two twin cells TW1 and TW2 are selected in parallel, and internal read data Q is generated based on the stored data of the two twin cells. The memory cell selection mode in which the two twin cells are selected in parallel is hereinafter referred to as “double twin cell mode”. Accordingly, in the twin cell mode, one bit of tune information is stored by one twin cell, and in the double twin cell mode, one bit of tune information is stored by two twin cells.

  In the double twin cell mode, a current flows in parallel through two memory cells storing data of the same logic level in one memory array, so that a double memory cell current can flow. Since complementary data is stored in memory arrays 1a and 1b, the current difference between internal read data lines RD and RDN can be doubled compared to the normal twin cell mode. Therefore, the read margin of the read circuit 5 can be sufficiently increased, and the tune information can be read accurately even before the circuit characteristics of the read circuit 5 and the like are tuned.

  FIG. 3 is a diagram showing an example of an electrical equivalent circuit of the memory cell MC shown in FIGS. 1 and 2. In FIG. 3, a memory cell MC is an MRAM cell, and includes a variable magnetoresistive element VR and an access transistor AT connected in series between a bit line BL and a source line SL. The variable magnetoresistive element VR is composed of a free layer and a fixed layer that are arranged to face each other with a barrier layer in between. The free layer and the fixed layer are composed of a ferromagnetic layer, and the magnetization direction of the fixed layer is constant regardless of the stored data, and the magnetization direction of the free layer is set according to the stored data. When the magnetization directions of the free layer and the fixed layer are parallel (when they coincide), the resistance value becomes small. On the other hand, when the magnetization directions of the free layer and the fixed layer are antiparallel, the resistance value becomes large. The resistance value of the variable magnetoresistive element is made to correspond to binary data (H data and L data). Access transistor AT is formed of, for example, an N-channel MOS transistor (insulated gate field effect transistor), and is selectively turned on according to the signal potential on word line WL. When turned on, variable magnetoresistive element VR is electrically connected to source line SL. Join.

  At the time of data reading, current is supplied to bit line BL from read circuit 5 shown in FIG. 2, and source line SL is maintained at the ground voltage level. The word line WL is driven to the selected state, and the access transistor AT is turned on. The amount of current flowing from the bit line BL to the source line SL differs according to the resistance value of the variable magnetoresistive element VR. The read circuit 5 detects the amount of current flowing through the bit line BL.

  FIG. 4 is a diagram showing an electrical equivalent circuit of each bit line in the double twin cell mode. In FIG. 4, a resistor RL is connected in parallel to the bit line BLA in the memory array 1a, and a resistor RH is connected in parallel to the bit line BLB in the memory array 1b. The resistors RH and RL correspond to the resistance value of the variable magnetoresistive element VR of the memory cell. The memory cells MCA1 and MCA2 store H data, and the resistor RL is in a low resistance state. On the other hand, the memory cells MCB1 and MCB2 store L data, and the resistor RH is in a high resistance state.

  At the time of data reading, a read current is supplied to bit lines BL and BLB from sense amplifier circuit 8 included in read circuit 5 in accordance with sense activation signal SAE. A current IL flows through the resistor RL, and a current IH flows through the resistor RH. Sense amplifier circuit 8 differentially amplifies currents flowing through bit lines BLA and BLB to generate internal read data Q.

  FIG. 5 is a diagram showing a comparison between the read current in the first embodiment of the present invention and the read current in another operation mode. In FIG. 5, the horizontal axis represents time t, and the vertical axis represents the current value supplied to the readout circuit 5 (the unit is arbitrary).

  In FIG. 5, curve I shows a bit line current waveform at the time of reading a 2-bit memory cell storing H data in the double twin cell mode. Curve II is a bit line current waveform at the time of reading of a 2-bit memory cell storing L data in the double twin cell mode. A curve III shows a current (bit line current) waveform flowing through a memory cell storing 1-bit H data in the twin cell mode. A curve IV shows a current (bit line current) waveform flowing through a memory cell storing 1-bit L data in the twin cell mode.

  As shown in FIG. 5, in the double twin cell mode, read current difference DIFA detected by sense amplifier circuit 8 is a difference between curves I and II. Therefore, as shown in FIG. 4, this current difference DIFA corresponds to 2 · (IL−IH). The current difference in the normal twin cell mode is the difference DIFB between curves III and IV. This current difference DIFB corresponds to (IL-IH). The current difference value DIFA in the double twin cell mode is larger (about twice) than the current difference value DIFB in the twin cell mode. Therefore, a sufficient current difference can be supplied to the sense amplifier circuit 8, and the internal read data Q can be accurately generated even when the read circuit 5 and the like are in an unadjusted state after the power is turned on.

  The difference values DIFC and DIFD are the difference values of the reference current Iref, the read current (bit line current) of the 1-bit H data storage cell, and the read current (bit line current) of the 1-bit H data storage cell, respectively. is there. This reference current Iref is generated using a dummy cell, or is supplied to the read circuit 5 by a reference current generation circuit. When normal data processed by a processing device other than the tune information is read, a 1-bit memory cell is selected, and a current (bit line current) flowing through the selected memory cell is compared with a reference current Iref. Therefore, in the normal twin cell mode, a current difference value DIFB equal to the sum of the current difference values DIFC and DIFD in the “single cell mode” in which this 1-bit memory cell is selected is obtained. Therefore, even when the cell size is reduced, a relatively large current difference can be generated and the read circuit 5 can perform differential amplification. However, according to this double twin cell mode, a larger current difference can be generated for the read circuit 5, and even when the element size is reduced and the current flowing through the memory cell becomes minute, The tune information can be read by performing a sensing operation in the read circuit 5. In addition, data is read by the open bit line system, and tune information can be easily written as will be described later. Hereinafter, a configuration for realizing the twin cell mode and the double twin cell mode will be described.

  FIG. 6 schematically shows an example of the configuration of row selection drive circuits 2a and 2b shown in FIG. Since these row selection drive circuits 2a and 2b have the same configuration, the row selection drive circuits 2a and 2b are generically indicated by reference numeral 2 in FIG.

  In FIG. 6, row selection drive circuit 2 (2a, 2b) includes a row decoder 10 for decoding row address bits RA <n: 1>, an odd / even word line decoder 12 for decoding row address bits RA <0>, A word line drive circuit 14 for driving a word line to a selected state in accordance with a row decode signal X from the row decoder 10 and a decode signal ZRA from the odd / even word line decoder 12 is included.

  The (n + 1) -bit row address RA <n: 0> is generated and supplied from the control circuit 6 shown in FIG. 1 using, for example, an address counter according to the power-on detection signal POR. The row decoder 10 decodes the upper row address bits RA <n: 1>, and by the decode signal X, in the corresponding memory array 1 (1a or 1b), the even address word line (WLE) and the odd address Word lines (WLO) are designated in parallel.

  When the tune information read instruction signal PRME is activated, the odd / even word line decoder 12 degenerates the least significant 1-bit row address RA <0>, and designates both the odd address word line and the even address word line. When the tune information read instruction signal PRME is inactive, the odd / even word line decoder 12 decodes the least significant 1-bit row address RA <0>, and selects even-numbered word lines or odd-addressed word lines according to the decoding result. specify.

  When word line activation signal WLACN is activated, word line drive circuit 14 drives a designated word line of even-numbered word line group WLEG and odd-numbered word line group WLOG to a selected state in accordance with decode signals X and ZRA.

  Therefore, when tune information read instruction signal PRME is activated, odd / even word line decoder 12 degenerates 1-bit row address RA <0>, and even word line WLE and odd word line WLO specified by decode signal X Are driven to the selected state in parallel.

  FIG. 7 is a diagram showing an example of the configuration of odd / even word line decoder 12 and word line drive circuit 14 shown in FIG. FIG. 7 representatively shows a configuration of a word line driver for driving even word line WLE and odd word line WLO in word line drive circuit 14.

  7, odd / even word line decoder 12 receives NOR address NG1 receiving row address bit RA <0> and tune information read instruction signal PRME, complementary row address bit RA_B <0> and tune information read instruction signal PRME. Including a NOR gate NG2. Row address bits RA <0> and RA_B <0> are complementary address bits. Tune information read instruction signal PRME is at the H level when activated.

  In the word line drive circuit 14, a NOR gate NG3 and an AND gate AG1 are provided for the even word line WLE, and a NOR gate NG4 and an AND gate AG2 are provided for the odd word line WLO. NOR gate NG3 receives an output signal of NOR gate NG1 and word line activation signal WLACN. NOR gate NG4 receives an output signal of NOR gate NG2 and word line activation signal WLACN.

  AND gate AG1 receives the output signal of NOR gate NG3 and row decode signal Xi. AND gate AG2 receives the output signal of NOR gate NG4 and row decode signal Xi. Row decode signal Xi is generated in common for the pair of word lines WLEi and WLOi, and is generated for each even-numbered and odd-numbered word line pair according to the decoding result of row address bits RA <n: 1>. Word line activation signal WLACN is at L level when activated.

  FIG. 8 is a diagram showing a list of state transitions in the read mode of odd / even word line decoder 12 and word line drive circuit 14 shown in FIG. In FIG. 8, the logical value “0” corresponds to the L level, and the logical value “1” corresponds to the H level.

  As shown in FIG. 8, when word line activation signal WLACN is inactive (at H level), output signal bits ZRA <0> and ZRA_B <0> of NOR gates NG3 and NG4 are both at L level. . Accordingly, corresponding word lines WLEi and WLOi are in a non-selected state (L level). At this time, the logical value of the row decode signal Xi may be either 1 or 0.

  When word line activation signal WLACN is in an active state (logic value “0”), NOR gates NG3 and NG4 operate as inverters. When tune information read instruction signal PRME is “0”, NOR gates NG1 and NG2 operate as inverters. Therefore, when tune information read instruction signal PRME is inactive and word line activation signal WLACN is in an active state, signals from NOR gates NG3 and NG4 according to row address bits RA <0> and RA_B <0> The logical values of ZRA <0> and ZRA_B <0> are determined. In this state, when row decode signal Xi is in the selected state (“1”), one word line is driven to the selected state among word lines WLEi and WLOi (in FIG. 8, the word line in the selected state is driven). A logical value “1” indicates a non-selected word line by a logical value “0”).

  On the other hand, when the tune information read instruction signal PRME is in the active state, the output signals of NOR gates NG1 and NG2 are at L level (“0”) regardless of the logical values of row address bits RA <0> and RA_B <0>. It becomes. Therefore, in this case, when word line activation signal WLACN is in the active L level, internal signals ZRA <0> and ZRA_B <0> from NOR gates NG3 and NG4 both have a logical value “1”. In this state, when row decode signal Xi is selected, both word lines WLEi and WLOi are driven to the selected state.

  That is, by activating tune information read instruction signal PRME, row address bit RA <0> is set in a degenerated state, and internal signals ZRA <0> and ZRA_B <0> are both driven to a selected state. Thereby, both the even word line WLEi and the odd word line WLOi can be driven to the selected state. At this time, when row decode signal Xi is in a non-selected state, both word lines WLEi and WLOi are in a non-selected state.

  As described above, even-numbered word lines and odd-numbered word lines are selectively selected in parallel by selectively setting 1-bit row address RA <0> to a degenerate state in accordance with tune information read instruction signal PRME. The twin cell mode and the double twin cell mode can be realized.

  The reason why the row address bits are selectively set to the degenerate state using the tune information read instruction signal PRME is as follows. That is, when tune information read instruction signal PRME is set to an inactive state, data reading of this semiconductor device can be performed in the twin cell mode. Therefore, in this semiconductor device, when redundant data such as defective address information for repairing a defective cell is stored, the tuning information is read in the double twin cell mode and the operating characteristics of each circuit are adjusted (tuned). In the twin cell mode, redundant data can be read out and set in a redundant program circuit, and current consumption can be reduced.

  When the memory cell is a spin injection type MRAM cell, a write current is supplied to the memory cell via the bit line and the source line. The direction of the write current is set according to the stored data. When the memory cell is a toggle type MRAM cell, the direction of the write current is constant. At the time of writing, by selecting a word line in the twin cell mode, data can be written in units of twin cells, the write current can be reduced accordingly, and the size of the write current generating circuit can be reduced. Can be reduced.

  In addition, in the same memory array as normal memory cells for storing normal data, a storage area (memory block) for storing tune information is aligned with an area for storing redundant information for repairing defective bits such as other defective addresses. (This configuration will be described in detail later).

  FIG. 9 schematically shows an example of the configuration of control circuit 6 shown in FIG. 9, a control circuit 6 includes a read control circuit 20 that generates a tune information read instruction signal PRME, a timer 21 that generates a clock signal by performing an oscillating operation in a predetermined cycle in accordance with the tune information read instruction signal PRME, 21 includes an address counter 22 that generates an address bit designating a memory cell according to a clock signal from 21, a word line control circuit 23 that controls memory cell selection, and a sense control circuit 24.

  The address counter 22 performs a count operation in synchronization with the clock signal from the timer 21, and generates a row address bit RA <n: 0> and a column address bit CA <m: 0> based on the count value CNT. The word line control circuit 23 activates the word line activation signal WLACN for a predetermined period according to the update of the count value of the address counter 22. Sense control circuit 24 activates sense activation signal SAE according to activation of word line activation signal WLACN, and deactivates sense activation signal SAE in response to deactivation of word line activation signal WLACN. To do.

  In accordance with count-up instruction signal CUP from address counter 22 and sense activation signal SAE from sense control circuit 24, timer 21 and read control circuit 20 are reset.

  Control circuit 6 shown in FIG. 9 is supplied with power-on detection signal POR from power-on detection circuit 18 in order to activate the tune information reading operation. As an example, the power-on detection circuit 18 stabilizes the voltage VIN that is stabilized most slowly among power supply voltages supplied to a circuit (tune target circuit) that uses this tune information or a semiconductor device that stores the tune information. When the voltage VIN is detected, the power-on detection signal POR is activated.

  Although not clearly shown in FIG. 9, a column selection activation signal for activating a column selection operation (bit line selection operation) is generated in synchronization with the word line activation signal WLACN. To the column selection signal generating circuits 3a and 3b shown in FIG.

  FIG. 10 is a signal waveform diagram showing the operation of the control circuit 6 shown in FIG. The operation of the control circuit 6 shown in FIG. 9 will be described below with reference to FIG.

  After the power is turned on, the voltage level of the internal voltage VIN increases. When the internal voltage VIN becomes equal to or higher than a predetermined voltage level or stabilizes, the power-on detection circuit 18 activates the power-on detection signal POR. Read control circuit 20 activates tune information read instruction signal PRME in accordance with activation of power-on detection signal POR. In response to the activation of the tune information read instruction signal PRME, the timer 21 oscillates at a predetermined cycle to generate a clock signal.

  The address counter 22 counts the clock signal from the timer 21 and generates row and column address bits based on the count value CNT. The word line control circuit 23 activates the word line activation signal WLACN for a predetermined period according to the change of the count value CNT. At this time, a column selection activation signal (not shown) is also activated according to the change in the count value CNT.

  Sense control circuit 24 activates sense activation signal SAE in accordance with word line activation signal WLACN. When a predetermined period elapses, word line activation signal WLACN and sense activation signal SAE are deactivated, and one cycle of reading tune information is completed.

  For each cycle of the clock signal from the timer 21, the memory cell is selected and the stored data in the selected memory cell is read in the double twin cell mode using the count value CNT from the address counter 22 as an address.

  When the count value CNT of the address counter 22 reaches the maximum value CNTmax, the count-up instruction signal CUP from the address counter 22 is activated in accordance with the fall of the clock signal output from the timer 21. In response to the activation of the count up instruction signal CUP and the deactivation of the sense activation signal SAE, the timer 21 is deactivated and the oscillation operation is stopped. In synchronization with the deactivation of timer 21, read control circuit 20 is deactivated and tune read instruction signal PRME is deactivated. After the timer 21 is reset, the count value of the address counter 22 is reset to the initial value in accordance with the sense activation signal SAE and the count up instruction signal CUP. In accordance with the reset of the address counter 22, the count up instruction signal CUP is inactivated.

  With the above-described configuration, the tune information read instruction signal PRME can be deactivated internally after all necessary tune information is read after power-on.

  The address counter 22 may be configured to update the count value CNT corresponding to the address bit after a predetermined number of clock signals are generated from the timer 21. Reading of the tune information can be started after the oscillation operation of the timer 21 is stabilized. Further, even if the power-on detection signal POR is supplied to each of the timer 21, address counter 22, word line control circuit 23 and sense control circuit 24 in the control circuit 6, their internal states are reset to the initial state. Good.

  The tune information read from the memory array (1a, 1b) is also used to adjust the operation timing of the timer 21, address counter 22, word line control circuit 23, and sense control circuit 24 included in the control circuit 6. It may be used for adjusting the activation period of the word line activation signal WLACN and the sense activation signal SAE.

  FIG. 11 schematically shows a structure of a portion for setting tune information using the semiconductor device according to the first embodiment of the invention. 11, the tune information storage unit 30 has the configuration of the semiconductor device shown in FIG. 1, stores tune information, and doubles according to the activation of the power-on detection signal POR from the power-on detection circuit 18. In the twin cell mode, the tune information Q is read sequentially.

  The tune information Q from the tune information storage unit 30 is given to the tuning target unit 32. The tuning target unit 32 includes a latch circuit 35 that latches the tune information Q from the tune information storage unit 30, a decoder 36 that decodes the latch information of the latch circuit 35, and a tuning whose state is set according to the decode signal of the decoder 36. A circuit 37 and a target circuit 38 whose operation characteristics are set by the tuning circuit 37 are included.

  The latch circuit 35 latches the tune information Q from the tune information storage unit 30 according to the tune information strobe signal QS from the tune information storage unit 30. The tune information strobe signal QS is generated in synchronization with the clock signal generated from the timer (21) in the control circuit (see FIG. 9) included in the tune information storage unit 30 (one cycle later).

  The decoder 36 decodes the multi-bit latch data of the latch circuit 35 and generates a decode signal. By decoding the tune information latched by the latch circuit 35 by the decoder 36, the tuning setting of the tuning target circuit 38 can be performed with a small number of bits. For example, when the tune information is 2-bit data, the decoder 36 can set one of four tuning states.

  Tuning circuit 37 includes a switching element that is selectively turned on in accordance with a decode signal from decoder 36. That is, in the tuning circuit 37, a switching element is provided in place of the fuse element in the fuse program circuit that sets the tuning state by fusing / not blowing the fuse element. By selectively setting the switching element to a conductive / non-conductive state according to a decode signal from the decoder 36, tuning such as a short circuit of the resistance element and adjustment of the number of unit transistors is performed.

  The target circuit 38 is a circuit whose circuit operation characteristics can be tuned, and may be any of an internal voltage generation circuit, a control circuit, and a write / read circuit in a storage device. The generated voltage level, operation timing, activation period, and the like are set according to the tuning information.

  In the tuning target unit 32, when there are a plurality of target circuits 38 and a plurality of latch circuits 35 are provided, the following configuration is used as an example. That is, the latch circuit 35 is connected to form a scan path, for example, and the tune information is sequentially transferred according to the strobe signal QS. As such a scan path, for example, in a semiconductor integrated circuit device, the same configuration as that of a Vandaris campus used as a test circuit can be used.

  In this case, a tune information data transfer path may be provided separately from the tune information storage unit 30 according to the type (voltage, operation timing / operation period) of each tune information, and the type of the target circuit 38 ( For example, a tune information data transfer path may be provided separately according to a write / read circuit, a buffer circuit, and an internal voltage generation circuit.

  As shown in FIG. 11, the power-on detection signal POR from the power-on detection circuit 18 is also given to the tuning target unit 32. In accordance with the power-on detection signal POR, the tuning information is set after the internal state of the tuning target unit 32 is set to the initial state, and then the operation of the target circuit 38 is permitted.

  In the configuration shown in FIG. 11, the tune information storage unit 30 and the tuning target unit 32 may be included in separate blocks (macro or module) and arranged on the same semiconductor chip. It may be commonly arranged in a block (or macro), for example, a memory block (macro).

  As described above, according to the first embodiment of the present invention, data is read in the double twin cell mode when reading tune information from the memory cell storing tune information. Therefore, even before the circuit operation characteristics are tuned by the tune information, the tune information can be read stably and the circuit operation characteristics can be set accurately.

  The tune information read instruction signal enables reading in either the double twin cell mode or the twin cell mode. Therefore, in the case of the nonvolatile semiconductor memory device, the memory cell storing the tune information and the memory cell storing the redundant data and the normal data can be arranged in the same array by switching the read mode by the tune information read instruction signal. it can.

[Embodiment 2]
FIG. 12 shows a structure of memory cell MC used in the second embodiment of the present invention. As shown in FIG. 12, memory cell MC includes a variable magnetoresistive element VR and an access transistor AT. Access transistor AT is selectively turned on in response to a signal potential on word line WL, and electrically connects variable magnetoresistive element VR to source line SL.

  A digit line (write word line) DL is provided in parallel with the word line WL. A current is applied to digit line DL in a predetermined fixed direction during data writing, and a magnetic field is applied to variable magnetoresistive element VR. Variable magnetoresistive element VR of memory cell MC is coupled to bit line BL. The variable magnetoresistive element VR may be a spin injection type element or a TMR (tunneling magneto resistance) element. In the case of a spin injection type element, the direction of the current flowing between the bit line BL and the source line SL is set according to the write data. In this case, the magnetic field induced by the current flowing through the digit line DL is used as an assist magnetic field, and accelerates the change in the magnetization direction of the variable magnetoresistive element VR.

  On the other hand, when the variable magnetoresistive element VR is a TMR element, the access transistor AT is in an off state. A current is supplied to the bit line BL in a direction corresponding to the write data, and a current in a fixed direction is supplied to the digit line DL. The resistance value of the variable magnetoresistive element VR is set by the magnetic fields induced by the currents flowing through the digit line DL and the bit line BL.

  The memory cell MC may be a toggle MRAM cell in which an MTJ (magneto tunnel junction) element is used as a variable magnetoresistive element. In the case of this cell, a current in a fixed direction is supplied to the digit line DL and the bit line at different timings. By supplying the digit line current and the bit line current in a predetermined sequence in each write cycle, the magnetization state of the variable magnetoresistive element is changed, and the stored data is changed.

  FIGS. 13A and 13B are diagrams schematically showing a data writing mode when the variable magnetoresistive element VR is a TMR element. In FIG. 13A, the variable magnetoresistive element VR includes a fixed layer FXL whose magnetization direction is fixed, a free layer FRL whose magnetization direction is set according to stored data, and a fixed layer FXL and a free layer FRL. Including a barrier layer BRL.

  The magnetization direction of the free layer FRL is determined by the combined magnetic field of the magnetic field (digit current magnetic field) Hd induced by the current flowing through the digit line DL and the magnetic field (bit line current magnetic field) Hb induced by the current flowing through the bit line BL. In FIG. 13A, a clockwise magnetic field is formed, and the magnetization direction of the free layer FRL is set to be opposite to the magnetization direction of the fixed layer FXL. In this case, the magnetoresistive value of the variable magnetoresistive element VR becomes large and is associated with a state where data “L” is stored.

  The configuration of memory cell MC can also be used as a memory cell in the first embodiment. Also in the first embodiment, when an MRAM cell is used as a memory cell for storing tune information, any one of the above-described variable magnetoresistive elements is used.

  On the other hand, as shown in FIG. 13B, when the combined magnetic field of the digit line current magnetic field Hd and the bit line current magnetic field Hb is a counterclockwise magnetic field, the free layer FRL is magnetized in the rightward direction, The magnetization directions of the free layer FRL and the fixed layer FXL coincide (become parallel). In this case, the resistance value of the magnetoresistive element VR becomes small and is associated with a state of storing data “H”.

  FIG. 14 schematically shows an overall configuration of a semiconductor device for storing tune information according to the second embodiment of the present invention. In FIG. 14, the tune information storing semiconductor device includes two memory arrays 40a and 40b. In each of memory arrays 40a and 40b, memory cells MC are arranged in a matrix. The memory cell MC has the configuration shown in FIGS. 12 and 13 as an example. In memory array 40a, word line WLA and digit line DLA are arranged corresponding to the row of memory cells MC, and bit line BLA and source line SLA are arranged corresponding to the memory cell column. Also in memory array 40b, word line WLB and digit line DLB are arranged corresponding to each row of memory cells MC, and bit line BLB and source line SLB are arranged corresponding to the memory cell column.

  A word line selection drive circuit 41a, a digit line selection drive circuit 42a, a read column selection gate circuit 44a, and bit line drive circuits 45aa and 45ab are arranged for memory array 40a. Also for memory array 40b, word line selection drive circuit 41b, digit line selection drive circuit 42b, read column selection gate circuit 44b, and bit line drive circuits 40ba and 45bb are arranged.

  Word line selection drive circuits 41a and 41b correspond to row selection drive circuits 2a and 2b in the first embodiment, and when tune information read instruction signal PRME is activated, word lines WLA and WLB are set to a selected state in double twin cell mode. To drive.

  Digit line selection drive circuits 42a and 42b drive two digit lines to the selected state in parallel in corresponding memory arrays 40a and 40b when tune information write instruction signal PWME is activated. Digit line selection drive circuits 42a and 42b drive one digit line to the selected state in each of corresponding memory arrays 40a and 40b when tune information write instruction signal PWME is inactivated during data writing. To do.

  Read column select gate circuits 44a and 44b correspond to column select gate circuits 4a and 4b in the first embodiment. In accordance with a column select signal from column select signal generating circuits 43a and 43b, a corresponding memory array 40a is read out. And bit lines BLA and BLB of the addressed column of 40b are selected and coupled to read circuit 46 via internal read data lines. Read circuit 46 corresponds to read circuit 5 in the first embodiment, and generates internal read data Q according to the current flowing through the selected bit line when sense activation signal SAE is activated.

  Bit line drive circuits 45aa and 45ab are arranged on both sides of the bit line of memory array 40a, and are selected according to complementary internal write data from write data generation circuit 48a and a column selection signal from column selection signal generation circuit 43a. A current corresponding to the write data is supplied to the bit line of the column (at the time of data writing).

  Similarly, bit line drive circuits 45ba and 45bb are arranged on both sides of bit line BLB of memory array 40b, and at the time of data writing, the column selection signal from column selection signal generation circuit 43b and the complementary from write data generation circuit 48b In accordance with the internal write data, a current corresponding to the write data is supplied to the bit line of the selected column.

  Bit line drive circuits 45aa and 45ab are arranged on both sides of the bit lines of memory array 40a, and bit line drive circuits 45ba and 45bb are arranged on both sides of the bit lines of memory array 40b, so as to respond to write data. Thus, the direction of the current flowing through the selected bit line can be switched (assuming a case where a memory cell is constituted by TMR elements).

  Write data generation circuits 48a and 48b generate complementary write data in accordance with the write data supplied from data input circuit 47 at the time of data writing. In the second embodiment, the tune information is written in the double-twin cell mode, so that complementary write data from data input circuit 47 is applied to write data generation circuits 48a and 48b. . The write data D applied to the data input circuit 47 is applied at the time of initialization (after completion of the test operation in the final process of the manufacturing process) from an external tester or the like based on the tune information.

  A control circuit 49 is provided to control the internal operation of the semiconductor device. When power-on detection signal POR is activated, control circuit 49 activates tune information read instruction signal PRME and sense activation signal SAE at a predetermined timing (see FIG. 9). When instruction TM is given, tune information write instruction signal TWME is activated.

  FIG. 15 schematically shows a selection mode of a memory cell at the time of writing tune information in the semiconductor device according to the second embodiment of the present invention. In FIG. 15, memory cells MCA3 and MCB3 in the same row and column of memory arrays 40a and 40b constitute twin cell TW3 and store complementary data. Memory cells MCA4 and MCB4 arranged in the same row and column of memory arrays 40a and 40b constitute twin cell TW4 and store complementary data.

  In memory array 40a, memory cells (first memory cells) MCA3 and MCA4 store data of the same logical value, and in memory array 40b, memory cells MCB3 and MCB4 store data of the same logical value. The storage mode of the tune information is the same as that in the first embodiment.

  In digit line selection drive circuit 42a, digit line driver 52ao is provided for odd digit line DLAo, and digit line driver 52ae is provided for even digit line DLAe. When data writing, digit line drivers 52ao and 52ae are selected during data writing, they simultaneously drive digit lines DLAo and DLAe to a selected state. Digit lines DLAo and DLAe have one end coupled to the ground node. Therefore, when selected, digit line current is always supplied in the same direction by digit line drivers 52ao and 52ae.

  In bit line drive circuits 45aa and 45ab, bit line drivers 50aa and 50ab are provided on both sides of bit line BLA, respectively. Bit line driver 50aa drives bit line BLA according to write column selection signal WCSL and write data D, and bit line driver 50ab applies bit line according to write column selection signal WCSL and complementary write data D_B. Drive BLA.

  Internal write data D and D_B are mutually complementary data supplied from write data generation circuit 48a shown in FIG. Write column selection signal WCSL is applied at the time of data writing from column selection signal generation circuit 43a shown in FIG. Therefore, one of the bit line drivers 50aa and 50ab functions as a current source and the other functions as a current sink, and a current flows through the bit line BLA. Data can be written in parallel to memory cells MCA3 and MCA4 by the bit line current and the digit line current.

  Similarly, digit line drivers 52be and 52bo are provided for even digit line DLBe and odd digit line DLBo, respectively, in digit line selection drive circuit 42b for memory array 40b. Are driven to the selected state in parallel.

  In bit line drive circuits 45ba and 45bb, bit line drivers 50ba and 50bb are arranged on both sides of bit line BLB, respectively. Bit line driver 50ba drives bit line BLB in accordance with write column selection signal WCSL and complementary internal write data D_B. Bit line driver 50bb drives bit line BLB in accordance with write column selection signal WCSL and internal write data D. Therefore, a current flows to bit line BLB with one of bit line drivers 50ba and 50bb as a current source and the other as a current sink, and data of the same logical value is written into memory cells MCB3 and MCB4.

  When writing the tune information, in the memory array 40a, for example, when a bit line current flows from left to right on the bit line BLA, in the memory array 40b, a bit line current flows from right to left. Thereby, data of opposite logical values can be written in parallel to the first memory cells (MCA3 and MCA4) and the second memory cells (MCB3 and MCB4) of the twin cells TW3 and TW4.

  Even when tune information is written, the number of data write cycles can be halved by writing in the double-twin cell mode as compared to writing in the twin-cell mode. Accordingly, the time required for writing tune information can be shortened, and the test time can be shortened (writing of tuning information is usually performed at the final step of the test process). Also, complementary data can be easily written in parallel to memory arrays 40a and 40b.

  FIG. 16 shows an example of the configuration of digit line selection drive circuits 42a and 42b shown in FIG. Since these digit line selection drive circuits 42a and 42b have the same configuration, in FIG. 16, these digit line selection drive circuits 42a and 42b are generically indicated by reference numeral 42.

  In FIG. 16, digit line selection drive circuit 42 (42a, 42b) includes decode stage 54 for decoding row address bit RA <0>, digit line DLEi and output signal of decode stage 54 and digit line activation signal DLACN, And a drive stage 56 for driving DLOi. Decode stage 54 includes NOR gate NG5 receiving tune information write instruction signal PWME and row address bit RA <0>, and NOR gate NG6 receiving complementary row address bit RA_B <0> and tune information write instruction signal PWME. including.

  The decode stage 56 includes a NOR gate NG7 that receives the digit line activation signal DLACN and the output signal of the NOR gate NG5, a NOR gate NG8 that receives the digit line activation signal DLACN and the output signal of the NOR gate NG6, and a row decode signal Xi. AND gate AG3 that drives even digit line DLEi according to output signal ZRA <0> of NOR gate NG7, and AND gate AG4 that drives odd digit line DLOi according to row decode signal Xi and output signal ZRA_B <0> of NOR gate NG8 including.

  The configuration of the digit line selection drive circuit shown in FIG. 16 has the same logical configuration as that of the row selection drive circuit shown in FIG. Therefore, the state transition shown in FIG. 8 can be used by replacing tune information read instruction signal PRME with tune information write instruction signal PWME and replacing word line activation signal WLACN with digit line activation signal DLACN. That is, when tune information write instruction signal PWME is in the active state of H level (“1”), digit lines DLEi and DLOi are driven to the selected state in parallel (according to activation of digit line activation signal DLACN). . On the other hand, when tune information write instruction signal PWME is at an inactive L level (“0”), one of digit lines DLEi and DLOi is selected according to row address bit RA <0> and row decode signal Xi. Driven to the state (when the decode signal Xi is in the selected state).

  Note that the row decode signal Xi is generated by a row decoder (see FIG. 6) as in the first embodiment.

  The configuration of word line selection drive circuits 41a and 41b shown in FIG. 14 is the same as the configuration of row selection drive circuits 2a and 2b shown in the first embodiment.

  FIG. 17 schematically shows an example of the configuration of control circuit 49 shown in FIG. Also in the control circuit 49 shown in FIG. 17, in accordance with the power-on detection signal POR from the power-on detection circuit 18, the tune information is read out in the double twin cell mode.

  In FIG. 17, a control circuit 49 includes a read control circuit 60 that generates a tune information read instruction signal PRME, a timer 61 that defines an operation cycle during reading, and an address that generates row and column addresses during writing and reading. Counter 62.

  Read control circuit 60 activates tune information read instruction signal PRME in response to activation of power-on detection signal POR. Read control circuit 60 also always maintains tune information read instruction signal PRME in an inactive state when tune information write instruction TM is given by an external tester. When this tune information write instruction TM is in an inactive state and read instruction signal PRME is in an active state, timer 61 performs an oscillation operation to generate a clock signal at a predetermined cycle. When the tune information write instruction TM is asserted, the timer 61 is deactivated and its oscillation operation is stopped.

  Address counter 62 performs a counting operation in accordance with a clock signal output from timer 61 or a test clock signal TCLK provided from an external tester, and uses count value CNT as row address RA <n: 0> and column address CA <m. : 0>. Address counter 62 resets its count value to the initial value in accordance with activation of tune information write instruction TM.

  The control circuit 49 further includes a word line control circuit 63 for generating the word line activation signal WLACN, a column selection control circuit 64 for generating the column selection activation signal CACN, and a sense control circuit for generating the sense activation signal SAE. And a digit line control circuit 66 for generating a digit line activation signal DLACN.

  The word line control circuit 63 maintains the word line activation signal WLACN in an active state for a predetermined period according to the transition of the count value of the address counter 62 when the tune information write instruction TM is deasserted (see the first embodiment). When tune information write instruction TM is asserted, word line control circuit 63 is maintained in an inactive state, and word line activation signal WLACN is always maintained in an inactive state.

  The column selection control circuit 64 generates a column selection activation signal CACN that is in an active state for a predetermined period in accordance with the transition of the count value CNT of the address counter 62, and applies it to the column selection signal generation circuits 43a and 43b. In accordance with column selection activation signal CACN, column selection signal generation circuits 43a and 43b (see FIG. 14) decode column address CA <m: 0> included in count value CNT, and when tune information write instruction TM is asserted, The write column selection signal WCSL for the selected column is driven to the selected state. When tune information read instruction TM is in the deasserted state and tune information read instruction signal PRME is in the asserted state (active state), column select signal generating circuits 43a and 43b generate read column select signals (RCSL), Data is read from the selected bit line.

  The sense control circuit 65 activates the sense activation signal SAE according to the word line activation signal WLACN from the word line control circuit 63, and outputs the sense activation signal SAE in response to the deactivation of the word line activation signal WLACN. It is deactivated (see Embodiment 1). Therefore, in the tune information write mode in which word line activation signal WLACN is always maintained in an inactive state, sense activation signal SAE from sense control circuit 65 is always maintained in an inactive state, as shown in FIG. Read circuit 46 is maintained in an inactive state.

  Digit line control circuit 66 generates digit line activation signal DLACN that is active for a predetermined period in accordance with the transition of the count value from address counter 62 when tune information write instruction TM is asserted. When tune information write instruction TM is in the deasserted state, digit line control circuit 66 always maintains digit line activation signal DLACN in the inactive state.

  FIG. 18 is a timing chart showing the operation of the control circuit 49 shown in FIG. Hereinafter, the operation of the control circuit 49 shown in FIG. 17 when writing tune information will be described with reference to FIG.

  At the time of writing tune information, first, tune information write instruction TM is asserted (indicated by H level in FIG. 18). In response, read control circuit 60 and timer 61 are maintained in an inactive state.

  When this tune information write instruction TM is given, a test clock signal TCLK having a predetermined cycle is then given from an external tester (not shown), and the address counter 62 performs a counting operation according to this test clock signal TCLK. And the count value CNT is updated. In synchronization with the test clock signal TCLK, tune information is given as write data D from an external tester.

  When tune information write instruction TM is asserted, both word line control circuit 63 and sense control circuit 65 are inactive, and read control circuit 60 is also inactive. Therefore, word line activation signal WLACN, sense activation signal SAE and tune information read instruction signal PRME are maintained in an inactive state during the tune information write operation. That is, word line activation signal WLACN is always maintained at the H level, and sense amplifier activation signal SAE and tune information read instruction signal PRME are maintained at the L level.

  Digit line control circuit 66 maintains digit line activation signal DLACN in an active state for a predetermined period in accordance with the transition of count value CNT from address counter 62. Thus, the decoding operation is performed in the digit line selection drive circuit shown in FIG. 16, even digit line DLE and odd digit line DLO are selected according to count value CNT, and the tune information is written in the double twin cell mode. It is. The count value CNT is updated in synchronization with the test clock signal TCLK, and tune information is written to each address.

  When the count value CNT reaches the maximum value CNTmax, the final tune information Dmax is written. When writing of the final tune information Dmax is completed, the tune information write instruction TM is deasserted and the address counter 62 is reset. Also, the supply of the test clock signal TCLK is stopped.

  Whether or not the final value CNTmax of the count value CNT has been reached is determined by counting the number of tune information in an external tester.

  When the power-on detection signal POR is activated, the tune information read instruction signal PRME is activated in the same manner as in the first embodiment, and the tune information is read in the double twin cell mode.

  By using control circuit 49 shown in FIG. 17, tune information can be read and written in the double twin cell mode when tune information is accessed.

  Memory cell MC is a memory cell into which data is written by spin injection. When digit line DL is not used, the word line is driven to a selected state at the time of data writing and reading. In this case, the potential of the selected bit line and the source is set to a voltage level according to the write data, and the direction in which the current flows is set according to the write data. In this case, word line control circuit 63 shown in FIG. 17 is activated during tune information reading and writing, and sense control circuit 65 is maintained in an inactive state during tune information writing. A write driver and a source line driver are provided in place of the bit line driver, and the selected bit line is driven by the write driver and the source line driver via the source line and the internal data bus (write data line). Then, the direction in which the current of the selected memory cell flows is set.

  In the case of a toggle MRAM cell, the source line potential is fixed. When writing data, the digit line is driven to a selected state in a predetermined sequence, and a current is supplied to the selected bit line via the write data line by the write driver. In this case, both the word line and the digit line are driven to the selected state. In a spin injection type memory cell (spin torque transfer MRAM cell), a digit line current may be used to generate an assist magnetic field in order to easily perform writing. Also in this case, both the word line and the digit line are driven to the selected state. Therefore, the internal configuration of the semiconductor device and the configuration of the control circuit are appropriately adjusted according to the configuration of the memory cell MC.

  As described above, according to the second embodiment of the present invention, the writing is performed in the double twin cell mode even when the tune information is written. Therefore, the writing time can be shortened compared with the case where the tune information is written in the twin cell mode, and the test time can be shortened accordingly. The double twin cell mode is used at the time of writing because it matches the mode at the time of reading tune information, and the multi twin cell mode in which more word lines are selected at the time of reading tune information is used. In some cases, even during writing, a large number of word lines are selected accordingly, and tune information is written in the multi-twin cell mode.

[Embodiment 3]
FIG. 19 schematically shows a whole structure of the semiconductor integrated circuit device according to the third embodiment of the present invention. In FIG. 19, a semiconductor integrated circuit device 70 includes a processor 72, an MRAM module (macro) 74, an SRAM (static random access memory), and a module 76. These processor 72, MRAM module 74 and SRAM module 76 are coupled via an internal data bus 78.

  The semiconductor integrated circuit device 70 shown in FIG. 19 is a so-called “system LSI”, and is integrated on one semiconductor chip to constitute one system. The SRAM module 76 stores information that requires high-speed processing such as instructions, and the MRAM module 74 stores a large amount of information such as image / audio data and ROM information (boot program, ID information). . The processor 72 exchanges data / codes with these MRAM module 74 and SRAM module 76, and executes processing specified by the program.

  The MRAM module 74 includes an MRAM 80, a tune information storage unit 82, a power-on detection circuit 84, and a test interface 86. The MRAM 80 includes an MRAM cell array, a memory selection circuit, and a data write / read circuit, and has the same configuration and function as one MRAM single chip.

  The tune information storage unit 82 has the same configuration as the semiconductor device for storing tune information shown in the first embodiment or the second embodiment. The power-on detection circuit 84 detects a power supply voltage supplied from the processor 72 or from the outside, and sets the state of the power-on detection signal POR. The tune information storage unit 82 transfers the stored tune information to the MRAM 80 according to the power-on detection signal POR from the power-on detection circuit 84, and sets the internal state of the MRAM 80. The tune information storage unit 82 can be coupled to an external tester via the test interface 80. When writing tune information, the test clock signal TCLK and the tune information write instruction signal TM are sent via the test interface 86. And tune information D. By using this test interface 86, it is possible to write tune information by connecting the tune information storage unit 82 to an external pin terminal even after packaging.

  The MRAM module 74 is prepared as one library, used as one macro at the time of system construction, and arranged in the system LSI. This semiconductor integrated circuit device 70 may be provided with a circuit for performing analog processing, such as another analog / digital conversion circuit.

  Also in the semiconductor integrated circuit device for constructing such a system LSI, the tune information storage unit 82 is arranged in the MRAM module 74 and the tune information is read out in the double twin cell mode, so that the MRAM 80 can be read at an early timing after power-on. Can be set to desired operating characteristics.

  The tune information storage unit 82 may be configured to store the tune information of the MRAM 80, the tune information of the processor 72, and the tune information of the SRAM. By using the scan path, the tune information can be transferred to each tuning target circuit on the chip (semiconductor integrated circuit device 70).

[Embodiment 4]
FIG. 20 schematically shows a structure of a main portion of the semiconductor device according to the fourth embodiment.

  20, the semiconductor device according to the fourth embodiment of the present invention includes memory mats 90A and 90B arranged separately from each other. Memory mat 90A includes a normal cell array 92a, a redundant cell array 94a, a redundant data storage area 96a, and a tune information storage area 98a in which memory cells having the same configuration are arranged in a matrix. Normal memory cell array 92b, redundant cell array 94b, redundant data storage area 96b, and tune information storage area 98b.

  In each of normal cell arrays 92a and 92b, memory cells storing normal data are arranged in a matrix. Redundant cell arrays 94a and 94b are used as redundant cells for storing redundant data for relieving defective cells of corresponding normal cell arrays 92a and 92b by replacement, respectively. In FIG. 20, each of redundant cell arrays 94a and 94b is shown arranged to relieve a defective row. However, in redundant cell arrays 94a and 94b, redundant cells are arranged so as to relieve defective columns.

  Redundant data storage areas 96a and 96b store defective addresses indicating defective row / column addresses of normal cell arrays 92a and 92b. Similarly, the tune information storage areas 98a and 98b store tune information for adjusting the operation characteristics of each circuit in the semiconductor device.

  Therefore, in memory mats 90A and 90B, memory cells having the same configuration are arranged in a matrix for storing normal data, redundant data, and tune information. In the fourth embodiment, as an example of the memory cell, an MRAM cell in which data is written by spin injection is used. In this memory cell structure, during data writing, a current is passed between the bit line of the selected column and the source line of the selected column in accordance with the write data. A digit line (write word line) may be used to generate an assist magnetic field for accelerating magnetization reversal during data writing.

  A row selection drive circuit 100a and a column selection circuit 102a are provided for the memory mat 90A, and a row selection drive circuit 100b and a column selection circuit 102b are provided for the memory mat 90B. Row selection drive circuits 100a and 100b each drive a word line arranged corresponding to a selected row in a corresponding memory mat to a selected state. Row selection circuits 100a and 100b are provided in common to redundant data storage regions 96a and 96b and tune information storage regions 98a and 98b (word lines arranged corresponding to memory cell rows are memory mats 90A and 90B). The row selection drive circuits 100a and 100b drive the word line to the selected state when selecting normal cells, selecting redundant data storage cells, and selecting tune information storage cells. To do).

  Column selection circuits 102a and 102b each include a column selection signal generation circuit and a column selection gate circuit, and select an addressed column in the corresponding memory mat. Columns (bit lines) selected by column selection circuits 102a and 102b are coupled to internal data buses 104a and 104b, respectively. Internal data buses 104a and 104b are provided in common for both internal write data and internal read data, and have a plurality of bit widths. Internal data buses 104a and 104b are coupled to read circuit 106 and write circuit 108, respectively. In FIG. 20, read circuit 106 and write circuit 108 are shown facing opposite ends of internal data buses 104a and 104b. These circuits 106 and 108 are connected to internal data buses 104a and 104b. It may be arranged adjacent on one side.

  A control circuit 110 is provided to control internal operations, and controls normal cell data write and read operations, redundant data write and read operations, and tune information write and read operations.

  This semiconductor device is an MRAM, and each of the internal circuits (row selection drive circuits 100a and 100b, readout circuit 106, and control circuit 110) can be tuned in its operating characteristics. And the operating characteristics are adjusted according to the tune information stored by 98b.

  FIG. 21 is a diagram showing a more specific structure of the semiconductor device shown in FIG. 20 (hereinafter referred to as a semiconductor memory device). In FIG. 21, the memory mat 90A is divided into a normal data area 112a and a PROM data area 114a. The normal data area 112a includes a normal cell array 92a and a redundant cell array 94a, and the PROM data area 114a includes a redundant data storage area 96a and a tune information storage area 98a.

  In memory mat 90A, word line WLA is arranged corresponding to the memory cell row, and dummy word line DWLA is arranged in parallel with word line WLA. Bit line BLA is arranged to cross these word line WLA and dummy word line DWLA. A normal cell MC and a dummy cell DMC are arranged corresponding to the intersection of the word line WLA, the dummy word line DWLA, and the bit line BLA. Dummy cell DMC is a cell that supplies a reference current during normal data reading, and its resistance value is set to an intermediate value between the high resistance state and the low resistance state of the memory cell.

  Similarly, the memory mat 90B is divided into a normal data area 112b and a PROM data area 114b. The normal data area 112b includes a normal cell array 92b and a redundant cell array 94b, and the PROM data area 114b includes a redundant data storage area 96b and a tune information storage area 98b.

  Similarly, in memory mat 90B, word lines WLB and bit lines BLB are arranged corresponding to the rows and columns of memory cells MC, and dummy word lines DWLB are arranged corresponding to the rows of dummy cells DMC.

  Internal data bus 104a is divided into a normal data bus 104an for exchanging data with data area 112a and a PROM data bus 104ap for exchanging data with PROM data area 114a. Normal data bus 104b is divided into a normal data bus 104bn for exchanging data with normal data area 112b and a PROM data bus 104bp for exchanging data with PROM data area 114b.

  Read circuit 106 includes normal read circuit 106n for generating internal read data NQ according to data (current) on normal data buses 104an and 104bn, and redundant data or tune information according to data (current) on PROM data buses 104ap and 104bp. Some program data RQ is generated.

  Normal read circuit 106n and PROM read circuit 106p are complementarily enabled / disabled in accordance with PROM data access activation signal ENPROM. That is, when data is read from PROM data areas 114a and 114b, PROM data access activation signal ENPROM is activated, PROM read circuit 106p is enabled, and tune information and redundant data are read in accordance with activation of a sense activation signal (not shown). Reading is performed. At this time, normal read circuit 106n is disabled and no read operation is performed. When reading data in normal data areas 112a and 112b, PROM data access activation signal ENPROM is inactive, PROM read circuit 106p is disabled, and normal read circuit 106n is enabled. When normal reading circuit 106n is enabled, it performs a sensing operation in accordance with a sense activation signal (not shown) to generate normal data NQ.

  Write circuit 108 includes a normal write circuit 108n for generating internal write data on normal data buses 104an and 104bn, and a PROM write circuit 108p for generating internal write data on PROM data buses 104ap and 104bp. . In write circuit 108, when tune information write instruction TM is asserted, PROM write circuit 108p is enabled, and internal write data is generated according to program data RD including redundant data (redundant address information) or tune information. Normal write circuit 108n is enabled when this tune information write instruction TM is deasserted, and generates internal write data according to external normal write data ND.

  At the time of data writing, the direction in which current flows between the bit line and the source line is determined according to write data ND and RD. Therefore, in write circuit 108, normal write circuit 108n and PROM write circuit 108p include a circuit for driving a source line and a circuit for driving a bit line, respectively.

  FIG. 22 schematically shows a memory cell selection mode at the time of reading normal data of 1 bit in the normal data region in the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 22 shows a memory cell selection mode when memory cell MC is selected in normal data region 112a and data in selected memory cell MC is read. In this case, in normal data area 112a, word line WLA and bit line BLA are selected, and memory cell MC is coupled to normal data bus 104an via bit line BLA. On the other hand, in normal data region 112b, dummy word line DWLB and bit line BLB are selected, and dummy cell DMC is coupled to normal data bus 104bn via bit line BLB. Bit lines BLA and BLB are selected according to the same column address.

  Normal read circuit 106n generates internal read data NQ according to memory cell current Im flowing through memory cell MC and reference current Iref flowing through dummy cell DMC.

  Normal read circuit 106n is provided with a sense amplifier circuit that performs a differential amplification operation corresponding to each data bit. According to which of the memory mats 90A and 90B the selected memory cell MC is included in, the connection between the normal data buses 104an and 104bn and the input of the differential amplifier circuit is switched. By this bus connection switching, the first input (for example, positive input) of the differential amplification type sense amplifier circuit is always connected to the memory cell MC, and the second input (for example, negative input) is always connected to the dummy cell DMC. The

  The number of memory cells to be selected is determined according to the bit width of data, and an internal read data bit is generated by a similar sensing operation for each data bit.

  In this case, word line WLA and dummy word line DWLB are also selected in PROM data areas 114a and 114b, respectively. However, at the time of normal data reading, PROM reading circuit 106p is in a disabled state, and PROM data is not read even when a memory cell storing PROM data is selected. Since normal data buses 104an and 104bn are provided separately from PROM data buses 104ap and 104bp, there is no collision of read data, and normal data stored in the selected memory cell can be read accurately. .

  FIG. 23 schematically shows a memory cell selection mode at the time of writing 1-bit data in the normal data area. In FIG. 23, mat A write circuits 108na and 108nb are coupled to normal data buses 104an and 104bn, respectively. The mat A write circuit 108na and the mat B write circuit 108nb are included in the normal write circuit 108n. The mat A write circuit 108na and the mat B write circuit 108n are selectively activated according to the mat selection signals BKA and BKB, respectively.

  When the memory mat 90A is selected, the source line SLA for the selected column is coupled to the mat A write circuit 108na by a source line selection circuit (not shown) in the memory mat 90A, and the bit line BLA of the selected column is normal data. The mat A write circuit 108na is coupled to the bus 104an. Since mat selection signal BKA is in an active state when mat A is selected, mat A write circuit 108na passes a current between bit line BLA and source line SLA in accordance with write data D. The direction of the write current is determined according to the logical value of the write data D.

  On the other hand, since no selected memory cell exists in memory mat 90B, no word line is selected, and mat B write circuit 108nb is maintained in an inactive state. Also in the memory mat 90B, selection of a word line, a bit line, and a source line may be performed. By maintaining both the bit line and the source line of the selected column at the ground voltage level, writing of normal data can be prevented in the memory mat 90B.

  In this case, the PROM write circuit 108p is maintained in the disabled state because the tune information write instruction TM is in the deasserted state as shown in FIG.

  FIG. 24 schematically shows a memory cell selection mode in reading 1-bit redundant data from the redundant data storage area. In FIG. 24, word lines WLA and WLB are driven to the selected state in parallel in memory mats 90A and 90B, respectively. In redundant data storage areas 96a and 96b, bit lines BLA and BLB in the same column are selected and connected to PROM data buses 104ap and 104bp. In memory mats 90A and 90, in data read mode, source lines SLA and SLB are maintained at the ground voltage level regardless of reading of normal data and redundant data.

  PROM data buses 104ap and 104bp are coupled to PROM read circuit 106p. Complementary storage data of memory cells MC1 and MC2 constituting twin cell TW appear on PROM data buses 104ap and 104bp. In accordance with the data stored in twin cell TW, PROM read circuit 106p generates internal read data RQ as redundant data. The internal read redundant data RD is transmitted to a redundant program circuit (not shown) and stored as a defective address. The redundancy decoder (included in the row selection drive circuit and the column selection circuit) is selectively activated in accordance with the coincidence / non-coincidence between the defective address stored in the redundancy program circuit and the external address, and the normal data areas 112a and 112b When a defective address is designated, the normal decoder is replaced with a redundant decoder. Thus, when a defective cell row / column is selected, replacement with a redundant cell row / column is performed to repair the defective cell.

  At the time of redundant data reading, word lines WLA and WLB are similarly selected in tune information storage areas 98a and 98b. However, the corresponding bit line is in a non-selected state, and reading of tune information is avoided.

  FIG. 25 schematically shows a manner of selecting memory cells when writing 1-bit redundant data stored in redundant data storage areas 96a and 96b. PROM writing circuit 108p includes a mat APROM writing circuit 108pa provided for memory mat 90A and a mat BPROM writing circuit 108pb provided for memory mat 90B. The mat APROM write circuit 108pa is coupled to the PROM data bus 104ap, and the mat BPROM write circuit 108pb is coupled to the PROM data bus 104bp. These mat PROM write circuits 108pa and 108pb generate complementary data according to PROM data (redundant data) RD when tune information write instruction TM is asserted.

  In each of memory mats 90A and 90B, word lines WLA and WLB in the same row are driven to a selected state, and bit lines BLA and BLB in the same column are selected. Source lines SLA and SLB provided corresponding to these selected bit lines BLA and BLB are coupled to corresponding mat APROM write circuit 108pa and mat BPROM write circuit 108pb via source select driver SD, respectively. Is done. The mat APROM write circuit 108pa, the mat BPROM write circuit 108pb and the source line selection driver SD generate write currents Iw1 and Iw2 in opposite directions in the bit lines BLA and BLB, and the memory cell MC1 constituting the twin cell TW and Complementary data is written to MC2.

  Normal write circuit 108n is maintained in the inactive state when tune information write instruction TM is in the asserted state.

  FIG. 26 schematically shows a memory cell selection mode at the time of reading 1-bit tune information. In FIG. 26, when 1-bit tune information is read from tune information storage areas 98a and 98b, word lines WLAe and WLAo are driven to a selected state in memory mat 90A, and word lines WLBe and WBLBo are selected in memory mat 90B. Driven to state. In tune information storage areas 98a and 98b, bit lines BLA and BLB are selected and coupled to PROM data buses 104ap and 104bp, respectively. In tune information storage area 98a, storage information of memory cells MC1e and MC1o is read, and in tune information storage area 98b, storage information of memory cells MC2e and MC2o is read. Memory cells MC1e and MC2e constitute a twin cell, and memory cells MC1o and MC2o constitute a twin cell. Memory cells MC1e and MC1o store the same information, and memory cells MC2e and MC2o store the same information. Therefore, the tune information is read in the double twin cell mode, the internal read data RQ is generated by the PROM read circuit 106p, and the read internal read data RQ is transmitted to the tuning target circuit such as the normal read circuit 106n.

  FIG. 27 schematically shows a memory cell selection mode in writing 1-bit tune information to tune information storage areas 98a and 98b. In FIG. 27, also in writing tune information, word lines WLAe and WLAo are driven to the selected state in memory mat 90A, and word lines WLBe and WLBo are driven to the selected state also in memory mat 90B. In tune information storage areas 98a and 98b, bit lines BLA and BLB are selected and coupled to PROM data buses 104ap and 104bp, respectively. Source lines SLA and SLB of the selected column are coupled to mat APROM write circuit 108pa and mat BPROM write 108pb via source select driver SD, respectively.

  Matt APROM write circuit 108pa and mat BPROM write circuit 108pb generate complementary data according to external write data RD, as in the redundant data write to redundant data recording areas 96a and 96b. In the reverse direction, write currents Iw1 and Iw2 flow in tune information storage areas 98a and 98b, respectively. Thereby, the tune information can be written in the double twin cell mode.

  In the above description, the spin injection memory cell is described. However, data may be written to the memory cell by a bit line current induced magnetic field and a digit line (write word line) current induced magnetic field. Instead of the source line drive at the time of writing, a current is caused to flow from both sides of the bit line by the bit line driver. Further, a digit line may be used, and an assist magnetic field at the time of writing may be generated by a digit line current. During the write cycle, the digit line is selected in the same manner as the word line selection manner. Further, the writing of the tune information may be performed in the twin cell mode as in the case length data.

  FIG. 28 shows an exemplary configuration of row select drive circuits 100a and 100b of the semiconductor memory device according to the fourth embodiment of the present invention. Row selection drive circuits 100a and 100b differ from memory mats 90A and 90B only in the application manner of the most significant row address bits, and the internal configuration is the same. Therefore, in FIG. Row selection drive circuits 100a and 100b are shown.

  In FIG. 28, row selection drive circuit 100 includes an OR gate OG1 that receives PROM data access activation signal ENPROM and most significant row address bit RA <n>, a row address bit RA <n−1: 1>, and an OR gate. And a decoder 120 that performs a decoding operation in accordance with the output signal of OG1 to generate a row decode signal Xi.

  This PROM data access activation signal ENPROM is activated to access (read and write) data in PROM data areas 114a and 114b. One of memory mats 90A and 90B is designated by the most significant row address bit RA <n>. When memory mat 90A is designated when most significant row address bit RA <n> is “1”, complementary most significant address bit RA_B <n> is selected for the row selection drive circuit for memory mat 90B. Is given.

  Decoder 120 is composed of a normal NAND type decode circuit, for example, and performs decode operation of row address bits RA <n: 1> using the output signal of OR gate OG1 as the most significant row address bit to generate decode signal Xi To do.

  Row select drive circuit 100 further includes NOR gates NG10-NG13, AND gates AG5-AG7, and gate circuit GG1. NOR gate NG10 receives tune information read / write instruction signal PRWME and least significant row address bit RA <0>. NOR gate NG11 receives tune information write / read instruction signal PRWME and complementary least significant row address bit RA_B <0>. NOR gate NG12 receives an output signal of NOR gate NG10 and word line activation signal WLACN. NOR gate NG13 receives an output signal of NOR gate NG11 and word line activation signal WLACN. AND gate AG5 receives complementary row address bit RA_B <n> and word line activation signal WLACN. The AND gate AG6 receives the row decode signal Xi and the output signal of the NOR gate NG12 and drives the even word line WLEi. The AND gate AG7 receives the row decode signal Xi and the output signal of the NOR gate NG13, and drives the odd word line WLOi.

  Complementary most significant address bits RA <n> and RA_B <n> are applied to AND gate AG5 and OR gate OG1. Since the corresponding memory mat is designated according to the bit value of row address bit RA <n>, when the corresponding memory mat is designated when row address bit RA_B <n> is “1”. The AND gate AG5 is supplied with a row address bit RA <n> designating another memory mat.

  Gate circuit GG1 receives the output signal of AND gate AG5 and PROM data access activation signal ENROM, and selectively drives dummy word line DWL. Gate circuit GG1 operates as a buffer circuit when PROM data access activation signal ENPROM is inactive (at L level), and drives dummy word line DWL according to the output signal of AND gate AG5. On the other hand, when the PROM data access activation signal ENPROM is activated, the gate circuit GG1 always maintains the dummy word line DWL in a non-selected state. Therefore, at the time of PROM data access, dummy word line DWL is always kept in the non-selected state, and at the time of data access of normal data regions 112a and 112b, dummy word line DWL is driven to the selected state in the non-selected memory mat. The

  The configuration of the portion for selecting the word line of the row selection drive circuit shown in FIG. 28 is substantially equivalent to the configuration of the even / odd word line decoder and the word line drive circuit shown in FIG. 7 in the first embodiment. It is. When data is accessed in normal data areas 112a and 112b, PROM data access activation signal ENPROM and tune information write / read instruction signal PRWME are both inactive. Therefore, one of word lines WLEi and WLOi is designated according to row address bits RA <n: 0>. When no word line is designated in the corresponding memory mat, dummy word line DWL is driven to a selected state by AND gate AG5 and gate circuit GG1.

  On the other hand, when data is accessed in redundant data areas 96a and 96b, PROM access activation signal ENPROM is in an active state, most significant row address bit RA <n> is in a degenerated state, and the output signal of OR gate OG1 is The H level in the selected state. Therefore, in memory mats 90A and 90B, decoder 120 performs a decoding operation to generate row decode signal Xi. At this time, tune information write / read instruction signal PRWME is inactive, and one of even-numbered word line WLEi and odd-numbered word line WLOi is designated according to row address bits RA <0> and RA_BRA <0>. At this time, the PROM data access activation signal ENPROM is in an active state, and the gate circuit GG1 maintains the dummy word line DWL in a non-selected state. Thereby, in each of memory mats 90A and 90B, one word line is driven to a selected state.

  At the time of accessing the tune information, the PROM data access activation signal ENPROM is in the active state. Similarly to the redundant data access, the decoder 120 operates for each of the memory mats 90A and 90B, and the row decode signal Xi is the row address. It is generated according to bits RA <n-1: 1>. The dummy word line DWL is maintained in a non-selected state by the gate circuit GG1. At this time, tune information write / read instruction signal PRWME is activated, lowest-order row address bit RA <0> is degenerated, and the output signals of NOR gates NG10 and NG11 are both selected. In accordance with word line activation signal WLACN, both even word line WLEi and odd word line WLOi corresponding to the addressed row are driven to a selected state. Thereby, data access (write / read) of tune information can be performed in the double twin cell mode.

  By using the row selection drive circuit 100 shown in FIG. 28, a row selection drive circuit can be provided in common for an area for storing PROM data including redundant data and tune information and an area for storing normal data. An increase in the layout area of the circuit can be suppressed.

  FIG. 29 schematically shows an exemplary configuration of a portion related to data writing of the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 29 shows a configuration of a portion corresponding to one memory mat in order to avoid complication of the drawing. A write circuit shown in FIG. 29 is provided for each of memory mats 90A and 90B. PROM read circuit 106p and normal read circuit 106n are provided in common to memory mats 90A and 90B.

  In FIG. 29, as described above, the memory mat 90 (90A, 90B) is divided into the normal data area 112 (112a, 112b) and the PROM data area 114 (114a, 114b). For normal data region 112, normal column selection gate circuit 124n and normal source line drive circuit 128n are provided. For the PROM data area 114, a PROM column selection gate circuit 124p and a PROM source line drive circuit 128p are provided.

  A bit line decode circuit 122 is provided in common for column select gate circuits 124n and 124p, and a source line decode circuit 126 is provided in common for source line drive circuits 128n and 128p. Normal column selection gate circuit 124n includes normal column selection gates NCG0 to NCGj arranged corresponding to the bit lines included in normal data region 112, and PROM column selection gate circuit 124p includes each bit of PROM data region 114. PROM column selection gates PCG0 to PCGk arranged corresponding to the lines are included. A column selection signal from bit line decode circuit 122 is commonly applied to column selection gate circuits 124n and 124p.

  Bit line decode circuit 122 decodes column address bits CA <m: 0>, and generates a column selection signal designating a column in common to normal data area 112 and PROM data area 114. In column select gate circuits 124n and 124p, since the number of bit lines is different, the number of column select gates provided is also different. In FIG. 29, in order to clearly show that the column selection signal from the bit line decoding circuit 122 is commonly applied to the normal column selection gate circuit 124n and the PROM column selection gate circuit 124p, in the PROM data area 114, the bit line It is shown that all the column selection signals from the decode circuit 122 are given. Actually, a necessary number of column selection signals are used according to the number of bit lines in the PROM data area 114.

  Normal column selection gate circuit 124n couples the bit line of the selected column of normal data area 112 to normal data bus 104n, and PROM column selection gate circuit 124p connects the bit line of the selected column of PROM data area 114 to the PROM data bus. Binds to 104p.

  A source line selection signal from the source line decoding circuit 126 is applied in common to the normal source line driving circuit 128n and the PROM source line driving circuit 128p. When the write instruction signal WE is activated, the source line decode circuit 126 decodes the column address bits CA <m: 0>, enables the source line driver of the selected column, and the enabled source line driver The corresponding source line is driven according to the write data. That is, the normal source line drive circuit 128n is supplied with write data from the normal write circuit 108n, and the PROM source line drive circuit 128p is supplied with write data from the PROM write circuit 108p. Therefore, at the time of data writing, the source line driver arranged for the source line corresponding to the column designated by source line decoding circuit 126 drives the corresponding source line according to the write data.

  At this time, PROM write circuit 108p and normal write circuit 108n transmit write data to the bit line of the selected column via PROM data bus 104p and normal data bus 104n, respectively. At the time of writing data to PROM data area 114, normal write circuit 108n is inactive, and normal source line drive circuit 128n maintains the corresponding source line at the ground voltage level. On the other hand, the PROM write circuit 108p sets the voltage levels of the source line and the bit line in the selected column according to the write data via the PROM source line drive circuit 128p and the PROM column selection gate circuit 124p. Therefore, the column selection signal from bit line decode circuit 122 is commonly used for normal column selection gate circuit 124n and PROM column selection gate circuit 124p, and the column selection signal from source line decode circuit 126 is commonly used. Even if it is used for the source line driving circuit 128n and the PROM source line driving circuit 128p, no writing malfunction occurs.

  That is, when writing PROM data, in normal data region 112, the bit line is at the ground voltage level, and the source line is also maintained at the ground voltage level in common. Therefore, even if the word line is arranged in common in the normal data area 112 and the PROM data area 114, erroneous writing of PROM data to the normal data area 112 does not occur. Similarly, when data is written to normal data region 112, even if PROM write circuit 108p is inactive and column selection is performed for PROM data region 114, the voltage levels of the bit line and the source line are maintained. At the ground voltage level, normal data is not written to PROM data area 114.

  In the data read operation, PROM data bus 104p is coupled to PROM read circuit 106p, and normal data bus 104n is coupled to normal read circuit 106n. By these read circuits 106p and 106n, data is read according to the open bit line system. Also in this case, even if the PROM data bus 104p and the normal data bus 104n are provided separately, and the bit line decode circuit 122 is provided in common for the normal data area 112 and the PROM data area 114, the read data collision occurs. Therefore, the data of the memory cell to be accessed can be read accurately.

  30 is a diagram showing an example of the configuration of source line drivers included in normal source line drive circuit 128n and PROM source line drive circuit 128p shown in FIG. In FIG. 30, a source line driver 130 is an AND type driver that receives a column selection signal CSLi from the source line decode circuit 126 and internal write data WDin from the corresponding writing and drives the corresponding source line SLi. Composed. When column select signal CSLi and internal write data WDin are both at H level (“1”), corresponding source line SLi is driven to H level. When at least one of column selection signal CSLi and internal write data WDin is at L level, corresponding source line SLi is maintained at the ground voltage level. Source line decode circuit 126 is inactive at the time of data reading, and column selection signal CSLi is in an unselected state at L level. Therefore, corresponding source line SLi is maintained at the ground voltage level (L level) during data reading.

  At the time of data writing, internal write data is supplied from corresponding write circuits 108p and 108n. Therefore, even if column select signal CSLi is applied commonly to normal source line drive circuit 128n and PROM source line drive circuit 128p, internal write data WDin from the inactive write circuit is at L level. The corresponding source line is maintained at the ground voltage level. The voltage of the source line SLi of the selected column is set according to the internal write data WDin from the activated write circuit 108p or 108n.

  The PROM write circuit 108p and the normal write circuit 108n also have a configuration similar to the source line driver 130 of the source line drive circuit. When the corresponding write instruction is activated, complementary internal write data is generated in accordance with external write data and transmitted to the corresponding internal data bus and source line drive circuit. The bit line and source line of the selected column are driven according to complementary internal write data. Note that the PROM writing circuit generates internal write data complementary to memory mats 90A and 90B when writing PROM data. Normal write circuit 108n generates data of the same logic in memory mats 90A and 90B. In the non-selected memory mat, the word line is in a non-selected state during normal data writing, and data writing is prevented.

  PROM write circuit 108p is activated, for example, when PROM data access activation signal ENPROM and write instruction signal WE are activated, and normal write circuit 108n has PROM data access activation signal ENPROM deactivated. When write instruction signal WE is activated, it is activated to generate complementary internal write data in accordance with external write data. Write instruction signal WE is activated when normal data and PROM data are written.

  Note that in the above structure, the source line SL is disposed in parallel with the bit line BL. When source line SL is arranged in parallel with word line WL, the source line decoding circuit may be configured to perform the same decoding operation as the row selection drive circuit that selects the word line.

  FIG. 31 schematically shows a structure of control circuit 110 shown in FIG. In FIG. 31, the control circuit 110 generates signals for controlling various internal operations in accordance with a power-on detection signal POR from the power-on detection circuit 18 and a command CMD designating an external operation mode.

  In FIG. 31, a control circuit 110 includes a mode detection circuit 130 that detects a mode designated in accordance with a command CMD and a power-on detection signal POR, a timer 132 that is activated under the control of the mode detection circuit 130, and a timer 132. And an address counter 134 for counting oscillation signals from.

  The mode detection circuit 130 activates the PROM data activation signal ENPROM when the command CMD from the outside designates a mode in which redundant data or tune information is written or when the power-on detection signal POR is activated. Instruction signal WE and tune information writing instruction TM are activated. Mode detection circuit 130 selectively activates tune information write / read activation signal PRWEN according to count value CNT of address counter 134 when reading PROM data including redundant data and tune information. The timer 132 is composed of an oscillation circuit, and is activated by the mode detection circuit 130 when the power-on detection signal POR is activated, and performs an oscillation operation at a predetermined cycle.

  Address counter 134 counts clock signal from timer 132 or test clock signal TCLK supplied from an external tester at the time of PROM data writing, and count value CNT is assigned to row address bits RA <n: 0> and column address bits. CA <m: 0> is generated.

  Control circuit 110 further includes a word line control circuit 136, a bit line control circuit 138, and a source line control circuit 140 that control activation of the word line, the bit line, and the source line, respectively. These word line control circuit 136, bit line control circuit 138 and source line control circuit 140 are activated for a predetermined period at a predetermined timing according to the transition of count value CNT output from address counter 134 when writing and reading PROM data. A word line activation signal WLACN, a bit line activation signal (column selection activation signal) CACN, and a source line activation signal SACN that are in a state are generated.

  At the time of data access in the normal normal data area, the word line control circuit 136, the bit line control circuit 138, and the source line control circuit 140 are respectively in the respective access cycles under the control of the mode detection circuit 130 that receives the command CMD. At a predetermined timing, the word line activation signal WLACN, the bit line activation signal (column selection activation signal) CACN, and the source line activation signal SACN are activated.

  Control circuit 110 further includes a sense control circuit 142 that generates sense activation signal SAE and a write control circuit 144 that generates write activation signal WDACT. When write instruction signal WE from mode detection circuit 130 is inactivated, sense control circuit 142 activates sense activation signal SAE according to the timing of the word line activation signal output from word line control circuit 136. . Write control circuit 144 activates write activation signal WDACT at a predetermined timing in response to word line activation signal WLACN output from word line control circuit 136 when write instruction signal WE is activated. . Normal write circuit 108n and PROM write circuit 108p are activated in accordance with write activation signal WDACT from write control circuit 144 (however, in combination with tune information write instruction TM instructing PROM data write) According to). When the tune information write instruction TM is activated (asserted), the PROM write circuit 108p is activated according to the write activation signal, and when the tune information write instruction TM is inactivated, the normal write circuit 108n is activated. Activated. This tune information write instruction TM is activated when redundant data and tune information are written.

  In the configuration of control circuit 110 shown in FIG. 31, the activation period of tune information write / read activation signal PRWEN from mode detection circuit 130 is adjusted by the count value from address counter 134. Thus, data can be written / read in the twin cell mode when reading redundant data in the redundant data storage area, and can be written / read in the double twin cell mode when writing / reading tune information.

  In the configuration shown in FIG. 31, mode detection circuit 130 generates tune information write instruction TM according to command CMD. The tune information write instruction TM may be given from an external tester when writing PROM data.

  The redundant data storage area and the tune information storage area are provided with bit lines separately. In this case, first, a selected column is fixed, word lines are sequentially selected, a memory cell is selected, and one row of data / information is accessed. By repeating this access for each column, one of the tune information and redundant data is accessed and then the other data is accessed. By using this configuration, the tune information in the tune information storage area and the redundant data in the redundant data storage area can be distinguished by column addresses and accessed in the double twin cell mode and the twin cell mode, respectively. By using the higher-order count bits of the address counter 134 as column address bits CA <m: 0> and the lower-order count bits as row address bits RA <n: 0>, the columns are fixed and the word lines sequentially You can choose.

  As described above, according to the fourth embodiment of the present invention, in the MRAM, an area for storing tune information and redundant data is provided in the same memory array as that for storing normal data. Therefore, it is not necessary to transfer the tune information from the outside of the MRAM into the MRAM, and the tune information and redundant data can be set at an early timing after the power is turned on. Further, the PROM data storage cell and the normal data storage cell can be manufactured in the same manufacturing process, and the manufacturing process can be simplified.

  In the above-described configuration, the writing is performed in the double twin cell mode even when the tune information is written. However, the twin cell mode may be used when writing the tune information, and the double twin cell mode may be used only when reading the tune information.

[Modification 1]
FIG. 32 schematically shows a structure of a modification 1 of the semiconductor memory device according to the fourth embodiment of the present invention. 32 also shows a configuration for one memory mat in order to avoid complication of the drawing. In FIG. 32, memory mat 90 (90A, 90B) includes a normal data area 112 and a PROM data area 114, as in the configuration shown above. Normal data area 112 is divided into a plurality of normal memory blocks MB0-MBk. Internal data lines IO0-IOk are provided corresponding to normal memory blocks MB0-MBk, respectively. An internal data line IOp is provided for PROM data area 114, and this internal data line IOp is coupled to internal data line IOk. That is, internal data line IOk is provided in common for normal memory block MBk and PROM data area 114.

  Read / write circuits 150-0 to 150-k are provided corresponding to internal data lines IO0 to IOk, respectively. That is, normal memory blocks MB0-MBk correspond to so-called "IO blocks", each storing 1-bit data, and accessing (reading / writing) 1-bit data in parallel when a column is selected.

  Read / write circuits 150-0 to 150- (k-1) (not shown) are activated when PROM data access activation signal ENPROM is inactivated, and read or write data. On the other hand, read / write circuit 150-k executes read / write regardless of normal data and PROM data when data is accessed.

  In the configuration shown in FIG. 32, a column selection circuit (not shown) is provided in common in PROM data area 114 and normal data area 112, and writing / reading of PROM data and normal data is performed in a common read / write circuit. Can be used.

  FIG. 33 is a diagram more specifically showing a configuration of a main part of the semiconductor memory device shown in FIG. FIG. 33 representatively shows bit lines (normal bit lines) NBL0 to NBLk in memory blocks MB0 to MBk and bit lines (PROM bit lines) PBL in PROM data area 114, respectively.

  Corresponding to normal bit lines NBL0 to NBLk, column selection gates TG0 to TGk are provided, and column selection gate TGp is provided for PROM bit line PBL. Column select gates TG0 to TGk are commonly supplied with an output signal of gate circuit GG2 receiving column select signal CSLi and PROM data access activation signal ENPROM as a column select signal. On the other hand, for column select gate TGp, an output signal of AND gate AG10 receiving column select signal CSLi and PROM data access activation signal ENPROM is applied as a column select signal.

  Gate circuit GG2 maintains its output signal in a non-selected state when PROM data access activation signal ENPROM is activated, and generates an output signal in accordance with column selection signal CSLi when PROM data access activation signal ENPROM is inactive. To do. The AND gate AG10 generates an output signal according to the column selection signal CSLi when the PROM data access activation signal ENPROM is activated, and the output signal is not selected when the PROM data access activation signal ENPROM is deactivated. To maintain the column selection gate TGp in the off state.

  Although the column selection signal for the PROM data area 114 and the column selection signal for the normal data area 112 are commonly generated from a column selection signal generation circuit (not shown), the gate circuit GG2 and the AND circuit AG10 A block of the column selection gate to be turned on is designated.

  Read / write circuits 150-0 to 150- (k-1) are maintained in an inactive state when PROM data access activation signal ENPROM is activated. Read / write circuit 150-k performs read / write in the operation mode. Therefore, PROM data can be written / read and normal data can be written / read using read / write circuit 150-k.

  Output signals from gate circuit GG2 and AND gate AG10 are also applied as column selection signals to memory line MB0-MBk and source line drivers for driving source lines in PROM data area 114, respectively. The common source line for the source line in normal data region 112 and the source line in PROM data region 114 can be used for writing normal data and writing PROM data. As the configuration of the source line driver, the configuration shown in FIG. 30 can be used.

  As a circuit for generating each control signal, the configuration of the control circuit 110 shown in FIG. 31 can be used. Further, the distinction between redundant data and tuning data is performed according to the column address.

  In the arrangement shown in FIG. 33, the load on internal data line IOk is larger than those on other internal data lines IO0-IOk-1. In this case, a load capacitor for balancing the load may be connected to each of internal data lines IO0-IOk-1.

  In the case of the configuration of the first modification, it is required to arrange the gate circuit GG2 and the AND gate AG10 for each wiring that transmits the column selection signal CSLi. However, the column decoder that generates the column selection signal CSLi is a NAND decoder, and is configured to generate a final output column selection signal CSLi by inverting the NAND gate that decodes the column address and the output signal of the NAND gate. In this case, an area increase of the column selection signal generation unit is suppressed by using the following configuration. That is, a final output stage inverter is provided for each of normal data area 112 and PROM data area 114, and an inverted signal of PROM data access activation signal ENPROM and Supply a non-inverted signal.

  For example, when the normal data area 112 is accessed, the activation signal ENPROM is at L level and its inverted signal is at H level. Therefore, for the normal data area 112, a column selection signal is generated by the corresponding inverter, and for the PROM data area 114, the output signal of the corresponding inverter is fixed to the L level (the high field side of the inverter). And the low-side power supply voltage is ground voltage level). In this case, since the inverters in the non-selected column have an output high impedance with respect to the PROM data area, the reset transistors (turned on according to the inverted signal of the PROM access activation signal ENPROM) are output to the outputs of the inverters in the PROM data area 114 N channel MOS transistor) is arranged to fix the control electrodes of column select gates TGp0 to TGpk to the ground voltage level. Similarly, a reset transistor that is turned on in accordance with the PROM access activation signal ENPROM is arranged at the output of the final stage inverter that generates the column selection signal for the normal data area 112, and the column selection gate TG0 for the normal data area is accessed during PROM data access. -Maintain the control electrode of TGk at ground voltage.

  By using the above-described configuration, an increase in the size of the column selection signal generation circuit in the column direction is sufficiently suppressed, an increase in the area of the array peripheral circuit is suppressed, and normal data and PROM data of the row selection drive circuit are suppressed. The effect of suppressing the area increase due to the common use is sufficiently obtained.

[Modification 2]
FIG. 34 schematically shows a structure of a main portion of the semiconductor memory device according to the second modification of the fourth embodiment of the present invention. FIG. 34 also shows the configuration of the column selection unit of one memory mat, as in FIG. The configuration of the column selection unit shown in FIG. 34 is arranged for each memory mat.

  The configuration of the semiconductor memory device shown in FIG. 34 is different from the configuration of the semiconductor memory device shown in FIG. 33 in the following points. That is, in the PROM data area 114, column selection gates TGp0 to TGpk provided for (k + 1) bit lines PBL0 to PBLk are selectively turned on in accordance with an output signal of the AND gate AG10. Each of select gates TGp0-TGpk couples corresponding bit lines PBL0-PBLk to internal data lines IO0-IOk when conducting. Read / write circuits 150-0 to 150-k perform a sense operation or a write operation in accordance with a sense activation signal or a write activation signal, regardless of normal data and PROM data.

  The other configuration of the semiconductor memory device shown in FIG. 34 is the same as that of the semiconductor memory device shown in FIG. 33, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In the configuration shown in FIG. 34, (K + 1) -bit PROM data is read in parallel in each of read / write circuits 150-0 to 150-k even when PROM data is read. Therefore, reading and setting of redundant data and tune information after power-on can be performed at higher speed.

  Since internal data lines IO0-IOk are always coupled with the same number of bit line loads, internal data lines IO0-IOk can have the same load, and stable reading / writing can be performed. Can do.

  In the source line selection drive circuit, the same column selection signal generation system configuration as shown in FIG. 34 is used, and the same signal as the output signal of gate circuit GG2 or AND gate AG10 is supplied to the source line driver. Is provided as a source line selection signal.

  Further, as the configuration of the column selection signal generator, the configuration described in the first modification example can be used. In the case of parallel selection of a plurality of columns, there is a possibility that redundant data and tune data are read in parallel when reading PROM data. In order to avoid this state, for example, the following configuration can be used.

  The redundant data storage area and the tune information storage area are divided not by column addresses but by word line addresses. The column address is set according to the number of tune information and redundant data. An address counter is provided for each of the redundant data area and the tune information area. After turning on the power, first, in the double twin cell mode, the tune information is read according to the count of the tune information address counter. After all the tune information has been read, the redundant data is read in the twin cell mode according to the count value of the redundant data address counter. Alternatively, the address counter is arranged in common in the PROM area, and after turning on the power, sequentially reads both the tune information and the redundant data in the double twin cell mode. The tune information and the redundant data are distinguished by the word line address and the transfer path is switched, or simply transferred sequentially through the scan path and stored in the corresponding register.

  Therefore, if the arrangement of the tune information storage area and the redundant data storage area is appropriately set according to the number of words and the bit width of the redundant data and the number of words and the bit width of the tune information, the multi-bit tune information and the redundant data Data can be read and written accurately.

  As described above, according to the fourth embodiment of the present invention, the MRAM and the area for storing redundant data and tune information are arranged in the same memory mat, the layout area can be reduced, and the propagation of PROM data The route can be shortened. In addition, a row selection circuit can be used in common for normal data and PROM data, and an increase in layout area is suppressed.

  In addition, the write and read circuits can be used in common for normal data and PROM data, and an increase in the layout area of the peripheral circuit is suppressed.

  In general, the present invention is applied to a nonvolatile semiconductor memory device that reads data depending on the amount of current flowing through a memory cell that stores information in a nonvolatile manner. A highly reliable nonvolatile semiconductor memory device that can be reliably read can be realized. Accordingly, the memory cells are not limited to MRAM cells, and flash memory cells, resistive RAM (RRAM) cells, and phase change memory cells can be used.

1 schematically shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the invention. FIG. FIG. 2 schematically shows a memory cell connection mode at the time of reading tune information in the semiconductor memory device shown in FIG. 1. FIG. 3 is a diagram showing an example of an electrical equivalent circuit of the memory cell shown in FIGS. 1 and 2. FIG. 3 schematically shows a load on a bit line when a memory cell shown in FIG. 2 is selected. It is a figure which shows the electric current difference at the time of memory cell data read in double twin cell mode, twin cell mode, and normal mode. 1 schematically shows a configuration of a row selection drive circuit of a semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 7 is a diagram showing an example of a configuration of an odd / even word line decoder and a word line driving circuit shown in FIG. 6. FIG. 8 is a diagram showing a list of state transitions of the circuit shown in FIG. 7. FIG. 5 schematically shows a configuration of a control circuit of the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a timing diagram illustrating an operation of the control circuit illustrated in FIG. 9 when reading tune information. It is a figure which shows roughly an example of the structure of the transfer path | route of a tune information and the tuning object circuit in Embodiment 1 of this invention. It is a figure which shows an example of a structure of the memory cell of the semiconductor memory device according to Embodiment 2 of this invention. (A) and (B) are figures which show the magnetization direction at the time of the data writing of the memory cell shown in FIG. 12 with a memory cell structure. It is a figure which shows roughly the whole structure of the non-volatile semiconductor memory device according to Embodiment 2 of this invention. FIG. 11 schematically shows a selection mode of a memory cell at the time of data writing in a semiconductor memory device according to a second embodiment of the present invention. It is a figure which shows an example of the structure of the digit line decoder of the semiconductor memory device according to Embodiment 2 of this invention. It is a figure which shows an example of a structure of the control circuit of the semiconductor memory device according to Embodiment 2 of this invention. FIG. 18 is a timing chart showing an operation at the time of writing tune information of the control circuit shown in FIG. 17. It is a figure which shows an example of a structure of the semiconductor integrated circuit device containing the tune information storage unit according to Embodiment 3 of this invention. FIG. 14 schematically shows a structure of a main portion of a semiconductor memory device according to the fourth embodiment of the invention. FIG. 21 schematically shows arrangement of memory cells and connection of internal data lines in the semiconductor memory device shown in FIG. 20. FIG. 14 schematically shows a memory cell selection manner at the time of data reading in the normal mode of the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 14 schematically shows a memory cell selection manner at the time of data writing in a normal mode of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 14 schematically shows a memory cell selection manner at the time of reading redundant data in the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 14 schematically shows a memory cell selection mode in writing redundant data in a semiconductor memory device according to a fourth embodiment of the present invention. It is a figure which shows roughly the memory cell selection aspect at the time of the tune information read of the semiconductor memory device according to Embodiment 4 of this invention. It is a figure which shows roughly the memory cell selection aspect at the time of the tune information writing of the semiconductor memory device according to Embodiment 4 of this invention. FIG. 25 is a diagram showing an example of a configuration of a row selection drive circuit shown in FIG. 24. It is a figure which shows more specifically the structure of the principal part of the semiconductor memory device according to Embodiment 4 of this invention. FIG. 30 is a diagram illustrating an example of a configuration of a source line driver of the source line driving circuit illustrated in FIG. 29. It is a figure which shows roughly an example of a structure of the control circuit of the semiconductor memory device according to Embodiment 4 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to the modification 1 of Embodiment 4 of this invention. FIG. 33 is a diagram more specifically showing a connection mode of internal data lines of the semiconductor memory device shown in FIG. 32. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to the modification 2 of Embodiment 4 of this invention.

Explanation of symbols

  1, 1a, 1b memory array, 2, 2a, 2b row selection drive circuit, 3a, 3b column selection signal generation circuit, 4a, 4b column selection gate circuit, 5 readout circuit, 6 control circuit, 10 row decoder, 12 odd-even word Line decoder, 14 word line drive circuit, 18 power-on detection circuit, 30 tune information storage unit, 32 tuning target unit, 40a, 40b memory array, 41a, 41b word line selection drive circuit, 42a, 42b data line selection drive circuit, 43a, 43b column selection signal generation circuit, 45a, 45ab, 45ba, 45bb bit line drive circuit, 46 read circuit, 47 data input circuit, 48a, 48b write data generation circuit, 49 control circuit, 70 semiconductor integrated circuit device, 72 Processor, 74 MRAM module, 80 MRAM, 82 Chu Unit information storage unit, 84 power-on detection circuit, 86 test interface, 90A, 90B memory mat, 92a, 92b memory array, 94a, 94b redundant cell array, 96a, 96b redundant data storage area, 98a, 98b tune information storage area, 100a, 100b Row selection drive circuit, 102a, 102b Column selection circuit, 104a, 104b Internal data bus, 106 Read circuit, 108 Write circuit, 110 Control circuit, 112a, 112b, 112 Normal data area, 114a, 114b, 114 PROM Data area, 104an, 104bm normal data bus, 104ap, 104bp PROM data bus, 108pa mat APROM writing circuit, 108pb mat BPROM writing circuit, 120 decoder, 1 22 bit line decode circuit, 124 normal column select gate circuit, 124p PROM column select gate circuit, 126 source line decode circuit, 128n normal source line drive circuit, 128p PROM source line drive circuit, 150-0 to 150-k read / write TG0-TGk column selection gate, GG2 gate circuit, AG10 AND gate.

Claims (6)

A plurality of memory cells arranged in a matrix, wherein the plurality of memory cells are grouped into a plurality of twin cells each having first and second memory cells storing complementary data;
A plurality of word lines arranged corresponding to each memory cell row and connected to the memory cells in the corresponding row,
A plurality of bit lines arranged corresponding to each memory cell column and connected to memory cells in each corresponding column, and a word line addressed from the plurality of word lines according to a row address signal at least in a data read cycle The row selection drive circuit includes a plurality of word lines so that the first and second memory cells of the twin cell are selected in parallel in the first operation mode. The first number of word lines are selected and more second word lines than the first number are selected in parallel in the second operation mode and more than in the first operation mode. Select twin cells in parallel, the twin cells selected in parallel store the same data,
A column selection circuit for selecting a bit line corresponding to a column addressed in accordance with a column address signal, wherein the first transistor of the selected twin cell is connected to the first bit line, and the second transistor is a first transistor; Connected to two bit lines, the column selection circuit selects the first and second bit lines in parallel,
A semiconductor device comprising: an internal read circuit that detects storage information of a selected twin cell and generates internal read data in accordance with a signal of a bit line selected by the column selection circuit. The plurality of memory cells are arranged divided into first and second memory arrays,
A first memory cell of each of the twin cells is disposed in the first memory array, a second memory cell is disposed in the second memory array,
The first bit line is arranged in the first memory array corresponding to each column of the first memory cells, and the second bit line corresponds to each column of the second memory cells. Arranged in the second memory array,
The row selection drive circuit is arranged corresponding to each of the first and second memory arrays, and at least in the second operation mode, a plurality of word lines are parallel to each of the first and second memory arrays. To the selected state,
The semiconductor device according to claim 1, wherein the column selection circuit selects the first and second bit lines in parallel in the first and second memory arrays, respectively. Each of the memory cells is a memory cell including a variable magnetoresistive element whose magnetization state is set according to stored data,
The semiconductor device further includes:
A plurality of digit lines arranged corresponding to each of the memory cell rows;
In the write cycle of the first operation mode, the digit line arranged corresponding to the row addressed according to the address signal is selected to supply the digit line current, and the write in the second operation mode A digit line selection driving circuit for supplying a digit line current by selecting a larger number of digit lines in parallel during the cycle than in the first operation mode, and a magnetic field induced by the digit line current The semiconductor device according to claim 1, wherein the semiconductor device is supplied to a variable magnetoresistive element of a memory cell in a row. The plurality of memory cells are arranged divided into first and second memory arrays,
A first memory cell of each of the twin cells is disposed in the first memory array, a second memory cell is disposed in the second memory array,
The digit line selection drive circuit drives a plurality of digit lines in a selected state in parallel in each of the first and second memory arrays during a write cycle in the second operation mode. Semiconductor device. The plurality of memory cells store tune information for adjusting circuit operating characteristics;
The semiconductor device according to claim 1, wherein the semiconductor device is arranged in a region different from a circuit to be tuned whose operating characteristics are adjusted according to the tune information. The plurality of memory cells store tune information for adjusting circuit operating characteristics;
The semiconductor device further includes:
A plurality of normal cells arranged in the same mat in alignment with the plurality of memory cells and having the same configuration as the memory cells for storing data;
5. The circuit according to claim 1, further comprising a selection / write / read system circuit that includes a circuit whose operation characteristics are adjusted in accordance with the tune information and selects the normal cell to write / read data. Semiconductor device.

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