JP5002352B2 - Semiconductor integrated circuit placement and routing method and semiconductor integrated circuit placement and routing support program - Google Patents

Description

  In the present invention, a plurality of output gate circuits (for example, clock gate circuits) are arranged in a timing tree path (for example, clock tree path) for supplying a timing signal (for example, clock signal) to a synchronization circuit (for example, clock synchronization circuit). A placement and routing method for performing placement and routing processing on the gate circuit of a semiconductor integrated circuit, and also a placement and routing support program for supporting the placement and routing processing by executing it using a computer device, for example, EWS (Engineering Work Station) The present invention relates to a technique that is effective when applied to a DA (design automation) tool that uses a).

  Power consumption by the clock synchronization circuit that stops operation by arranging multiple clock gate circuits in the clock tree path for supplying the clock signal to the clock synchronization circuit and selectively suppressing the clock output operation of the clock gate circuit Can be reduced. When a clock gate circuit is interposed in the clock tree path, the delay due to the clock synchronization circuit must be taken into account in the timing verification of the clock synchronization circuit. Patent Document 1 describes a technique for calculating a setup condition between a clock input terminal and a clock enable signal terminal of a clock gating cell corresponding to a clock gate circuit based on delay prediction information. Patent Document 2 describes a technique in which a timing analysis register is connected to a gated clock cell so that the timing analysis of the gated clock cell corresponding to the clock gate circuit can be performed using a static timing analysis tool. The

JP 2006-201825 A JP 2007-4695 A

  When a BIST (built-in self test) circuit for detecting a failure in an asynchronous signal transmission path is provided, it is desirable to add the clock enable signal transmission path of the clock gate circuit to the failure detection target by the BIST. it is conceivable that. That is, the clock gate circuit has a test terminal for transmitting a clock enable signal input for clock output control to the failure detection path of the asynchronous signal path. A plurality of asynchronous signals transmitted to the failure detection path of the asynchronous signal path are input to a corresponding exclusive OR gate (EXOR) and converted into a failure detection sample signal, and the converted failure detection sample signal is scanned. It can be read out externally via a campus scan latch.

  The clock skew of the clock signal output from each of the clock gate circuits must be within an allowable range. Therefore, for a clock gate circuit having too many clock synchronization circuits commonly connected to the clock output terminal of the clock gate circuit, a plurality of the clock gate circuits are multiplexed to obtain one clock gate circuit. It is necessary to reduce the driving load. Conversely, for a clock gate circuit in which the number of clock synchronization circuits connected in common to the clock output terminals of the clock gate circuit is too small, a plurality of such clock gate circuits are integrated to provide one clock gate. It is necessary to increase the driving load of the circuit.

  However, when multiplexing or integrating the clock gate circuits, the signal lines connected to the test terminals of the clock gate circuits that have been abolished by the integration are floating, and the failure detection logic based on the corresponding failure detection sample signal is maintained. Can not do. If the test terminal of the clock gate circuit added by multiplexing is left floating, the failure detection rate decreases, and if it is forcibly connected to other exclusive OR gates, etc., the failure detection equivalence can be maintained. become unable. When the test terminal of the clock gate circuit added by multiplexing is connected to the same connection destination as the test terminal of the clock gate circuit before multiplexing, the asynchronous signal path is broken to the multiple clock gate circuits related to multiplexing. It becomes impossible to recognize, and the failure detection rate decreases. These problems are not limited to the propagation path of the clock signal, but apply widely to all timing signals propagated through the tree circuit.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for arranging and wiring a semiconductor integrated circuit in which a failure detection rate in an asynchronous signal path is not lowered and a failure detection logic is not changed by multiplexing and integration of output gate circuits such as clock gate circuits. There is.

  Another object of the present invention is to easily realize a placement and routing method in which the failure detection rate in the asynchronous signal path is not lowered and the failure detection logic is not changed by multiplexing and integration of output gate circuits such as clock gate circuits. An object of the present invention is to provide a placement and routing support program that can be used.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, when a plurality of clock gate circuits are arranged in the clock tree path, it is determined whether the clock gate circuits are multiplexed or integrated in order to keep the skew of the clock signal output from the clock gate circuit within an allowable range. When the integration is performed, a circuit element that connects the input terminal of the clock enable signal of the clock gate circuit to the failure detection path is arranged instead of the clock gate circuit that is abolished by the integration. When the multiplexing is performed, a new scan latch is allocated and connected to the clock gate circuit added by multiplexing.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to prevent the failure detection rate in the asynchronous signal path from being lowered and the failure detection logic from being changed even by multiplexing and integration of the output gate circuits.

  By arranging and integrating the output gate circuits, it is possible to easily realize a placement and routing method in which the failure detection rate in the asynchronous signal path is not lowered and the failure detection logic is not changed.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A placement and routing method for the semiconductor integrated circuit (1) includes a plurality of timing tree paths (for example, clock tree paths) for supplying a timing signal (for example, clock signal CLKJ) to a synchronization circuit (for example, clock synchronization circuit SQNC). This is a method of performing placement and routing processing on the clock gate circuit of a semiconductor integrated circuit in which an output gate circuit (for example, clock gate circuit CGC) is placed. The semiconductor integrated circuit generates and generates a failure detection sample signal for detecting a failure in the asynchronous signal path of the semiconductor integrated circuit based on one or more asynchronous signals transmitted to the failure detection path of the asynchronous signal path. The failure detection sample signal is supplied to the scan latch (SLAT) of the scan path so that it can be read out to the outside. The clock gate circuit has a test terminal (Tscn) for transmitting a clock enable signal (CEN) input for clock output control to a failure detection path of the asynchronous signal path. In this placement and routing method, the placement and routing process uses a computer device to determine whether to multiplex or integrate the clock gate circuit in order to keep the skew of the clock signal output from the clock gate circuit within an allowable range, In addition, a process for multiplexing or integrating the clock gate circuits according to the determination result is included. In the integration process, a circuit element (3) for connecting from the input terminal of the clock enable signal of the clock gate circuit to the test terminal is arranged instead of the clock gate circuit (CGC2) to be abolished by the integration. including. The multiplexing process includes a process of assigning a scan latch to the test terminal of the clock gate circuit added by multiplexing.

  According to the above means, instead of the clock gate circuit to be abolished by the integration, a circuit element that connects the input terminal of the clock enable signal of the clock gate circuit to the test terminal is arranged, so that it has been abolished by the integration. The signal line to which the test terminal of the clock gate circuit was connected does not float, and the failure detection logic based on the corresponding failure detection sample signal can be maintained. Also, since a new scan latch is allocated and connected to the test terminal of the clock gate circuit added by multiplexing, the test terminal of the clock gate circuit added by multiplexing is not left floating, and the failure detection rate decreases. do not do. Since the test terminal of the multiplexed clock gate circuit is not connected to the same connection destination as the test terminal of the clock gate circuit before multiplexing, a failure that occurs in the asynchronous signal path to the multiple clock gate circuits related to multiplexing Cannot be recognized, and a decrease in failure detection rate can be suppressed in this respect.

  The integration process includes, for example, a process of connecting a clock synchronization circuit connected to an output of a clock gate circuit to be abolished by integration to an output of a clock gate circuit remaining by integration.

  The multiplexing process includes, for example, a process of connecting a part of the clock synchronization circuit connected to the output of the clock gate circuit before multiplexing to the output of the clock gate circuit added by multiplexing.

  The process of arranging the circuit elements is, for example, a process of arranging a wiring and a process of arranging a buffer circuit (BUF) that secures a delay time as necessary.

  The process of allocating and connecting the scan latch is a process of allocating the spare scan latch when there is a spare scan latch prepared in advance and allocating a newly added scan latch when there is no spare scan latch. When it is intended to reduce the number of redesigns of the test as much as possible according to the result of the placement and routing, a preliminary scan latch is usually prepared, and the former is taken into consideration. Furthermore, by using a preliminarily arranged spare scan latch, the configuration of the scan path is not changed and the test cost is not increased.

  [2] A placement and routing support program for a semiconductor integrated circuit is executed by using a computer device, whereby a timing tree path (for example, a clock) for supplying a timing signal (for example, a clock signal) to a synchronization circuit (for example, a clock synchronization circuit) This is for supporting the placement and routing process for the clock gate circuit of a semiconductor integrated circuit in which a plurality of output gate circuits (for example, clock gate circuits) are arranged on the tree path. The semiconductor integrated circuit generates and generates a failure detection sample signal for detecting a failure in the asynchronous signal path of the semiconductor integrated circuit based on one or more asynchronous signals transmitted to the failure detection path of the asynchronous signal path. The failure detection sample signal is provided to the scan latch of the scan path so that it can be read out to the outside. The clock gate circuit has a test terminal for transmitting a clock enable signal input for clock output control to a failure detection path of the asynchronous signal path. In this place-and-route support program, the place-and-route processing uses a computer device to determine whether the clock gate circuit is multiplexed or integrated in order to keep the skew of the clock signal output from the clock gate circuit within an allowable range. And processing for multiplexing or integrating the clock gate circuits according to the determination result. The process of performing the integration includes a process of arranging a circuit element that connects the input terminal of the clock enable signal of the clock gate circuit to the test terminal in place of the clock gate circuit that is abolished by the integration. The multiplexing process includes a process of assigning a scan latch to the test terminal of the clock gate circuit added by multiplexing.

  By executing this place-and-route support program on a computer device, the place-and-route method that does not reduce the failure detection rate in the asynchronous signal path due to multiplexing and integration of the clock gate circuits and does not change the failure detection logic is easily realized. Can be possible.

2. Details of Embodiments Embodiments will be further described in detail.

<< Clock tree circuit of semiconductor integrated circuit >>
FIG. 3 illustrates a clock tree circuit of a semiconductor integrated circuit. The semiconductor integrated circuit 1 has a clock pulse generator (CPG) 2. The clock tree circuit constitutes a clock path for transmitting the clock signal generated by the clock pulse generator 2 to the clock synchronization circuit SQNC. The clock tree circuit shown in the figure has representatively shown clock transmission paths CK_PAS1 to CK_PAS4 for transmitting a clock signal generated by the clock pulse generator 2, and is shown representatively in the middle. Clock gate circuits CGC1 to CGC6 are provided, and clock signals output from the clock gate circuits CGC1 to CGC6 are supplied to the corresponding clock synchronization circuits SQNC. A clock buffer (not shown) is arranged in the middle of the clock transmission path represented by CK_PAS1 to CK_PAS4. The clock gate circuits represented by CGC1 to CGC6 are circuit cells that can select the supply of clocks to a plurality of corresponding clock synchronization circuits SQNC, and by stopping the clock supply to the clock synchronization circuits that are not operating. Realize low power consumption.

  Here, the plurality of clock synchronization circuits SQNC are synchronization circuits operated in synchronization with each other. Therefore, the clock skew (phase shift) of the clock signal supplied to the clock synchronization circuit SQNC by the clock tree circuit must be within a predetermined allowable range. This is to satisfy the setup and hold timing of the data transmission system in which the latch circuit and the flip-flop are arranged. The clock synchronization circuit SQNC has a latch circuit and a flip-flop that are operated in synchronization with a corresponding clock signal.

  In the layout design of the semiconductor integrated circuit 1, the arrangement of the clock gate circuit in the clock tree circuit may have to be changed. This is because when the automatic layout is performed according to the logical design, a difference exceeding the allowable range may occur in the driving load of the clock synchronization circuit by one clock gate circuit. For example, in the first layout LYOT1 of the semiconductor integrated circuit 1, when the clock gate circuits CGC1 and CGC2 drive two clock synchronization circuits SQNC, the clock gate circuit CGC3 must drive eight clock synchronization circuits SQNC. . Here, for the sake of simplicity, the description will be given assuming that the clock input loads of the individual clock synchronization circuits FF are equal.

  In order to eliminate the unbalance, the clock gate circuit is multiplexed or integrated using a layout tool. The second layout LYOT2 in FIG. 3 shows the result of multiplexing and integrating the clock gate circuit with respect to the first layout RYOT1. In the second layout LYOT2, the clock gate circuit CGC2 is integrated with the clock gate circuit CGC1, and the clock gate circuit CGC3 is multiplexed with the clock gate circuit 3 and the clock gate circuit CGC3_m. The integrated clock gate circuit CGC1 and the multiplexed clock gate circuits CGC3 and CGC3_m each drive four clock synchronization circuits.

  FIG. 4 illustrates a failure detection path for a clock gate circuit and an asynchronous signal. A clock gate circuit CGC representing CGC1 to CGC6 is supplied with a clock enable signal CEN and a test signal SMC for clock output control together with a clock signal CLK, and has an OR gate OR1, a latch circuit LAT1, and an AND gate AND1. The logical sum signal of the clock enable signal CEN and the test signal SMC is latched by the latch circuit LAT1 in synchronization with the clock signal CLK. When the latched value is the logical value 1, the clock signal CLK is transferred from the AND gate AND1 as the clock signal GCLK. Is output. The enable levels of the clock enable signal CEN and the test signal SMC are both logical values 1. The clock gate circuit CGC has a test terminal Tscn that outputs the input clock enable signal CEN to the failure detection path of the asynchronous signal path. An output signal (test output signal) of the test terminal Tscn is given an OBS reference symbol.

  The asynchronous signal path means a signal path of an asynchronous signal such as an enable signal or a strobe signal. For example, in the case of FIG. 4, the clock enable signal CEN is a signal path transmitted to the input terminal of the OR gate OR1. For example, AND gates AND2 and AND3 and an exclusive OR gate EXOR1 are provided as failure detection paths of the asynchronous signal path. Other asynchronous signals are input to the AND gates AND2 and AND3, and the exclusive OR gate EXOR1 receiving the outputs of the AND gates AND1 and AND generates a failure detection sample signal SMPL corresponding to the input signal. FIG. 4 representatively shows scan latches SLAT1 and SLAT2 included in the scan path SPAS. The failure detection sample signal SMPL is latched in the scan latch SLAT1 in synchronization with the scan clock SCLK in the BIST (built-in self test) operation of the semiconductor integrated circuit 1, and is shifted and transferred. The failure detection path is not limited to an AND gate and an exclusive OR gate for inputting a plurality of test output signals, and may be another logic circuit or a simple signal wiring. The reason for using a logic circuit that inputs a plurality of test output signals is to consolidate the states of the plurality of test output signals into one failure detection sample signal.

<< Integration of clock gate circuit (Declone) >>
Of the clock gate circuit integration (DCLN: declone) and multiplexing (CLN: clone) processes described with reference to FIG. 3, the clock gate circuit integration process will be described first.

  FIG. 1 illustrates a clock gate circuit integration processing method. FIG. 1 illustrates a case where the clock gate circuit CGC2 is integrated with the clock gate circuit CGC1. Before the integration, the failure detection path of the clock gate circuit CGC1 is exemplified by AND gates ANDi and ANDi + 1 and an exclusive OR gate EXORi as described in FIG. The output of the exclusive OR gate EXORi is connected to the scan latch SLATi of the scan path. The failure detection path of the clock gate circuit CGC2 is exemplified by the AND gate ANDj and the exclusive OR gate EXORj as described in FIG. The output of the exclusive OR gate EXORj is connected to the scan latch SLATj of the scan path. The scan latches SLATi and SLATj are connected in series.

  The integration process is performed by causing a computer device such as an engineering work station to execute a placement and routing support program. First, it is determined whether or not a plurality of clock gate circuits arranged in the clock tree circuit in the initial placement and routing process are to be integrated (S1). For example, in the clock tree circuit, in order to keep the clock skew of the clock signal output from each clock gate circuit within the allowable range, the clock gate circuit whose clock skew is smaller than the lower limit of the allowable range, that is, the advance of the clock phase is large. The clock gate circuit that passes is targeted for integration. Such a determination is made by determining whether or not the skew of the clock signal OBS is smaller than the lower limit threshold value of the allowable value. Here, the clock gate circuits CGC1 and CGC2 are designated as integration targets.

  A process of connecting the clock synchronization circuit 2 connected to the clock gate circuit CGC2 to be deleted by integration among the clock gate circuits to be integrated to the output terminal of the clock signal GCLK of the clock gate circuit CGC1 remaining by the integration is performed. Performed (S2). Thereafter, the clock gate circuit CGC2 is deleted from the clock tree circuit (S3), and instead of the deleted clock gate circuit CGC2, the clock enable signal input terminal of the clock gate circuit CGC2 is connected to its test terminal Tscn. Processing for arranging the circuit element 3 to be performed is performed (S4). The process S4 for arranging the circuit element 3 is a process for arranging a wiring, and a process for arranging a buffer circuit for securing a delay time if necessary. In the example of FIG. 1, a wiring and a buffer BUF are arranged as circuit elements. The delay time of the buffer BUDF is the propagation delay time of the clock enable signal CEN in the abandoned clock gate circuit CGC2.

  FIG. 5 shows a state before and after the integration processing according to FIG. BFR_DCLN indicates a state before the integration process, and AFT_DCLN indicates a state after the integration process. A circuit element 3 including a wiring and a buffer BUF is disposed at the original position of the clock gate circuit CGC2 that has been abolished by the integration. FIG. 6 shows a state BFR_DCLN before integration and a state AFT_DCLNflt after integration when the circuit element 3 is not replaced. When the replacement by the circuit element 3 is not performed, as shown in FIG. 6, the input Tj of the AND gate ANDj to which the output terminal of the clock signal GCLK of the abolished clock gate circuit CGC2 was originally connected is made floating. . Then, the generation logic of the failure detection sample signal SMPL output from the exclusive OR gate EXORj in the state AFT_DCLNflt in FIG. 6 is the failure detection sample signal output from the exclusive OR gate EXORj in the state AFT_DCLN in FIG. Therefore, the failure detection logic from the exclusive OR gate EXORj cannot be maintained. As a result, the test data that can be sampled via the scan path will differ, so it will be necessary to modify or change the test program or test evaluation program for testing asynchronous signals, which will increase test design costs. . If the circuit element 3 is inserted as in the state AFT_DCLN in FIG. 5, no modification or change of the test program or the test evaluation program is required.

  FIG. 7 shows another example of integration. Here, the clock gate circuit CGC2A is integrated with the clock gate circuit CGC1A. At this time, the AND gate ANDn and the exclusive OR gate EXORn arranged in the failure detection path indicated by 4 are degenerated and replaced with simple wiring. Whether or not degeneration can be performed is determined by other signals input to the AND gate ANDn and the exclusive OR gate EXORn, and if the logical configuration is such that the output of the exclusive OR gate EXORn is the same as the clock enable signal CEN, Degeneration is possible. Thus, the AND gate ANDn and the exclusive OR gate EXORn are originally unnecessary, and are determined at the time of integration. As a result, after integration, the output of the buffer BUF of the circuit element 3 substituting for the clock gate circuit CGC4 is directly connected to the data input terminal of the corresponding scan latch SLATn.

  FIG. 8 shows another example of a circuit element that replaces the clock gate circuit by the integration process. For example, one example of the integration result by the integration process is shown in FIG. This corresponds to the result of integrating the clock gate circuit CGC2A of FIG. 7 into the clock gate circuit CGC1A. In the integration process, the buffer BUF can be omitted as illustrated in (B), and a logic gate such as an AND gate ANDx can be interposed instead of the buffer BUF as illustrated in (C). is there. The example of (B) means a case where the necessary delay time can be covered by the wiring delay. (C) means that when the test signal SMC is supplied to the other input terminal of the AND gate ANDm in FIG. 7, the degeneration is possible with the AND gate ANDn being left, and at that time, by the buffer. Since the delay is comparable to the operation delay of the AND gate ANDn, the buffer BUF is omitted.

<< Multiplication of clock gate circuit (clone) >>
FIG. 2 illustrates a multiplexing process method of the clock gate circuit. FIG. 2 illustrates a case where the clock gate circuit CGC3 is multiplexed with the clock gate circuits CGC3 and CGC_m. Prior to multiplexing, the AND gate ANDk and the exclusive OR gate EXORk are exemplified in the failure detection path of the clock gate circuit CGC3 as described with reference to FIG. The output of the exclusive OR gate EXORk is connected to the scan latch SLATk of the scan path.

  The multiplexing process is performed by causing a computer device such as an engineering work station to execute a placement and routing support program. First, it is determined whether or not a plurality of clock gate circuits arranged in the clock tree circuit in the initial placement and routing process are to be multiplexed (S11). For example, in order to keep the clock skew of the clock signal output from each clock gate circuit in the clock tree circuit within the allowable range, the clock gate circuit in which the clock skew is larger than the upper limit of the allowable range, that is, the clock phase delay is large. Overclocking clock gate circuits are subject to additional processing. Such a determination is made by determining whether or not the skew of the clock signal GCLK is larger than the upper limit threshold value of the allowable value. Here, it is assumed that the clock gate circuit CGC3 is designated as a target of the multiplexing process.

  Next, it is determined whether or not a spare scan latch that can be used for the clock gate circuit added by multiplexing has already been laid out (S12). In order to reduce the test cost by suppressing the configuration change of the scan path for BIST as much as possible, it is generally performed in advance to arrange a large number of spare scan latches. If there is such a pre-scan latch, it can be used. A buffer BUFspr corresponding to the propagation delay time of the clock enable signal path of the clock gate circuit CGC3 is attached to the preliminary scan latch. If there is no preliminary scan latch, a scan latch for connecting to the clock gate circuit added by multiplexing and a buffer BUFspr are added to the layout (S13). In FIG. 2, SLATk + 1 means a scan latch previously arranged or added. Thereafter, the buffer BUFspr is replaced with a new clock gate circuit CGC3_m (S14). Then, of the four synchronization circuits SQNC that receive the clock signal GCLK from the clock gate circuit CGC3 before multiplexing, two motive circuits SQNC are connected to the output terminal of the clock signal GCLK of the clock gate circuit CGC3_m (S15). The buffer BUFspr is positioned as a seed of a clock gate circuit to be added by multiplexing, in other words, a seed of a clone.

  FIG. 9 shows a state before and after the multiplexing process shown in FIG. BFR_CLN indicates a state before the multiplexing process, and AFT_CLN indicates a state after the multiplexing process. In this example, a spare scan latch laid out in advance is used for multiplexing. The scan latch SLAT [3_m] k + 1 is assigned to the clock gate circuit CGC3_m added by multiplexing. When the scan latch is not assigned to the clock gate circuit added by multiplexing, the test terminal Tscan of the clock gate circuit CGC3_m added by multiplexing is made floating as shown in the state AFT_CLNflt of FIG. The As a result, failure detection in the transmission path of the clock enable signal CEN in the multiplexed clock gate circuit CGC3_m cannot be performed. If the scan latch SLATk + 1 is assigned as indicated by the state AFT_CLN in FIG. 9, no correction or change of the test program or the test evaluation program is required, and the failure detection rate does not decrease. Furthermore, by using a preliminarily arranged spare scan latch, the scan path configuration is not changed and the test cost is not increased. In addition, since the test terminal Tscn of the clock gate circuit CGC3_m added by multiplexing is not connected to the same connection destination as the test terminal Tscn of the clock gate circuit CGC3 before multiplexing, a plurality of clock gate circuits related to multiplexing In this respect, it is possible to suppress a decrease in the failure detection rate. In short, if the same signal is input to the same exclusive OR gate, it cannot be determined from the output of the exclusive OR gate even if the logical value of the signal violates the expected value.

  FIG. 11 shows another example of multiplexing. The new scan latch assigned to the clock gate circuit added by multiplexing is not limited to the spare scan latch or the new scan latch described above. As exemplified in FIG. 11, it is possible to couple to the input terminal of the gate circuit GAT circuit arranged in the failure detection path of other asynchronous signals, and the existing scan latch SLATx is assigned.

《Layout design flow》
FIG. 12 illustrates a processing flow of the overall layout design of the semiconductor integrated circuit. Layout design includes creation of a floor plan (S21), optimization before placement according to the floor plan (S22), placement processing after optimization (S23), optimization after placement (S24), and generation of a clock tree. This is performed by processing (S25), optimization after clock tree generation (S26), wiring processing of arranged circuit elements (S27), and optimization processing after wiring (S28).

  The clock tree generation process (S25) includes the integration process and the multiplexing process described with reference to FIGS. Both processes can be summarized in steps S31 to S36. In step S31, it is determined whether or not the clock signal skew value satisfies the allowable range in the clock tree, and this corresponds to step S1 in FIG. 1 and step S11 in FIG. For the clock gate circuit related to the excessive advance of the clock signal phase, the clock gate circuit for the declones is integrated (S36). This processing corresponds to S2 to S4 in FIG. For the clock gate circuit related to the excessive delay of the clock signal phase, it is first determined whether there is a clone seed (S32). If there is no clone seed, the clone seed is added (S33). Multiplexing is performed (S34), and if there is a seed, the clock gate circuit for the clone is multiplexed using it (S34).

  Step S32 corresponds to step S12 in FIG. 2, S33 corresponds to S13 in FIG. 2, and S34 corresponds to S14 in FIG. Thereafter, reconfiguration of the clock tree and deletion of redundant logic are performed (S35), and the process returns to step S31 to make a determination on another clock gate circuit.

  The placement and routing support processing program for realizing the clock tree generation processing and the like is loaded into a memory or an auxiliary storage device of a computer device such as EWS, and the computer device executes the program. Such a placement and routing support processing program is used as a placement and routing tool.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the logic configuration is not limited to that in FIG. 3 and can be changed as appropriate for the configuration of the clock synchronization circuit and the failure detection path of the asynchronous signal path. Further, the circuit elements to be inserted in the integration process are not limited to wiring, buffers, and AND gates, and can be changed as appropriate. The clock synchronization circuit can be expanded to a synchronization circuit, the clock signal to a timing signal, the clock tree path to a timing tree path, and the clock gate circuit to an output gate circuit. In short, the present invention can be applied not only to a clock transmission system but also to other timing signal transmission systems.

It is explanatory drawing which illustrates the integrated processing method of a clock gate circuit. It is explanatory drawing which illustrates the multiplexing processing method of a clock gate circuit. It is explanatory drawing which illustrates the clock tree circuit of a semiconductor integrated circuit. It is a logic circuit diagram illustrating a failure detection path of a clock gate circuit and an asynchronous signal. FIG. 2 is a logic circuit diagram illustrating a state before and after the integration process according to FIG. 1. FIG. 10 is a logic circuit diagram showing a state BFR_DCLN before integration and a state AFT_DCLNflt after integration when no substitution is performed by circuit elements. It is a logic circuit diagram which shows another example of integration. It is a logic circuit diagram which shows another example of the circuit element which substitutes a clock gate circuit by integrated processing. FIG. 3 is a logic circuit diagram illustrating a state before and after a multiplexing process according to FIG. 2. FIG. 10 is a logic circuit diagram showing a state AFT_CLCflt after multiplexing when no scan latch is assigned to a clock gate circuit added by multiplexing. It is a logic circuit diagram which shows another example of multiplexing. It is a flowchart which illustrates the processing flow of the whole layout design of a semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Clock pulse generator (CPG)
SQNC clock synchronization circuit CK_PAS1 to CK_PAS4 clock transmission path CGC1 to CGC6 clock gate circuit CGC3_m clock gate circuit added by multiplexing CLK clock signal CEN clock enable signal SMC test signal Tscn test terminal OBS test terminal Tscn output signal (test output signal) )
AMPL failure detection sample signal SLAT1, SLAT2 scan latch SCLK scan clock 3 circuit element BUF buffer

Claims (12)

A semiconductor integrated circuit arrangement and wiring method for performing an arrangement and wiring process on a semiconductor integrated circuit in which a plurality of output gate circuits are arranged in a timing tree path for supplying a timing signal to a synchronous circuit,
The semiconductor integrated circuit generates and generates a failure detection sample signal for detecting a failure in the asynchronous signal path of the semiconductor integrated circuit based on one or more asynchronous signals transmitted to the failure detection path of the asynchronous signal path. A test function that allows the sample signal for failure detection provided to the scan latch of the scan path to be read out externally,
The output gate circuit has a test terminal that transmits an output enable signal input for output control of a timing signal to a failure detection path of the asynchronous signal path,
The placement and routing process uses a computer device to determine whether to multiplex or integrate the output gate circuit in order to keep the skew of the timing signal output from the output gate circuit within an allowable range, and the determination result Including the process of multiplexing or integrating the output gate circuit according to
The process of performing the integration includes a process of arranging a circuit element for connecting the input terminal of the output enable signal of the output gate circuit to the test terminal instead of the output gate circuit to be abolished by the integration,
The process of performing the multiplexing includes a process of assigning a new scan latch to the test terminal of the output gate circuit added by multiplexing.   2. The placement and routing of a semiconductor integrated circuit according to claim 1, wherein the integration processing includes processing for connecting a synchronous circuit connected to an output of an output gate circuit to be abolished by integration to an output of an output gate circuit left by integration. Method.   3. The semiconductor according to claim 2, wherein the multiplexing process includes a process of connecting a part of a synchronization circuit connected to the output of the output gate circuit before multiplexing to the output of the output gate circuit added by multiplexing. Integrated circuit placement and routing method.   4. The method of arranging and wiring a semiconductor integrated circuit according to claim 3, wherein the process of arranging the circuit elements is a process of arranging a wiring, and a process of arranging a buffer circuit that secures a delay time if necessary.   The process of assigning and connecting the new scan latch is a process of assigning the spare scan latch when there is a spare scan latch prepared in advance, and assigning a newly added scan latch when there is no spare scan latch. 5. A method of arranging and wiring a semiconductor integrated circuit according to claim 4.   2. The placement and routing method for a semiconductor integrated circuit according to claim 1, wherein the synchronization circuit is a clock synchronization circuit, the timing signal is a clock signal, the timing tree path is a clock tree path, and the output gate circuit is a clock gate circuit. A semiconductor that supports placement and routing processing for the output gate circuit of a semiconductor integrated circuit in which a plurality of output gate circuits are arranged in a timing tree path for supplying a timing signal to the synchronization circuit by executing using a computer device An integrated circuit placement and routing support program,
The semiconductor integrated circuit generates and generates a failure detection sample signal for detecting a failure in the asynchronous signal path of the semiconductor integrated circuit based on one or more asynchronous signals transmitted to the failure detection path of the asynchronous signal path. A test function that allows the sample signal for failure detection provided to the scan latch of the scan path to be read out externally,
The output gate circuit has a test terminal that transmits an output enable signal input for output control of a timing signal to a failure detection path of the asynchronous signal path,
The placement and routing process uses a computer device to determine whether to multiplex or integrate the output gate circuit in order to keep the skew of the timing signal output from the output gate circuit within an allowable range, and the determination result Including the process of multiplexing or integrating the output gate circuit according to
The process of performing the integration includes a process of arranging a circuit element for connecting the input terminal of the output enable signal of the output gate circuit to the test terminal instead of the output gate circuit to be abolished by the integration,
The process of performing multiplexing includes a process for supporting placement and routing of a semiconductor integrated circuit, including a process of assigning a new scan latch to the test terminal of an output gate circuit added by multiplexing.   8. The placement and routing of a semiconductor integrated circuit according to claim 7, wherein the integration processing includes processing for connecting a synchronous circuit connected to an output of an output gate circuit to be abolished by integration to an output of an output gate circuit left by integration. Support program.   9. The semiconductor according to claim 8, wherein the multiplexing process includes a process of connecting a part of a synchronization circuit connected to the output of the output gate circuit before multiplexing to the output of the output gate circuit added by multiplexing. Integrated circuit placement and routing support program.   10. The placement / wiring support program for a semiconductor integrated circuit according to claim 9, wherein the processing for arranging the circuit elements is processing for arranging wiring and processing for arranging a buffer circuit for securing a delay time as required.   The process of assigning and connecting the new scan latch is a process of assigning the spare scan latch when there is a spare scan latch prepared in advance, and assigning a newly added scan latch when there is no spare scan latch. 11. A program for supporting placement and routing of a semiconductor integrated circuit according to claim 10.   8. The place-and-route support program according to claim 7, wherein the synchronization circuit is a clock synchronization circuit, the timing signal is a clock signal, the timing tree path is a clock tree path, and the output gate circuit is a clock gate circuit.

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