JP5001866B2 - Loss signal repair method and loss signal repair circuit - Google Patents

Description

  The present invention relates to a loss signal repair method and a loss signal repair circuit that automatically repair a loss of a received signal received through a wired transmission line.

  When a signal is received through a wired transmission path, for example, in the case of long-distance transmission or high-speed transmission, the high-frequency component of the received signal is attenuated, so that the high-frequency component of the received signal cannot be correctly reproduced. Therefore, conventionally, a loss signal restoration circuit that automatically repairs a high-frequency component attenuated in a received signal has been proposed (for example, Non-Patent Documents 1 and 2).

  In the loss signal repair circuit of Non-Patent Document 1, the high-frequency component of the received signal is extracted by a high-pass filter, the extracted signal is attenuated by a slicer circuit, and the extracted signal is made closer to the extracted signal by an enhancement circuit. By emphasizing, the attenuated high-frequency component is automatically repaired.

  Further, the loss signal repair circuit of Non-Patent Document 2 automatically repairs the attenuated high-frequency component by measuring the jitter of the received signal and adjusting the circuit constant so as to reduce the jitter.

S. Gondi, J. Lee, D. Takeuchi, B. Razavi, “A 10Gb / s CMOS Adaptive Equalizer for Backplane Applications,” ISSCC Dig.tech.Papers, pp.328-329, Feb., 2005 Y. Hidaka, W. Gai, et al., “A 4-Channel 3.1 / 10.3Gb / s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer,” ISSCC Dig.tech.Papers, pp.442-443, Feb., 2007

  Since the loss signal restoration circuit of Non-Patent Document 1 includes a high-pass filter, there is a problem that the circuit area becomes large.

  Further, in the lost signal repair circuit of Non-Patent Document 2, since it is necessary to perform sampling at a sufficiently high speed capable of measuring the jitter of the received signal, there is a problem that power consumption becomes large, and clock timing management is difficult. There is a problem.

  The present invention has been made in order to solve the above-described problems, and a lost signal repairing method that prevents an increase in circuit area, prevents an increase in power consumption, and facilitates clock timing management. It is an object to provide a lost signal repair circuit.

  In order to solve the above problems, a first aspect of the present invention is a lost signal repairing method for repairing a loss of a received signal received through a wired transmission path, and (i) an amplitude of the received signal in a certain period. (Ii) multiplying the maximum amplitude value by a predetermined constant to obtain a second reference amplitude, and the signal amplitude after full-wave rectification of the received signal is always greater than the second reference amplitude for a certain period of time. And enhancing the received signal so as to be larger.

  According to the first embodiment of the present invention, since it is not necessary to measure the jitter of the high-pass filter and the received signal Sr as in the prior art, it is possible to prevent an increase in circuit area, an increase in power consumption, and a clock signal. Easy timing management.

Embodiment 1 FIG.
The loss signal repair circuit according to this embodiment repairs the loss (attenuation) of the received signal received through the wired transmission path.

  First, the repair principle (lost signal repair method) used in the lost signal repair circuit will be described with reference to FIG.

  Generally, when a signal (input signal) Si including a high-frequency component and a low-frequency component and having a maximum amplitude Vpp is transmitted through a wired transmission line, the signal (reception signal) Sr is lost by the wired transmission line on the receiving side. In particular, it is received in a state where the high frequency component is attenuated.

Focusing on the input signal Si, since there is no loss (attenuation) in the ideal waveform, as shown in FIGS. 1A to 1C, the average value of the signal amplitude Vsig after the full-wave rectification processing of the low-frequency component Si ^L is performed. Vave ^L (hereinafter referred to as an amplitude average value) is expressed by Equation 1 because the width h is very short even if the ripple R exists in the waveform after the full-wave rectification processing.

Vave ^L = Vpp Equation 1

The amplitude average value Vave ^H after full-wave rectification processing of the high-frequency component Si ^H of the input signal Si is expressed by Equation 2 when the high-frequency component Si ^H is approximated to a sine wave as shown in FIGS. It becomes. Note that the coefficient of Equation 2 is 2 / π because the high frequency component Si ^H is approximated by a sine wave, but when approximated by another function, the coefficient varies depending on the function.

Vave ^H = (2 / π) × Vpp Equation 2.

Therefore, from Equation 1 and Equation 2, the amplitude average value Vave ^H after the full-wave rectification processing of the high frequency component Si ^H of the input signal Si is expressed by Equation 3.

Vave ^H = (2 / π) × Vave ^L Equation 3

Equation 3 is established for an ideal waveform signal without loss. Therefore, if the received signal Sr is emphasized so that the average amplitude values Vave ^H and Vave ^L satisfy Expression 3, the loss of the received signal Sr can be repaired (that is, the waveform of the received signal Sr can be restored to the waveform of the input signal Sr). ).

  Actually, according to the procedure of steps S1 and S2 in FIG. 1, the received signal Sr is emphasized so that the received signal Sr approximately satisfies Equation 3, and the loss of the received signal Si is repaired.

That is, in step 1, the maximum amplitude value Vpp of the received signal Sr (actually the maximum amplitude value in a certain period of time) Vpp is measured, and the maximum amplitude value Vpp is measured as the low frequency component Sr ^L The amplitude average value Vave ^L after the full-wave rectification processing is obtained. Here, since the low frequency component Sr ^L of the received signal Sr is hardly attenuated, the amplitude average value Vave ^L after the full-wave rectification processing of the low frequency component Sr ^L of the received signal Sr is the maximum amplitude value Vpp of the received signal Sr. Is used to be almost equal.

Then, in Step 2, based on Equation 3, the measured amplitude average value Vave ^L is multiplied by a predetermined constant (for example, 2 / π), and the amplitude average value after the full-wave rectification processing of the high-frequency component Sr ^H of the received signal Sr. Vave ^H (second reference amplitude) is obtained. Then, the received signal Sr is emphasized so that the signal amplitude Vsig after the full-wave rectification processing of the received signal Sr is always greater than the obtained average amplitude value Vave ^H (always for a sufficiently long period of time). At that time, it is desirable that the signal amplitude Vsig be equal to or less than the measured amplitude maximum value Vpp. In this way, the loss of the received signal Sr is repaired.

In step S2, since it is technically difficult to measure the amplitude average value Vave ^H after the full-wave rectification processing of the high-frequency component Sr ^H of the reception signal Sr, after the full-wave rectification processing of the reception signal Sr as described above. As described above, the amplitude average values Vave ^H and Vave ^L of the received signal Sr are obtained by emphasizing the received signal Sr so that the signal amplitude Vsig of the received signal Sr is always larger than the obtained average amplitude value Vave ^H for a certain period of time. Equation 3 is approximately satisfied.

  Next, the configuration of the loss signal repair circuit will be described with reference to FIG. The loss signal repair circuit is configured based on the repair principle described above.

  As shown in FIG. 2, the loss signal restoration circuit 1 includes an equalizer unit 3 that adjusts the signal amplitude Vsig of the reception signal Sr, an amplitude measurement unit 5 that measures the signal amplitude Vsig of the reception signal Sr, the equalizer unit 3 and the amplitude. And a control circuit 7 for controlling the measurement unit 5.

  The equalizer unit 3 is controlled to switch the processing mode between the first processing mode and the second processing mode by the control circuit 7. In the first processing mode, the equalizer unit 3 outputs the reception signal Sr without adjustment, and in the second processing mode, The received signal Sr is emphasized and output under the control of the control circuit 7. Here, the equalizer unit 3 is set to the first processing mode in the initial state, and is controlled to be switched to the second processing mode by the control circuit 7.

  The equalizer unit 3 is configured, for example, by connecting a plurality of equalizers EQ in series. Each equalizer EQ includes resistors R1, R2, and R3, NMOS transistors Tr1 and Tr2, constant current sources K1 and K2, variable capacitors C1 and C2 whose capacitances are controlled by the control circuit 7, for example, as shown in FIG. Input terminals Tin1 and Tin2 and output terminals Tout1 and Tout2 are provided.

  The resistor R1, the drain-source of the NMOS transistor Tr1, and the constant current source K1 are connected in series between the power supply Vdd and the ground point A in that order from the power supply Vdd side. The resistor R2, the drain-source of the NMOS transistor Tr2, and the constant current source K2 are connected in series between the power source Vdd and the ground point A in that order from the power source Vdd side. The variable capacitor C1 is connected between a node N1 between the NMOS transistor Tr1 and the constant current source K1 and the ground point A. The variable capacitor C2 is connected between the node N2 between the NMOS transistor Tr2 and the constant current source K2 and the ground point A. The resistor R3 is connected between the nodes N1 and N2. The input terminals Tin1 and Tin2 are connected to the gates of the NMOS transistors Tr1 and Tr2, respectively. The output terminals Tout1 and Tout2 are connected to the nodes N3 and N4, respectively. Note that the node N3 is a branch point between the resistor R1 and the NMOS transistor Tr1, and the node N4 is a branch point between the resistor R2 and the NMOS transistor Tr2.

  With this circuit configuration, each equalizer EQ outputs the signals input to the input terminals Tin1 and Tin2 from the output terminals Tout1 and Tout2 without adjustment in the first processing mode, and the control circuit 7 in the second processing mode. By adjusting the capacitances of the variable capacitors C1 and C2, the signals input to the input terminals Tin1 and Tin2 are emphasized and output from the output terminals Tout1 and Tout2.

  The amplitude measuring unit 5 is controlled so that its processing mode is switched between the first processing mode and the second processing mode by the control circuit 7. In the first processing mode, the output signal of the equalizer unit 3 (that is, the reception signal Sr) is constant. In the second processing mode, a value obtained by multiplying the maximum amplitude value Vpp by a predetermined constant (for example, 2 / π) is set as the second reference amplitude, and the output signal of the equalizer section 3 is measured. This is to detect whether the signal amplitude Vsig after the full-wave rectification processing is larger than the second reference amplitude value.

  In the measurement of the maximum amplitude value Vpp, the reference amplitude Vref is gradually increased until it becomes always larger than the signal amplitude Vsig of the reception signal Sr for a certain period, and the reference amplitude Vref at that time becomes the reception signal Sr. Is performed by a method of setting the amplitude maximum value Vpp in a certain period of time.

  The amplitude measurement unit 5 generates, for example, a buffer circuit 5a that amplifies the output signal of the equalizer unit 3, a full-wave rectification circuit 5b that performs full-wave rectification processing on the signal amplified by the buffer circuit 5a, and a reference amplitude Vref. The reference amplitude generation circuit 5c and a voltage comparison circuit 5d that compares the signal amplitude Vsig after the full-wave rectification processing of the output signal of the equalizer unit 3 with the reference amplitude Vref are configured.

  The reference amplitude generation circuit 5c is controlled so that its processing mode is switched between the first processing mode and the second processing mode by the control circuit 7. In the first processing mode, the reference amplitude Vref has a sufficient absolute value as controlled by the control circuit 7. In the second processing mode, the first reference amplitude output at the time of switching to the second processing mode is set as the maximum amplitude value Vpp, and the second reference amplitude is output. And the second reference amplitude is output as the reference amplitude Vref. Here, the reference amplitude Vref is output to the voltage comparison circuit 5d via the full-wave rectification circuit 5b.

  The voltage comparison circuit 5d compares the signal amplitude Vsig from the full-wave rectification circuit 5b with the reference amplitude Vref, and outputs an H level signal to the control circuit 7 when the signal amplitude Vsig is larger than the reference amplitude Vref. When Vsig is less than or equal to the reference amplitude Vref, an L level signal is output to the control circuit 7.

  FIG. 4 is an example of a circuit configuration of each of the buffer circuit 5a, the full-wave rectifier circuit 5b, and the reference amplitude generation circuit 5c.

  As shown in FIG. 4, the buffer circuit 5a includes resistors R4 and R5, NMOS transistors Tr3 and Tr4, a constant current source K3, input terminals Tin3 and Tin4, and output terminals Tout3 and Tout4.

  The drain and source of the resistor R4 and the NMOS transistor Tr3 are connected in series between the power source Vdd and the constant current source K3 in that order from the power source Vdd side. The drain and source of the resistor R5 and the NMOS transistor Tr4 are connected in series between the power source Vdd and the constant current source K3 in that order from the power source Vdd side. The input terminals Tin3 and Tin4 are connected to the gates of the NMOS transistors Tr3 and Tr4, respectively. The output terminals Tout3 and Tout4 are connected to the nodes N5 and N6, respectively. Note that the node N5 is a branch point between the resistor R4 and the NMOS transistor Tr3, and the node N5 is a branch point between the resistor R5 and the NMOS transistor Tr4.

  With this circuit configuration, the buffer circuit 5a amplifies the signals input to the input terminals Tin3 and Tin4 (the output signal of the equalizer unit 3) and outputs them from the output terminals Tout3 and Tout4.

  As shown in FIG. 4, the reference amplitude generating circuit 5c includes resistors R6 to R8, a variable resistor R9 controlled by the control circuit 7, a switch SW1 controlled on / off by the control circuit 7, NMOS transistors Tr5 and Tr6, And a constant current source K4 and output terminals Tout5 and Tout6.

  The drain and source of the resistor R6 and the NMOS transistor Tr5 are connected in series between the power source Vdd and the constant current source K4 in that order from the power source Vdd side. The drain and source of the resistor R7 and the NMOS transistor Tr6 are connected in series between the power source Vdd and the constant current source K4 in that order from the power source Vdd side. The gate of the NMOS transistor Tr5 is connected to the power supply Vdd, and the gate of the NMOS transistor Tr6 is grounded. The variable resistor R9 is connected between the drains of the NMOS transistors Tr5 and Tr6. The resistor R8 and the switch SW1 are connected in parallel to the variable resistor R9 in a state where they are directly connected to each other. The output terminals Tout3 and Tout4 are connected to the downstream ends of the resistors R6 and R7, respectively.

  With this circuit configuration, in the first processing mode, the reference amplitude generating circuit 5c is turned off by the control circuit 7 and the resistance value of the variable resistor R9 is adjusted by the control circuit 7, and thereby the reference value is output from the output terminals Tout1 and Tout2. The first reference amplitude is output as the amplitude Vref. In the second processing mode, the resistance value of the variable resistor R9 is fixed by the control circuit 7 in accordance with the switching to the second processing mode (note that the first reference amplitude output at the time of the fixing is the received signal Sr). The switch SW1 is turned on (in addition, the first reference amplitude is multiplied by (2 / π) by this ON), whereby the reference amplitude is output from the output terminals Tout1 and Tout2. The second reference amplitude is output as Vref.

  As shown in FIG. 4, the full-wave rectifier circuit 5b includes PMOS transistors Tr7 to Tr10, NMOS transistors Tr11 and Tr12, input terminals Tin5 to Tin8, and output terminals Tout7 and Tout8.

  The PMOS transistors Tr7 and Tr8 have their sources connected to the power supply Vdd, their drains connected to each other and commonly connected to the drain of the PMOS transistor Tr11, and their gates connected to the input terminals Tin5 and Tin6, respectively. It is arranged. The output terminals Tout6 and Tout5 of the reference amplitude generation circuit 5c are connected to the input terminals Tin5 and Tin6, respectively.

  The PMOS transistors Tr9 and Tr10 have their sources connected to the power supply Vdd, their drains connected to each other and commonly connected to the drain of the PMOS transistor Tr12, and their gates connected to the input terminals Tin7 and Tin8, respectively. It is arranged. The output terminals Tout4 and Tout3 of the buffer circuit 5a are connected to the input terminals Tin7 and Tin8, respectively.

  The NMOS transistor Tr11 has a drain and a gate connected to each other and commonly connected to the output terminal 7, and a source connected to the ground. The NMOS transistor Tr12 has a drain connected to the output terminal 8, a gate connected to the gate of the NMOS transistor Tr11, and a source grounded.

  With this circuit configuration, the full-wave rectifier circuit 5b outputs the output signal (reference amplitude Vref) of the reference amplitude generation circuit 5c inputted to its input terminals Tin5 and Tin6 from its output terminal Tout7, and its input terminals Tin7 and Tin8. The output signal (received signal Sr) of the buffer circuit 5a input to the signal is subjected to full-wave rectification processing and output from the output terminal Tout8.

  The control circuit 7 switches and controls each processing mode of the equalizer unit 3 and the amplitude measuring unit 5 between the first processing mode and the second mode. In the initial state, the equalizer unit 3 and the amplitude measuring unit 5 are in the first processing mode. When the maximum amplitude value Vpp of the output signal (that is, the reception signal Sr) of the equalizer unit 3 is measured by the amplitude measuring unit 5 to operate, the equalizer unit 3 and the amplitude measuring unit 7 are operated in the second processing mode. The received signal Sr is emphasized by controlling the equalizer unit 3 so that the signal amplitude Vsig of the output signal of the unit 3 becomes larger than the reference amplitude Vref (that is, the first reference amplitude).

  For example, as shown in FIG. 2, the control circuit 7 includes a flip-flop 7a, a selector 7b, a first timer 7c, a second timer 7d, a processing mode control circuit 7e, and first and second code increments 7f. , 7g, a NOT circuit 7h, and a switch SW2.

  The NOT circuit 7h inverts the output signal (that is, the reception signal Sr) from the voltage comparison circuit 5d.

  The switch SW2 outputs the output signal of the voltage comparison circuit 5d to the flip-flop 7a via the NOT circuit 7h, or outputs the output signal of the voltage comparison circuit 5d to the flip-flop 7a without passing through the NOT circuit 7h. Switching is performed. The processing mode of the switch SW2 is controlled to be switched between the first processing mode and the second processing mode by the processing mode control circuit 7e. In the first processing mode, the output signal of the voltage comparison circuit 5d is not passed through the NOT circuit 7h. In the second processing mode, the output signal of the voltage comparison circuit 5d is output via the NOT circuit 7h.

  The flip-flop 7a outputs the H level signal when the up edge of the H level signal from the voltage comparison circuit 5d or the NOT circuit 7h is input, and outputs the L level signal when the down edge of the L level signal is input. .

  When the processing mode of the selector 7b is controlled to be switched between the first processing mode and the second processing mode by the processing mode control circuit 7e, and the output signal of the flip-flop 7a is switched to the H level signal, in the first processing mode, The reference amplitude Vref (that is, the first reference amplitude) output from the reference amplitude generation circuit 5c of the amplitude measuring unit 5 via the first code increment 7f is increased by a predetermined amount. In the second processing mode, the second code increment 7g is increased. The equalizer unit 3 is controlled through the control (that is, the capacitances of the variable capacitors C1 and C2 of each equalizer EQ are adjusted), and the received signal Sr is emphasized by a predetermined amount.

  The first timer 7c is configured to stop the operation of the flip-flop 7a until the reference amplitude Vref is stabilized when the reference amplitude Vref output from the reference amplitude generation circuit 5c is increased by a predetermined amount by the selector 7b. When the output signal of the flip-flop 7a is switched to the H level signal, the first timer 7c starts measuring time (first predetermined period) necessary for stabilizing the reference amplitude Vref, and during that time, The flip-flop 7a is reset and the output signal of the flip-flop 7a is forced to the L level signal to stop its operation.

  The second timer 7d measures the predetermined time necessary for determining whether the signal amplitude Vsig of the reception signal Sr is always larger than the reference amplitude Vref for a predetermined period (second predetermined period). The second timer 7d starts measuring the second predetermined period at the same time as the first timer 7f finishes counting the first predetermined period, and during that time, the output signal of the flip-flop 7a switches to the H level signal. In the case of switching, the timing of the second predetermined period is stopped, and on the other hand, the output signal of the flip-flop 7a is not switched to the H level signal during the timing (that is, the L level signal continues to be output). Outputs a timeout signal.

  The processing mode control circuit 7e switches and controls the processing mode of the reference amplitude generating circuit 5c, the switch SW2, and the selector 7b between the first processing mode and the second processing mode in response to the output of the timeout signal from the second timer 7d. .

  More specifically, the processing mode control circuit 7e sets the reference amplitude generation circuit 5c, the switch SW2, and the selector 7b to the first processing mode in the initial state. That is, the switch SW2 is switched so that the output signal of the voltage comparison circuit 5d is output to the flip-flop 7a without passing through the NOT circuit 7h, and the switch SW1 of the reference amplitude generation circuit 5c is turned off to refer to the reference amplitude generation circuit 5c. The first reference amplitude having a sufficiently small absolute value is output as the amplitude Vref, and the reference amplitude is generated via the first code increment 7f each time the output signal of the flip-flop 7a is switched to the H level signal to the selector 7b. The variable resistor R9 of the circuit 5c is adjusted to increase the first reference amplitude output from the reference amplitude generation circuit 5c by a predetermined amount.

When the time-out signal is output from the second timer 7d, the processing mode control circuit 7e switches the reference amplitude generating circuit 5c, the switch SW2, and the selector 7b to the second processing mode. That is, the switch SW2 is switched so that the output signal of the voltage comparison circuit 5d is output to the flip-flop 7a via the NOT circuit 7h, and the adjustment of the variable resistor R9 of the reference amplitude generation circuit 5c is stopped for the selector 7b (this The reference amplitude Vref at that time is the maximum amplitude value Vpp of the received signal Sr (= the average amplitude value Vave ^L of the received signal Sr), and the switch SW1 of the reference amplitude generating circuit 5c is turned on to set the reference amplitude Vref ( The second reference amplitude (= (2 / π) × Vave ^L ) is output as the reference amplitude Vref from the reference amplitude generation circuit 5c, and the output of the flip-flop 7a is output to the selector 7b. Each time the signal is switched to the H level signal, the equalizer section 3 is controlled via the second code increment 7g (that is, the variable capacitors C1 and C2 of each equalizer EQ are adjusted). The received signal Sr is emphasized by a predetermined amount.

  Next, the operation of the lost signal repair circuit 1 will be described with reference to FIG.

  In the initial state, the equalizer unit 3, the reference amplitude generation circuit 5c, the switch SW2, and the selector 7b are set to the first processing mode. When the reception signal Sr is received by the equalizer unit 3 in this state, the maximum amplitude value Vpp of the reception signal Sr in a certain period (second predetermined period) is measured.

  Here, as will be described later, the reference amplitude Vref is gradually increased until it becomes larger than the signal amplitude Vsig of the received signal Sr for a certain period, and the reference amplitude Vref at that time is increased for a certain period of the received signal Sr. The maximum amplitude value Vpp is measured by a method which is regarded as the maximum amplitude value Vpp at the same time.

  That is, the received signal Sr is not adjusted by the equalizer unit 3 but is output to the full-wave rectifier circuit 5b through the buffer circuit 5a, is subjected to full-wave rectification processing by the full-wave rectifier circuit 5b, and is output to the voltage comparison circuit 5d. In this state, the reference amplitude generating circuit 5c outputs the first reference amplitude having a sufficiently small absolute value as the reference amplitude Vref in the initial state, and the reference amplitude Vref is a voltage via the full-wave rectifier circuit 5b. It is output to the comparison circuit 5d. Then, the voltage comparison circuit 5d compares the signal amplitude Vsig of the reception signal Sr with the reference amplitude Vref, and when the signal amplitude Vsig of the reception signal Sr is larger, an H level signal is output from the voltage comparison circuit 5d. When the signal amplitude Vsig of the reception signal Sr is smaller, an L level signal is output from the voltage comparison circuit 5d. When the reference amplitude Vref is not always larger than the signal amplitude Vsig of the reception signal Sr for a certain period, the output signal of the voltage comparison circuit 5d changes to an H level signal and an L level signal.

  When the up edge of the H level signal from the voltage comparison circuit 5d is input to the flip flop 7a, the H level signal is output from the flip flop 7a. The output of the H level signal causes the selector 7b to increase the reference amplitude Vref of the reference amplitude generation circuit 5c by a predetermined amount via the first code increment 7f, and the first timer 7c generates the increased reference amplitude Vref. Time measurement required for stabilization (first predetermined period) is started, and during the time measurement, the flip-flop 7a is reset, and the output of the flip-flop 7a is forcibly set to an L level signal to operate the flip-flop 7b. Is stopped.

  When the time measurement of the first predetermined period by the first timer 7c ends, the reset of the flip-flop 7a by the first timer 7c is released, the flip-flop 7a becomes operable, and the second predetermined time is received by the second timer 7d. Time counting starts.

  When the signal amplitude Vsig of the reception signal Sr is not always larger than the reference amplitude Vref for a certain period (second predetermined period), the flip-flop 7a is in the middle of measuring the second predetermined period by the second timer 7d. The up edge of the H level signal from the voltage comparison circuit 5d is input again, and the output signal of the flip-flop 7a is switched to the H level signal again. Due to the output of the H level signal, the second timer 7d stops the timing of the second predetermined period, and the same operation as described above (that is, the reference timer Vref is increased by a predetermined amount by the selector 7b, the first timer 7c). The operation of the flip-flop 7b during the first predetermined period is stopped, and the second timer 7d starts measuring the second predetermined period). Thus, each time the output signal of the flip-flop 7a is switched to the H level signal, the reference amplitude Vref is increased by a predetermined amount.

  If the L level signal is always output from the selector 7b until the second timer 7d finishes counting the second predetermined period, the reference amplitude Vref is always a received signal for a certain period (second predetermined period). It is assumed that the signal amplitude Vsig of Sr has become larger, and a time-up signal is output from the second timer 7d. By outputting the time-up signal, the processing mode control circuit 7e switches the reference amplitude generating circuit 5c, the switch SW2, and the selector 7f to the second processing mode.

As a result, the switch SW2 is turned on, the output signal of the voltage comparison circuit 5d is inverted and output by the NOT circuit 7h, and the increase in the reference amplitude Vref of the reference amplitude generation circuit 5c by the selector 7b is stopped. The amplitude ref is regarded as the maximum amplitude value Vpp of the received signal Sr (= the average amplitude value Vave ^L of the received signal), and (2 / π) times the maximum amplitude value Vpp is a second value in the reference amplitude generation circuit 5c. The second reference amplitude is set as the reference amplitude, the second reference amplitude is output as the reference amplitude Vref from the reference amplitude generation circuit 5c, and the second code is output each time the output signal of the flip-flop 7a is switched to the H level signal by the selector 7b. The equalizer unit 3 is controlled via the increment 7g so that the received signal Sr is emphasized by a predetermined amount.

  When the reception signal Sr is received by the equalizer unit 3 in this state, the signal amplitude Vsig of the reception signal Sr is always larger than the reference amplitude Vref (= (2 / π) × Vpp) for a certain period (second predetermined period). Similarly, the received signal Sr is emphasized.

  That is, the received signal Sr is not adjusted at first by the equalizer unit 3, but is output to the full-wave rectifier circuit 5b through the buffer circuit 5a, is subjected to full-wave rectification processing by the full-wave rectifier circuit 5b, and is output to the voltage comparison circuit 5d. . In this state, the second reference amplitude (= (2 / π) × Vpp) is output as the reference amplitude Vref from the reference amplitude generation circuit 5c, and the reference amplitude Vref is output via the full-wave rectification circuit 5b. The voltage is output to the voltage comparison circuit 5d. Then, the voltage comparison circuit 5d compares the signal amplitude Vsig of the reception signal Sr with the reference amplitude Vref, and when the signal amplitude Vsig of the reception signal Sr is larger, an H level signal is output from the voltage comparison circuit 5d. When the signal amplitude Vsig of the reception signal Sr is smaller, an L level signal is output from the voltage comparison circuit 5d. In the state where the reception signal Sr is attenuated, the signal amplitude Vsig of the reception signal Sr is not always larger than the reference amplitude Vref for a certain period, so that the output signal of the voltage comparison circuit 5d changes into an H level signal and an L level signal. Yes.

  The output signal of the voltage comparison circuit 5d is inverted by the NOT circuit 7h and output to the lip flop 7a. The subsequent processing is the same as that in the case of measuring the maximum amplitude value Vpp of the received signal Sr in a certain period except that the selector 7b performs the above operation (operation in the second processing mode). Is done.

As a result, every time the output signal of the flip-flop 7a switches to the H level signal, the equalizer unit 3 is controlled via the second code increment 7g and the received signal Sr is emphasized by a predetermined amount. When the L level signal is always output from the selector 7b until the second timer 7d finishes counting the second predetermined period, the signal amplitude Vsig of the reception signal Sr is always constant (second predetermined period). It is considered that the reference amplitude has become larger than the reference amplitude Vref (= (2 / π) × Vpp), and the processing of the loss signal repair circuit 1 is finished. As a result, the received signal Sr received thereafter is emphasized by the equalizer unit 3 so that its loss (that is, attenuation of the high frequency component Sr ^H ) is restored to the original state.

  According to the loss signal restoration circuit 1 configured as described above, (i) the maximum amplitude value Vpp of the reception signal Sr in a certain period is measured, and (ii) the amplitude maximum value Vpp is set to a predetermined constant (for example, 2 / The second reference amplitude value is obtained by multiplying by π), and the received signal Sr is emphasized so that the signal amplitude Vsig after the full-wave rectification processing of the received signal Sr is always larger than the second reference amplitude value for a certain period. Since it is not necessary to measure the high-pass filter and the jitter of the received signal Sr as in the prior art, an increase in circuit area can be prevented, an increase in power consumption can be prevented, and clock timing management can be facilitated.

  Further, since the predetermined constant is 2 / π, the loss can be repaired with high accuracy for the received signal Sr that can be approximated by a sine wave.

  Further, in the first processing mode, the received signal Sr is output without adjustment, and in the second processing mode, the equalizer unit 3 that emphasizes and outputs the signal amplitude Vsig of the received signal Sr, and in the first processing mode, the equalizer is output. The maximum amplitude value Vpp of the output signal of the unit 3 (that is, the received signal Sr) in a certain period is measured, and in the second processing mode, a value obtained by multiplying the maximum amplitude value Vpp by a predetermined constant is set as the second reference amplitude. The amplitude measuring unit 5 that detects whether or not the output signal of the equalizer unit 3 has become larger than the second reference amplitude, and the equalizer unit 3 and the amplitude measuring unit 5 are operated in the first processing mode, and the amplitude measuring unit 5 When the maximum amplitude value Vpp is measured by the above, the equalizer unit 3 is set so that the output signal of the equalizer unit 3 becomes larger than the second reference amplitude while operating the equalizer unit 3 and the amplitude measuring unit 5 in the second processing mode. System And a control circuit 7 which emphasize the signal amplitude Vsig of the received signal Sr and. That is, the equalizer unit 3, the amplitude measuring unit 5, and the control circuit 7 each have a first processing mode corresponding to the process (i) and a second processing mode corresponding to the process (ii). The control circuit 7 switches between the first processing mode and the second processing mode. Thereby, the equalizer unit 3, the amplitude measuring unit 5 and the control circuit 7 can be used in the processes (i) and (ii), respectively, and an increase in circuit area can be prevented.

  In addition, the amplitude measuring unit 5 gradually converts the output signal (that is, the received signal Sr) of the equalizer unit 3 into a full-wave rectified wave by the control circuit 7 as a reference amplitude Vref in the first processing mode. The first reference amplitude that is raised is output, and in the second processing mode, the first reference amplitude that is output at the time of switching to the second processing mode is set as the maximum amplitude value Vpp of the output signal of the equalizer unit 3 for a certain period, A value obtained by multiplying the maximum amplitude value Vpp by a predetermined constant is set as the second reference amplitude, and the reference amplitude generating circuit 5c that outputs the second reference amplitude as the reference amplitude Vref, and the full-wave rectification of the output signal of the equalizer unit 3 When the processed signal amplitude Vsig is larger than the reference amplitude Vref, an H level signal is output to the control circuit 7, and when the signal amplitude Vsig after the full-wave rectification processing of the output signal of the equalizer unit 3 is smaller than the reference amplitude Vref, L Lebe Since the structure and a voltage comparator circuit 5d which outputs a signal to the control circuit 7, the amplitude measurement section 5 can be realized with a simple configuration.

  Further, the control circuit 7 outputs a NOT circuit 7h for inverting the output signal of the voltage comparison circuit 5d, and outputs the output signal of the voltage comparison circuit 5d via the NOT circuit 7h, or outputs the output signal of the voltage comparison circuit 5d as a NOT circuit. In the first processing mode, the output signal of the voltage comparison circuit 5d is output without passing through the NOT circuit 7h, and in the second processing mode, the output signal of the voltage comparison circuit 5d is switched. Is output via the NOT circuit 7h, and when the up edge of the H level signal from the voltage comparison circuit 5d or the NOT circuit 7h is input, the H level signal is output and the down edge of the L level signal is input. Then, when the flip-flop 7a that outputs the L level signal and the output signal of the flip-flop 7a are switched to the H level signal, the first process is performed. In the mode, the reference amplitude Vref of the reference amplitude generation circuit 5c is increased by a predetermined width, and in the second processing mode, the selector 7b that controls the equalizer unit 3 to emphasize the signal amplitude Vsig of the reception signal Sr by a predetermined amount, and the flip-flop 7a When the output signal is switched to the H level signal, the first timer starts counting the first predetermined period and resets the flip-flop 7a to force the output signal of the flip-flop 7a to the L level signal during the time counting. 7c and when the first timer 7c finishes counting the first predetermined period and starts measuring the second predetermined period, and the output signal of the flip-flop 7a is switched to the H level signal during the time counting. When the timing of the second predetermined period is stopped and the output signal of the flip-flop 7a is not switched to the H level signal during the timing. The second timer 7d that outputs a time-out signal, the reference amplitude generating circuit 5c, the NOT circuit 7h, and the selector 7b are set to the first processing mode in the initial state, and the time-out signal is output from the second timer 7d. Since the processing mode control circuit 7e for switching to the two processing mode is provided, the processing circuit of the control circuit 7 can be shared by the first processing mode and the second processing mode, and an increase in circuit area can be prevented.

  When the output signal of the flip-flop 7a is switched to the H level signal by the first timer 7c, the timing of the first predetermined period is started and the flip-flop 7a is reset during the timing to output the output signal of the flip-flop 7a. Therefore, when the reference amplitude VrefVref is increased by a predetermined amount by the selector 7b7b7b, the operation of the flip-flop 7a can be stopped until the reference amplitude VrefVref is stabilized. Thereby, the control circuit 7 can be stably operated.

  This embodiment includes a lost signal repair method.

FIG. 3 is a diagram for explaining the repair principle of the lost signal repair circuit according to the first embodiment. 1 is a schematic configuration diagram of a loss signal repair circuit according to a first embodiment. It is an example figure of the circuit block diagram of the equalizer EQ of FIG. FIG. 2 is an example of a circuit configuration diagram of a buffer circuit 5a, a full-wave rectifier circuit 5b, and a reference amplitude generation circuit 5c in FIG.

Explanation of symbols

  1 Loss signal repair circuit, 3 equalizer section, 5 amplitude measurement section, 5a buffer circuit, 5b full-wave rectifier circuit, 5c reference amplitude generation circuit, 5d voltage comparison circuit, 7 control circuit, 7a flip-flop, 7b selector, 7c first Timer, 7d second timer, 7e processing mode control circuit, 7f first code increment, 7g second code increment, 7h NOT circuit, EQ equalizer, R1, R2, R3 resistors, TR1, Tr2 NMOS transistors, C1, C2 variable capacitors , K1, K2 constant current source, Tin input terminal, Tout output terminal, SW1, SW2 switch.

Claims (6)

A loss signal repair method for repairing a loss of a received signal received through a wired transmission line,
(I) measuring a maximum amplitude value of the received signal in a certain period;
(Ii) multiplying the maximum amplitude value by a predetermined constant to obtain a reference amplitude, and emphasizing the received signal so that the signal amplitude after full-wave rectification processing of the received signal is always larger than the reference amplitude for a certain period of time When,
A lost signal repairing method comprising:   The loss signal repairing method according to claim 1, wherein the predetermined constant in the step (ii) is 2 / π. A loss signal repair circuit for repairing a loss of a received signal received through a wired transmission path,
In the first processing mode, an equalizer unit that outputs the received signal without adjusting its signal amplitude, and in the second processing mode, an equalizer unit that emphasizes and outputs the received signal amplitude;
In the first processing mode, the maximum amplitude value of the output signal of the equalizer section in a certain period is measured, and in the second processing mode, a value obtained by multiplying the maximum amplitude value by a predetermined constant is set as a reference amplitude, and the equalizer An amplitude measurement unit for detecting whether the output signal of the unit is greater than the reference amplitude;
When the equalizer unit and the amplitude measuring unit are operated in the first processing mode, and the maximum amplitude value is measured by the amplitude measuring unit, the equalizer unit and the amplitude measuring unit are operated in the second processing mode. However, a control circuit that emphasizes the signal amplitude of the received signal by controlling the equalizer unit so that the output signal of the equalizer unit becomes larger than the reference amplitude,
A loss signal repair circuit comprising:   4. The loss signal repair circuit according to claim 3, wherein the predetermined constant is 2 / π. The amplitude measuring unit is
A full-wave rectification circuit for full-wave rectification processing of the output signal of the equalizer unit;
In the first processing mode, the first reference amplitude that is gradually increased by the control circuit is output as the reference amplitude, and in the second processing mode, the first reference amplitude that is output when switching to the second processing mode is used as the reference amplitude. A reference amplitude generating circuit that sets the maximum amplitude value of the output signal of the equalizer section in a certain period, sets a value obtained by multiplying the maximum amplitude value by a predetermined constant as a second reference amplitude, and outputs the second reference amplitude as a reference amplitude When,
When the signal amplitude after full-wave rectification processing of the output signal of the equalizer section is larger than the reference amplitude, an H level signal is output to the control circuit, and the signal amplitude after full-wave rectification processing of the output signal of the equalizer section Is smaller than the reference amplitude, a voltage comparison circuit that outputs an L level signal to the control circuit;
The loss signal repair circuit according to claim 3, further comprising: The control circuit includes:
A NOT circuit for inverting the output signal of the voltage comparison circuit;
Switching between whether the output signal of the voltage comparison circuit is output through the NOT circuit or whether the output signal of the voltage comparison circuit is output without passing through the NOT circuit is performed. A switch that outputs the output signal of the comparison circuit without passing through the NOT circuit, and in the second processing mode, the switch that outputs the output signal of the voltage comparison circuit through the NOT circuit;
A flip-flop that outputs an H level signal when an up edge of an H level signal from the voltage comparison circuit or the NOT circuit is input, and outputs an L level signal when a down edge of the L level signal is input;
When the output signal of the flip-flop is switched to an H level signal, in the first processing mode, the reference amplitude of the reference amplitude generation circuit is increased by a predetermined amount, and in the second processing mode, the equalizer unit is controlled to A selector that emphasizes the signal amplitude of the received signal by a predetermined amount;
When the output signal of the flip-flop is switched to the H level signal, the clocking of the first predetermined period is started, and during the timing, the flip-flop is reset and the output signal of the flip-flop is forced to the L level signal. A first timer;
When the first timer finishes counting the first predetermined period and starts counting the second predetermined period, and when the output signal of the flip-flop switches to the H level signal during the timing, A second timer for outputting the time-out signal when the timing of the second predetermined period is stopped and the output signal of the flip-flop is not switched to an H level signal during the timing;
A processing mode control circuit that sets the reference amplitude generation circuit, the NOT circuit, and the selector to a first processing mode in an initial state and switches to a second processing mode when the time-out signal is output from the second timer;
The loss signal repair circuit according to claim 5, further comprising:

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