JP4433885B2 - Differential peak detection circuit - Google Patents

Description

  The present invention relates to a differential peak detection circuit that detects the magnitude of a signal amplitude of an input differential signal.

  Conventionally, a peak detection circuit is used in various applications (application fields). For example, in data reproduction of a magnetic disk, an optical disk, etc., it is used for an automatic gain adjustment circuit (AGC circuit) as follows. That is, in data reproduction from a magnetic disk or optical disk, although the reproduction data itself is digital data, it is difficult to obtain a digital data string directly from the reproduction waveform due to the so-called transmission path including the recording medium. It is handled as a waveform, and waveform shaping processing such as equalization processing, analog / digital (AD) conversion processing, and the like are performed.

  However, the equalization processing circuit (continuous time filter) and AD converter can handle a limited signal dynamic range, and if the waveform is distorted at these signal processing stages, the playback error rate will be greatly degraded. It is necessary to provide an AGC circuit and automatically adjust and maintain the desired amplitude level. At this time, AGC is realized by detecting the peak level of the signal at the node whose amplitude is to be adjusted and controlled.

  Alternatively, in high-speed data communication such as serial transmission, whether or not a data signal is transmitted from the opposite node is determined by first detecting the signal amplitude with a peak detection circuit and comparing this with a preset criterion level. , Making use of judgment and so on.

  The conventional system is a single-ended configuration having a comparator, a charge pump circuit, and an integration capacitor as basic elements, as described in Patent Document 1, for example. Therefore, when the input is a differential signal, it is necessary to add a full wave rectifier (FWR) first.

  A conventional peak detection circuit will be described with reference to FIG. In FIG. 4, reference numerals 101 and 102 denote input terminals to which a positive phase input signal and a negative phase input signal of a differential pair input signal are input, respectively. The input terminal 101 is connected to the non-inverting input terminal of the comparator 103 constituting the full-wave rectifier 110 and one end of the resistance element 104, and the input terminal 102 is connected to the inverting input terminal of the comparator 103 and one end of the resistance element 105. The other ends of the resistance elements 104 and 105 are connected to one end of a capacitance element (capacitor) 106 and an output terminal 131, and the other end of the capacitor 106 is connected to the ground.

  The input terminal 101 constitutes a full-wave rectifier circuit 110 and is connected to the connection terminal 107a of the switch 107 controlled by the output of the comparator, the input terminal 102 is connected to the connection terminal 107b of the switch 107, and the common terminal 107c is the comparator 111. Is connected to the inverting input terminal. The output of the comparator 111 is input to the charge pump circuit 120.

  The charge pump circuit 120 is composed of, for example, a CMOS transistor and a current source. One end of the charge pump circuit 120 is connected to the terminal 112 of the power source, and the other end of the current source 113 is a p-channel MOS transistor (hereinafter simply referred to as “transistor”). 114 source terminals are connected. Further, the source terminal of an n-channel MOS transistor (hereinafter simply referred to as “transistor”) 115 and one end of the current source 116 are connected, and the other end of the current source 116 is connected to the ground.

  The output terminal of the charge pump circuit 120 is connected to one end of the capacitive element 117, and the other end of the capacitive element 117 is connected to the ground. Furthermore, one end of the capacitive element 117 is connected to the non-inverting input terminal of the comparator 111 and to the output terminal 132.

  The operation of the peak detection circuit shown in FIG. 4 will be described. First, a differential signal at a node whose amplitude level is to be automatically adjusted is input to the full-wave rectifier circuit 110 and extracted from the differential signal as a component having a common-mode potential or higher. In the processing so far, for example, the differential waveform before rectification (see FIG. 5A) is passed through the comparator 103 via the input terminals 101 and 102 to determine whether the differential signal is positive or negative. Thereafter, the switch 107 is switched by the output of H (high) and L (low) of the positive / negative determination signal (see FIG. 5B). When the positive / negative determination signal is positive (H), full-wave rectification is performed by passing a positive-phase signal out of the original differential signal, and when negative (L), a negative-phase signal is passed. The switch 107 here is mainly a MOS switch.

  Next, this full-wave rectified waveform is input to the first input terminal (inverted input terminal in the example of FIG. 4) of the next-stage comparator 111, and the peak of the full-wave rectified waveform and the second input terminal ( The signals input to the non-inverting input terminal in the example of FIG. 4 are compared (see FIG. 5C).

  The comparator 111 is a clock signal whose pulse waveform is low when the peak of the full-wave rectified waveform exceeds the signal input to the second input terminal of the comparator 111 and is high during other periods (see FIG. 5D). Is output. The next-stage charge pump circuit 120 is driven by this clock signal, and the capacitance of the capacitor 117 is charged / discharged by the charge pump current, and at the same time, the control voltage of the second input terminal of the comparator 111 is set. As is well known, the charge pump circuit 120 switches whether the output is a source current or a sink current depending on the logic value of the clock signal.

  Here, when the peak value of the full-wave rectified waveform is larger than the potential of the second input terminal of the comparator 111, that is, when the output of the comparator 111 is a low pulse, the charge pump current (source current) is By setting it sufficiently larger than the current charge pump current (sink current), feedback is applied so that the peak value of the full-wave rectified waveform becomes the integration capacitor terminal potential. As a result, the steady-state potential difference Vp between the input common-mode potential appearing between the output terminals 131 and 132 and the integration capacitor terminal potential becomes equal to the peak value of the full-wave rectified waveform, and the peak can be detected.

  Further, instead of using a full-wave rectifier, a method has been proposed in which positive and negative phase signals are level-shifted and positive and negative peaks are detected independently (divided into two systems) (see, for example, Patent Document 2). ).

Furthermore, as another conventional example, a technique has been proposed in which a diode clamp technique, which has been used in a single-ended configuration for a long time, is applied to a differential CMOS circuit (see, for example, Patent Document 3).
JP 7-218559 A Japanese Patent Laid-Open No. 10-322151 Japanese Patent No. 2646189

  However, as is obvious from the above description, the one described in Patent Document 1 is a full-wave rectifier 110 in spite of originally treating the reproduced signal as a differential signal from the viewpoint of resistance to external noise. At the time of full-wave rectification, the signal to be handled becomes single-ended, and the finally obtained DC level signal with peak detection is also single-ended. Therefore, the resistance to common mode noise such as substrate noise and power supply noise mainly caused by digital external noise is weak, and as a result, the reliability of the peak detection result is lowered. Further, when signal processing is performed based on a plurality of peak detection results from different signal systems, it is necessary to remove each in-phase component, resulting in an increase in additional circuits.

  Further, the conventional system in which a full-wave rectifier is indispensable has a problem that the signal band is limited by the input capacitance of the MOS switch 107 and the comparator 111 that follows. For this reason, the applicable signal band is determined not by the comparator 111 or the charge pump circuit 120 but by the full-wave rectifier, leading to a significant deterioration in detection accuracy for a wide band signal.

  In addition, the one described in Patent Document 2 is an improved proposal that focuses only on band limitation by a full-wave rectifier, and without using a full-wave rectifier, the positive and negative peaks of a differential input signal are detected by two single-ended comparators. Each is compared and only the logical sum of the comparison results is taken, and the problem of external noise resistance is not solved at all. On the contrary, the accuracy of the newly required level shifter degrades the peak detection accuracy, or the single-ended comparator that was one in the conventional example shown in FIG. For example, two were required, which caused deterioration in detection accuracy and increased circuit scale.

  In addition, the diode clamping method using the diode and the storage capacitor described in Patent Document 3 is, as pointed out in Patent Document 1 described above, a forward voltage drop of the diode or a source follower circuit for correcting the voltage drop. Due to the temperature dependence, bias current dependence, and variation, a differential offset occurs, resulting in an inaccurate differential peak detection voltage. Another problem is that since the time constant until peak detection is completed is determined by the storage capacitor and the circuit bias current, the time constant cannot be easily changed. For example, a reproduction signal of a magnetic disk or an optical disk, for example, has a data rate that changes 2 to 3 times on the inner and outer circumferences of the disk, and further, a reproduction speed, that is, a rotation speed of the disk is changed. Therefore, it is required to set the time constant of the peak detection circuit.

  As described above, the differential signal peak detection is performed as it is, and the resulting DC level signal is also a differential signal, which is a fully differential peak detection circuit, and the peak detection is completed. There has been a demand for a peak detection circuit that can set the time constant up to 10 to 100 times by a simple method.

  In view of such a point, the present invention performs the peak detection for the differential input signal as it is, the resultant DC level signal is also the differential signal, and the time constant until the peak detection is completed. It is an object to provide a differential peak detection circuit that can be easily set.

In order to solve the above-described problems and achieve the object, the present invention detects a magnitude of a differential input signal amplitude, and includes a first transistor in which a positive-phase input signal is input to a gate, and a reverse to the gate. The second transistor to which the phase input signal is input, the third transistor and the fourth transistor that obtain a peak detection differential potential between the gates, the drains of the first and second transistors are connected to the input unit and the third transistor And a current mirror circuit in which the drain of the fourth transistor is connected to the output unit, and an output current signal corresponding to the magnitude relationship between the differential input signal amplitude and the peak detection differential potential is output from the output unit. A first and second current source connected in series and connectable in series; and a third and fourth current source connected in series and connectable; and a gate of the third transistor is connected to the third and fourth current sources. A capacitive element connected to the connection point of the current source and connected to the gates of the third and fourth transistors, wherein the gate of the fourth transistor is connected to the connection point of the first and second current sources; to have a differential charge pump circuit to a load.
The differential charge pump circuit includes a switch that performs an intermittent operation on each current source in accordance with the current direction of the output current signal from the differential comparator circuit, and the switch has a differential input signal amplitude with a peak detection differential. When the potential is smaller than the potential, the first and fourth current sources are connected and the third and second current sources are disconnected. On the other hand, when the differential input signal amplitude is larger than the peak detection differential potential , the third and second current sources are connected. the first and fourth current sources with a current source is connected performs intermittent operation to a non-connected.
A first charging current value set by the first and fourth current sources and a second charging current value in a direction opposite to the first charging current value set by the third and second current sources Depending on the difference, the terminal voltage accumulated in the capacitive element is fed back to the differential comparator circuit. The direction is changed so that the peak detection differential voltage of the differential input signal is obtained at both ends of the capacitive element.

According to such present invention, the difference of a differential comparator circuit for fully differential input by a pair of parallel transistors in which the source and drain commonly connected, and detects the peak value in one of the parallel transistors data The differential charge pump circuit is driven based on the output current signal from the differential comparator circuit corresponding to the input signal. The differential charge pump circuit feeds a charging current based on the output current signal to the capacitive element as a load, feeds back the terminal voltage to the other parallel transistor of the differential comparator circuit, and inputs a differential DC signal. Thereby, in the differential comparator circuit, two differential potentials can be compared with each other, so that the peak detection result can be obtained as a differential signal.

  According to the present invention, it is possible to provide a fully differential peak detection circuit in which a differential signal is input, peak detection is performed as it is, and the resultant DC level signal is also a differential signal. Thus, for example, there is an effect that it is possible to realize a differential peak detection circuit having good resistance to external common mode noise such as substrate noise and power supply noise from a digital circuit block.

  This eliminates the need for additional circuits such as a noise countermeasure circuit and a pseudo peak countermeasure circuit, which have been conventionally required, and can reduce the circuit scale and the total power consumption.

  Furthermore, even when it is necessary to appropriately set the peak detection time constant due to a change in the reproduction rate, such as a magnetic disk or an optical disk, there is an effect that it can be handled very easily by a simple method.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a circuit diagram of an example of an embodiment of the present invention. The circuit of the example of FIG. 1 mainly compares two differential potentials and outputs the result to the outside, and converts an output current signal from the differential comparator circuit 10 into a voltage signal. The current comparator circuit 50 and a signal obtained by smoothing the differential pair input signal are input, and the capacitive element of the load is charged / discharged based on the voltage signal of the current comparator circuit 50, and a differential DC signal is supplied to the differential comparator circuit 10. It comprises a differential charge pump circuit 30 that feeds back and a circuit that smoothes the differential pair input signal.

  In FIG. 1, reference numerals 1 and 2 denote input terminals to which a positive phase input signal and a negative phase input signal of a differential pair input signal are input, respectively. The input terminal 1 is connected to a p-channel MOS transistor (hereinafter simply referred to as “transistor”). And the input terminal 2 is connected to the gate terminal of the transistor 12. The input terminals 1 and 2 are connected to one end of the capacitive element 5 through the resistance elements 4 and 3, respectively, and are connected to the inverting input terminal of the comparator 45. The other end of the capacitive element 5 is connected to the ground.

  Further, the drain terminals of the transistors 11 and 12 are connected in common and connected to the drain terminal of an n-channel MOS transistor (hereinafter simply referred to as “transistor”) 15 which is a low impedance input terminal of the active current mirror circuit 20. The source terminals of the transistors 11 and 12 are connected in common, and are connected to the source terminals of the transistors 13 and 14 paired with these transistors. The drain terminals of the transistors 13 and 14 are connected in common and connected to the drain terminal of the transistor 17 which is a high impedance input terminal of the active current mirror circuit 20. The source terminals of the commonly connected transistors 11 to 14 are connected to the other end of a current source 22 for supplying a predetermined constant current I0. One end of the current source 22 is connected to a terminal 21 to which power is supplied. ing.

  The current mirror circuit 20 includes transistors 15, 16, 17, and 18. The current mirror circuit 20 connects the source terminal of the transistor 15 and the drain terminal of the transistor 16, and connects the source terminal of the transistor 16 to the ground. Similarly, the source terminal of the transistor 17 and the drain terminal of the transistor 18 are connected, and the source terminal of the transistor 18 is connected to the ground. The gate terminals of the transistors 15 and 17 are connected in common and connected to the input terminal 19 to which the input voltage Vb is input. The gate terminals of the transistors 16 and 18 are connected in common and connected to the drain terminal of the transistor 15.

  Then, the output terminal of the current mirror circuit 20 constituting the differential comparator circuit 10 is connected to the input terminal of the current comparator 50 in which two CMOS inverters are connected. That is, the drain terminal of the transistor 17 is connected to the input terminal of the CMOS transistor composed of the transistors 52 and 53. Further, the output terminal of the CMOS transistor composed of the transistors 52 and 53 and the input terminal of the CMOS transistor composed of the transistors 56 and 57 are connected, and the output terminal of the CMOS transistor is connected to the output terminal 58, so that the differential charge pump is connected. A voltage signal Vcp for controlling the circuit 30 is obtained. Further, the input terminal and the output terminal of the CMOS transistor composed of the transistors 52 and 53 are connected via a feedback resistance element 54.

  The differential charge pump circuit 30 is controlled by a capacitive element 41 whose integration capacitance is a load of the differential charge pump, current sources 31, 34, 35, and 38, and an output signal Vcp of the current comparator 50, and each current source. Are provided with switches 32, 33, 36, and 37 that can intermittently supply the current from the power source. For example, MOS switches are mainly used for these switches.

  First, one end of the capacitive element 41 is connected to the gate terminal of the transistor 13 constituting the differential comparator circuit 10, and the other end is connected to the gate terminal of the transistor 14. Further, one end of the current source 31 is connected to a terminal 39 a to which power is supplied, and the other end of the current source 31 is connected to one end of the switch 32. The other end of the switch 32 is connected to the other end of the capacitive element 41 and also connected to one end of the switch 33. Further, the other end of the switch 33 is connected to one end of the current source 34, and the other end is connected to the ground.

  Similarly, one end of the current source 35 is connected to a terminal 39 b to which power is supplied, and the other end of the current source 35 is connected to one end of the switch 36. The other end of the switch 36 is connected to one end of the capacitive element 41 and also connected to one end of the switch 37. Further, the other end of the switch 37 is connected to one end of the current source 38, and the other end is connected to the ground.

  The switches 32 and 37 perform the same opening / closing operation based on the output signal Vcp of the current comparator 50. The switches 33 and 36 operate in reverse to the opening and closing operation of the switches 32 and 37, and are closed when the switches 32 and 37 are simultaneously opened, and are opened when the switches 32 and 37 are simultaneously closed.

  One end of the capacitive element 41 is connected to one end of the resistive element 42, the other end of the capacitive element 41 is connected to one end of the resistive element 43, and the resistive element 42 and the other end of the resistive element 43 are connected. The other ends of the resistance elements 42 and 43 are connected to the ground via the capacitive element 44 and to the non-inverting input terminal 45 of the comparator 45. The comparator 45 compares the two input signals and controls the current values of the current sources 34 and 38 based on the comparison result.

  Next, the operation of the differential peak detection circuit in the example of FIG. 1 will be described with reference to FIGS. FIG. 2 is a diagram showing an example of the static characteristics of the MOS transistor. 3 is a diagram showing waveforms in respective parts of the circuit shown in FIG. 1. A is a differential input signal input to the gates of the transistors 11 and 12, and B is a gate to the transistors 13 and 14, respectively. An input peak detection DC signal, C represents an output current signal from the differential comparator circuit 10, and D represents a voltage signal obtained at the output terminal 58.

  The differential comparator circuit 10 does not compare two single potentials as in the prior art, but compares two differential potentials. For example, a normal phase input signal is input from the input terminal 1 to the gate of the transistor 11 of the differential comparator circuit 10, and a negative phase input signal is input to the gate of the transistor 12 of the input terminal 2 (see FIG. 3A). On the other hand, the detected peak level signal Vpk is obtained between the gate of the transistor 13 and the gate of the transistor 14 which make a pair (see FIG. 3B).

  As shown in FIG. 2, the static characteristics of the MOS transistor are

μ：チャネル中のキャリアの移動度、Ｃox：ゲート酸化膜のキャパシタンス、Ｗ：チャネル幅、Ｌ：チャネル長
である。

μ: carrier mobility in the channel, Cox: capacitance of the gate oxide film, W: channel width, L: channel length.

  Therefore, for example, when the input differential amplitude is 2ΔV, the sum of the drain-source currents of the transistors 11 and 12 is

と表される。つまり、合計電流は同相入力電位による成分と差動入力電位による成分に分解でき、同相入力電位が同じ場合、入力差動電位同士を図１に示す回路で比較できることを示している。

It is expressed. That is, the total current can be decomposed into a component due to the common-mode input potential and a component due to the differential input potential. When the common-mode input potential is the same, the input differential potentials can be compared by the circuit shown in FIG.

For example, as shown in FIG. 3C, in the region where the differential input amplitude between the gates of the transistors 11 and 12 is smaller than the differential DC potential between the gates of the transistors 13 and 14, the differential pair output current of the differential comparator circuit 10. Iout flows in the source direction (right direction in FIG. 1). Conversely, in the region where the differential input amplitude between the gates of the transistors 11 and 12 is larger than the differential DC potential between the gates of the transistors 13 and 14, the sink direction (left in FIG. 1). Direction). Accordingly, the magnitude of the two differential potentials can be compared and determined according to the current direction of Iout, and Iout is set to the CMOS logic level by the current comparator circuit 50 in order to drive the differential charge pump circuit 30 according to the determination result. It converts into a voltage signal (refer FIG. 3D).

  That is, in the region where the differential input amplitude between the gates of the transistors 11 and 12 is larger than the differential DC potential Vpk between the gates of the transistors 13 and 14 (see FIG. 3C), Iout flows in the sink direction, and the output of the current comparator circuit 50 A clock signal is obtained in which the pulse goes low and goes high in other periods. The next-stage differential charge pump circuit 30 is driven by this clock signal, and the integral capacitance of the capacitive element 41 is charged / discharged by the differential charge pump current. At the same time, the voltage across the capacitive element 41 is between the gates of the transistors 13 and 14. The differential DC potential Vpk is fed back to the differential comparator circuit 10.

In the differential charge pump circuit 30, the direction of the current flowing through the capacitive element 41 is switched according to the logic value of the clock signal of the current comparator circuit 50. In the example of FIG. 1, when the differential input amplitude between the gates of the transistors 11 and 12 is larger than the differential DC potential Vpk between the gates of the transistors 13 and 14, the current sources 34 and 35 are enabled (connected) by the switches 33 and 36. At the same time, the current sources 31 and 38 are disabled (not connected) by the switches 32 and 37. As a result, the gate potential of the transistor 13 is increased, and the integration capacitance of the capacitor 41 is decreased in the direction of decreasing the gate potential of the transistor 14. Charge.

On the contrary, when the differential input amplitude between the gates of the transistors 11 and 12 is smaller than the differential DC potential Vpk between the gates of the transistors 13 and 14, the current sources 34 and 35 are disabled by the switches 33 and 36 . The current sources 31 and 38 are enabled by the switches 32 and 37. As a result, the gate potential of the transistor 13 is lowered, and the integration capacitor of the capacitor 41 is charged in the direction of raising the gate potential of the transistor 14. Here, at least in the steady state, the current values of the current sources 34 and 35 are equal (I2 = I3), and the current values of the current sources 31 and 38 are equal (I1 = I4).

  Here, in the example of FIG. 1, the charge pump current (I2 and I3 in FIG. 1) when the output pulse obtained at the output terminal 58 of the current comparator circuit 50 is a low pulse is the charge pump current (FIG. 1). Is set to be 10 times, for example, 10 times, so that the differential DC level signal Vpk as the peak detection result becomes equal to the differential input amplitude between the gates of the transistors 11 and 12. It takes. Specifically, since the current integrated values of the charge pump currents I2 and I3 and the current integrated values of I1 and I4 are fed back to each other, as a result, I1 (= I4) / I2 (= I3) The current ratio is the ratio of low pulse to high pulse.

  Note that the charge pump current ratio when the output pulse is a low pulse and a high pulse is not limited to this example. For example, the peak detection differential DC potential is set to a peak amplitude of the differential input signal as the output pulse becomes larger, for example, 20 times. The value can be kept constant at a value close to, and a more accurate peak detection result can be obtained.

  The resistive elements 3 and 4 and the resistive elements 42 and 43 detect the common-mode potential of the differential input signal and the common-mode potential superimposed with the differential direct-current level signal Vpk as the peak detection result, respectively. This is a so-called common-mode feedback circuit that applies negative feedback to the charge pump current so that the common-mode potential superimposed with the level signal Vpk is equal to the common-mode potential of the input signal. In the example of FIG. 1, feedback is applied from the comparator 45 to the current source 34 and the current source 38, and the current I2 of the current source 34 or the current I4 of the current source 38 is changed as necessary. In the present embodiment, the common-mode potential of the differential DC potential of the capacitor 41 is used as the average voltage of the differential input signal in order to make it easier to use the static characteristics of the MOS transistor described in FIG.

  Regarding this mechanism, various methods have been proposed in relation to the differential charge pump circuit, and can be applied to the differential charge pump circuit which is a component of this example as it is. Thus, with respect to the implementation of the present invention, the example of FIG. 1 does not limit the way in which common mode feedback is implemented.

  In the example of FIG. 1, the time constant for peak detection is determined by the charge pump current and the differential integration capacitance. Here, since the set current value of the charge pump current can be easily changed, it is very easy to appropriately change the setting of the peak detection time constant according to the reproduction data rate.

  Further, a switch (not shown) that short-circuits both terminals of the capacitive element 41, that is, a switch that can be opened and closed in parallel with the capacitive element 41 is connected. Prior to the peak detection sequence, the switch is closed, and the differential integration capacitance of the capacitive element 41 is once discharged / reset. In this case, for example, when an abnormal capacity is accumulated in the capacitor 41, an abnormal voltage is applied to the transistors 13 and 14, and the input signal is cut off. It can be operated normally while avoiding the state of not operating.

  According to the example of the embodiment described above, in the differential peak detection circuit having the differential signal as an input, the peak detection is performed as the differential signal, and the resulting DC level signal is also a differential signal. A differential peak detection circuit can be provided. As a result, a differential peak detection circuit having good resistance to external common mode noise such as substrate noise and power supply noise from the digital circuit block can be realized.

  This eliminates the need for additional circuits such as a noise countermeasure circuit and a pseudo peak countermeasure circuit, which have been conventionally required, and enables reduction in circuit scale and total power consumption.

  Furthermore, it is possible to cope with a case where it is necessary to appropriately set the peak detection time constant by changing the reproduction rate, such as a magnetic disk or an optical disk.

  Note that even if the polarity of the n-channel and the p-channel of each transistor in the example of FIG. 1 is switched, a circuit having the same function can be configured, and the same effect can be obtained.

  Further, the present invention is not limited to the above-described embodiments, and various other configurations can be taken without departing from the gist of the present invention.

It is a circuit diagram which shows the example of one embodiment of this invention. It is a diagram which shows an example of a MOS transistor static characteristic. It is a diagram which shows the waveform of the circuit shown in FIG. It is a figure which shows the example of the conventional peak detection circuit. It is a diagram which shows the waveform of each part of the peak detection circuit shown in FIG.

Explanation of symbols

  1, 2, 19 ... input terminals, 3, 4, 42, 43, 54 ... resistance elements, 5, 41, 44 ... capacitive elements, 10 ... differential comparator circuits, 11, 12, 13, 14, 52, 56 ... n-channel MOS transistor, 15, 16, 17, 18, 53, 57 ... p-channel MOS transistor, 58 ... output terminal, 20 ... current mirror circuit, 22, 31, 34, 35, 38 ... current source, 30 ... charge pump Circuit, 32, 33, 36, 37 ... switch, 45 ... comparator, 50 ... current comparator circuit

Claims (5)

A differential peak detection circuit for detecting the magnitude of a differential input signal amplitude,
A first transistor in which a positive phase input signal is input to the gate; a second transistor in which a negative phase input signal is input to the gate; a third transistor and a fourth transistor that obtain a peak detection differential potential between the gates; The drains of the first and second transistors are connected to the input unit, and the drains of the third and fourth transistors are connected to the output unit. The magnitude relationship between the differential input signal amplitude and the peak detection differential potential A differential comparator circuit including a current mirror circuit that outputs an output current signal according to the output unit,
First and second current sources connected in series and interruptible, and third and fourth current sources connected in series and interruptable, the gate of the third transistor being connected to the third and fourth current sources A capacitive element connected to the middle point and connected to the gates of the third and fourth transistors, wherein the gate of the fourth transistor is connected to the connection middle point of the first and second current sources, is loaded. A differential charge pump circuit
The differential charge pump circuit includes a switch that performs an intermittent operation on each current source corresponding to a current direction of the output current signal from the differential comparator circuit, and the switch has an amplitude of the differential input signal of the differential charge pump circuit. When smaller than the peak detection differential potential, the first and fourth current sources are connected and the third and second current sources are disconnected, while the differential input signal amplitude is greater than the peak detection differential potential. big time performs the intermittent operation to a non-connecting said first and fourth current sources with connecting the third and second current sources,
The difference between the first charging current value set by the first and fourth current sources and the second charging current value in the opposite direction to the first charging current value set by the third and second current sources In response, the terminal voltage accumulated in the capacitive element is fed back to the differential comparator circuit,
As a result of the feedback, the direction of the differential charging current flowing through the capacitive element is changed according to the magnitude relationship between the differential input signal and the peak detection differential potential, and peak detection of the differential input signal is performed at both ends of the capacitive element. Get differential voltage
Differential peak detector circuit. A current comparator circuit having a configuration in which the input / output terminals of the CMOS inverter are connected by a resistance element;
The output current signal output from the differential comparator circuit is converted into a voltage signal, and the switch is intermittently operated with respect to the first, second, third and fourth current sources of the differential charge pump circuit by the voltage signal. Control
Differential peak detector circuit 請 Motomeko 1 wherein. The difference between the first charging current value and the second charging current value is 10 times or more.
Differential peak detector circuit 請 Motomeko 1 wherein. The common-mode potential of the peak detection differential potential obtained between the gates of the third and fourth transistors is the average value voltage of the differential input signal.
Differential peak detector circuit 請 Motomeko 1 wherein. A switch for short-circuiting both ends of the capacitive element is provided.
Differential peak detector circuit 請 Motomeko 1 wherein.

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