JP4997453B2 - MOS transistor circuit using double insulated gate field transistor and CMOS transistor circuit, SRAM cell circuit, CMOS-SRAM cell circuit, integrated circuit using the same - Google Patents

Description

  The present invention relates to a double insulated gate field effect transistor, particularly a MOS transistor circuit using a four-terminal double insulated gate field effect transistor, and a CMOS transistor circuit, SRAM cell circuit, CMOS-SRAM cell circuit and integrated circuit using the same. About.

In general, in a MOS integrated circuit (see Patent Document 2 below) using an insulated gate field effect transistor (MOST) (see Patent Document 1 below), in order to improve performance (improvement of operation speed, expansion of integration scale, etc.) MOST element dimensions have been miniaturized. At the same time, power supply voltage has been lowered in order to prevent a reduction in reliability due to the limit of withstand voltage and to reduce power consumption. Increasing the operating speed and reducing the power consumption are contradictory events, but reducing the so-called threshold voltage of MOST can improve the operating speed and satisfy them simultaneously. However, a decrease in threshold voltage causes an increase in leakage current when the MOST is off. That is, so-called standby power consumption or steady power consumption increases. Conventionally, this standby power consumption or steady state power consumption was sufficiently small compared with the operating power consumption and could be ignored.However, as the miniaturization progressed, the standby power consumption increased exponentially, Expected to be about the same as power consumption during operation. Therefore, there has been a concern that the operation speed cannot be improved.
JP 2002-270850 A JP 2003-163356 A

As a solution to the above problems, a MOST having a different threshold voltage has been prepared in the past, and an element having a high threshold voltage is used for a circuit in a portion where the operation speed may be slow, so that it operates at high speed. The circuit portion that must be used has been to use an element having a low threshold voltage. In an integrated circuit with a fixed function, a circuit portion that normally has to operate at high speed is often a small percentage of the integrated circuit as a whole, and this method can solve the problem to some extent. However, when further speeding up the entire integrated circuit, the low-speed part must be made faster, and the increase in power consumption due to leakage current cannot be ignored, and a small part of the high-speed circuit is consumed in steady state. Even an increase in power and standby power consumption may not be ignored. In FPGA (Field Programmable Gate Array) that dynamically changes the circuit configuration, it is difficult to assign a plurality of fixed threshold voltages as in this method.
On the other hand, in a four-terminal double insulated gate field effect transistor that is different from the conventional element structure, in the three-terminal operation in which two gate electrodes are connected, the change in the drain current with respect to the gate voltage from the off state to the on state is the conventional element. Even when the threshold voltage is smaller than that of the conventional device, the standby leakage current can be made smaller than that of the conventional device. Alternatively, if the same leakage current is allowed, a lower threshold voltage can be set, and a higher speed operation than the conventional device is possible. However, when further miniaturization is attempted such that the power supply voltage is 1 V or less, it is required to further reduce the threshold voltage, and the same problems as in the conventional device arise.
The four-terminal double insulated gate field effect transistor has a feature that the threshold voltage seen from one gate to which an input signal is applied can be controlled by the potential of the other gate electrode. By using this fact, a method is considered in which the threshold voltage is lowered in a high-speed circuit, and a high threshold voltage is set for other parts that are good at a low speed. However, on the other hand, the change in drain current with respect to the gate voltage from the off state to the on state becomes duller than in the three-terminal operation, so that there is a disadvantage that the leakage current increases when the threshold voltage is lowered for high-speed circuits. Therefore, an increase in steady state power consumption and standby power consumption in the circuit portion where the threshold voltage is set low is still a problem.

  The object of the present invention is to eliminate the above-mentioned drawbacks, and to operate the unit circuit at high speed and not in use (a MOS transistor group to which a power supply voltage is applied but not used in a desired circuit configuration) or at a steady state or To provide a MOS transistor circuit using a double insulated gate field transistor that achieves both reduced power consumption during standby, and a CMOS transistor circuit, SRAM cell circuit, CMOS-SRAM cell circuit, and integrated circuit using the same. .

  Leakage current is a problem at steady state or standby time, so the threshold voltage is reduced only in the transient state and dynamically controlled to increase the threshold voltage in other states to solve this problem. it can. Even if the threshold voltage is actually reduced for high speed, the leakage current can be reduced by two orders of magnitude or more compared to the on-state current, and the transient state time is usually shorter than the steady state time. The time when the increase in leakage current becomes a problem is even shorter. Therefore, the increase in power consumption due to the increase in leakage current in a transient state can be made sufficiently smaller than the overall power consumption. The conventional method of dynamically adjusting the threshold voltage is a method of adjusting the time including the steady state. In this case, since the leakage current in the steady state remains increased, the increase in power consumption due to the leakage current cannot be suppressed.

In the present invention, the above object is achieved by the following configuration.
Of the two gates of the four-terminal double insulated gate field effect transistor, one gate is used as a signal input terminal, one end of a resistor is connected to the other gate, and the other end is connected to a power source having a constant potential. In the above structure, one gate and the other gate are connected by an external capacitor. In the above configuration, one end of the external capacitor is further connected to the other gate to which one end of the resistor is connected, and the other end is connected to a pulse power source such as a clock power source. Whether a CMOS transistor circuit is configured using an N-type four-terminal double insulated gate field effect transistor and a P-type four-terminal double insulated gate field effect transistor, and the above configuration is used for the N-type four-terminal double insulated gate field effect transistor. Alternatively, the above configuration is used for a P-type four-terminal double insulated gate field effect transistor, or the above configuration is used for both. Furthermore, this power supply A (not a constant voltage power supply, for example, a pulse power supply is used to increase the voltage during operation and to decrease the voltage during standby, etc., thereby making the voltage value variable in time and controlling the threshold voltage. The power supply for reducing power consumption during standby) is set to a potential that decreases the threshold voltage during operation, while the threshold voltage increases in the steady state, standby, or when not in use. It is dynamically variable so as to be a potential. Further, these are dynamically variable by synchronizing with the clock.

More specifically, it is as follows.
(1) One gate is an input terminal, the other gate is connected to one end of a resistor connected to the second power source, the source is connected to the first power source, and the drain is the output terminal. One conductivity type four-terminal double insulated gate field effect transistor, one gate as an input terminal, the other gate connected to one end of a resistor connected to the fourth power source, and the source connected to the third A four-terminal double-insulated gate field effect transistor of the second conductivity type opposite to the first conductivity type using the drain as an output terminal, and using one of the gates as an input terminal. A CMOS transistor circuit is formed by connecting the drains as output terminals.

(2) Two CMOS transistor circuits described in (1 ) above are provided, and the input terminal of one circuit is connected to the output terminal of the other circuit, and the input terminal of the other circuit is connected to the output terminal of one circuit, respectively. Each output terminal is a CMOS-SRAM cell circuit in which the source or drain of a pass transistor made of an insulated gate field effect transistor is connected.

The load element of each circuit is an insulated gate field effect transistor or a MOS transistor circuit having a resistor.
In the above MOS transistor circuit or SRAM cell circuit, a part or all of the potentials of one or a plurality of the third power supplies are dynamically changed.
In the MOS transistor circuit, a load element is a four-terminal double insulated gate field effect transistor having a conductivity type opposite to that of the four-terminal double insulated gate field effect transistor, or an insulated gate field effect transistor having an opposite conductivity type. Is connected to the one gate of the four-terminal double insulated gate field effect transistor.

(3) The pass transistor is a four-terminal double insulated gate field effect transistor, each one of the gates is connected to a cell selection line, and each of the other gate electrodes is connected to a respective threshold voltage control power source. The CMOS-SRAM cell circuit according to the above (2), which is connected to the CMOS .

(4) One connection point of a parallel connection circuit in which a plurality of four-terminal double insulated gate field effect transistors according to claim 10 of the first conductivity type are connected in parallel is defined as a second conductivity opposite to the first. The same number of four-terminal double insulated gate field effect transistors as claimed in claim 10 are connected to one end of a series connection circuit connected in series to form an output terminal, and the other end of the series connection circuit is a first terminal. Connected to a power source, the other end of the parallel connection circuit is connected to a second power source, and each one gate of the four-terminal double insulated gate field effect transistors of a plurality of first conductivity types is a plurality of Each of the corresponding four-terminal double insulated gate field effect transistors of the second conductivity type is electrically connected to the corresponding one of the gates to form the same number of input terminals, and a plurality of the first conductivity types of the four-terminal double insulated gate field effect transistors. Four terminal double insulated gate field effect transistor And the other end of each resistor connected to the other gate of each of the four terminal double insulated gate field effect transistors of the second conductivity type. A multi-input CMOS transistor circuit is connected to a plurality of third and fourth power supplies each having a constant potential.
(5) In the CMOS transistor circuit according to any one of (1) to (4), means for dynamically controlling the potential of the third power supply or the fourth power supply connected through the resistors. A CMOS transistor circuit provided with
(6) An integrated circuit including the circuit described in any one of (1) to (5 ) above .

  The four-terminal double insulated gate field effect transistor as referred to in the present invention is a so-called double gate field effect transistor or double gate MOS transistor, and is an element having a structure in which two gate electrodes are electrically independent. . The threshold voltage seen from the other gate can be controlled by the potential of one gate electrode. The channel is formed on the semiconductor surface facing each gate. However, when the potentials of both gates are lower than the threshold voltage, the channel is not formed on each semiconductor surface.

FIG. 1 shows a first embodiment of the present invention. In the figure, Rg is a resistor connected to the other gate of the four-terminal double insulated gate field effect transistor, and Vtc is a power source having a constant potential and is connected to the resistor. VSS and VDD are power supplies, respectively. The drain of the four-terminal double insulated gate field effect transistor is connected to the power supply VDD through the load element Load.
Therefore, consider a circuit configuration in which the gate 1 is a signal input terminal as shown in FIG. 1, the resistor Rg is connected to the gate 2, and the other end of Rg is connected to the power supply VSS through the power supply Vtc having a constant potential, for example.

FIG. 2 shows an equivalent circuit when the other gate is viewed from one gate which is the input terminal of the four-terminal double insulated gate field effect transistor of the embodiment of FIG.
Since no channel is formed, it can be considered that the gate insulating film capacitors Cg1 and Cg2 and the semiconductor capacitor Csi sandwiched between the gates 1 and 2 are connected in series as shown in FIG. It can be considered that a so-called differentiation circuit is configured. Then, the potential of the gate 2 is obtained by differentiating the input signal of the gate 1.
FIG. 3 is an equivalent circuit of FIG. 2 and schematically shows a waveform (FIG. 3B) appearing at the gate 2 when a rectangular wave input (FIG. 3A) is given to the gate 1. FIG.

  If the input signal is a rectangular wave and the time change of the potential of the gate 2 is schematically shown in FIG. Therefore, assuming an N-type four-terminal double insulated gate field effect transistor, the rising portion of the input signal is the direction in which the channel 1 is formed on the semiconductor surface facing the gate 1, that is, the transistor is turned on. The falling part disappears channel 1, that is, turns the transistor off. Looking at the change in the potential of the gate 2, the threshold voltage is reduced in the direction in which the transistor is turned on, and thus the threshold voltage is turned on earlier and the threshold is turned off in the off direction. It acts to increase the value voltage and thus to turn off earlier. The working time and peak value can be adjusted by the time constant depending on the resistance and capacitance, but the capacitance is determined by the structure of the four-terminal double insulated gate field effect transistor, so the value of the resistance Rg is adjusted. . The peak value does not change if an ideal input waveform has a transient time of zero, but usually has a positive value of the transient time, and therefore changes with a time constant. If the time constant is small, the peak value tends to be small. Furthermore, in the steady state, the potential is constant, in this case VSS + Vtc, and the threshold voltage of the transistor when this potential is applied to the gate 2 is appropriately increased within a range that does not hinder the on / off operation. If it is set so that the leakage current is sufficiently low when the potential of the gate 1 turns off the transistor, the power consumption in the steady state can be sufficiently reduced. That is, it is possible to simultaneously realize high-speed operation and reduction of power consumption during normal operation or standby.

  If you want to increase speed even at the expense of some reduction in power consumption due to leakage current, or conversely, the threshold voltage is sufficiently high, but if the leakage current is large, The value of the power supply Vtc at the other end of Rg is set to a potential that lowers the threshold voltage in the former case, and is set to a potential that increases the threshold voltage in the latter case. The same effect can be obtained by adjusting the threshold voltage. In this case, the steady-state value of the differential waveform applied to the gate 2 is a constant potential as shown in FIG. 3 and VSS + Vtc, so that the speed-up effect on the ON side and the OFF side is different. Both are faster than the case. Furthermore, this potential is dynamically controlled, for example, the potential is set so that the threshold voltage becomes extremely high when not in use, and is set to a threshold voltage suitable for operation when in use (see the description regarding the power supply A above). For example, it is possible to more effectively realize both high-speed operation and reduction of power consumption due to leakage current.

The peak value of the differential waveform shown in FIG. 3 is ideally the peak value of the input waveform, but actually, channel 1 starts to form facing gate 1 before that, so that the shielding effect causes gate 1 to gate 2 to be formed. Is not visible electrically. In other words, since the gate 1 is not electrically visible from the gate 2, the peak value is kept low.
FIG. 4 shows a second embodiment of the present invention. An external capacitor Cgg is further connected to the gate 2 of the four-terminal double insulated gate field effect transistor of FIG. 1, and the other end of Cgg is connected to the gate 1.
In this case, as shown in FIG. 4, the gate 1 and the gate 2 can be connected by an external capacitor Cgg to reduce this phenomenon.
FIG. 5 shows a third embodiment of the present invention. An external capacitor Cck is further connected to the gate 2 of the four-terminal double insulated gate field effect transistor of FIG. 1, and the other end of Cck is connected to a clock or pulse power source.
Further, when the operation is synchronized with the clock, the above phenomenon can be reduced by connecting the gate 2 to the clock power supply by the external capacitor Cck as shown in FIG. It is ideal if it can be connected to a pulse power source whose potential changes from the steady value for the transient time, for example, a pulse power source that changes so that the threshold voltage decreases on the ON side and increases on the OFF side.

1 shows a first embodiment of the present invention. The equivalent circuit when the other gate is seen from one gate which is the input terminal of the four-terminal double insulated gate field effect transistor of the embodiment of FIG. 1 is shown. In the equivalent circuit of FIG. 2, a waveform that appears at the gate when a rectangular wave input is given to the gate 1 is schematically shown. It is a 2nd Example of this invention. It is a 3rd Example of this invention. It is a 4th example of the present invention. It is a 5th example of the present invention. It is a 6th example of the present invention. It is a 7th example of the present invention. The eighth embodiment of the present invention is an example of a multi-input gate circuit. The ninth embodiment of the present invention is another example of the multi-input gate circuit. It is a 10th example of the present invention. This is an eleventh embodiment of the present invention. It is a twelfth embodiment of the present invention. The thirteenth embodiment of the present invention is an example of a multi-input CMOS gate circuit.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

A first embodiment of the present invention is shown in FIG.
FIG. 1 shows a first embodiment of the present invention. In the figure, Rg is a resistor connected to the other gate of the four-terminal double insulated gate field effect transistor, and Vtc is a power source having a constant potential and is connected to the resistor. VSS and VDD are power supplies, respectively. The drain of the four-terminal double insulated gate field effect transistor is connected to the power supply VDD through the load element Load.
N-type or P-type may be used. Of the two gates of the four-terminal double insulated gate field effect transistor, gate 1 is used as an input terminal, gate 2 is connected to one end of resistor Rg, and the other end of the resistor is connected to a constant potential power source. It is connected to the power source VSS through Vtc. Further, the source is connected to VSS, and the drain is connected to the power supply VDD through the load element Load. This circuit acts as an inverter circuit having the gate 1 as an input terminal.
FIG. 4 shows a second embodiment. In addition to the configuration of FIG. 1, one end of the external capacitor Cgg is further connected to the gate 2 of the four-terminal double insulated gate field effect transistor, and the other end is connected to the gate 1. By adding the external capacitance Cgg, a channel starts to be formed, and accordingly, the gate 1 and the gate 2 start to be electrically separated, thereby preventing the peak value of the differential waveform appearing at the gate 2 from being lowered.

FIG. 5 shows a third embodiment. In addition to the configuration of FIG. 1, one end of an external capacitor Cck is further connected to the gate 2 of the four-terminal double insulated gate field effect transistor, and the other end is a clock or pulse power supply Vck. The differential waveform synchronized with the clock is induced in the gate 2.
FIG. 6 shows a fourth embodiment of the present invention. Two sets of the circuit shown in FIG. 1 are prepared, one output is connected to the other output to form the memory portion of the SRAM cell circuit, pass transistors PT1 and PT2 are connected to each output terminal, and the other ends are bit lines. This is an SRAM cell circuit connected to BL1 and BL2, and further connected to the row selection line WL at the gates of PT1 and PT2.
EXAMPLE Two four-terminal double insulated gate field effect transistors of FIG. 1 are prepared, one input terminal is connected to the other output terminal, and the drains or sources of the pass transistors PT1 and PT2 are connected to the respective output terminals. The other end of the source or drain is connected to the bit lines BL1 and BL2, and the gate of the pass transistor is connected to the row selection line WL. Furthermore, the drain or output terminal of each four-terminal double insulated gate field effect transistor is connected to the power supply VDD through load elements Load1 and Load2, respectively, and the respective potentials of the power supply Vtc1 and the constant potential through resistors Rg1 and Rg2, respectively. A so-called SRAM cell circuit is configured by being connected to Vtc2 and further to the power source VSS. Also in this case, the effect of Rg1 and Rg2 changes the state at a high speed, and an increase in power consumption due to a leakage current is reduced in a steady state or during standby.

FIG. 7 shows a fifth embodiment of the present invention. Two sets of the circuit shown in FIG. 4 are prepared, one output is connected to the other output to form the memory portion of the SRAM cell circuit, pass transistors PT1 and PT2 are connected to each output terminal, and the other ends are bit lines. This is an SRAM cell circuit connected to BL1 and BL2, and further connected to the row selection line WL at the gates of PT1 and PT2.
FIG. 8 shows a sixth embodiment of the present invention. Two sets of the circuit shown in FIG. 5 are prepared, one output is connected to the other output to form the memory portion of the SRAM cell circuit, pass transistors PT1 and PT2 are connected to each output terminal, and the other ends are bit lines. This is an SRAM cell circuit connected to BL1 and BL2, and further connected to the row selection line WL at the gates of PT1 and PT2.

  FIG. 9 shows a seventh embodiment. In the SRAM cell circuit in the fourth to sixth embodiments, the pass transistors PT1 and PT2 are four-terminal double insulated gate field effect transistors, and each gate 1 is connected to the WL line. The gates 2 are connected to the threshold voltage control power sources VPT1 and VPT2, respectively. That is, the threshold voltage is set low during cell selection to perform high-speed operation, and the threshold voltage is set high during standby to reduce leakage current through the pass transistor. In an integrated circuit, even if it is a constant potential power supply, it is supplied through a power supply line, so there may be some dynamic fluctuation due to mixing of pulse noise, etc. It is called a constant potential power source. The same applies hereinafter.

  FIG. 10 shows an eighth embodiment in which a plurality of four-terminal double insulated gate field effect transistors in the embodiment of FIG. 1 are connected in series (two in the figure, indicated by T1 and T2), and one end is connected to a power source. Connected to VSS, the other end as an output terminal, and connected to the power supply VDD through the load element Load, and a plurality of input terminals are configured with one of the gates of T1 and T2 as an input terminal, and the resistors Rg1 and Rg2 are connected. Each of the other gates is a so-called positive logic NAND circuit connected to power sources Vtc1 and Vtc2 having a constant potential. In general, in the NAND circuit, when T1 is turned off and T2 is turned on in the previous operation, the connection point between T1 and T2 is at a high level. This state continues for a while due to the influence of stray capacitance, etc., but when a signal for turning on T1 and turning on T2 is input in this state, it takes time until T1 is turned on, and there is a risk that a correct output is delayed. There is. However, the circuit shown in FIG. 10 has the effect of accelerating the operation of T1 by acting so that T1 can be turned on even by the gate 2 by the differential circuit composed of the gate capacitance of Rg1 and T1. Note that even when a plurality of four-terminal double insulated gate field effect transistors in the embodiment of FIGS. 4 and 5 are used, a circuit similar to that of FIG.

FIG. 11 shows a ninth embodiment in which a plurality of four-terminal double insulated gate field effect transistors in the embodiment of FIG. 1 are connected in parallel (two in the figure, indicated by T1 and T2) and connected in common. One end is connected to the power supply VSS, the other end is connected to the power supply VDD through the load element Load, and a plurality of input terminals are formed with one gate of T1 and T2 as input terminals, The other gates to which Rg1 and Rg2 are connected are so-called positive logic NOR circuits respectively connected to power sources Vtc1 and Vtc2 having a constant potential. Note that even when a plurality of four-terminal double insulated gate field effect transistors in the embodiments of FIGS. 4 and 5 are used, a circuit similar to that in FIG. 11 can be configured, and similar effects can be obtained.
FIG. 12 shows a CMOS inverter circuit according to the tenth embodiment, in which the load element Load of FIG. 1 is a four-terminal double insulated gate field effect transistor T2 having a conductivity type opposite to that of T1. In this case, the gate 1 and the gate 2 of the four-terminal double insulated gate field effect transistor of T2 are connected and used as a three-terminal double insulated gate field effect transistor, so that this is used as usual. May be replaced with a three-terminal double insulated gate field effect transistor connected in advance or a normal insulated gate field effect transistor. In this circuit, T2 is off when T1 is on, but the leakage current at this time is determined by the leakage current of T2. The effect of reducing power consumption is reduced. However, if this is done, the operating speed becomes slower by the increase in the threshold voltage, and both must be adjusted. The same effect can be obtained by replacing the load element Load in FIGS. 4 to 11 with a four-terminal double insulated gate field effect transistor having a conductivity type opposite to that of T1.

  A configuration example in which the above embodiment is further improved is an eleventh embodiment shown in FIG. 13, which is a CMOS inverter circuit in which the load element Load is a four-terminal double insulated gate field effect transistor T2 having a conductivity type opposite to that of T1. In this case, one of the gates of T1 and T2 is connected to serve as an input terminal, and the other gate is connected to resistors Rg1 and Rg2, and further connected to power sources VSS and VDD through power sources Vtc1 and Vtc2 having a constant potential, respectively. ing. The connection point between T1 and T2 is an output terminal. In this case, Tg has the same effect as T1 due to Rg2, and even in the CMOS transistor circuit, there is little leakage current in the steady state, and both high-speed operation and compatibility can be achieved during operation. The configuration is the same as that of the four-terminal double insulated gate field effect transistor shown in the embodiments of FIGS. 1, 4 and 5, but is the same as the configuration of the four-terminal double insulated gate field effect transistor of the opposite conductivity type. The same effect can be obtained even if they are configured in the same manner using each as a load element. Moreover, you may use combining these freely. This configuration method can also be applied to the load elements of the embodiments shown in FIGS.

FIG. 14 shows a twelfth embodiment of the present invention. Two sets of the circuit shown in FIG. 13 are prepared, one output is connected to the other output to form the memory portion of the SRAM cell circuit, pass transistors PT1 and PT2 are connected to each output terminal, and the other ends are bit lines. This is an SRAM cell circuit connected to BL1 and BL2, and further connected to the row selection line WL at the gates of PT1 and PT2.
FIG. 15 shows an example of a multi-input CMOS gate circuit according to the thirteenth embodiment of the present invention. A plurality of four-terminal insulated gate field effect transistors in FIG. 1 (two in the figure, T1 and T2) are prepared, these are connected in series, one end is connected to the power supply VSS, and the other end is an output terminal. There are also the same number of four-terminal insulated gate field effect transistors (two in the figure, T3 and T4) of the opposite conductivity type, which are connected in parallel, one end connected to the output terminal, and the other Is connected to the power supply VDD. Furthermore, the gates 1 of T1 and T3 are connected to each other as an input terminal 1, and the gates 1 of T2 and T4 are connected to each other as an input terminal 2 to constitute a multi-input CMOS gate circuit. A similar circuit can be configured by switching the series and parallel connections, and another logic operation can be performed.

T1, T2: Four-terminal insulated gate field effect transistors T3, T4: Four-terminal insulated gate field effect transistors PT1, PT2 of opposite conductivity type: Pass transistors Load, Load1, Load2: Load elements Rg, Rg1, Rg2, Rg3, Rg4: Resistors Cg1, Cg2, Csi, Cgg, Cck, Cgg1, Cgg2, Cck1, Cck2: Capacitance VDD, VSS: Power supply Vtc, Vtc1, Vtc2, Vtc3, Vtc4: Power supply or dynamically variable power supply BL1, BL2: Bit line WL: Row selection line

Claims (3)

One gate is the input terminal,
Connect one end of the resistor with the other end connected to the second power supply to the other gate,
Connect the source to the first power source,
A four-terminal double insulated gate field effect transistor of the first conductivity type with the drain as the output terminal;
One gate is the input terminal,
Connect one end of the resistor with the other end connected to the fourth power supply to the other gate,
Connect the source to a third power source
A four-terminal double insulated gate field effect transistor of the second conductivity type opposite to the first conductivity type with the drain as an output terminal;
Two CMOS transistor circuits are provided in which both the gates are connected as input terminals and the drains are connected as output terminals ,
The input terminal of one circuit is connected to the output terminal of the other circuit, the input terminal of the other circuit is connected to the output terminal of one circuit, and each output terminal is a path comprising an insulated gate field effect transistor. In a CMOS-SRAM cell circuit in which the source or drain of a transistor is connected,
The pass transistor is a four-terminal double insulated gate field effect transistor, each one of the gates is connected to a cell selection line, and each of the other gate electrodes is connected to a respective threshold voltage control power source. And a CMOS-SRAM cell circuit. 2. The CMOS- SRAM cell circuit according to claim 1, further comprising means for dynamically controlling the potential of the second power source or the fourth power source connected through the resistors. . 請 Motomeko 1 to the integrated circuit, characterized in that consisted circuit according to any one of 2.