JP2011096950A - Semiconductor device, sense amplifier circuit, method of controlling semiconductor device, and method of controlling sense amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device etc., capable of having excellent characteristics by suitably controlling a back gate voltage of a functional circuit using a double-gate transistor, and a method of controlling the same. <P>SOLUTION: The semiconductor device includes the functional circuit including the double-gate transistor, and a voltage control circuit including reference transistors 20 and 30 having a double-gate structure. The reference transistors 20 and 30 are applied with reference voltages Vrp and Vrn at first gate electrodes, potentials of second gate electrodes are so controlled that drain currents Ip and In match reference currents Irp and Irn, and those potentials are output as control voltages VBGP and VBGN. The control voltages VBGP and VBGN are applied to second gate electrodes of the double-gate transistor of the functional circuit to impart desired characteristics to the functional circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a functional circuit using a double gate transistor, a sense amplifier circuit using a double gate transistor, and a method for controlling the semiconductor device and the sense amplifier circuit.

  Conventionally, when controlling a double gate MOSFET provided with two gate electrodes (front gate and back gate) facing each other across a channel region, the threshold voltage of the front gate is changed by controlling the back gate voltage. It has been known. An example of the structure of such an independently controlled double gate (IDG) MOSFET will be described with reference to FIG. FIG. 17A is a diagram showing a general circuit symbol of a double-gate MOSFET, and shows a double-gate MOSFET having two gate electrodes, a front gate FG and a back gate BG, and a source S and a drain D. Has been. FIG. 17B is a diagram showing an SOI-MOSFET structure applied to a double gate MOSFET, and FIG. 17C is a diagram showing a FinFET structure applied to a double gate MOSFET. In the structure of FIG. 17B, the source S and drain D are formed in the upper region of the insulating film 101 on the silicon substrate 100, and one gate electrode (front) is sandwiched between the gate dielectric film 102 and the upper portion of the channel region. Gate FG) is formed, and the lower region of the silicon substrate 100 becomes the other gate electrode (back gate BG). In the structure of FIG. 17C, a Fin having a source S and a drain D is provided on the insulating film 103, and two independent gate electrodes are formed on both sides of the gate dielectric 104, One functions as a front gate FG and the other functions as a back gate BG. Specific examples to which the configuration using the double gate MOSFET and the control method are applied are disclosed in various prior documents (for example, see Non-Patent Document 1 and Patent Documents 1, 2, 3, and 4).

  Non-Patent Document 1 discloses a technique for controlling a threshold voltage by a back gate voltage for an IDG-MOSFET having an N-type FinFET structure. According to the technique disclosed in Non-Patent Document 1, when the back gate voltage is 0 V, the threshold voltage becomes a negative voltage (depletion), and a large drain current flows with respect to the front gate voltage. It is shown that when the gate voltage is lowered to a negative voltage (−1V), the threshold voltage becomes almost 0V and the drain current flowing with respect to the front gate voltage decreases. The same control is possible for the IDG-MOSFET having the P-type FinFET structure by the reverse voltage polarity.

  Patent Document 1 describes that the threshold voltage of the MOSFET to be controlled can be controlled to an optimum value during operation and standby according to the back gate voltage. Patent Document 2 discloses a method for controlling the back bias voltage of a MOSFET constituting a circuit block. According to this control method, the above-described back bias voltage is independently and statically controlled by the master control block for each circuit block of the circuit block group that transitions between the operating state and the standby state. Patent Document 3 discloses a technique for always keeping the threshold voltage of a pair of MOSFETs constituting a sense amplifier constant. According to this technique, a monitor circuit using substantially the same MOSFET as the MOSFET of the sense amplifier is provided, and the back bias voltage of the MOSFET of the sense amplifier is feedback controlled so as to cancel the fluctuation of the threshold voltage of the MOSFET of the monitor circuit.

  Patent Document 4 discloses a technique for controlling the substrate voltage of a MOSFET constituting a sense amplifier circuit of a DRAM. According to the technique disclosed in Patent Document 4, by dynamically controlling the substrate voltage via the substrate voltage control terminal provided in the MOSFET during sense amplification, the threshold voltage of the MOSFET is lowered, and the low voltage, high speed, An operation with a low leakage current is realized. Patent Document 4 describes specific control (FIG. 22) for the sense amplifier circuit (FIG. 21). By such control, the above-mentioned object is achieved by changing the pair of bit lines BL and / BL with a desired waveform (lower part in FIG. 22).

Japanese Patent Laid-Open No. 2003-0778026 JP 2004-336016 A JP 2007-073143 A JP-A-10-189957

Liu et. Al., “Flexible Threshold Voltage FinFETs with Independent Double Gates and an Ideal Rectangular Cross-Section Si-Fin Channel” 18.8.1, IEDM’03

  However, in order to actually apply the above conventional technique to a logic circuit or a sense amplifier circuit using MOSFET, there are various problems as described below. Patent Document 1 does not disclose a specific method for controlling the threshold voltage of a MOSFET, and it is difficult to actually apply it to a logic circuit or the like. Patent Document 2 does not disclose a specific method for determining the back bias voltage, and it is a problem that the back bias voltage cannot be determined so as to optimize the operation characteristics according to the state. The technique disclosed in Patent Document 3 is merely to cancel the variation of the threshold voltage of the sense amplifier, and it is difficult to apply to various uses in a general logic circuit or the like.

  In addition, when the sense amplifier circuit of Patent Document 4 is operated with a low power supply voltage, there is a problem that when the signal is amplified and read out to an external signal line, it cannot be read out with a sufficient signal voltage. In addition, the sense latch is easily inverted at this time, causing a malfunction, and the time for driving the bit line to the power supply voltage is increased when writing data via the external signal line, which increases the writing time. It becomes. Patent Document 4 does not disclose measures against these problems. Furthermore, according to the technique disclosed in Patent Document 4, since the threshold voltage is controlled by the substrate voltage, it is necessary to control the PN junction between the source of the MOSFET and the substrate not to be forward biased when the threshold voltage is lowered. Therefore, it is difficult to set the threshold voltage to an optimum value.

  Therefore, the present invention has been made to solve these problems. When a functional circuit such as a logic circuit or a sense amplifier circuit is configured using a double gate transistor, the back gate voltage is appropriately controlled. An object of the present invention is to provide a semiconductor device and the like and a control method thereof capable of realizing good characteristics of a functional circuit that operates at high speed and with low power consumption by changing the threshold voltage of a double gate transistor.

  In order to solve the above problems, a semiconductor device of the present invention includes a functional circuit including one or a plurality of double-gate transistors, and a reference transistor having a double-gate structure that serves as a reference for characteristics of the double-gate transistor, and the reference transistor A predetermined reference voltage is applied to the first gate electrode, and the potential of the second gate electrode of the reference transistor is controlled so that the drain current flowing through the reference transistor matches the predetermined reference current, thereby controlling the potential. A voltage control circuit that outputs a voltage, and the control voltage is applied to a second gate electrode of the double gate transistor of the functional circuit.

  According to the semiconductor device of the present invention, the potential of the second gate electrode is such that the drain current when the reference voltage is applied to the first gate electrode matches the reference current with respect to the reference transistor having the double gate structure of the voltage control circuit. Is controlled, and the potential is output as a control voltage and applied to the second gate electrode of each double-gate transistor of the functional circuit. Thus, by appropriately setting the reference voltage and the reference current of the control circuit, it is possible to change the threshold voltage of the double gate transistor constituting the functional circuit and to impart desired characteristics to the functional circuit.

  In order to solve the above problem, the sense amplifier circuit of the present invention includes a determination latch circuit that performs binary determination by comparing the potential of a bit line to which a signal read from a memory cell is transmitted with a reference bit line potential. Two P-type transistors having a double gate structure in which a first back gate voltage is applied to a commonly connected back gate, and a second back gate to a commonly connected back gate. And two N-type transistors having a double gate structure to which a voltage is applied. In the sense amplifier circuit of the present invention, at the time of sense amplification, the first back gate voltage is controlled to a voltage value lower than normal, and the second back gate voltage is controlled to a voltage value higher than normal.

  According to the sense amplifier circuit of the present invention, a determination latch circuit is configured using a double-gate transistor, and a first back gate voltage is applied to the back gates of two P-type transistors, Control is performed such that the second back gate voltage is applied to the back gate of the N-type transistor, and the first back gate voltage is lowered and the second back gate voltage is raised during sense amplification compared to the normal time. . As a result, the threshold voltage of each transistor of the determination latch circuit can be lowered, and the sense amplification speed can be improved.

  The present invention can be effectively applied to both the control method of the semiconductor device and the control method of the sense amplifier circuit.

  According to the present invention, in a semiconductor device including a functional circuit using one or a plurality of double gate transistors, the threshold voltage is changed through the control of the second gate electrode of each double gate transistor, so that a desired function circuit can be obtained. Properties can be imparted. In this case, by controlling so that the functional circuit always maintains a constant characteristic regardless of the operation state, characteristic variations caused by manufacturing process variations and temperature variations can be suppressed. Alternatively, by dynamically changing the characteristics according to the operating state of the functional circuit, for example, in the power-down state, the leakage current is suppressed, and in the active state, the operating speed is increased and the consumption current is reduced. Various requirements for the operation of the functional circuit can be realized.

  Further, according to the present invention, in a sense amplifier circuit including a determination latch circuit using two P-type transistors and two N-type transistors, the back gate voltage in each double gate structure is appropriately controlled. The threshold voltage of the transistor can be optimized, and the sense amplification speed can be improved while suppressing the leakage current. Also, during the read operation, the operation margin is improved while securing a sufficient signal voltage to the external signal line, and during the write operation, the time required to drive the bit line to the power supply voltage is shortened to improve the write speed. be able to.

FIG. 3 is a diagram illustrating a circuit configuration of a driver circuit including four-stage inverters in the first embodiment. FIG. 2 is a diagram illustrating a case where the circuit configuration of FIG. 1 is configured using P-type and N-type reference MOSFETs. FIG. 2 is a block diagram of a VBGP control circuit and a block diagram of a VBGN control circuit. It is a figure which shows the specific structural example of the VBGP control circuit of FIG. 3 (A). FIG. 4 is a diagram illustrating a specific configuration example of a VBGN control circuit in FIG. It is a figure which shows the structural example of 2 input NAND gate. It is a figure which shows the structural example of 2 input NOR gate. It is a figure which shows an example of the value set for every operation mode regarding reference voltages Vrp and Vrn and reference currents Irp and Irn. Shows the operation waveforms of each part of the control circuit in process monitor mode It is a figure which shows the operation waveform of each part of a control circuit at the time of controlling a power down mode and a 1st active mode independently. It is a figure which shows the operation waveform of each part of a control circuit at the time of controlling a power down mode and a 2nd active mode independently. It is a figure which shows the example of a circuit structure of the single end type | mold hierarchical sense amplifier circuit to which this invention is applied. It is a figure which shows the example of a structure of the DLL circuit to which this invention is applied. It is a figure which shows the circuit structure of the sense amplifier circuit of 2nd Embodiment. It is a figure which shows the operation | movement waveform of the sense amplifier circuit of 2nd Embodiment. It is a figure which shows the operation waveform for comparing with the operation waveform of FIG. It is a figure explaining the structural example of the conventional independent control type | mold double gate MOSFET.

  Embodiments of the present invention will be described with reference to the drawings. In the following, a configuration (first embodiment) in which the present invention is applied to a semiconductor device including a functional circuit using a MOSFET having a double gate structure (double gate MOSFET) and a sense amplifier circuit using the double gate MOSFET are described. On the other hand, the form (2nd Embodiment) to which this invention is applied is each demonstrated.

[First Embodiment]
The first embodiment of the present invention will be described below. First, in the semiconductor device of the first embodiment, a configuration of a functional circuit using a double gate MOSFET and control of its characteristics will be described with reference to FIGS. FIG. 1 shows a circuit configuration of a driver circuit composed of four stages of inverters. The driver circuit of FIG. 1 includes P-type double gate gate MOSFETs 10, 12, 14, and 16 and N-type double gate MOSFETs 11, 13, 15, and 17, and is supplied with a power supply voltage VDD and a ground potential VSS. An input signal Sin is input to each front gate (first gate electrode of the present invention) of the pair of MOSFETs 10 and 11 of the first-stage inverter, and an output signal Sout is output from each drain of the pair of MOSFETs 16 and 17 of the fourth-stage inverter. Is output. In addition, a back gate voltage VBGP (first control voltage of the present invention) is applied to each back gate (second gate electrode of the present invention) of the P-type MOSFETs 10, 12, 14, 16 and the N-type MOSFETs 11, 13, A back gate voltage VBGN (second control voltage of the present invention) is applied to each of the back gates 15 and 17 (second gate electrode of the present invention).

  In the following description, unless otherwise distinguished, the double gate MOSFET is simply expressed as “MOSFET” (“P type” or “N type” is added as necessary), and the front of the double gate MOSFET is used. The gate is simply expressed as “gate”.

  Each of the MOSFETs 10 to 17 in FIG. 1 is appended with a magnification (where n times is expressed as xn) when the gate width of the reference MOSFET is 1. Both the P-type MOSFET 10 and the N-type MOSFET 11 of the first stage inverter have a gate width of 1 time (× 1), and the inverters in the 2nd to 4th stages are sequentially 4 times (× 4), 16 times (× 16), and 64 times. (× 64) and the gate width increases. In FIG. 1, it is assumed that each inverter is configured by connecting n reference MOSFETs having a reference gate width in parallel when the gate width is n times. Therefore, the channel length of the MOSFET is the same as that of the reference MOSFET. Note that the P-type and N-type reference MOSFETs do not have to have the same gate width / channel length. For example, the gate width of the P-type MOSFET is set to twice the gate width of the N-type MOSFET. May be.

  Here, a case where the circuit configuration of FIG. 1 is configured using P-type and N-type reference MOSFETs will be described. FIG. 2A shows a circuit portion of the second-stage inverter that receives the signal S1 from the first-stage inverter and outputs the signal S2 to the third-stage inverter in the driver circuit of FIG. FIG. 2B shows a circuit configuration in which the circuit configuration of FIG. 2A is expressed using P-type and N-type reference MOSFETs. In FIG. 2B, four reference P-type MOSFETs 20 are connected in parallel and four reference N-type MOSFETs 30 are connected in parallel. As a whole, the same characteristics as those of a MOSFET having a quadruple gate width are obtained. It is done. The four reference P-type MOSFETs 20 have the back gate voltage VBGP applied to the back gates connected in common, and the four reference N-type MOSFETs 30 have the back gates connected to the back gates connected in common. A voltage VBGN is applied.

  FIG. 3A shows a block diagram of a VBGP control circuit that generates a back gate voltage VBGP for a P-type MOSFET. In FIG. 3A, the reference P-type MOSFET 20 has a source connected to the power supply voltage VDD and a gate to which a variable reference voltage Vrp is applied. The current comparison circuit 21 compares the variable reference current Irp with the drain current Ip of the standard P-type MOSFET 20. The VBGP generation circuit 22 receives the comparison result of the current comparison circuit 21 and generates a back gate voltage VBGP. The back gate voltage VBGP is fed back to the back gate of the standard P-type MOSFET 20, and the value of the back gate voltage VBGP is controlled so that the drain current Ip matches the reference current Irp. Thereby, if the reference voltage Vrp and the reference current Irp are arbitrarily set, the value of the back gate voltage VBGP is determined so as to obtain required characteristics.

  FIG. 3B shows a block diagram of a VBGN control circuit that generates a back gate voltage VBGN for an N-type MOSFET. In FIG. 3B, the standard N-type MOSFET 30 has a source connected to the ground and a variable reference voltage Vrn applied to the gate. The current comparison circuit 31 compares the variable reference current Irn with the drain current In of the standard N-type MOSFET 30. The VBGN generation circuit 32 receives the comparison result of the current comparison circuit 31 and generates a back gate voltage VBGN. The back gate voltage VBGN is fed back to the back gate of the reference N-type MOSFET 30, and the value of the back gate voltage VBGN is controlled so that the drain current In matches the reference current Irn. Thereby, if the reference voltage Vrn and the reference current Irn are arbitrarily set, the value of the back gate voltage VBGN is determined so as to obtain required characteristics.

  Next, specific configuration examples of the VBGP control circuit in FIG. 3A and the VBGN control circuit in FIG. 3B will be described with reference to FIGS. FIG. 4 is a diagram illustrating a circuit configuration example of the VBGP control circuit. The tap selection circuit 50, the first selector 51, the second selector 52, the filter 53, the reference P-type MOSFET 20, the P-type MOSFET 54, A configuration including 55 and two operational amplifiers 56 and 57 is shown. In FIG. 4, the tap selection circuit 50 sends control signals to the first selector 51 and the second selector 52 in accordance with the received operation mode signal Sm. The first selector 51 outputs a reference voltage Vrp selected according to the value of the variable resistance between the power supply voltage VDD and the ground based on the control signal of the tap selection circuit 50. The reference voltage Vrp is smoothed by the filter 53 and then input to the gate of the standard P-type MOSFET 20, and the drain current Ip flows from the standard P-type MOSFET 20 to the resistor R1. On the other hand, based on the control signal of the tap selection circuit 50, the second selector 52 selects the current value of the P-type MOSFET 54 serving as a current source according to the value of the variable resistance, and flows from the P-type MOSFET 55 to the resistor R1 accordingly. A reference current Irp is determined. The tap selection circuit 50, the first selector 51, and the second selector 52 function as a selection circuit according to the present invention.

  In the operational amplifier 56, the voltage R1 · Ip proportional to the drain current Ip is input to the positive input terminal, and the voltage R1 · Irp proportional to the reference current Irp is input to the negative input terminal. To be compared. The output signal of the operational amplifier 56 is input to the operational amplifier 57 that operates as a voltage follower, and the back gate voltage VBGP is output from the operational amplifier 57. This back gate voltage VBGP is applied to the back gate of the reference P-type MOSFET 20 in FIG. 4 and is supplied to each reference P-type MOSFET 20 included in the functional circuit described above. With the configuration of FIG. 4, the value of the back gate voltage VBGP can be appropriately determined according to the set values of the reference voltage Vrp and the reference current Ip so that the standard P-type MOSFET 20 has desired characteristics.

  FIG. 5 is a diagram showing a circuit configuration example of the VBGN control circuit. The tap selection circuit 60, the third selector 61, the fourth selector 62, the filter 63, the reference N-type MOSFET 30, the N-type MOSFET 64, A configuration including 65 and two operational amplifiers 66 and 67 is shown. In FIG. 5, the tap selection circuit 60 receives an operation mode signal Sm that designates an operation mode, and controls the third selector 61 and the fourth selector 62 in accordance with the operation mode signal Sm. The third selector 61 outputs a reference voltage Vrn selected according to the value of the variable resistance between the power supply voltage VDD and the ground. The reference voltage Vrn is smoothed by the filter 63, and then input to the gate of the standard N-type MOSFET 30, and the drain current In flows through the reference N-type MOSFET 30 via the resistor R2. On the other hand, in the fourth selector 62, the current value of the N-type MOSFET 64 serving as a current source is selected according to the value of the variable resistor, and the reference current Irn flowing through the N-type MOSFET 65 is determined through the resistor R2. The tap selection circuit 60, the third selector 61, and the fourth selector 62 function integrally as a selection circuit of the present invention.

  In the operational amplifier 66, the voltage R2 · In proportional to the drain current In is input to the positive input terminal, and the voltage R2 · Irn proportional to the reference current Irn is input to the negative input terminal. To be compared. An output signal of the operational amplifier 66 is input to an operational amplifier 67 that operates as a voltage follower, and a back gate voltage VBGN is output from the operational amplifier 67. The back gate voltage VBGN is applied to the back gate of the reference N-type MOSFET 30 in FIG. 5 and is supplied to each reference N-type MOSFET 30 included in the functional circuit described above. With the configuration of FIG. 5, the value of the back gate voltage VBGN can be appropriately determined so that the reference N-type MOSFET 30 has desired characteristics according to the set values of the reference voltage Vrn and the reference current In.

  In the first embodiment, the present invention is not limited to the driver circuit of FIG. 1 and can be applied to various logic circuits as functional circuits. A configuration example of another logic circuit using the above-described MOSFET will be described with reference to FIGS. FIG. 6 shows a configuration example of a two-input NAND gate using MOSFETs having double and quadruple gate widths. The 2-input NAND gate shown in FIG. 6A is composed of P-type MOSFETs 40 and 43 and N-type MOSFETs 41 and 42. Among these, the P-type MOSFETs 40 and 43 have a double gate width (× 2), and the N-type MOSFETs 41 and 42 have a quadruple gate width (× 4). The input signal A is input to the gates of the MOSFETs 40 and 41, the input signal B is input to the gates of the MOSFETs 42 and 43, and the output signal C that is the result of the NAND operation of the input signals A and B is the MOSFETs 40, 41, and 43. Output from each drain.

  FIG. 6B is a circuit configuration in which the circuit configuration of FIG. 6A is expressed using the reference P-type MOSFET 20 and the reference N-type MOSFET 30. As shown in FIG. 6B, four series circuits composed of one reference P-type MOSFET 20 and two reference N-type MOSFETs 30 are connected in parallel. The input signal A is input to the gates of the two reference P-type MOSFETs 20 on the left side of the upper stage and the four reference N-type MOSFETs 30 on the middle stage, and the input signal B is input to the two reference P-type MOSFETs 20 on the right side of the upper stage and the lower stage. The output signal C is output from a node between the upper four reference P-type MOSFETs 20 and the middle four reference N-type MOSFETs 30. The back gate voltage VBGP is applied to the back gates of the four reference P-type MOSFETs 20, and the back gate voltage VBGN is applied to the back gates of the eight reference N-type MOSFETs 30 in total.

  FIG. 7 shows a configuration example of a two-input NOR gate using MOSFETs having double and quadruple gate widths. The 2-input NOR gate shown in FIG. 7A includes P-type MOSFETs 44 and 45 and N-type MOSFETs 46 and 47. Among these, the P-type MOSFETs 44 and 45 have a four times larger gate width (× 4), and the N-type MOSFETs 46 and 47 have a doubled gate width (× 2). An input signal A is input to the gates of the MOSFETs 44 and 47, an input signal B is input to the gates of the MOSFETs 45 and 46, and an output signal C that is the result of the NOR operation of the input signals A and B is output from the MOSFETs 45, 46, and 47. Output from each drain.

  FIG. 7B is a circuit configuration in which the circuit configuration of FIG. 7A is expressed using the reference P-type MOSFET 20 and the reference N-type MOSFET 30. As shown in FIG. 7B, four series circuits composed of two reference P-type MOSFETs 20 and one reference N-type MOSFET 30 are connected in parallel. The input signal A is input to the gates of the upper four reference P-type MOSFETs 20 and the lower right two reference N-type MOSFETs 30, and the input signal B is the middle four reference P-type MOSFETs 20 and the lower left side. The output signal C is output from a node between the four reference P-type MOSFETs 20 in the middle stage and the four reference N-type MOSFETs 30 in the lower stage. A back gate voltage VBGP is applied to each back gate of the eight reference P-type MOSFETs 20 in total, and a back gate voltage VBGN is applied to each back gate of the four reference N-type MOSFETs 30.

  Next, operation modes in the semiconductor device of the first embodiment will be described. In the first embodiment, an operation mode associated with the parameter setting in the configurations of FIGS. 4 and 5 is assumed. FIG. 8 shows an example of values set for each operation mode with respect to the reference voltages Vrp and Vrn and the reference currents Irp and Irn. As operation modes in the first embodiment, four types of process monitor mode, power down mode, first active mode, and second active mode are prepared. Among these, the process monitor mode related to the control method (first mode) of FIG. 9 to be described later does not perform dynamic control corresponding to the operation state, and constantly monitors the manufacturing process and temperature, while maintaining the P type and N type. The threshold voltage of the MOSFET is controlled so as to always maintain a predetermined set value.

  On the other hand, in the power-down mode, the first active mode, and the second active mode related to the control method (second mode) shown in FIGS. 10 and 11 described later, the MOSFET characteristics are dynamically changed and controlled according to the operating state. To do. The power-down mode is a mode that is set to a standby state, and is set to a setting value that greatly reduces the off-leakage current of the MOSFET. In addition, the first active mode and the second active mode are selected depending on which of the MOSFET operating speed improvement and operating power reduction is important, and when the operating power reduction is important, the first active mode is set, The second active mode is set when importance is placed on improving the operating speed. In the first active mode, the on-current of the MOSFET is set to a relatively small value so as to obtain an effect when applied to a normal path functional circuit whose operation speed is not critical even in a low power functional circuit or a high speed device. On the other hand, in the second active mode, the on-current of the MOSFET is set to a relatively large value so that the effect can be obtained when applied to a functional circuit of a path whose operation speed is critical even in a high-speed function circuit or a high-speed device. .

  Next, specific operations in each operation mode shown in FIG. 8 will be described with reference to FIGS. In each of FIGS. 9 to 11, the operation waveforms of the reference currents Irp and Irn are shown in the upper part, and the operation waveforms of the reference voltages Vrp and Vrn and the back gate voltages VBGP and VBGN are shown in the lower part. 9 to 11, the current value is expressed in logarithmic form on the vertical axis, and the voltage value is shown on the vertical axis in the lower part of FIGS. 9 to 11, and the positive voltage VPP, power supply voltage VDD, ground potential VSS, In addition to the negative voltage VBB (VPP> VDD> VSS> VBB), the P-type and N-type threshold voltages Vtp and Vtn are indicated by arrows.

  FIG. 9 shows operation waveforms of each part of the control circuit in the process monitor mode. In the process monitor mode, the same control is performed in the power-down state and the active state, that is, the reference currents Irp and Irn are both kept constant at 100 nA, and the reference voltages Vrp and Vrn are Vrp = VDD−Vtp, respectively. , Vrn = VSS + Vtn, and a constant voltage value is maintained. Therefore, for example, the P-type back gate voltage VBGP is controlled to a voltage value approximately between the positive voltage VPP and the power supply voltage VDD, and the N-type back gate voltage VBGN is approximately halfway between the negative voltage VBB and the ground potential VSS. Controlled by voltage value. The characteristics of each MOSFET to which the back gate voltages VBGP and VBGN are applied are controlled according to the process variation and temperature so that the drain current when the reference voltages Vrp and Vrn are applied to the gate matches the reference currents Irp and Irn. Is done. As a result, in the process monitor mode, the functional circuit can always be operated with the same characteristics regardless of process variations and temperature.

  FIG. 10 shows operation waveforms of each part of the control circuit when the power-down mode and the first active mode are controlled independently. First, in the power down mode, the reference currents Irp and Irn are both kept constant at 1 nA, and the reference voltages Vrp and Vrn are kept at constant voltage values of Vrp = VDD−Vtp and Vrn = VSS + Vtn, respectively. Therefore, for example, the P-type back gate voltage VBGP is controlled to a voltage value slightly lower than the positive voltage VPP, and the N-type back gate voltage VBGN is controlled to a voltage value slightly higher than the negative voltage VBB. Thereby, each MOSFET to which the back gate voltages VBGP and VBGN are applied has a large absolute value of the threshold voltage, so that the off-leakage current can be greatly reduced.

  Subsequently, when shifting to the first active mode, the reference currents Irp and Irn are both controlled to be 10 μA constant, and the reference voltages Vrp and Vrn are controlled to constant voltage values of Vrp = VSS and Vrn = VDD, respectively. Therefore, for example, the P-type back gate voltage VBGP is controlled to a voltage value slightly higher than the power supply voltage VDD, and the N-type back gate voltage VBGN is controlled to a voltage value slightly lower than the ground potential VSS. The on-current is controlled to be 10 μA. By controlling the on-state current in this way, the functional circuit to be controlled is given the characteristics when the low current consumption is more important than the high-speed operation in the active state. In the case of FIG. 10 as well, as in the process monitor mode, the functional circuit can always be operated with the same characteristics regardless of process variation and temperature.

  FIG. 11 shows operation waveforms of each part of the control circuit when the power-down mode and the second active mode are controlled independently. First, reference currents Irp and Irn, reference voltages Vrp and Vrn, and back gate voltages VBGP and VBGN in the power down mode are all controlled in the same manner as in FIG.

  Subsequently, when shifting to the second active mode, the reference currents Irp and Irn are both controlled to be constant at 20 μA, and the reference voltages Vrp and Vrn are controlled to constant voltage values of Vrp = VSS and Vrn = VDD, respectively. Therefore, for example, the P-type back gate voltage VBGP is controlled to a voltage value lower than the power supply voltage VDD, the N-type back gate voltage VBGN is controlled to a voltage value higher than the ground potential VSS, and the on-current of the reference MOSFET is It is controlled to be 20 μA. By controlling the on-state current in this manner, the functional circuit to be controlled is given characteristics when high-speed operation is emphasized in the active state. In the case of FIG. 11 as well, as in the process monitor mode, the functional circuit can always be operated with the same characteristics regardless of process variation and temperature.

  Next, as an application example of the first embodiment, a case where the present invention is applied to a sense amplifier circuit and a DLL circuit mounted in a DRAM or the like will be described. FIG. 12 is a diagram showing an example of a circuit configuration of a single-ended hierarchical sense amplifier circuit to which the present invention is applied. A memory cell 70, a local sense amplifier 71, a global sense amplifier 72, and a P-type MOSFET 73 are shown. ing. The memory cell 70 includes an N-type selection transistor Q0 and a capacitor Cs. The selection transistor Q0 has a source connected to the local bit line LBL and a gate connected to the word line WL. One end of the capacitor Cs is connected to the selection transistor Q0, and the other end is connected to the voltage VDD / 2.

  The local sense amplifier 71 includes four N-type MOSFETs 80, 81, 82, and 83. The MOSFETs 80 and 81 are connected in series between the global bit line GBL and the ground, and the local bit line LBL is connected to the gate of the MOSFET 80. The drain current of the MOSFET 80 is determined depending on the signal voltage read from the memory cell 70 to the local bit line LBL, thereby changing the speed at which the level of the global bit line GBL is pulled from high to low. The control signal RT applied to the gate of the MOSFET 81 is controlled to be high for a predetermined period after the signal is read to the local bit line LBL. MOSFETs 82 and 83 are also connected in series between the global bit line GBL and the ground, and an intermediate node thereof is connected to the local bit line LBL. The write control MOSFET 82 is conduction controlled in accordance with a control signal WT applied to the gate, and the local bit line precharge MOSFET 83 is conduction controlled in response to a precharge signal PC applied to the gate.

  The global sense amplifier 72 includes eight N-type MOSFETs 84, 85, 88, 89, 90, 91, 92, 93 and two P-type MOSFETs 86, 87. A determination latch circuit that binary-determines the signal transmitted to the global bit line GBL is configured by the inverter including the pair of MOSFETs 86 and 88 and the inverter including the pair of MOSFETs 87 and 89. The determination latch circuit determines high reading when the potential of the global bit line GBL is lower than the logical threshold value of the inverter composed of the MOSFETs 86 and 88 in a predetermined period in which the control signal RT is controlled high. When it is not lowered, it operates so as to determine row reading.

  Further, MOSFETs 84 and 85 are connected between the nodes N1 and N2 on both sides of the determination latch circuit and the global bit line GBL. The MOSFET 84 controls the connection between the global bit line GBL and one node N1 according to the control signal LTC applied to the gate, and the MOSFET 85 controls the global bit according to the control signal RES applied to the gate. The connection between the line GBL and the other node N2 is controlled. The MOSFET 73 outside the global sense amplifier 72 precharges the global bit line GBL to the power supply voltage VDD when the inverted precharge signal / PCG applied to the gate is low. The MOSFETs 90 and 91 constitute a read circuit, and transmit the signal of the node N2 to the read signal line / RDL. The MOSFETs 92 and 93 constitute a write circuit, and transmit a signal from the write signal line / WDL to the node N1 according to the control signal WE. A selection signal YS is commonly applied to the gates of the MOSFETs 90 and 91.

  In the sense amplifier circuit of FIG. 12, in order to improve the sense margin in the sensing operation, it is necessary to always keep the threshold voltages of the MOSFET 80 of the local sense amplifier 71 and the MOSFETs 86 and 88 of the global sense amplifier 72 at design values. Therefore, the process monitor mode control method is applied, and as shown in FIG. 12, the back gate voltage VBGN is applied to the back gates of the MOSFETs 80 and 88, and the back gate voltage VBGP is applied to the back gate of the MOSFET 86. As a result, the threshold voltages of the MOSFETs 80, 86, and 88 can always be kept at the designed values regardless of process variations and temperatures, so that the sense margin can be improved.

  On the other hand, FIG. 13 is a diagram showing an example of the configuration of a DLL circuit to which the present invention is applied. A variable delay circuit 74 that delays an external clock, a replica circuit 75 that transmits an output clock from the variable delay circuit 74, A phase comparison circuit 76 that compares the external clock and the output signal of the replica circuit 75 and supplies the comparison result to the variable delay circuit 74 is included. In the DLL circuit, the variable delay circuit 74 and the phase comparison circuit 76 need to operate at low power and at high speed, and therefore, the back gate voltage VBGP / VBGN is applied to the back gate of each internal MOSFET. This enables high-speed and low-power operation in the active mode while suppressing an increase in off-leakage current in the power-down mode such as a standby state. In particular, high-speed operation is possible by operating in the first active mode when the clock frequency of the external clock does not exceed 2 GHz, for example, and operating in the second active mode within the range of 2 GHz or more. In addition, since the process monitor mode is applied in each operation state, a constant performance can be maintained even if there is a process variation or a temperature variation.

  In the first embodiment, the case where two types of the first active mode and the second active mode are set has been described, but the active mode is not limited to two types. That is, a plurality of active modes that are further subdivided according to the operation state may be set, or only one type of active mode may be set.

  As described above, according to the first embodiment, functional circuits such as a logic circuit and a sense amplifier circuit are configured using MOSFETs having a double gate structure, and the respective back gate voltages VBGP and VBGN are controlled. Since the VBGP generation circuit 22 and the VBGN generation circuit 32 are provided, desired characteristics can be imparted to the functional circuit based on the settings of the reference voltages Vrp and Vrn and the reference currents Irp and Irn. And, for functional circuits, control that maintains constant characteristics regardless of manufacturing process fluctuations and temperature fluctuations, and according to the operating state, such as suppression of leakage current, improvement of operating speed, reduction of current consumption, etc. Control that realizes various characteristics is possible.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described. In the second embodiment, a configuration of a latch-type sense amplifier circuit using a MOSFET and control of its characteristics will be described. FIG. 14 is a diagram illustrating a circuit configuration of the sense amplifier circuit according to the second embodiment. The sense amplifier circuit shown in FIG. 14 includes four N-type MOSFETs 100, 103, 104, and 105 and two P-type MOSFETs 101 and 102. Among these, the MOSFETs 101 to 104 constituting the determination latch circuit all have a double gate structure, and the back gate control voltage VBGP is applied to the back gates of the two P-type MOSFETs 101 and 102, and the two N-type MOSFETs 103. , 104 are applied with a back gate control voltage VBGN. Control of the respective back gate control voltages VBGP and VBGN will be described later.

  In FIG. 14, the left bit line BL is connected to one input node of the determination latch circuit, and the right bit line / BL is connected to the other input node of the determination latch circuit. As a result, the minute signal read from the memory cell 70 (not shown in FIG. 14) to one bit line BL is compared with the reference voltage which is the potential of the other bit line / BL and sense-amplified. The common drive voltage PCS is supplied to the commonly connected sources of the two P-type MOSFETs 101 and 102, and the common drive voltage NCS is supplied to the commonly connected sources of the two N-type MOSFETs 103 and 104. After a minute signal is read to the bit line BL during sense amplification, the common drive voltage PCS is controlled from VDD / 2 to VDD based on the power supply voltage VDD and the ground potential VSS, and the common drive voltage NCS is changed from VDD / 2. By controlling to VSS, a minute signal of the bit line BL is sense-amplified.

  One bit line BL is connected to the external signal line LIO via the MOSFET 100 to which the selection signal YS is applied to the gate, and the other bit line / BL is connected to the MOSFET 105 to which the selection signal YS is applied to the gate. To the external signal line / LIO. In the sense amplifier circuit of FIG. 14, a period during which the selection signal YS is high corresponds to a reading period or a writing period. The sense amplifier circuit includes a precharge circuit (not shown), and the precharge circuit precharges the bit line BL and the bit line / BL to a voltage (VDD / 2) that is half of the equalized power supply voltage VDD. The

  Next, the operation of the sense amplifier circuit of FIG. 14 will be described with reference to FIGS. FIG. 15 shows operation waveforms of the sense amplifier circuit of the second embodiment. 15, the P-type back gate voltage VBGP is kept at the positive voltage VPP, the N-type back gate voltage VBGN is kept at the negative voltage VBB, and the common drive voltages PCS and NCS are kept at the voltage VDD / 2. I'm leaning. In this state, a high level minute voltage is read to the bit line / BL. Subsequently, in the sense amplification period T1, the back gate voltage VBGP drops to the power supply voltage VDD, the back gate voltage VBGN rises to the ground potential VSS, the common drive voltage PCS is driven to the power supply voltage VDD, and the common drive voltage NCS is grounded. Drive to potential VSS. At this time, since the threshold voltages of the MOSFETs 101 to 104 are lowered, a high-speed sensing operation is performed, the potential of the bit line / BL is raised to the power supply voltage VDD, and the potential of the bit line BL is lowered to the ground potential VSS.

  When the sense amplification period T1 ends, the back gate voltage VBGP returns to the positive voltage VPP, and the back gate voltage VBGN returns to the negative voltage VBB. Subsequently, in the read period T2, the selection signal YS is controlled to a high level, and the MOSFETs 100 and 105 on both sides in FIG. 14 are turned on. In FIG. 14, data of logic “0” is read. On the other hand, since the back gate voltage VBGN rises from the negative potential VBB to the ground potential VSS, the threshold voltages of the two N-type MOSFETs 103 and 104 are lowered and the current driving capability is improved. As a result, the voltage of one external signal line LIO is greatly reduced from the power supply voltage VDD via the N-type MOSFET 104 having a high current driving capability. On the other hand, since the bit line / BL is driven to the power supply voltage VDD, the voltage of the other external signal line / LIO is kept at the power supply voltage VDD. Therefore, the potential difference between the pair of external signal lines LIO and / LIO is read out as a large signal. At this time, the potential of the bit line BL rises from the ground potential VSS, but since the level is sufficiently low, the determination latch circuit is not inverted.

  When the read period T2 ends, the back gate voltage VBGN returns to the negative voltage VBB, and the threshold voltages of the two N-type MOSFETs 103 and 104 are increased, so that the leakage current is suppressed. Further, the selection signal YS returns to the low level, and the external signal line LIO and the bit line BL also return to the original state. Subsequently, in the writing period T3, the selection signal YS is controlled to a high level, and the MOSFETs 100 and 105 on both sides in FIG. 14 are turned on. In FIG. 14, data of logic “1” is written. In the write operation, the external signal line / LIO changes from the power supply voltage VDD to the ground potential VSS, and the potential of the bit line / BL is lowered from the power supply voltage VDD to the ground potential VSS. Since the back gate voltage VBGP drops from the positive potential VPP to the power supply voltage VDD in a predetermined period after the transition to the writing period T3, the threshold voltage of the two P-type MOSFETs 101 and 102 is lowered and the current driving capability is improved. To do. Therefore, the potential of the bit line BL can be driven at high speed to the power supply voltage VDD through the P-type MOSFET 102 having high current driving capability. When the writing period T3 ends, the back gate voltage VBGP returns to the positive voltage VPP, and the threshold voltages of the two P-type MOSFETs 101 and 102 increase, so that the leakage current is suppressed.

  Here, FIG. 16 shows operation waveforms when the back gate voltages VBGP and VBGN of the four MOSFETs 100 to 104 are not dynamically changed and controlled, for comparison with the operation waveforms of the second embodiment (FIG. 15). Is shown. In the operation waveform of FIG. 16, one back gate voltage VBGP is always kept at the positive voltage VPP, and the other back gate voltage VBGN is always kept at the negative voltage VBB. Therefore, as compared with the operation waveform of FIG. 15, the potential of each bit line BL, / BL in the sense amplification period T1 changes gently, so that the sense amplification operation is delayed correspondingly. In addition, the floating of the potential of the bit line BL in the read period T2 increases, and the operation margin is reduced and the possibility that the inverting latch circuit is inverted and malfunctions increases. Further, in the writing period T3, the time until the bit line BL is driven to the power supply voltage VDD becomes longer, and the writing operation is delayed.

  As described above, according to the sense amplifier circuit of the second embodiment, the back gate voltages VBGP and VBGN of the four MOSFETs 101 to 104 having the double gate structure constituting the determination latch circuit are dynamically controlled, and each MOSFET 101 to By reducing the threshold voltage of 104 at a desired timing, it is possible to improve the speed of sense amplification during sense amplification while suppressing leakage current. In addition, a sufficient signal level of the pair of external signal lines LIO and / LIO is ensured at the time of reading, and an operation margin can be improved by suppressing inversion of the judgment latch circuit, and a time for driving the bit line BL is shortened at the time of writing operation. As a result, the writing operation can be speeded up.

  The contents of the present invention have been specifically described above based on the above embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. it can. For example, in the first and second embodiments, the case where N-type and P-type MOSFETs having a double gate structure are used has been described. However, if similar effects can be obtained, double-gate transistors (for example, MISFETs) having different structures can be obtained. Etc.), the present invention can be applied. The present invention is not limited to a semiconductor storage device such as a DRAM, but includes a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an ASSP (Application It can be applied to general semiconductor devices such as Specific Standard Circuit).

10-17, 40-47, 54-55, 64-65, 73, 80-93, 100-105 ... MOSFET
20 ... Reference P-type MOSFET
21, 31 ... Current comparison circuit 22 ... VBGP generation circuit 30 ... Reference N-type MOSFET
32 ... VBGN generation circuit 50, 60 ... tap selection circuit 51 ... first selector 52 ... second selector 53, 63 ... filters 56, 57, 66, 67 ... op amp 61 ... third selector 62 ... fourth selector 70 ... memory cell 71 ... Local sense amplifier 72 ... Global sense amplifier 74 ... Variable delay circuit 75 ... Replica circuit 76 ... Phase comparison circuit WL ... Word line GBL ... Global bit line LBL ... Local bit line Q0 ... Select transistor Cs ... Capacitor / RDL ... Read signal Line / WDL ... Write signal line VDD ... Power supply voltage VSS ... Ground potential VPP ... Positive voltage VBB ... Negative voltage VBGP, VBGN ... Back gate voltage Vrp, Vrn ... Reference voltage Irp, Irn ... Reference current Sm ... Operation mode signals RT, WT , LTC, RES, WE ... control signal PC ... Charge signal / PCG ... inverted precharge signal YS ... selection signal N1, N2 ... node

Claims (18)

A functional circuit including one or more double-gate transistors;
A reference transistor having a double-gate structure which serves as a reference for the characteristics of the double-gate transistor, a predetermined reference voltage is applied to the first gate electrode of the reference transistor, and a drain current flowing through the reference transistor is a predetermined reference current A voltage control circuit that controls the potential of the second gate electrode of the reference transistor so as to match, and outputs the potential as a control voltage;
And the control voltage is applied to a second gate electrode of the double gate transistor of the functional circuit. The functional circuit includes a P-type transistor as the double gate transistor,
The voltage control circuit is controlled so that a first reference voltage is applied to the first gate electrode of a standard P-type transistor as the reference transistor, and the drain current matches the first reference current. Outputting the potential of the second gate electrode as the first control voltage;
The semiconductor device according to claim 1, wherein the first control voltage is applied to a back gate of the P-type transistor of the functional circuit. The functional circuit includes an N-type transistor as the double gate transistor,
The voltage control circuit is controlled such that a second reference voltage is applied to the first gate electrode of a standard N-type transistor serving as the reference transistor, and the drain current coincides with a second reference current. Outputting the potential of the second gate electrode as a second control voltage;
The semiconductor device according to claim 1, wherein the second control voltage is applied to a back gate of the N-type transistor of the functional circuit.   2. The semiconductor device according to claim 1, wherein each of the double gate transistors included in the functional circuit is configured by connecting double gate transistors having the same size as the reference transistor in parallel.   The semiconductor device according to claim 1, further comprising a selection circuit that selectively sets the plurality of set values of the reference voltage and the plurality of set values of the reference current.   6. The semiconductor device according to claim 5, wherein the set values of the reference voltage and the reference current are controlled to be constant regardless of the operation state of the functional circuit.   6. The semiconductor device according to claim 5, wherein each set value of the reference voltage and the reference current is controlled to be dynamically changed according to an operation state of the functional circuit.   The semiconductor device according to claim 6, wherein the functional circuit is a single-ended hierarchical sense amplifier circuit.   The semiconductor device according to claim 7, wherein the functional circuit is a DLL circuit. A sense amplifier circuit including a determination latch circuit that performs binary determination by comparing a potential of a bit line to which a signal read from a memory cell is transmitted with a reference bit line potential;
Two P-type transistors having a double gate structure in which a first back gate voltage is applied to a commonly connected back gate;
Two N-type transistors having a double gate structure in which a second back gate voltage is applied to a commonly connected back gate;
With
In the sense amplification, the first back gate voltage is controlled to a voltage value lower than normal, and the second back gate voltage is controlled to a voltage value higher than normal.   11. The first back gate voltage is maintained at a normal voltage value during a data read operation, and the second back gate voltage is controlled to be higher than a normal voltage value. The sense amplifier circuit described in 1.   The first back gate voltage is controlled to a voltage value lower than the normal value and the second back gate voltage is maintained at the normal voltage value in a predetermined period after the data write operation starts. The sense amplifier circuit according to claim 10 or 11, characterized in that: A method for controlling a semiconductor device, comprising: a functional circuit including one or a plurality of double-gate transistors; and a voltage control circuit including a reference transistor having a double-gate structure serving as a reference for characteristics of the double-gate transistor,
In accordance with the operating state of the functional circuit, a reference voltage value to be applied to the first gate electrode of the reference transistor and a reference current value corresponding to the drain current of the reference transistor are set.
Controlling the potential of the second gate electrode of the reference transistor when the drain current of the reference transistor is controlled to match the reference current with the reference voltage applied to the first gate electrode of the reference transistor Output as voltage,
Applying the control voltage to a second gate electrode of each of the double gate transistors;
A method for controlling a semiconductor device. A plurality of operation modes corresponding to the operation state of the functional circuit can be selectively set;
When the first mode is set as the operation mode, control is performed so that the set values of the reference voltage and the reference current are kept constant in the power-down state and the active state of the functional circuit. The method for controlling a semiconductor device according to claim 13, wherein: A plurality of operation modes corresponding to the operation state of the functional circuit can be selectively set;
When the second mode is set as the operation mode, control is performed so that the set values of the reference voltage and the reference current are dynamically changed between the power-down state and the active state of the functional circuit. The method of controlling a semiconductor device according to claim 13. A determination latch circuit that performs binary determination by comparing a potential of a bit line to which a signal read from a memory cell is transmitted with a reference bit line potential, and a first back gate voltage is applied to the commonly connected back gates; Control method of a sense amplifier circuit having two P-type transistors having a double gate structure and two N-type transistors having a double gate structure in which a second back gate voltage is applied to a commonly connected back gate Because
In the sense amplification period by the determination latch circuit, the first back gate voltage is controlled to a voltage value lower than normal, and the second back gate voltage is controlled to a voltage value higher than normal.
And a control method of the sense amplifier circuit.   The first back gate voltage is maintained at a normal voltage value and the second back gate voltage is controlled to a voltage value higher than normal during a read period for reading data to an external signal line. The method of controlling a sense amplifier circuit according to claim 16. The first back gate voltage is controlled to a voltage value lower than normal during a predetermined period after shifting to a write operation period for writing data from the external signal line, and the second back gate voltage is set to a voltage during normal operation. 18. The sense amplifier circuit control method according to claim 16, wherein control is performed so as to maintain the value.

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