JP4994747B2 - Photoelectric conversion device and imaging system - Google Patents

Description

  The present invention relates to a photoelectric conversion device, and more particularly to a MOS type photoelectric conversion device.

In recent years, the demand for photoelectric conversion devices is rapidly expanding as an imaging device for a two-dimensional image input device centering on a digital still camera and a video camcorder, or as a one-dimensional image reading device centering on a facsimile and a scanner.
CCD and MOS type photoelectric conversion devices are used as these photoelectric conversion devices.

  Such a photoelectric conversion device needs to reduce noise generated in the photoelectric conversion region. As one of the noises, there is a problem of hot carriers generated in a MOS transistor arranged in the photoelectric conversion region. Hot carriers are carriers generated when a strong electric field is applied to a PN junction composed of a drain region and a channel end when a voltage is applied to the gate of a MOS transistor. In a device that handles minute signals such as a photoelectric conversion device, noise generated by such hot carriers may be particularly problematic.

As an example of this noise reduction method, there is a method in which a MOS transistor constituting a pixel has an LDD structure (Lightly Doped Drain) (Patent Document 1). With such a structure, the electric field strength between the channel and the drain formed under the gate is relaxed, and the influence of hot carriers can be reduced.
JP 2000-012822 A

  According to Patent Document 1, it is said that deterioration of element characteristics can be suppressed by making an MOS transistor constituting a pixel have an LDD structure.

  However, when the gate insulating film is thinned with miniaturization in such a configuration, the gate insulating film between the diffusion region and the antireflection film becomes thin at the bottom of the side spacer of the MOS transistor. As a result, there is a problem that reliability of transistor characteristics is reduced by hot carriers.

  The present invention solves the above problems.

In view of the above problems, a photoelectric conversion device according to the present invention includes a photoelectric conversion region in which a plurality of photoelectric conversion elements and a first MOS transistor for reading a signal based on the charge of the photoelectric conversion elements are arranged, and the first And a peripheral circuit region in which a second MOS transistor that performs at least one of driving the MOS transistor or amplifying a signal read from the photoelectric conversion region is disposed on the same semiconductor substrate, and receiving light of the photoelectric conversion element A photoelectric conversion device having an antireflection film on a surface thereof, wherein an impurity concentration of a drain of the first MOS transistor is lower than an impurity concentration of a drain of the second MOS transistor, and the second MOS transistor has an LDD structure in which the side spacer was arranged made of an insulating film containing silicon nitride film on the side wall of the gate electrode The silicon oxide film disposed between the side spacer and the drain is thicker than the silicon oxide film disposed between the antireflection film disposed in the photoelectric conversion region and the light receiving surface of the photoelectric conversion element. Features.

  According to the present invention, MOS transistors suitable for the photoelectric conversion region and the peripheral circuit region can be arranged. In addition, the influence of hot carriers on the MOS transistors arranged in the peripheral circuit region can be reduced.

  The configuration of the present invention will be described. In the present invention, the photoelectric conversion region is a region where a plurality of photoelectric conversion elements and a MOS transistor for reading a signal based on the charge of the photoelectric conversion elements are arranged. A plurality of MOS transistors can be provided for one photoelectric conversion element to amplify the charge.

  The peripheral circuit region is a region where a circuit for driving a MOS transistor disposed in the above-described photoelectric conversion region, a circuit for amplifying a signal from the photoelectric conversion region, and the like are disposed.

  FIG. 1 shows a plan layout of the photoelectric conversion device. Reference numeral 111 denotes a photoelectric conversion region. When a unit of a signal read from one photoelectric conversion element is a pixel, an area where the photoelectric conversion element is arranged can be called a pixel area. A pixel is a minimum unit of an element set for reading one photoelectric conversion element and a signal from the photoelectric conversion element to an output line. The element set includes a transfer unit such as a transfer MOS transistor described later, an amplification unit such as an amplification MOS transistor, and a reset unit such as a reset MOS transistor. Adjacent photoelectric conversion elements can share the above elements, but in this case as well, they are defined by the minimum unit of an element set for reading a signal of one photoelectric conversion element.

  Reference numeral 112 denotes a signal processing circuit for amplifying a signal read from the photoelectric conversion region. However, the circuit is not limited to an amplifier circuit, and may be a circuit that removes pixel noise by CDS processing. Further, it may be a circuit for converting serially read signals from a plurality of columns into serial. Reference numeral 113 denotes a vertical shift register for driving a MOS transistor arranged in the photoelectric conversion region. Reference numeral 114 denotes a horizontal shift register for driving a MOS transistor of the signal processing circuit. 112 to 114 may be included in the peripheral circuit region. Further, when AD conversion is performed in the photoelectric conversion device, an AD conversion circuit may be included therein.

  Here, the MOS transistors respectively disposed in the photoelectric conversion region and the peripheral circuit region will be described.

  When the MOS transistor has an LDD structure, if the concentration of the electric field relaxation region is too low or too wide, the parasitic resistance (series resistance) of the transistor increases, and the driving force and static characteristics are greatly impaired. Become. In particular, when the driving force and circuit characteristics are important, it is preferable to narrow the electric field relaxation region, that is, increase the impurity concentration of the drain region to some extent. Such a MOS transistor is preferably used in the peripheral circuit region. On the other hand, when it is necessary to further relax the electric field for the purpose of miniaturization or the like, it is desirable to form a wide electric field relaxation region. That is, it is preferable to reduce the impurity concentration in the drain region to some extent.

  Therefore, it is preferable to make the impurity concentration of the drain region of the MOS transistor arranged in the photoelectric conversion region lower than the impurity concentration of the MOS transistor arranged in the peripheral circuit region. As one example for realizing this, a MOS transistor disposed in the peripheral circuit region has an LDD structure, and a drain of the MOS transistor disposed in the photoelectric conversion region is a semiconductor having a low impurity concentration for constituting the LDD structure. It can be considered to be composed of regions.

  Here, a countermeasure against hot carriers of the MOS transistor arranged in the peripheral circuit region is further considered. As described above, the MOS transistor disposed in the peripheral circuit region has an LDD structure, the impurity concentration on the side near the gate end (channel end) is low, and impurities are implanted into other regions of the drain to increase the impurity concentration. It has become. Usually, this high impurity concentration region is formed by ion implantation using a side spacer (side wall) such as a silicon nitride film as a mask. As a result, the impurity concentration is high in the region below the end of the side spacer of the drain, and a large electric field is likely to occur. A silicon oxide film is formed between the side spacer and the drain region. Therefore, this region has a laminated structure of high concentration semiconductor region / SiO / SiN. In such a laminated structure, a level for trapping electrons occurs in the SiO / SiN interface or SiN, and hot carriers from the high-concentration semiconductor region are easily trapped in this level. The ease of trapping varies depending on the film thickness of the silicon oxide film, and the greater the film thickness of the silicon oxide film, the less likely it is trapped. This is presumably because hot carriers tunnel through the silicon oxide film and are trapped in the level. Accordingly, hot carriers are likely to be generated around the side spacers of the MOS transistors in the peripheral circuit region. On the other hand, the influence of hot carriers can be reduced by increasing the thickness of the silicon oxide film. Here, for the reason described above, the drain is already formed in the photoelectric conversion region by the low concentration semiconductor region, and such a hot carrier is hardly generated.

  Therefore, the thickness of the silicon oxide film disposed between the side spacer and the drain is made larger than the thickness of the silicon oxide film formed on the surface of the drain region of the MOS transistor disposed in the photoelectric conversion region. Thereby, as described above, it is possible to arrange MOS transistors suitable for the photoelectric conversion region and the peripheral circuit region. In addition, the influence of hot carriers on the MOS transistors arranged in the peripheral circuit region can be reduced.

  Here, the structure of the MOS transistor will be further described in detail.

  As described above, the impurity concentration of the drain region of the MOS transistor arranged in the photoelectric conversion region is lower than the impurity concentration of the MOS transistor arranged in the peripheral circuit region. As an example of this, a configuration in which a region having a low impurity concentration of the drain disposed in the photoelectric conversion region is disposed over a region wider than a region having a low impurity concentration of the drain disposed in the peripheral circuit region is considered. It is done.

  An effective effect in reducing the electric field of the MOS transistor is a portion from the gate end to the region (first region) where the drain and the conductor are in direct contact. Therefore, a large electric field relaxation effect can be obtained by lowering the impurity concentration in the region between the first region and the gate end in the photoelectric conversion region as compared with the peripheral circuit region.

  Specifically, the drain of the MOS transistor (first MOS transistor) disposed in the photoelectric conversion region has a first region that is in direct contact with the conductor. And it has the 2nd field arranged by the channel side of a MOS transistor rather than the 1st field. Similarly, the MOS transistor (second MOS transistor) arranged in the peripheral circuit region 102 has a drain electrically connected to a plug that is a conductor. The drain has a first region that is in direct contact with the plug and a second region that is disposed closer to the channel than the first region. Furthermore, the second region has a third region close to the channel and a fourth region disposed between the first region and the third region. The second region has a lower impurity concentration than the fourth region.

  This will be described in more detail with reference to FIG. FIG. 2A is a plan view of a MOS transistor arranged in the peripheral circuit region and a cross-sectional view taken along line AA ′. FIG. 2B is a plan view of the MOS transistor arranged in the photoelectric conversion region and a cross-sectional view taken along line BB ′. Reference numeral 2001 denotes a gate electrode, 2002 denotes a source, and 2003 denotes a conductor connection region (first region). Reference numeral 2004 denotes a semiconductor region (third region) having a low impurity concentration disposed in the vicinity of the gate. Reference numeral 2005 denotes a region having a higher impurity concentration than the third region disposed between the first region and the third region. Reference numeral 2006 denotes a semiconductor region (second region) having a low impurity concentration disposed between the channel and the first region. The second region has a lower impurity concentration than the fourth region.

  With such a structure, it is possible to reduce hot carriers of the MOS transistor arranged in the photoelectric conversion region. Further, in the peripheral circuit region, the electric field relaxation region of the MOS transistor in which the driving force and circuit characteristics are important can be formed relatively narrow.

  Next, an example of an equivalent circuit diagram of a pixel of a photoelectric conversion device applicable to the present invention is shown in FIG. The photoelectric conversion region includes at least the photoelectric conversion element 1, the transfer MOS transistor 2, the reset MOS transistor 4, and the amplification MOS transistor 5. The pixel is selected by the voltage supplied to the drain of the reset MOS transistor. The photoelectric conversion element is a photodiode, for example, and converts incident light into electric charge by photoelectric conversion. The transfer MOS transistor functions as a transfer unit that transfers the charge of the photoelectric conversion element to the input unit of the amplification unit. The amplification MOS transistor outputs a change in potential due to electric charges generated in the photoelectric conversion element to a signal line. Here, the potential change target may be a node that is floating when charge is transferred from the photoelectric conversion element, and floating diffusion (floating diffusion region: FD) is used. The FD and the gate of the amplification MOS transistor are connected to output a signal based on a change in the potential of the FD to the signal line. At this time, since the electric charge is amplified and output by the source follower operation, the MOS transistor 5 can be said to be an amplifying element. The power source 7, the amplification MOS transistor 5, the signal line, and the constant current source 6 constitute a source follower circuit. In this example, the selection operation is performed by the drain voltage of the reset MOS transistor. However, the selection may be performed by providing a selection MOS transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments, and can be combined and modified within the scope not exceeding the gist of the invention. In each embodiment, only a specific MOS transistor will be described as an example. However, the structure of each embodiment can be applied to all MOS transistors arranged in each region. In the above description, the drain has been described as an example, but the source may have such a configuration.

(First embodiment)
FIG. 4 shows a cross-sectional structure of the photoelectric conversion device according to the first embodiment of the present invention with respect to the photoelectric conversion unit and the peripheral circuit region. Reference numeral 101 denotes a photoelectric conversion unit, and reference numeral 102 denotes a peripheral circuit region. Reference numeral 103 denotes a first conductivity type semiconductor region. Reference numeral 104 denotes a second conductivity type semiconductor region (well). 103 and 104 constitute a PN junction to constitute a photodiode that functions as a photoelectric conversion element. Reference numeral 103 denotes the same conductivity type as the signal charge. When the signal charge is an electron, it becomes an N-type semiconductor region. Reference numeral 105 denotes a second conductivity type semiconductor region, which is provided to reduce dark current. An optical antireflection film 106 is disposed on the light receiving surface of the photodiode. This serves to reduce the interface reflection on the photodiode surface. The antireflection film 106 can be formed in a stacked structure containing SiN and SiO. This antireflection film is disposed so as to cover the photoelectric conversion region except for a contact hole bottom described later. Here, it is desirable that the antireflection film covers the entire photoelectric conversion region.

  Reference numeral 107 denotes a gate of a transfer MOS transistor, which transfers charges in the semiconductor region 103. Reference numeral 108 denotes a first conductivity type semiconductor region, which is a region where charges are transferred by a transfer MOS transistor. As will be described later, it can also be called a voltage converter for reading a voltage that changes based on the transferred charge. Further, since electric charge is in a floating state when the charge is transferred by the transfer MOS transistor, it can also be called a floating diffusion (hereinafter referred to as FD). The voltage signal is read to the signal line by the amplification MOS transistor 109 arranged in the photoelectric conversion region 101. Thereafter, the data is read out of the photoelectric conversion device by a reading circuit configured by the MOS transistor 110 disposed in the peripheral circuit region 102.

  In the present embodiment, the MOS transistor drain disposed in the photoelectric conversion region and the MOS transistor drain disposed in the peripheral circuit region have different structures. The source and drain of the FD 108 and the MOS transistor 109 and the source and drain regions of the MOS transistor 110 have different structures. That is, the first conductivity type semiconductor region 111 having a high impurity concentration is not arranged in the source and drain regions of the FD 108 and the MOS transistor 109. The first conductive type semiconductor region 114 having a low impurity concentration and the first conductive type semiconductor region 116 having a high impurity concentration formed under the contact hole 115 are formed.

  Here, the side spacer 113 may have the same layer configuration as the antireflection film 106. The first conductivity type semiconductor region 114 having a low impurity concentration can be formed by self-alignment with the gate electrode 112, and is also formed under the side spacer 113. The first conductivity type semiconductor region 111 having a high impurity concentration can be formed by self-alignment with respect to the side spacer 113, and is not formed under the side spacer 113 and the antireflection film 106.

  According to such a configuration, since the antireflection film 106 is not etched in the photoelectric conversion region, etching damage to the photoelectric conversion element can be reduced. In addition, after the formation of the antireflection film 106, there is no step of exposing the semiconductor surface other than the contact holes, and contamination by metal elements or the like can be prevented. As a result, the occurrence rate of point defects in the dark can be lowered. In general, a MOS transistor having an LDD structure can relax an electric field in a low-concentration electric field relaxation region (first conductivity type semiconductor region 114 having a low impurity concentration). By doing so, the electric field relaxation effect can be enhanced. Thereby, generation of hot carriers can be suppressed, and reliability and breakdown voltage can be improved. However, if the concentration of the electric field relaxation region is too low or too wide, the parasitic resistance (series resistance) of the transistor increases, resulting in a significant loss of driving force and static characteristics. Therefore, it is desirable that the electric field relaxation region be formed relatively narrow in the peripheral circuit region where the driving force and circuit characteristics are particularly important.

  According to the configuration of the present embodiment, both can be satisfied. In the MOS transistor in the photoelectric conversion region of the present embodiment, the portion having the effect of effectively relaxing the electric field extends from the ends of the gates 107 and 112 to the first conductivity type semiconductor region 116 having a low impurity concentration formed under the contact hole 115. Part. Thereby, a large electric field relaxation effect can be obtained. Note that the first conductivity type semiconductor region 116 having a high impurity concentration can be formed in the contact hole by self-alignment by ion implantation through the hole after the contact hole 115 is formed. For this reason, it becomes possible to design the size of the transistor small. The first conductivity type semiconductor region 116 having a high impurity concentration is preferably provided in order to obtain good electrical connection.

  In addition to the above-described effects, this embodiment has an effect of reducing pixel defects and random noise resulting from the leakage of the FD 108. As shown in FIG. 4, the FD 108 is composed of a low-concentration electric field relaxation region (first conductivity type semiconductor region 114 with a low impurity concentration), and has a large electric field relaxation effect other than at the gate end. That is, the electric field at the junction formed between the junction 104 formed with the well 104 and the channel stop region (not shown) below the isolation portion can be reduced. As a result, since leakage of the FD 108 can be reduced, random noise at the time of reading can be reduced. Further, it has been empirically understood that the probability that a pixel with a suddenly large leakage current of the FD 108 is generated has a correlation with the electric field of the FD 108, and it is possible to suppress point defects.

  Next, the configuration of the MOS transistor in the peripheral circuit region will be described. A silicon oxide film 118 is disposed between the side spacer 113 of the MOS transistor 110 and the first conductivity type semiconductor region 114 having a low impurity concentration. In the photoelectric conversion region, a silicon oxide film 119 is disposed between the antireflection film and the semiconductor substrate (FD 108). The silicon oxide film 118 is thicker than the silicon oxide film 119. In FIG. 4, h1 is the thickness of the silicon oxide film 119, and h2 is the thickness of the silicon oxide film 118. Therefore, h2 is larger than h1. As a result, a structure in which hot carriers are difficult to be trapped at the silicon nitride film / silicon oxide film interface or the trap level of the silicon nitride film is obtained. This is because the probability that hot carriers tunnel through the silicon oxide film can be lowered. Therefore, the influence of hot carriers on the MOS transistor arranged in the peripheral circuit region can be reduced. As a result, the reliability due to the generation of hot carriers can be improved.

  Further, as shown in FIG. 4, a silicon oxide film 117 may be disposed on the upper portion (upper surface) of the gate 112 of the MOS transistor. This can be formed, for example, by thermal oxidation. The silicon oxide film 117 can reduce ion implantation through the gate electrode when forming the first conductivity type semiconductor region 111 having a high impurity concentration. As a result, fluctuations in MOS transistor characteristics and increased variations can be prevented.

  In the above embodiment, the peripheral circuit region MOS transistor having the same conductivity type as that of the MOS transistor of the photoelectric conversion unit has been described. However, the peripheral circuit region may have a CMOS configuration. A side spacer structure can also be adopted for a MOS transistor having a conductivity type opposite to the MOS transistor in the photoelectric conversion region. This is particularly effective for an nMOS transistor in which hot carriers are easily generated. Therefore, it is an nMOS transistor in the photoelectric conversion region, and a particularly great effect can be obtained when the relationship between the nMOS transistor in the peripheral circuit region and the nMOS transistor in the photoelectric conversion region has the above configuration.

  On the other hand, when the MOS transistor arranged in the photoelectric conversion region is a pMOS transistor, the importance of the hot carrier problem is reduced, but the effect of ease of processing of a fine pixel can be obtained. In this embodiment, 106 functions as an antireflection film. However, even if the sensor is not in antireflection conditions, such as a single oxide film 106, effects such as electric field relaxation and point defect reduction can be obtained.

(Second Embodiment)
In this embodiment, a method for manufacturing a photoelectric conversion device will be described. FIGS. 5A to 5E show a flow of the manufacturing method.

  First, as shown in FIG. 5A, a first conductivity type (N type) well (not shown) and a second conductivity type (P type) well 39 are formed on a semiconductor substrate 38 such as silicon, and STI is formed. Then, the element isolation region 41 is formed by a selective oxidation method or the like. 5A to 5E, the photoelectric conversion region 101 and the peripheral circuit region 102 are illustrated adjacent to each other.

  Subsequently, as shown in FIG. 5B, after the gate electrodes 31, 32, and 42 of each MOS transistor are formed of polysilicon, an n-type impurity is introduced to form a semiconductor region of the photodiode that constitutes the photoelectric conversion element. 33 is formed. Next, a p-type impurity is introduced to form a surface p-type region 35 for embedding a photodiode.

  Next, n-type impurities are introduced by ion implantation using the gate electrode as a mask to form semiconductor regions 3, 34, and 44 constituting a part of the low impurity concentration source and drain that are self-aligned with the side surface of the gate electrode.

  Then, a thin silicon oxide film 30b is formed on the surface of the semiconductor substrate excluding the element isolation region and the gate electrode. The thin silicon oxide film 30b may leave the gate oxide film on the surface of the semiconductor substrate in anisotropic dry etching for forming a polysilicon gate electrode. Alternatively, it may be formed by thermal oxidation before depositing a silicon nitride film 36 described later. Alternatively, it may be formed by deposition.

  Then, as shown in FIG. 5C, a silicon nitride film 36 is formed, and a silicon oxide film 37 is formed thereon. The insulating films 36 and 37 made of the silicon nitride film and the silicon oxide film are formed so as to cover the photoelectric conversion region 101 and the peripheral circuit region 102. As a result, the photoelectric conversion region can be protected. This laminated structure functions as an antireflection film on the light receiving surface of the photoelectric conversion element.

  Next, a resist 50 is formed on the photoelectric conversion region, and the silicon nitride film 36 and the silicon oxide film 37 in the peripheral circuit region 102 are etched back. Thus, as shown in FIG. 5D, side spacers made of the silicon nitride film 36b and the silicon oxide film 37b are formed on the side walls of the gate electrode 42 in the peripheral circuit region 102. Then, heat treatment is performed to form a silicon oxide film 117 on the gate electrode 42. Further, the silicon oxide film 30c is subjected to additional oxidation by this heat treatment to increase the thickness of the silicon oxide film. Thereby, the film thickness is made thicker than the silicon oxide film 30c disposed in the photoelectric conversion region.

  Then, an n-type impurity is introduced using the gate electrode and the side spacer in the peripheral circuit region 102 as a mask for ion implantation. As a result, a semiconductor region 43 having a high impurity concentration constituting a source and a drain that are self-aligned with the side surfaces of the side spacers is formed. At this time, the amount of impurity ions implanted into the channel portion through the silicon oxide film 117 through the gate electrode 42 can be reduced. Thus, a structure as shown in FIG. 5D is obtained.

  Next, as shown in FIG. 5E, an insulating film 40 such as BPSG functioning as an interlayer insulating film is formed so as to cover the photoelectric conversion region and the entire peripheral circuit region. Next, the contact holes 42a and 42b are opened by anisotropic dry etching using the silicon nitride film 36a in the photoelectric conversion region as an etching stopper. Then, a contact hole in which a contact portion of the contact bottom portion of the photoelectric conversion region 101 is self-aligned is formed on the semiconductor substrate. Then, the contact holes 42a and 42b are filled with a conductor to form electrodes. In this way, the structure shown in FIG. 5E is obtained.

  In any step after the formation of the silicon oxide film, it is desirable to perform heat treatment at 350 ° C. or higher.

  As shown in FIG. 5 (e), the film thickness h1 of the silicon oxide film disposed between the antireflection film and the light receiving surface of the photoelectric conversion element, the side spacer disposed in the MOS transistor in the peripheral circuit region, When the thickness h2 of the silicon oxide film disposed between the drain and the drain is compared, h2 is thicker. As a result, it is possible to increase the operation speed of the MOS transistors in the peripheral circuit region and reduce the influence of hot carriers.

  In the above description, an example using an nMOS transistor has been described. However, when a photoelectric conversion device is manufactured by a CMOS process, a pMOS transistor can be similarly manufactured by changing the conductivity type.

  As described above, in this embodiment, the source and drain of the MOS transistor arranged in the photoelectric conversion region have a single drain structure composed of a low impurity concentration semiconductor region. The MOS transistor arranged in the peripheral circuit region has an LDD structure. The low impurity concentration region of the MOS transistor arranged in the photoelectric conversion region can be formed in the same process as the low impurity concentration region of the LDD structure of the MOS transistor arranged in the peripheral circuit region.

  The photoelectric conversion device formed by such a process achieves both suppression of characteristic deterioration due to hot carriers of MOS transistors in the photoelectric conversion area, realization of high drive capability of MOS transistors in peripheral circuit areas, and suppression of characteristic deterioration due to hot carriers. be able to.

  In addition, when the antireflection film is used as an etching stopper, the contact hole of the photoelectric conversion portion contacts only the surface of the semiconductor substrate in a self-aligning manner, so that leakage current between the source / drain and well of the MOS transistor can be suppressed. .

  Further, if the insulating film is used as an antireflection film and a contact etching stopper in the photoelectric conversion region and is used as a side spacer of the MOS transistor in the peripheral circuit portion, the manufacturing cost can be reduced.

  Further, when the insulating film is formed of a silicon nitride film containing a large amount of hydrogen molecules, trapping at the transistor interface or the silicon / silicon oxide film interface on the photodiode can be more effectively reduced.

(Example of imaging system)
FIG. 6 shows an example of a circuit block when the above-described photoelectric conversion device is applied to a camera. A shutter 1001 is provided in front of the taking lens 1002 and controls exposure. The amount of light is controlled by the aperture 1003 as necessary, and an image is formed on the photoelectric conversion device 1004. A signal output from the photoelectric conversion device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The output digital signal is further processed by a signal processing unit 1007. The processed digital signal is stored in the memory 1010 or sent to an external device through the external I / F 1013. The photoelectric conversion device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008, and the entire system is controlled by an overall control unit / calculation unit 1009. In order to record an image on the recording medium 1012, the output digital signal is recorded through a recording medium control I / F unit 1011 controlled by the overall control unit / arithmetic unit.

It is an example of the schematic top view of the photoelectric conversion apparatus concerning this invention. It is an example of the top view and sectional drawing of the MOS transistor concerning this invention. It is an example of the equivalent circuit schematic of a photoelectric conversion apparatus. It is sectional drawing of the photoelectric conversion apparatus of 1st Embodiment. It is a manufacturing process flowchart of the photoelectric conversion apparatus of a 2nd Example. It is a block diagram which shows an example of an imaging system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element 101 Photoelectric conversion area | region 102 Peripheral circuit area 2, 4, 5, 109 MOS transistor distribute | arranged to a photoelectric conversion area 110 MOS transistor distribute | arranged to a peripheral circuit area | region 106,107 Antireflection film

Claims (7)

A photoelectric conversion region in which a plurality of photoelectric conversion elements and a first MOS transistor for reading a signal based on charges of the photoelectric conversion elements are arranged;
A peripheral circuit region in which a second MOS transistor that performs at least one of driving the first MOS transistor or amplifying a signal read from the photoelectric conversion region is disposed on the same semiconductor substrate;
A photoelectric conversion device in which an antireflection film is disposed on a light receiving surface of the photoelectric conversion element,
The impurity concentration of the drain of the first MOS transistor is lower than the impurity concentration of the drain of the second MOS transistor,
It said second MOS transistor has an LDD structure in which the side spacer was arranged made of an insulating film containing silicon nitride film on the side wall of the gate electrode,
The silicon oxide film disposed between the side spacer and the drain is thicker than the silicon oxide film disposed between the antireflection film disposed in the photoelectric conversion region and the light receiving surface of the photoelectric conversion element. A featured photoelectric conversion device. The photoelectric conversion device according to claim 1, wherein the antireflection film includes a silicon nitride film. The photoelectric conversion device according to claim 2, wherein the silicon nitride film of the antireflection film and the silicon nitride film of the side spacer are formed of the same film. The antireflection film includes a silicon oxide film provided on the silicon nitride film,
4. The photoelectric conversion device according to claim 2, wherein the side spacer includes a silicon oxide film provided on the silicon nitride film. 5. The photoelectric conversion device according to any one of claims 1 to 4, characterized in that the silicon oxide film is disposed on the gate electrode upper surface of the second MOS transistor. 6. The photoelectric conversion device according to claim 5, wherein the silicon oxide film on the upper surface of the gate electrode of the second MOS transistor is formed by thermal oxidation. Having a photoelectric conversion device according, an optical system for focusing light to the photoelectric conversion device, and a signal processing circuit for processing an output signal from the photoelectric conversion device to any one of claims 1 to 6 An imaging system characterized by the above.

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