JP2017130693A - Image pickup device and manufacturing method thereof - Google Patents

Image pickup device and manufacturing method thereof Download PDF

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JP2017130693A
JP2017130693A JP2017079822A JP2017079822A JP2017130693A JP 2017130693 A JP2017130693 A JP 2017130693A JP 2017079822 A JP2017079822 A JP 2017079822A JP 2017079822 A JP2017079822 A JP 2017079822A JP 2017130693 A JP2017130693 A JP 2017130693A
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insulating film
film
formed
forming
waveguide
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孝宏 冨松
Takahiro Tomimatsu
孝宏 冨松
神野 健
Takeshi Jinno
健 神野
川村 武志
Takeshi Kawamura
武志 川村
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ルネサスエレクトロニクス株式会社
Renesas Electronics Corp
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Abstract

Deterioration of sensitivity of a pixel portion due to variation in distance between a waveguide and a photodiode and attenuation of light due to suppression of reflection of incident light is prevented.
In a pixel region PE, a waveguide WG that penetrates a fourth interlayer insulating film IF4 and the like and reaches a sidewall insulating film SWI is formed. The sidewall insulating film SWI has a laminated structure of a silicon oxide film and a silicon nitride film. The waveguide WG is formed so as to penetrate the silicon nitride film of the sidewall insulating film and reach the silicon oxide film SWO of the sidewall insulating film, or to reach the silicon nitride film of the sidewall. Yes.
[Selection] Figure 1

Description

  The present invention relates to an imaging device and a manufacturing method thereof, and in particular, can be suitably used for an imaging device provided with a waveguide.

  For example, an imaging apparatus including a CMOS (Complementary Metal Oxide Semiconductor) image sensor is applied to a digital camera or the like. Such an imaging device includes a pixel portion in which a photodiode that converts incident light into electric charges is formed, and a peripheral circuit portion that processes the electric charge converted by the pixel portion as an electric signal.

  In recent years, in order to cope with the miniaturization of digital cameras and the like, imaging apparatuses having a small pixel size in the pixel portion are increasingly required. As the pixel size decreases, the quantum efficiency inside silicon (Si) tends to decrease. Quantum efficiency refers to the number of output electrons per photon, and the higher the quantum efficiency within silicon (Si), the higher the sensitivity of the pixel portion.

  In order to improve the quantum efficiency inside the silicon (Si) as much as possible, there has been proposed an imaging device provided with a waveguide for guiding light to the photodiode of the pixel portion. In this type of imaging device, the waveguide is formed by etching an interlayer insulating film that covers the photodiode to form an opening, and filling the opening with a predetermined embedding material. Patent Documents 1 and 2 are patent documents that disclose an imaging device including a waveguide.

JP 2006-351759 A JP 2006-310825 A

  The conventional imaging apparatus has the following problems. In order to efficiently guide the incident light to the photodiode, it is necessary to control the distance between the waveguide and the photodiode (film thickness of the remaining film).

  In order to control this distance, the inventors made and evaluated an imaging device in which an etching stopper film was inserted in the middle of the interlayer insulating film. As a result, a plurality of antireflection films including an etching stopper film are formed on the photodiode, so that light is attenuated. Therefore, in order to improve the transmittance of the silicon (Si) substrate, the etching stopper film It has been found that it is necessary to form an opening (waveguide) so as to penetrate through. For this reason, in the structure in which the etching stopper film is inserted, the distance between the waveguide and the photodiode still varies within the wafer surface and between lots.

  In the conventional imaging device, there is a deterioration in the sensitivity of the pixel portion due to such a variation in the distance between the waveguide and the photodiode and attenuation of light due to the antireflection film of incident light.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An imaging device according to an embodiment includes a sidewall insulating film that covers a sidewall surface of a gate electrode of a transfer transistor and includes a portion that extends from a portion that covers the sidewall surface and covers a surface of the photoelectric conversion unit, and an interlayer A waveguide that penetrates the insulating film and reaches the sidewall insulating film and guides light to the photoelectric conversion unit.

  An imaging device manufacturing method according to another embodiment forms a predetermined insulating film so as to cover a gate electrode and a photoelectric conversion unit of a transfer transistor, and processes the predetermined insulating film to thereby form a gate electrode. Covering the sidewall surface, forming a sidewall insulating film including a portion extending from the portion covering the sidewall surface and covering the surface of the photoelectric conversion portion, and forming an opening reaching the sidewall insulating film in the interlayer insulating film And a step of forming a waveguide for guiding light to the photoelectric conversion unit in the opening.

  According to the imaging device according to the embodiment, the sensitivity of the pixel portion is improved, and the variation in sensitivity within the wafer surface of each pixel due to the variation in the distance between the waveguide and the photodiode, or between lots. It is possible to suppress variations in sensitivity.

  According to the method for manufacturing an imaging device according to another embodiment, an imaging device capable of improving the sensitivity of the pixel unit can be manufactured.

It is sectional drawing of the imaging device which concerns on embodiment. FIG. 4 is a first partial enlarged cross-sectional view of a pixel region in the same embodiment. FIG. 6 is a second partial enlarged cross-sectional view of a pixel region in the same embodiment. FIG. 10 is a cross-sectional view showing a step of the manufacturing method of the imaging device in the embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a partial cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a partial cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a partial cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a partial cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a partial cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a partial cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a partial cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. It is sectional drawing which shows the imaging device which concerns on a comparative example. It is sectional drawing which shows 1 process of the manufacturing method of the imaging device which concerns on a comparative example. In the embodiment, it is a fragmentary sectional view which shows 1 process of the manufacturing method of the imaging device which concerns on a modification. FIG. 30 is a partial cross-sectional view showing a step performed after the step shown in FIG. 29 in the same embodiment. FIG. 31 is a partial cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a partial cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a partial cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. FIG. 34 is a partial cross-sectional view showing a step performed after the step shown in FIG. 33 in the same embodiment.

  An imaging device and a manufacturing method thereof according to an embodiment will be described. As shown in FIG. 1, in the imaging device IS, the pixel region PE and the peripheral circuit region PC are defined by forming the element isolation insulating film EI on the semiconductor substrate SUB. In the pixel region PE, a p-type well PPW is formed from the surface of the semiconductor substrate SUB to a predetermined depth. In the p-type well PPW, a photodiode PD that converts light incident from the outside into electric charges and a transfer transistor TT that transfers the electric field are formed.

  The photodiode PD has an n-type region NR and a p-type region PR each formed at a predetermined depth from the surface of the p-type well PPW. The transfer transistor TT has a gate electrode TGE of the transfer transistor TT formed on the surface of the p-type well PPW with a gate insulating film TGI interposed therebetween. A sidewall insulating film SWI is formed to cover the side wall surface of the gate electrode TGE. The sidewall insulating film SWI includes a portion extending from the portion covering the side wall surface and covering the photodiode PD. The sidewall insulating film SWI formed in the pixel region PE is intended to include a portion extending from the portion covering the photodiode PD in addition to a portion covering the sidewall surface of the gate electrode TGE. A contact etch stress liner film CESL is formed so as to cover the sidewall insulating film SWI.

  On the other hand, the peripheral circuit region PC has a pixel transistor region in which a transistor of a pixel that processes an electrical signal converted from an electric charge is formed, and a logic region in which a transistor for a logic circuit that exchanges various signals is formed. doing.

  In the pixel transistor region, a p-type well IPW and an n-type well INW are respectively formed from the surface of the semiconductor substrate SUB to a predetermined depth. An n-channel MOS transistor INT is formed in the p-type well IPW, and a p-channel MOS transistor IPT is formed in the n-type well INW.

  The n-channel MOS transistor INT has a gate electrode ING and an n-type source / drain region INSD. The gate electrode ING is formed on the surface of the p-type well IPW with a gate insulating film IGI interposed therebetween. The p-channel MOS transistor IPT has a gate electrode IPG and a p-type source / drain region IPSD. The gate electrode IPG is formed on the surface of the n-type well INW with a gate insulating film IGI interposed therebetween.

  In the logic region, a p-type well LPW and an n-type well LNW are respectively formed from the surface of the semiconductor substrate SUB to a predetermined depth. An n-channel MOS transistor LNT is formed in the p-type well LPW, and a p-channel MOS transistor LPT is formed in the n-type well LNW.

  The n-channel type MOS transistor LNT has a gate electrode LNG and an n-type source / drain region LNSD. The gate electrode LNG is formed on the surface of the p-type well LPW with a gate insulating film LGI interposed therebetween. The p-channel MOS transistor LPT has a gate electrode LPG and a p-type source / drain region LPSD. The gate electrode LPG is formed on the surface of the n-type well LNW with the gate insulating film LGI interposed.

  A sidewall insulating film SWF is formed on each sidewall surface of the gate electrodes ING, IPG, LNG, and LPG. Each surface (upper surface) of the gate electrodes ING, IPG, LNG, LPG, each surface of the n-type source / drain regions INSD, LNSD, and each surface of the p-type source / drain regions IPSD, LPSD A silicide film MS is formed. A contact etch stress liner film CESL film is formed so as to cover the gate electrodes ING, IPG, LNG, LPG and the like.

  A first interlayer insulating film IF1 is formed as a contact interlayer insulating film so as to cover the photodiode PD, the transfer transistor TT, the n-channel MOS transistors INT and LNT, the p-channel MOS transistors IPT and LPT, and the like. . A first wiring M1 is formed on the surface of the first interlayer insulating film IF1. The first wiring M1 and the corresponding n-type source / drain regions INSD and LNSD and p-type source / drain regions IPSD and LPSD are electrically connected by contact plugs CP, respectively. The contact plug CP is formed so as to penetrate the first interlayer insulating film IF1.

  A second interlayer insulating film IF2 is formed on the first interlayer insulating film IF1 so as to cover the first wiring M1. A second wiring M2 is formed on the surface of the second interlayer insulating film IF2. The second wiring M2 and the corresponding first wiring M1 are electrically connected by the first via V1, respectively. The first via V1 is formed so as to penetrate the second interlayer insulating film IF2.

  A third interlayer insulating film IF3 is formed on the second interlayer insulating film IF2 so as to cover the second wiring M2. A third wiring M3 and a pad PDE are formed on the surface of the third interlayer insulating film IF3. The third wiring M3 and the corresponding second wiring M2 are electrically connected by the second via V2, respectively. The second via V2 is formed so as to penetrate the third interlayer insulating film IF3.

  A fourth interlayer insulating film IF4 is formed on the third interlayer insulating film IF3 so as to cover the third wiring M3 and the pad PDE. In the peripheral circuit region PC, a passivation film PAF is formed so as to cover the fourth interlayer insulating film IF4.

  In the pixel region PE, the fourth interlayer insulating film IF4, the third interlayer insulating film IF3, the second interlayer insulating film IF2, the first interlayer insulating film IF1, and the contact etch stress liner film CESL film are penetrated to form the sidewall insulating film SWI. A reaching waveguide WG is formed. The waveguide WG is filled with the protective film PF formed on the surface of the waveguide opening WGH formed so as to penetrate the fourth interlayer insulating film IF4 and the like, and the waveguide opening WGH covered with the protective film PF The embedded member FI is provided. For example, a silicon nitride film is applied as the protective film PF. As the embedded member FI, a coating material is applied, and for example, a siloxane material is used. A color filter CF and a microlens ML are formed on the waveguide WG.

  In the imaging device IS according to the present embodiment, the sidewall insulating film SWI has a laminated structure of the silicon oxide film SWO and the silicon nitride film SWN (see FIGS. 2 and 3), and silicon nitride is formed on the silicon oxide film. A film is formed. Sidewall insulating film SWI includes a portion covering the side wall surface of gate electrode TGE and a portion extending from the portion covering the side wall surface and covering photodiode PD. For the sidewall insulating film SWI (the portion covering the photodiode PD), there are two formation modes of the waveguide WG: a first formation mode and a second formation mode.

  That is, in the first formation mode, as shown in FIG. 2, the waveguide WG penetrates the silicon nitride film SWN of the sidewall insulating film SWI and reaches the silicon oxide film SWO of the sidewall insulating film SWI. Is formed. In the second formation mode, as shown in FIG. 3, the waveguide WG is formed so as to reach the silicon nitride film SWN on the sidewall. As will be described later, the deterioration of the sensitivity of the pixel portion is suppressed by setting the waveguide WG to the first formation mode or the second formation mode.

  Next, an example of a method for manufacturing the above-described imaging device will be described. First, as shown in FIG. 4, the pixel region PE and the peripheral circuit region PC are defined by forming the element isolation insulating film EI on the semiconductor substrate SUB.

  Next, the gate electrode TGE and the photodiode PD are formed in the pixel region PE. Gate electrodes ING, IPG, LNG, and LPG are formed in the peripheral circuit region PC. Next, by performing a predetermined photolithography process, a resist pattern RP2 that exposes the n-type well INW where the gate electrode IPG is formed and covers other regions is formed. Next, an extension region (not shown) is formed by implanting p-type impurities using resist pattern RP2 as a mask. Thereafter, the resist pattern RP2 is removed.

  Next, as shown in FIG. 5, by performing a predetermined photoengraving process, a resist pattern RP3 is formed that exposes the p-type well IPW in which the gate electrode ING is formed and covers other regions. Next, an extension region (not shown) is formed by implanting an n-type impurity using the resist pattern RP3 as a mask. Thereafter, the resist pattern RP3 is removed.

  Next, an offset spacer film is formed on the side wall surfaces of the gate electrodes ING, IPG, LNG, and LPG as necessary. First, an insulating film (not shown) serving as an offset spacer film is formed so as to cover the gate electrode TGE and the gate electrodes ING, IPG, LNG, and LPG. Next, as shown in FIG. 6, an etching process is performed using a resist pattern RP4 that covers the photodiode PD and exposes other regions as a mask. By this etching process, an offset spacer film (not shown) is formed on the side wall surfaces of the gate electrodes ING, IPG, LNG, and LPG.

  Next, as shown in FIG. 7, a predetermined photoengraving process is performed to form a resist pattern RP5 that exposes the p-type well LPW and covers other regions. Next, an extension region (not shown) is formed by implanting n-type impurities using resist pattern RP5 as a mask. Thereafter, resist pattern RP5 is removed.

  Next, as shown in FIG. 8, a predetermined photoengraving process is performed to form a resist pattern RP6 that exposes the n-type well LNW and covers other regions. Next, an extension region (not shown) is formed by implanting p-type impurities using resist pattern RP6 as a mask. Thereafter, resist pattern RP6 is removed.

  Next, a sidewall insulating film that covers the photodiode PD and the gate electrode TGE is formed. First, a predetermined insulating film (not shown) having a stacked structure in which a silicon nitride film is stacked on a silicon oxide film is formed so as to cover the gate electrode TGE and the gate electrodes ING, IPG, LNG, and LPG. Next, as shown in FIG. 9, a predetermined photolithography process is performed to form a resist pattern RP7 that covers the photodiode PD and the gate electrode TGE and exposes other regions.

  Next, an etching process is performed on a predetermined insulating film using resist pattern RP7 as a mask. Thereby, in the pixel region PE, the remaining insulating film is formed as a sidewall insulating film SWI that covers the photodiode PD and the gate electrode TGE. Sidewall insulating film SWI includes a portion covering the side wall surface of gate electrode TGE and a portion extending from the portion covering the side surface and covering photodiode PD. In the peripheral circuit region PC, a sidewall insulating film SWF is formed on the sidewall surfaces of the gate electrodes ING, IPG, LNG, and LPG. Thereafter, the resist pattern RP7 is removed.

  Next, as shown in FIG. 10, by performing a predetermined photolithography process, a resist pattern RP8 that exposes the n-type wells INW and LNW and covers other regions is formed. Next, by implanting p-type impurities using the resist pattern RP8 as a mask, a source / drain region IPSD is formed in the n-type well INW, and a source / drain LPSD is formed in the n-type well LNW. The Thereafter, resist pattern RP8 is removed.

  Next, as shown in FIG. 11, by performing a predetermined photolithography process, a resist pattern RP9 that exposes the p-type wells IPW and LPW and covers other regions is formed. Next, by implanting an n-type impurity using the resist pattern RP9 as a mask, a source / drain region INSD is formed in the p-type well IPW, and a source / drain region LNSD is formed in the p-type well LPW. Is done. Thereafter, the resist pattern RP9 is removed.

  Next, a silicide block film (not shown) that covers the pixel region PE and exposes the peripheral circuit region PC to prevent metal silicidation is formed. For example, a metal film (not shown) such as cobalt is formed so as to cover the silicide block film and the gate electrodes ING, IPG, LNG, LPG and the like. Next, heat treatment is performed under a predetermined temperature and atmosphere to perform metal silicidation in which metal and silicon are reacted. Thereafter, the unreacted metal film is removed. As a result, as shown in FIG. 12, the metal silicide film MS is formed on the upper surfaces of the gate electrodes ING, IPG, LNG, and LPG, and the metal silicide film MS is formed on the surfaces of the source / drain regions INSD, IPSD, LNSD, and LPSD. Is done. Next, a contact etch stress liner film CESL made of, for example, a silicon nitride film is formed so as to cover the gate electrode TGE and the gate electrodes ING, IPG, LNG, LPG, and the like.

  Next, as shown in FIG. 13, a first interlayer insulating film IF1 is formed as a contact interlayer insulating film made of, for example, a TEOS (Tetra Ethyl Ortho Silicate) oxide film so as to cover the contact etch stress liner film CESL. . Next, a predetermined photolithography process is performed to form a resist pattern (not shown) for forming contact holes. Next, using the resist pattern as a mask, the first interlayer insulating film IF1 is etched, and then the resist pattern is removed. As a result, as shown in FIG. 13, contact holes CH exposing the source / drain regions INSD, IPSD, LNSD, and LPSD (metal silicide film MS) are formed.

  Next, as shown in FIG. 14, a contact plug PG is formed in the contact hole CH. The contact plug PG includes a barrier metal. Next, for example, a metal film such as aluminum is formed so as to cover the first interlayer insulating film IF1. Next, the first wiring M1 made of aluminum is formed by subjecting the metal film to predetermined photolithography and etching.

  Next, as shown in FIG. 15, the second interlayer insulating film IF2 is formed so as to cover the first wiring M1. Next, a predetermined photolithography process is performed to form a resist pattern (not shown) for forming a via hole. Next, using the resist pattern as a mask, the second interlayer insulating film IF2 is etched, and then the resist pattern is removed. As a result, as shown in FIG. 15, the first via hole VH1 exposing the first wiring M1 is formed.

  Next, as shown in FIG. 16, the first via V1 is formed in the first via hole VH1. Next, for example, a metal film such as aluminum is formed so as to cover the second interlayer insulating film IF2. Next, a predetermined photoengraving process and an etching process are performed on the metal film, thereby forming the second wiring M2 made of aluminum.

  Next, as shown in FIG. 17, a third interlayer insulating film IF3 is formed so as to cover the second wiring M2. Next, a predetermined photolithography process is performed to form a resist pattern (not shown) for forming a via hole. Next, the third interlayer insulating film IF3 is etched using the resist pattern as a mask, and then the resist pattern is removed. Thereby, as shown in FIG. 17, the second via hole VH2 exposing the second wiring M2 is formed.

  Next, as shown in FIG. 18, the second via V2 is formed in the second via hole VH2. Next, for example, a metal film such as aluminum is formed so as to cover the third interlayer insulating film IF3. Next, a predetermined photolithography process and etching process are performed on the metal film, whereby a pad PDE is formed in the pixel region PE, and a third wiring M3 made of aluminum is formed in the peripheral circuit region. Next, as shown in FIG. 19, a fourth interlayer insulating film IF4 is formed so as to cover the pad PDE and the third wiring M3.

  Next, a waveguide is formed in the pixel region PE. As shown in FIG. 20, a resist pattern RP10 for forming a waveguide opening serving as a waveguide is formed by performing a predetermined photolithography process. Next, etching is performed on the fourth interlayer insulating film IF4 and the like using the resist pattern RP10 as a mask, thereby, as shown in FIG. 21, the fourth interlayer insulating film IF4 to the first interlayer insulating film IF1 and the contact etch stress liner. A waveguide opening WGH that penetrates the film CESL and exposes the sidewall insulating film SWI is formed.

  At this time, as already described, there are two formation modes of the waveguide opening WGH. In the first formation mode, the waveguide opening WGH is formed so as to penetrate the silicon nitride film SWN of the sidewall insulating film SWI and reach the silicon oxide film SWO of the sidewall insulating film SWI. In the second formation mode, the waveguide opening WGH is formed so as to reach the silicon nitride film SWN on the sidewall. Thereafter, resist pattern RP10 is removed.

  Next, as shown in FIG. 22, for example, a protective film PF made of a silicon nitride film is formed so as to cover the surface of the waveguide opening WGH. Next, as shown in FIG. 23, the waveguide opening WGH is filled with, for example, a siloxane embedded member FI as a coating system material. Next, as shown in FIG. 24, by performing a predetermined photoengraving process, a resist pattern RP11 for forming an opening exposing the pad PDE is formed. Next, using the resist pattern RP11 as a mask, the embedded member FI is etched to form an opening PDEH that exposes the pad PDE, as shown in FIG.

  Next, as shown in FIG. 26, the resist pattern RP11 is removed, and the waveguide WG is formed. Thereafter, as shown in FIG. 1, a passivation film PAF made of a silicon nitride film or the like is formed in the peripheral circuit region PC. In the pixel region PE, the color filter CF and the microlens ML are formed. Thus, the main part of the imaging device is formed.

  In the imaging device described above, the waveguide WG is formed so as to reach the sidewall insulating film SWI, so that deterioration in sensitivity of the pixel portion is suppressed. This will be described with the imaging device according to the comparative example.

  As shown in FIG. 27, a photodiode CPD including an n-type region CNR and a p-type CPR and a transfer transistor CTT are formed in the pixel region CPE of the imaging device according to the comparative example. In the peripheral circuit region CPC, an n-channel MOS transistor CINT and a p-channel MOS transistor CIPT are formed as pixel transistors for processing an electric signal converted from electric charges. Further, an n-channel MOS transistor CLNT and a p-channel MOS transistor CLPT are formed as logic circuit transistors for exchanging various signals.

  A contact etch stress liner film CCESL formed of a silicon nitride film is formed so as to cover these MOS transistors CINT, CIPT, CLNT, CLPT and transfer transistor CTT. The first layer is formed so as to cover the contact etch stress liner film CCESL. A lower interlayer insulating film CIF11 is formed. A first upper interlayer insulating film CIF12 is formed on the first lower interlayer insulating film CIF11 with an etching stopper film CES made of a silicon nitride film interposed therebetween. A first wiring CM1 is formed on the surface of the first upper interlayer insulating film CIF12.

  A second interlayer insulating film CIF2 is formed so as to cover the first wiring CM1. A second wiring M2 is formed on the surface of the second interlayer insulating film CIF2. A third interlayer insulating film CIF3 is formed so as to cover the second wiring M2. A third wiring M3 is formed on the surface of the third interlayer insulating film CIF3. A fourth interlayer insulating film CIF4 is formed so as to cover the third wiring M3.

  In the imaging device according to the comparative example, in order to control the distance between the waveguide and the photodiode CPD, an etching stopper is provided between the first lower interlayer insulating film CIF11 and the first upper interlayer insulating film CIF12 as a contact interlayer film. The film CES is interposed. However, in order to avoid attenuation of light due to the antireflection effect due to the etching stopper film CES by the silicon nitride film, the waveguide CWG is formed so as to penetrate the etching stopper film CES and reach the first lower interlayer insulating film CIF11. Is done. That is, as shown in FIG. 28, the waveguide opening CWGH serving as the waveguide is formed so as to reach the first lower interlayer insulating film CIF11.

  For this reason, in the imaging device according to the comparative example, the distance between the waveguide CWG and the photodiode CPD (see the arrow in FIG. 27) still varies, and this variation in distance is a cause of variation in sensitivity of the photodiode CPD. It becomes. Further, the contact etch stress liner film CCESL covering the transfer transistor CTT acts as an antireflection film, and light is attenuated. For this reason, the sensitivity of the photodiode CPD is deteriorated.

  Further, an etching stopper film CES made of a silicon nitride film is formed on the entire surface of the semiconductor substrate. For this reason, in the peripheral circuit region, the interlayer capacitance between the MOS transistors CINT, CIPT, CLNT, CLPT and the etching stopper film CES increases, and the operation speed decreases.

  Further, since the etching stopper film CES having different etching characteristics is interposed between the first lower interlayer insulating film CIF11 and the first upper interlayer insulating film CIF12, the first lower interlayer insulating film is formed when the contact hole is formed. The etching rate of the film CIF11 and the first upper interlayer insulating film CIF12 is different from the etching rate of the etching stopper film CES. For this reason, the opening diameter of the contact hole varies, and the MOS transistor CINT, CIPT, CLNT, CLPT and the first wiring CM1 may not be electrically connected. Furthermore, the barrier property of the barrier metal of the contact plug formed in the contact hole may deteriorate.

  In contrast to the comparative example, in the imaging device according to the embodiment, the etching stopper film having different etching characteristics is not interposed in the first interlayer insulating film IF1 as the contact interlayer insulating film. The waveguide WG passes through the fourth interlayer insulating film IF4, the third interlayer insulating film IF3, the second interlayer insulating film IF2, the first interlayer insulating film IF1, and the contact etch stress liner film CESL and reaches the sidewall insulating film SWI. It is formed as follows.

  The sidewall insulating film SWI extends from the portion covering the side wall surface of the gate electrode TGE of the transfer transistor TT and covers the photodiode PD. Therefore, the sidewall insulating film SWI is located in the vicinity of the surface of the photodiode PD. Thereby, the distance between the waveguide WG formed so as to reach the sidewall insulating film SWI and the photodiode PD can be shortened, and the sensitivity of the photodiode PD can be improved. Further, since the waveguide WG approaches the photodiode PD, the variation in sensitivity of the photodiode PD corresponding to the variation in the film thickness of the remaining film of the waveguide WG and the photodiode PD corresponding to the distance is reduced.

  Furthermore, an etching stopper film made of a silicon nitride film is not formed on the entire surface of the semiconductor substrate. Thereby, there is no interlayer capacitance as in the imaging device according to the comparative example, and the operation speed of the MOS transistors INT, IPT, LNT, and LPT is not lowered in the peripheral circuit region PC. Further, unlike the imaging device according to the comparative example, the opening diameter of the contact hole does not vary, and the MOS transistor CINT, CIPT, CLNT, CLPT and the first wiring CM1 can be electrically connected. Furthermore, the barrier property of the barrier metal (not shown) of the contact plug CP formed in the contact hole CH is not deteriorated. Further, by improving the sensitivity of the photodiode, the inclination angle (taper angle) of the waveguide opening WGH of the waveguide WG may be relaxed, and the etching process margin is improved.

Modified Example In the imaging device described above, the case where the waveguide WG is formed using a coating material has been described. As the waveguide, besides a coating material, for example, a CVD (Chemical Vapor Deposition) film may be applied. The manufacturing method will be described. As shown in FIG. 29, the pad PDE is formed on the surface of the third interlayer insulating film IF3 in the pixel region PE through the same processes as those shown in FIGS.

  Next, as shown in FIG. 30, by performing a predetermined photoengraving process, a resist pattern RP12 for forming a waveguide opening serving as a waveguide is formed. Next, by etching the third interlayer insulating film IF3 and the like using the resist pattern RP12 as a mask, as shown in FIG. 31, the third interlayer insulating film IF3 to the first interlayer insulating film IF1 and the contact etch stress liner A waveguide opening WGH that penetrates the film CESL and exposes the sidewall insulating film SWI is formed. Thereafter, as shown in FIG. 32, resist pattern RP12 is removed.

  Next, as shown in FIG. 33, for example, a buried film FF such as a silicon nitride film is formed by a chemical vapor deposition method so as to fill the waveguide opening WGH. Next, by performing an etch-back process on the buried film FF, as shown in FIG. 34, the buried film FF located on the upper surface of the third interlayer insulating film IF3 is removed. Thus, the buried film FF left in the waveguide opening WGH is formed as the waveguide WG. Thereafter, the main part of the imaging device is formed through the same process as the manufacturing process described above.

  Also in the imaging device according to the modification, the waveguide WG made of the buried film FF is formed so as to penetrate the third interlayer insulating film IF3 and the like and reach the sidewall insulating film SWI. Thereby, the sensitivity of the photodiode PD can be improved as in the above-described imaging device.

  In the above-described imaging device, aluminum has been described as an example of the wiring material of the first wiring M1 to the third wiring M3. The wiring material is not limited to aluminum, and the above-described waveguide structure can also be applied to copper (wiring).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  IS imaging device, SUB semiconductor substrate, EI element isolation insulating film, PE pixel region, PPW P well, PD photodiode, NR n-type region, PR p-type region, TT transfer transistor, TGI gate insulating film, TGE gate electrode, SWI sidewall insulating film, SWN sidewall nitride film, SWO sidewall oxide film, CESL contact etch stress liner film, WG waveguide, PF protective film, FI embedded member, PDE pad, CF color filter, ML microlens, PC peripheral Circuit region, INT n-channel MOS transistor, IPW p-well, IPT p-channel MOS transistor, INW n-well, IGI gate insulating film, ING gate electrode, IPG gate electrode, SWF Side wall insulating film INSD source / drain region, IPSD source / drain region, MS metal silicide film, LNT n-channel MOS transistor, LPW p-well, LPT p-channel MOS transistor, LNW n-well, LGI gate insulating film, LNG gate electrode, LPG gate Electrode, SWF sidewall insulating film, LNSD source / drain region, LPSD source / drain region, MS metal silicide film, IF1 first interlayer insulating film, CP contact plug, M1 first wiring, IF2 second interlayer insulating film, V1 first 1 via, M2 second wiring, IF3 third interlayer insulating film, V2 second via, M3 third wiring, IF4 fourth interlayer insulating film, PAF passivation film, RP1, RP2, RP3, RP4, RP5, RP6, RP7, RP8, R P9, RP10, RP11, RP12 Photoresist pattern, WGH, PDEH Waveguide opening, CH contact hole, VH1, VH2 via hole, CES waveguide etch stopper film.

Claims (16)

  1. A semiconductor substrate having a main surface;
    A pixel region and a peripheral circuit region formed on the semiconductor substrate and defined by an element isolation insulating film;
    A photoelectric conversion unit that is formed in the pixel region and converts incident light into electric charge;
    A gate electrode of a transfer transistor that is formed on a surface of the pixel region and transfers charges generated in the photoelectric conversion unit;
    A sidewall insulating film that covers a side wall surface of the gate electrode and includes a portion that extends from a portion that covers the side wall surface and covers a surface of the photoelectric conversion unit;
    A transistor including another gate electrode formed in the peripheral circuit region;
    Another sidewall insulating film formed from the same film as the sidewall insulating film so as to cover the other sidewall surface of the other gate electrode;
    An interlayer insulating film formed to cover the sidewall insulating film and the other sidewall insulating film;
    A waveguide that penetrates the interlayer insulating film and reaches the sidewall insulating film and guides light to the photoelectric conversion unit,
    The sidewall insulating film is
    Silicon oxide film,
    A silicon nitride film formed in contact with the surface of the silicon oxide film,
    The imaging device, wherein the waveguide is formed so as to reach at least the silicon oxide film.
  2.   The imaging device according to claim 1, wherein the waveguide is formed so as to penetrate the silicon nitride film and reach the silicon oxide film.
  3. The waveguide is
    A protective film covering the surface of the opening that penetrates the interlayer insulating film;
    The imaging apparatus according to claim 1, further comprising an embedded member that fills the opening covered by the protective film.
  4. The protective film is a silicon nitride film,
    The imaging device according to claim 3, wherein the embedded member is a coating material.
  5.   The imaging apparatus according to claim 1, wherein the waveguide includes a predetermined film that fills an opening that penetrates the interlayer insulating film.
  6.   The imaging apparatus according to claim 5, wherein the predetermined film is a silicon nitride film.
  7.   The imaging device according to claim 1, wherein in the sidewall insulating film, the silicon oxide film and the silicon nitride film are stacked with the same pattern.
  8. A stress liner film formed to cover the sidewall insulating film, the other sidewall insulating film, and the other gate electrode;
    The imaging device according to claim 1, wherein the waveguide is formed so as to penetrate the stress liner film and reach the sidewall insulating film.
  9. Defining a pixel region and a peripheral circuit region by forming an element isolation insulating film on a semiconductor substrate having a main surface;
    Forming a gate electrode of a transfer transistor for transferring charges on the surface of the pixel region, and forming another gate electrode in the peripheral circuit region;
    Forming a photoelectric conversion unit that converts incident light into electric charges by injecting an impurity of a predetermined conductivity type into one region of the pixel region located across the gate electrode; and
    A predetermined insulating film is formed so as to cover the gate electrode, the photoelectric conversion unit, and the other gate electrode, and the predetermined insulating film is processed to cover a side wall surface of the gate electrode, and the side Forming a sidewall insulating film including a portion extending from a portion covering the wall surface and covering the surface of the photoelectric conversion unit, and another sidewall insulating film covering the other sidewall surface of the other gate electrode; ,
    Forming an interlayer insulating film so as to cover the sidewall insulating film and the other sidewall insulating film;
    Forming an opening reaching the sidewall insulating film in the interlayer insulating film, and forming a waveguide for guiding light to the photoelectric conversion unit so as to fill the opening.
    The step of forming the sidewall insulating film includes
    As the predetermined insulating film,
    Forming a silicon oxide film;
    Forming a silicon nitride film in contact with the surface of the silicon oxide film,
    In the step of forming the opening, the opening is formed to penetrate at least the silicon nitride film through the interlayer insulating film,
    In the step of forming the waveguide, the waveguide is formed so as to reach the silicon nitride film.
  10. In the step of forming the opening, the opening is formed to penetrate the interlayer insulating film and the silicon nitride film, expose the silicon oxide film, and reach the silicon oxide film,
    The method for manufacturing an imaging device according to claim 9, wherein in the step of forming the waveguide, the waveguide is formed to reach the silicon oxide film.
  11. The step of forming the waveguide comprises:
    Forming a protective film to cover the surface of the opening;
    The method for manufacturing an imaging device according to claim 9, further comprising a step of filling the opening covered with the protective film with a coating material.
  12.   The method of manufacturing an imaging device according to claim 11, wherein siloxane is applied as the coating material in the step of forming the waveguide.
  13.   The method of manufacturing an imaging device according to claim 9, wherein the step of forming the waveguide includes a step of forming a predetermined film so as to embed the opening.
  14.   The method of manufacturing an imaging device according to claim 13, wherein a silicon nitride film is applied as the predetermined film in the step of forming the waveguide.
  15. The step of forming the sidewall insulating film includes
    Forming a resist pattern covering the photoelectric conversion part and the gate electrode;
    And patterning the silicon oxide film and the silicon nitride film with the same pattern by performing an etching process on the silicon nitride film and the silicon oxide film using the resist pattern as an etching mask. 14. A method for manufacturing an imaging device according to any one of claims 14 to 14.
  16. Forming a stress liner film so as to cover the sidewall insulating film, the other sidewall insulating film, and the other gate electrode;
    The manufacturing method of the imaging device according to claim 9, wherein, in the step of forming the opening, the opening is formed so as to penetrate the stress liner film and reach the sidewall insulating film. Method.
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