JP4991474B2 - 二進法データ「0」および「1」を表わす磁気トランジスタ回路 - Google Patents
二進法データ「0」および「1」を表わす磁気トランジスタ回路 Download PDFInfo
- Publication number
- JP4991474B2 JP4991474B2 JP2007266043A JP2007266043A JP4991474B2 JP 4991474 B2 JP4991474 B2 JP 4991474B2 JP 2007266043 A JP2007266043 A JP 2007266043A JP 2007266043 A JP2007266043 A JP 2007266043A JP 4991474 B2 JP4991474 B2 JP 4991474B2
- Authority
- JP
- Japan
- Prior art keywords
- magnetic
- magnetic transistor
- binary data
- current direction
- transistor circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/90—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of galvano-magnetic devices, e.g. Hall-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/45—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Hall/Mr Elements (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
- Electronic Switches (AREA)
- Soft Magnetic Materials (AREA)
Description
130 経路選択線
131a 第1の電流方向
131b 第3の電流方向
132a 第2の電流方向
132b 第4の電流方向
140 低電圧端
160 コンデンサ
161 経路選択線の末端
162 低電圧端の末端
170 磁気トランジスタユニットの出力端
200 第1の磁気トランジスタ
211a 第1の磁性素子の双極子
212 金属装置
213 第1の磁性素子
216 第2の磁性素子
217 金属装置
218a 第2の磁性素子の双極子
220 高電圧端
230 第2の磁気トランジスタ
231a 第3の磁性素子の双極子
232 金属装置
233 第3の磁性素子
236 第4の磁性素子
237 金属装置
238a 第4の磁性素子の双極子
Claims (7)
- 二進法データ「1」および「0」をそれぞれに表わしている、互いに逆向きの第1の電流方向および第2の電流方向に沿って電流を流すことができる経路選択線と、
出力端が前記経路選択線の末端に接続されることで、前記電流が前記経路選択線に流れる方向を制御する磁気トランジスタユニットとを少なくとも備え、
前記磁気トランジスタユニットは、
高電圧端に接続されている第1の磁性素子および前記出力端に接続されている第2の磁性素子を有する第1の磁気トランジスタと、
前記出力端に接続されている第3の磁性素子および低電圧端に接続されている第4の磁性素子を有する第2の磁気トランジスタとを少なくとも備えることを特徴とする二進法データ「0」および「1」を表わす磁気トランジスタ回路。 - 前記経路選択線と低電圧端との間に接続されるコンデンサを更に備えたことを特徴とする請求項1に記載の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
- 第1の電流方向が前記磁気トランジスタユニットから前記コンデンサに向かう方向であり、第2の電流方向が前記コンデンサから前記磁気トランジスタユニットに向かう方向であることを特徴とする請求項2に記載の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
- 第2の電流方向が前記磁気トランジスタユニットから前記コンデンサに向かう方向であり、第1の電流方向が前記コンデンサから前記磁気トランジスタユニットに向かう方向であることを特徴とする請求項2に記載の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
- 前記出力端から延びる前記経路選択線が折り返されてコ字状をなしていることを特徴とする請求項1の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
- 高電圧端の電圧値が約2.5V、3.3Vまたは5Vであることを特徴とする請求項1に記載の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
- 前記低電圧端の電圧値が約0Vであることを特徴とする請求項1に記載の二進法データ「0」および「1」を表わす磁気トランジスタ回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/549,272 | 2006-10-13 | ||
US11/549,272 US7403043B2 (en) | 2005-10-17 | 2006-10-13 | Magnetic Transistor Circuit Representing the Data ‘1’ and ‘0’ of the Binary System |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008099287A JP2008099287A (ja) | 2008-04-24 |
JP4991474B2 true JP4991474B2 (ja) | 2012-08-01 |
Family
ID=38461559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007266043A Expired - Fee Related JP4991474B2 (ja) | 2006-10-13 | 2007-10-12 | 二進法データ「0」および「1」を表わす磁気トランジスタ回路 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7403043B2 (ja) |
JP (1) | JP4991474B2 (ja) |
CN (1) | CN100544015C (ja) |
DE (1) | DE102007032378A1 (ja) |
FR (1) | FR2939565A1 (ja) |
GB (1) | GB2442820B (ja) |
TW (1) | TWI358842B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7269061B2 (en) * | 2005-10-17 | 2007-09-11 | Northern Lights Semiconductor Corp. | Magnetic memory |
US7397277B2 (en) * | 2005-10-17 | 2008-07-08 | Northern Lights Semiconductor Corp. | Magnetic transistor circuit with the EXOR function |
US7539046B2 (en) * | 2007-01-31 | 2009-05-26 | Northern Lights Semiconductor Corp. | Integrated circuit with magnetic memory |
CN105981116B (zh) | 2013-10-01 | 2019-09-06 | 埃1023公司 | 磁增强的能量存储系统及方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1054358A (ja) * | 1964-08-18 | |||
US6741494B2 (en) * | 1995-04-21 | 2004-05-25 | Mark B. Johnson | Magnetoelectronic memory element with inductively coupled write wires |
US5629549A (en) * | 1995-04-21 | 1997-05-13 | Johnson; Mark B. | Magnetic spin transistor device, logic gate & method of operation |
JP2003297071A (ja) * | 2002-01-30 | 2003-10-17 | Sanyo Electric Co Ltd | 記憶装置 |
US6593608B1 (en) * | 2002-03-15 | 2003-07-15 | Hewlett-Packard Development Company, L.P. | Magneto resistive storage device having double tunnel junction |
DE10255857B3 (de) * | 2002-11-29 | 2004-07-15 | Forschungsverbund Berlin E.V. | Magnetische Logikeinrichtung |
DE60307834T2 (de) * | 2003-08-29 | 2007-09-13 | Infineon Technologies Ag | Schaltungssystem und Methode zum Verbinden eines Moduls zu, oder dessen Entkopplung von, einem Hauptbus |
JP4631090B2 (ja) * | 2004-02-19 | 2011-02-16 | 株式会社 東北テクノアーチ | 磁気抵抗効果素子を用いたロジックインメモリ回路 |
-
2006
- 2006-10-13 US US11/549,272 patent/US7403043B2/en not_active Expired - Fee Related
-
2007
- 2007-07-11 DE DE102007032378A patent/DE102007032378A1/de not_active Withdrawn
- 2007-07-13 GB GB0713663A patent/GB2442820B/en not_active Expired - Fee Related
- 2007-09-20 TW TW096135195A patent/TWI358842B/zh not_active IP Right Cessation
- 2007-10-10 CN CNB200710162029XA patent/CN100544015C/zh not_active Expired - Fee Related
- 2007-10-11 FR FR0707123A patent/FR2939565A1/fr not_active Withdrawn
- 2007-10-12 JP JP2007266043A patent/JP4991474B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008099287A (ja) | 2008-04-24 |
GB0713663D0 (en) | 2007-08-22 |
CN101162728A (zh) | 2008-04-16 |
US7403043B2 (en) | 2008-07-22 |
TW200818560A (en) | 2008-04-16 |
DE102007032378A1 (de) | 2008-04-17 |
GB2442820A (en) | 2008-04-16 |
CN100544015C (zh) | 2009-09-23 |
FR2939565A1 (fr) | 2010-06-11 |
US20070097588A1 (en) | 2007-05-03 |
GB2442820B (en) | 2008-09-24 |
TWI358842B (en) | 2012-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7439770B2 (en) | Magnetic tunneling junction based logic circuits and methods of operating the same | |
US7397285B2 (en) | Magnetic transistor with the AND/NAND/NOR/OR functions | |
CN107004759B (zh) | 磁电器件和互连件 | |
US8934289B2 (en) | Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction | |
JP4991474B2 (ja) | 二進法データ「0」および「1」を表わす磁気トランジスタ回路 | |
JP4526557B2 (ja) | 排他的論理和機能を有する磁気トランジスタ回路 | |
JP5365813B2 (ja) | 不揮発ロジック回路 | |
US8339843B2 (en) | Generating a temperature-compensated write current for a magnetic memory cell | |
US7269061B2 (en) | Magnetic memory | |
KR102125166B1 (ko) | 자기터널접합구조체 기반 논리 게이트 | |
US10008350B2 (en) | Magnetic device | |
US10084126B1 (en) | Magnetic memory device | |
US7405599B2 (en) | Magnetic transistor with the OR/NOR/NAND/AND functions | |
JP2009059884A (ja) | 電子回路 | |
JP6555256B2 (ja) | 磁性体素子とその初期化方法および半導体集積回路 | |
KR102649376B1 (ko) | 스핀 전하 변환 기반의 스핀 로직 소자 | |
WO2021075343A1 (ja) | 磁気デバイス及び演算装置 | |
US20210126639A1 (en) | Logic device using spin torque | |
JP2020150123A (ja) | 磁気記憶装置 | |
KR20050068479A (ko) | 저전력용 자기 메모리소자 | |
JP2006172537A (ja) | 磁気メモリデバイス用書込回路および磁気メモリデバイス |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100413 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100622 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110215 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110516 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110519 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110614 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110617 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20111011 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120202 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120209 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120424 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120507 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150511 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |