JP4986373B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an active matrix liquid crystal module manufactured using TFTs, a display module typified by an EL module, and an electronic device in which such a display module is mounted as a component.

  2. Description of the Related Art In recent years, a semiconductor device having a large area integrated circuit formed using a TFT formed by using a semiconductor thin film (thickness of about several to several hundreds of nanometers) formed on a substrate having an insulating surface has progressed. Yes. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as representative examples. Furthermore, a system on panel has been proposed in which a CPU, DRAM, an image processing circuit, an audio processing circuit, and the like are provided on the same substrate in addition to the pixel portion and the drive circuit portion. In particular, a TFT having a crystalline semiconductor film as an active layer has high field effect mobility, and thus a circuit having various functions can be formed.

  For example, a liquid crystal module mounted on a liquid crystal display device controls a pixel circuit that displays an image for each functional block, a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, and a sampling circuit. A functional circuit including a CPU, a DRAM, an image processing circuit, an audio processing circuit, and the like, which are circuits other than the driving circuit, the pixel circuit, and the driving circuit, are formed on a single substrate.

  A TFT in the pixel region (hereinafter referred to as a pixel TFT) is an n-channel TFT, and is driven by applying a voltage to the liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, in order to keep power consumption low, it is important that the characteristics required for the pixel TFT have a sufficiently low off-current value (drain current that flows when the TFT is off).

  As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region, and this region is called an LDD region. The LDD structure has the effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection.

  Next, TFTs used in drive circuits (buffer circuits, level shifter circuits, sampling circuits, etc.) for driving pixel TFTs are based on CMOS circuits. The TFT used in the driver circuit is preferably structured so that on current is more important than off current. This structure has an LDD region under the gate electrode. In the LDD structure, there is an adverse effect that the on-current is suppressed at the same time as suppressing the off-current. However, this structure relaxes the electric field in the vicinity of the drain and suppresses the deterioration of the on-current due to hot carriers. Is possible.

  In the driver circuit, a buffer circuit, a level shifter circuit, a sampling circuit, and the like are circuits that apply a voltage to the gate wiring in the pixel region, and the applied voltage is high as in the pixel region. For this reason, a thick gate insulating film is required.

  Further, TFTs of functional circuits other than the pixel circuit and the drive circuit and including the CPU, DRAM, image processing circuit, audio processing circuit, and the like require a high-speed operation, and thus a short channel is preferable. However, in the case of a short-channel TFT, there is a problem that the threshold value decreases and off-current easily flows. For this reason, a TFT having a short channel length and a thin gate insulating film is preferable for a TFT of a CPU, DRAM, image processing circuit, audio processing circuit, or the like.

As described above, when TFTs having different structures are formed on the same substrate, the process becomes complicated. Specifically, if a short-channel TFT is to be manufactured, it is only necessary to change the mask design. However, when the thickness of the gate insulating film differs for each region of the substrate, it differs from the conventional process. A process must be introduced. Specifically, after etching only the gate insulating film of the TFT of the driving circuit, it is heated at a high temperature to form a thermal oxide film, the gate insulating film of the driving circuit TFT is thinned, and the gate insulating film of the pixel TFT is formed. The method of increasing the thickness is taken. (For example, refer to Patent Document 1).
JP 2000-284722 (pages 6 to 11, FIG. 3)

  In this way, pixel TFTs that place importance on high withstand voltage characteristics while suppressing off-current, and TFTs for drive circuits such as buffer circuits, shift register circuits, level shifter circuits, and sampling circuits that place importance on high withstand voltage characteristics while increasing on-current current No TFT structure has been established that can simultaneously satisfy the short channel structure and TFTs such as functional circuits including CPU, DRAM, image processing circuit, audio processing circuit, etc., which place importance on lowering the threshold value associated therewith. Is the current situation.

  In addition, if an attempt is made to form a TFT having an LDD structure or a TFT having a structure in which an LDD region is disposed to overlap a gate electrode via a gate insulating film, the manufacturing process becomes complicated and the number of processes increases. There is a problem. It is clear that an increase in the number of processes not only increases the manufacturing cost but also decreases the manufacturing yield.

  The present invention is a technique for solving such problems, and includes a semiconductor device having a circuit composed of TFTs, an electro-optical device typified by an active matrix liquid crystal display device manufactured using TFTs, and In a light-emitting device typified by an EL display device, a method is proposed in which TFTs having different structures are formed on the same substrate using a process similar to the conventional one. That is, a TFT having a multilayered gate insulating film and having an electrode (hereinafter referred to as an auxiliary electrode) different from the gate electrode on the semiconductor film is proposed.

  In accordance with the present invention, TFTs with different gate insulating film thicknesses are manufactured on the same substrate to improve the operating characteristics and reliability of the semiconductor device, reduce power consumption, and apply a conventional process. An object of the present invention is to provide a TFT structure that realizes reduction in manufacturing cost and improvement in yield.

  In addition, with increasing definition (increasing the number of pixels) and downsizing, each display pixel pitch is being miniaturized. When a miniaturized TFT is manufactured, alignment of the mask is important, and there is a problem that the yield is reduced due to the displacement of the mask position. The present invention provides a TFT structure that can improve the yield in an electro-optical device typified by an active matrix liquid crystal display device manufactured using TFTs and a light-emitting device typified by an EL display device.

  Configuration 1 of the invention disclosed in this specification includes a semiconductor layer having a channel formation region, a first insulating film formed on the semiconductor layer, and the channel formation region via the first insulating film. An auxiliary electrode formed on the outside, a second insulating film formed on the first insulating film and the auxiliary electrode, and a channel forming region via the first insulating film and the second insulating film And a formed gate electrode.

  A structure 2 of the invention disclosed in this specification includes a first insulating film formed on a semiconductor layer, a source region, a drain region, and a channel forming region of the semiconductor layer provided on the first insulating film. An auxiliary electrode for controlling the carrier concentration between the first insulating film and the second insulating film formed on the auxiliary electrode, the first insulating film and the second insulating film And a gate electrode formed over a channel formation region of the semiconductor layer.

  In configurations 1 and 2 of the present invention, the thickness of the first insulating film is 1 to 100 nm, preferably 5 to 50 nm, and the second insulating film is 5 to 100 nm.

  When the auxiliary electrode is one for the TFT, the auxiliary electrode is formed between the channel formation region and the drain region of the semiconductor layer. On the other hand, when there are a plurality of auxiliary electrodes for one TFT, the auxiliary electrode is provided between the source region and drain region of the semiconductor layer and the channel formation region.

  The auxiliary electrode and the first gate electrode are connected to different wirings.

  The auxiliary electrode may be partially covered by the gate electrode.

  Further, an impurity may be added to the region of the semiconductor layer that faces the auxiliary electrode through the first insulating film. That is, the semiconductor layer may have a low concentration impurity region between the source region or the drain region and the channel formation region. In this case, the low concentration impurity region is formed under the auxiliary electrode. Yes.

Configuration 3 of the invention disclosed in this specification includes a semiconductor layer having a first region, a second region, a source region, and a drain region, a first insulating film formed on the semiconductor layer, A first auxiliary electrode formed on the semiconductor layer via a first insulating film; a second insulating film formed on the first insulating film and the first auxiliary electrode; And a first gate electrode formed on the first region via the second insulating film, and the first region is formed between the source region and the drain region. ,
The second region is formed between at least one of a source region or a drain region and the first region, and the first auxiliary electrode is interposed between the second region and the first insulating film. A semiconductor device is formed over the semiconductor device.

  In Structure 3 of the present invention, the thickness of the first insulating film is 1 to 100 nm, preferably 5 to 50 nm, and the second insulating film is 5 to 100 nm.

  The first auxiliary electrode may be partially covered with the gate electrode.

  In addition, a second auxiliary electrode may be provided on the second insulating film. The second auxiliary electrode has a curved surface or an inclined surface.

  An impurity may be added to the second region.

  The first auxiliary electrode and the first gate electrode are connected to different wirings.

  A structure 4 of the invention disclosed in this specification is a semiconductor device including a first thin film transistor and a second thin film transistor over the same substrate, and the first thin film transistor includes a first semiconductor layer, a first semiconductor layer, and a first semiconductor layer. The second thin film transistor includes a second semiconductor layer, a stacked second gate insulating film, a second gate electrode, and the stacked gate insulating film. A first auxiliary electrode sandwiched between the second gate insulating films and formed outside the channel formation region of the second semiconductor layer, and the first gate insulating film includes the second gate insulating film It is characterized by being thinner than the gate insulating film.

  A structure 5 of the invention disclosed in this specification is a semiconductor device including a first thin film transistor and a second thin film transistor over the same substrate, and the first thin film transistor includes a first semiconductor layer, a first semiconductor layer, and a first semiconductor layer. The second thin film transistor includes a second semiconductor layer, a stacked second gate insulating film, a second gate electrode, and the stacked gate insulating film. A first auxiliary electrode that is sandwiched between the second gate insulating films and controls the carrier concentration between the source region, the drain region, and the channel formation region of the second semiconductor layer, The gate insulating film is thinner than the second gate insulating film.

  In Structure 4 or 5 of the invention disclosed in this specification, the first gate insulating film has a thickness of 1 to 100 nm, preferably 5 to 50 nm, and the second gate insulating film has a thickness of 6 to 200 nm.

  In addition, one of the plurality of insulating films constituting the stacked second gate insulating film is the first gate insulating film.

  The first auxiliary electrode, the first gate electrode, and the second gate electrode are connected to different wirings.

  Note that when there is one first auxiliary electrode, the first auxiliary electrode is formed between the channel formation region and the drain region of the semiconductor layer. On the other hand, when there are a plurality of first auxiliary electrodes, the first auxiliary electrodes are provided between the source region and drain region of the semiconductor layer and the channel formation region.

  The first thin film transistor may include an insulating film that covers the first gate electrode and the first gate insulating film, and may include a second auxiliary electrode formed over the insulating film.

  At this time, the second auxiliary electrode has a curved surface or an inclined surface.

  An impurity may be added to a region of the second semiconductor layer facing the first auxiliary electrode through the first insulating film. In other words, the second semiconductor layer may have a low concentration impurity region between the source region or the drain region and the channel formation region. In this case, the auxiliary electrode is formed on the low concentration impurity region. ing.

The structure 6 of the invention disclosed in this specification includes a first semiconductor layer formed of a first region, a first source region, and a first drain region, a second region, and at least one third region. A second semiconductor layer formed of the first region, the second source region, and the second drain region, and the first insulating layer formed on the first semiconductor layer and the second semiconductor layer, ,
A first auxiliary electrode formed on the second semiconductor layer via the first insulating film; and a first gate formed on the first semiconductor layer via the first insulating film. An electrode, a second insulating film formed on the first insulating film, the first auxiliary electrode, and the first gate electrode; and the second insulating film, and the second insulating film. A gate electrode formed on the region, wherein the second region is formed between the second source region and the second drain region, and the third region is the second region It is formed between at least one of a source region and a drain region and the second region, and the first auxiliary electrode is formed on the third region via the first insulating film. A semiconductor device characterized by the above.

  In Structure 6 of the present invention, the thickness of the first insulating film is 1 to 100 nm, preferably 5 to 50 nm, and the second insulating film is 5 to 100 nm.

  The first auxiliary electrode may be partially covered with the gate electrode.

  In addition, a second auxiliary electrode may be provided on the second insulating film. The second auxiliary electrode has a curved surface or an inclined surface.

  An impurity may be added to the third region.

  The first auxiliary electrode, the second auxiliary electrode, the first gate electrode, and the second gate electrode are connected to different wirings.

  A structure 7 of the invention disclosed in this specification includes a first thin film transistor including a first semiconductor layer, a first gate electrode, a first insulating film, and a second insulating film, a second semiconductor layer, A method of manufacturing a semiconductor device having a second thin film transistor having a second gate electrode, a first auxiliary electrode, the first insulating film, and the second insulating film, wherein the first thin film is formed on the insulating surface. And the second semiconductor layer, a first insulating film is formed on the first semiconductor layer and the second semiconductor layer, and a first gate is formed on the first insulating film. An electrode and a first auxiliary electrode are formed, a second insulating film is formed on the first gate electrode, the first auxiliary electrode, and the first insulating film, and the second insulating film is formed. A second gate electrode is formed thereon.

  The structure 7 of the invention disclosed in this specification is characterized in that etching is performed so that the first auxiliary electrode and each gate electrode are connected to different wirings.

  Further, a second auxiliary electrode may be formed on the first thin film transistor simultaneously with the formation of the second gate electrode. In this case, the second auxiliary electrode is connected to a different wiring from the first auxiliary electrode and each gate electrode.

  Note that when the second gate electrode is formed, the second gate electrode is formed over the second semiconductor layer and the first auxiliary electrode.

  According to the first or second aspect of the invention, the carrier concentration of the source region, the drain region, and the channel formation region can be controlled without forming the low concentration impurity region (LDD region). It is possible to avoid a shift in the position of the mask accompanying the formation process, and a reduction in yield can be suppressed.

  According to the third to seventh aspects of the invention, a plurality of TFTs having different gate insulating film thicknesses can be manufactured over the same substrate without using a special process. In addition, the carrier concentration in the semiconductor layer under each auxiliary electrode can be changed by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode without forming the LDD region. it can.

  In addition, a TFT having a thick gate insulating film is applied to a TFT and a pixel TFT of a drive circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit, so that a high withstand voltage function and low power consumption are achieved. Therefore, a highly reliable TFT can be manufactured. Furthermore, by applying a TFT having a short channel length and a thin gate insulating film to a TFT of a functional circuit including a CPU, DRAM, an image processing circuit, an audio processing circuit, and the like, the operating characteristics and reliability can be improved.

  According to the present invention, TFTs having different gate insulating film thicknesses can be manufactured over the same substrate without using a special process. Further, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode without forming the LDD region, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode is changed. be able to. Thereby, the hot carrier effect generated at the junction surface between the channel formation region and the source region or the drain region can be suppressed. Therefore, a TFT having a thin gate insulating film is applied to a functional circuit TFT (typically, a CPU, a DRAM, an image processing circuit, an audio processing circuit, etc.), and a pixel TFT or a driving circuit (typically By applying TFTs with thick gate insulating films to buffer circuits, shift register circuits, level shifter circuits, sampling circuits, etc., the operating characteristics and reliability of semiconductor devices are improved and power consumption is reduced. It can be done. Further, a pixel portion, a driver circuit, and a functional circuit can be provided over the same substrate, and a module used in a conventional display device such as a liquid crystal module or an EL module can be reduced in size, and the display device is provided. The electronic device can be shaped to be portable.

(First embodiment)
An example of the present invention is shown in FIG. In the present embodiment, a thin gate insulating film and a P-TFT having a first auxiliary electrode, an N-TFT (a TFT whose gate insulating film is G1 in FIG. 1), and a thick gate insulating film. , A step of simultaneously forming a first auxiliary electrode, a P-TFT having a second auxiliary electrode, and an N-TFT (in FIG. 1, TFTs whose gate insulating films are G1 and G2).

  As shown in FIG. 1A, after a crystalline semiconductor film is formed over a substrate 101 with an insulating film 102 serving as a base film, the crystalline semiconductor film is etched into an arbitrary shape and separated. Crystalline semiconductor films 103 to 106 are formed. Thereafter, a first gate insulating film (hereinafter referred to as G1 in this embodiment and FIG. 1) 107 is formed. The first gate insulating film (G1) 107 typically functions as a gate insulating film of a TFT that is required to operate at high speed, such as a drive circuit. The first gate insulating film (G1) 107 is thin and has a small thickness. The film thickness is preferably 1 to 100 nm, more preferably 5 to 50 nm. When the film thickness is thinner than this range, there is a problem that parasitic capacitance is formed and high-speed operation cannot be performed.

  Next, after forming the first conductive film, a mask (not shown) is formed using a photolithography technique, and then unnecessary portions of the first conductive film are removed by a known etching method. First gate electrodes 108 and 109 and first auxiliary electrodes 110a, 110b, 111a, and 111b having desired shapes are formed. A TFT having a thin gate insulating film serves as a gate electrode (hereinafter referred to as a first gate electrode in the present embodiment), and an auxiliary electrode (hereinafter referred to as present embodiment) in a TFT having a thick gate insulating film. In the embodiment, it is referred to as a first auxiliary electrode). The first auxiliary electrodes in one TFT are preferably arranged at an arbitrary interval. Typically, they are arranged with a substantially channel length interval (4 to 12 μm, preferably 6 to 10 μm).

  Next, as shown in FIG. 1B, a second gate insulating film 120 (hereinafter referred to as G2 in this embodiment and FIG. 1) is formed. The first gate insulating film (G1) and the second gate insulating film (G2) are gate insulating films of TFTs having a thick gate insulating film (TFTs having gate insulating films G1 and G2 in FIG. 1). The film typically functions as a gate insulating film of a TFT that requires a withstand voltage such as a pixel TFT or a buffer circuit. Therefore, the thickness (G2) of the second gate insulating film is preferably 5 to 100 nm, which is thicker than the first gate insulating film.

  Next, after the second conductive film 121 is formed, a mask (122, 123) is formed using a photolithography technique, and then unnecessary portions of the second conductive film are removed by a known etching method. Then, a second gate electrode and a second auxiliary electrode having a desired shape are formed. A TFT having a thin gate insulating film (in FIG. 1, a TFT having a gate insulating film G1 in FIG. 1) serves as an auxiliary electrode, and a TFT having a thick gate insulating film (in FIG. 1, the gate insulating film is G1 and In the TFT G2), it is formed as a gate electrode and an auxiliary electrode.

  When etching the second conductive film, first, resist masks 122 and 123 are formed in a portion where the second gate electrode is to be formed. After that, as shown in FIG. 1C, the second conductive film is etched to form second auxiliary electrodes 131a to 134a and 131b to 134b. At this time, by appropriately adapting the conditions, the second auxiliary electrode having a curved surface, that is, the first gate insulating film 107 and the second gate electrode formed on the semiconductor layers 103 to 106 having an arbitrary shape are provided. Second auxiliary electrodes 131a to 134a and 131b to 134b that are inclined toward the gate insulating film 120 are formed.

  In FIG. 1, for convenience, the thickness of the crystalline semiconductor film and the thickness of the first gate electrode are shown almost the same, but the thickness of the crystalline semiconductor film is actually 25 to 70 nm. The film thickness of the gate electrode is 120 to 500 nm. Therefore, an auxiliary electrode is formed on the side surface of the gate electrode having a large step, but no auxiliary electrode is formed on the side surface of the crystalline semiconductor film. Thereafter, by removing the resist mask, second gate electrodes 135 and 136 are formed.

Next, as shown in FIG. 1D, the first gate electrodes 108 and 109, the second auxiliary electrodes 131a to 134a, 131b to 134b, the second gate electrodes 135 and 136, and the first auxiliary electrode 110a. 110b, 111a, and 111b as masks, a source region and a drain region are formed by adding impurities. The source or drain regions 141 and 143 of the P-channel TFT and the source or drain regions 140 and 142 of the N-channel TFT are n-type or p-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ cm ^3. An impurity element imparting is added.

  Note that an LDD region may be provided by adding an impurity to the crystalline semiconductor film below the first auxiliary electrodes 110a, 110b, 111a, and 111b.

  In the n-channel TFT 152 and the p-channel TFT 153, two first auxiliary electrodes are formed, but one may be used. In this case, the auxiliary electrode is provided between the drain region and the gate electrode.

  Through the above steps, an n-channel TFT 150 and a p-channel TFT 151 with a thin gate insulating film, an n-channel TFT 152 and a p-channel TFT 153 with a thick gate insulating film are formed at the same time.

  In the present embodiment, since the first gate electrode, the first auxiliary electrode, the second gate electrode, and the second auxiliary electrode are each independently patterned, an arbitrary voltage is applied to each electrode. be able to. Therefore, in consideration of the required function of each TFT, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode, the crystalline semiconductor film below each auxiliary electrode The carrier concentration inside can be controlled. That is, it has the same function as the LDD region and can suppress the hot carrier effect. Typically, in a TFT with a low on-state current, the resistance in the crystalline semiconductor film may be reduced by increasing the carrier concentration by controlling the voltage applied to the auxiliary electrode. In a TFT having a high off-state current, the resistance in the crystalline semiconductor film may be increased by controlling the voltage applied to the auxiliary electrode to suppress the carrier concentration. Note that the second gate electrode and the second auxiliary electrode may be connected without being separated.

  In addition, the potentials of the first auxiliary electrode and the second auxiliary electrode do not need to be fixed, and can be changed over time in consideration of the function required for each TFT. That is, in one TFT, the on-current can be increased or the off-current can be decreased by adjusting the voltage applied to the auxiliary electrode. In this case, the voltage applied to the auxiliary electrode may be appropriately adjusted in accordance with the required off current or on current.

  Through the above steps, TFTs with different gate insulating film thicknesses can be manufactured over the same substrate without using any special steps. Further, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode without forming the LDD region, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode is changed. be able to. Thereby, the hot carrier effect generated at the junction surface between the channel formation region and the source region or the drain region can be suppressed. Therefore, a TFT having a thick gate insulating film is applied to a TFT and a pixel TFT of a driving circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit, so that a high withstand voltage function and low power consumption are achieved. Therefore, a highly reliable TFT can be manufactured. Furthermore, by applying a TFT having a short channel length and a thin gate insulating film to a TFT of a functional circuit including a CPU, DRAM, an image processing circuit, an audio processing circuit, and the like, the operating characteristics and reliability can be improved.

(Second Embodiment)
An example of the present invention is shown in FIG. This embodiment shows a step of forming a TFT having an LDD region on the active matrix substrate described in the first embodiment.

  As shown in FIG. 2A, after a crystalline semiconductor film was formed over a substrate 201 with an insulating film 202 as a base film, the crystalline semiconductor film was etched into an arbitrary shape and separated. Crystalline semiconductor films 203 to 206 are formed. Thereafter, a first gate insulating film (hereinafter referred to as G1 in this embodiment and FIG. 2) 207 is formed. The first gate insulating film (G1) 207 is thin, and the thickness of the first gate insulating film is 1 to 100 nm, preferably 5 to 50 nm.

  Next, after forming the first conductive film, a mask (not shown) is formed using a photolithography technique, and then unnecessary portions of the first conductive film are removed by a known etching method. First gate electrodes 208 and 209 and first auxiliary electrodes 210a, 210b, 211a, and 211b having a desired shape are formed. A TFT having a thin gate insulating film serves as a gate electrode (hereinafter referred to as a first gate electrode in the present embodiment), and an auxiliary electrode (hereinafter referred to as present embodiment) in a TFT having a thick gate insulating film. In the embodiment, it is referred to as a first auxiliary electrode). The first auxiliary electrodes in one TFT are preferably arranged at an arbitrary interval. Typically, they are arranged with an interval of approximately a channel length (4 to 12 μm, preferably 6 to 10 μm).

Next, an impurity is added into the crystalline semiconductor film other than the channel formation region. Although not shown in FIG. 2A, in a TFT having a thick gate insulating film (in FIG. 2, TFTs having gate insulating films G1 and G2), between the first auxiliary electrodes ( That is, the impurity is added after covering with a resist mask so that the impurity is not added to the crystalline semiconductor film between the regions 210a and 210b and between the regions 211a and 211b in FIG. An LDD region is formed by adding impurities. An impurity element imparting n-type or p-type in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ in the LDD regions 210 and 218 of the P-channel TFT and the LDD regions 215 and 217 of the N-channel TFT Is added.

  Next, as shown in FIG. 2B, a second gate insulating film 220 (hereinafter referred to as G2 in this embodiment and FIG. 2) is formed. The first gate insulating film (G1) and the second gate insulating film (G2) are gate insulating films of TFTs having a thick gate insulating film (TFTs having gate insulating films G1 and G2 in FIG. 2). It is a membrane. The film thickness (G2) of the second gate insulating film is thicker than that of the first gate insulating film and is preferably 5 to 100 nm.

  Next, as shown in FIG. 2C, after the second conductive film 221 is formed, masks 222 and 223 are formed using a photolithography technique, and then the second conductive film is formed by a known etching method. The unnecessary portions are removed to form second gate electrodes and second auxiliary electrodes having desired shapes. In a TFT having a thin gate insulating film (a TFT having a gate insulating film G1 in FIG. 2), a second auxiliary electrode is formed. On the other hand, in a TFT having a thick gate insulating film (in FIG. 2, TFTs whose gate insulating films are G1 and G2), a second auxiliary electrode and a second gate electrode are formed.

  When etching the second conductive film, first, resist masks 222 and 223 are formed in a portion where the second gate electrode is to be formed. After that, the second conductive film is etched to form second auxiliary electrodes 231a to 234a and 231b to 234b. At this time, by appropriately adapting the conditions, the second auxiliary electrode having a curved surface, that is, the first gate insulating film 207 and the second gate electrode formed on the semiconductor layers 203 to 206 having an arbitrary shape are provided. Second auxiliary electrodes 231a to 234a and 231b to 234b that are inclined toward the gate insulating film 220 are formed.

  Thereafter, by removing the resist mask, second gate electrodes 235 and 236 are formed.

Next, as shown in FIG. 2D, the first gate electrodes 208 and 209, the second auxiliary electrodes 231a to 234a, 231b to 234b, the second gate electrodes 235 and 236, and the first auxiliary electrode 210a. , 210b, 211a, 211b are used as masks to add a source region and a drain region by adding impurities. The source or drain regions 241 and 243 of the p-channel TFT and the source or drain regions 240 and 242 of the n-channel TFT are n-type or n-type in the concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. An impurity element imparting p-type is added. Note that an LDD region may be provided by adding impurities to the crystalline semiconductor film below the first auxiliary electrodes 210a, 210b, 211a, and 211b.

  Through the above steps, an n-channel TFT 250, a p-channel TFT 251 with a thin gate insulating film, and an n-channel TFT 252 and a p-channel TFT 253 with a thick gate insulating film are simultaneously formed on the same substrate. be able to.

  In the present embodiment, since the first gate electrode, the first auxiliary electrode, the second gate electrode, and the second auxiliary electrode are each independently patterned, an arbitrary voltage is applied to each electrode. be able to. Therefore, in consideration of the function required for each TFT, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode, the crystalline semiconductor film under each auxiliary electrode The carrier concentration inside can be controlled. In other words, it has the same function as LDD and can suppress the hot carrier effect. Typically, in a TFT with a low on-state current, the resistance in the crystalline semiconductor film may be reduced by increasing the carrier concentration by controlling the voltage applied to the auxiliary electrode. In a TFT having a high off-state current, the resistance in the crystalline semiconductor film may be increased by controlling the voltage applied to the auxiliary electrode to suppress the carrier concentration.

  In addition, the potentials of the first auxiliary electrode and the second auxiliary electrode do not need to be fixed, and can be changed over time in consideration of functions required of the respective TFTs. That is, in one TFT, the on-current can be increased or the off-current can be decreased by adjusting the voltage applied to the auxiliary electrode. In this case, the voltage applied to the auxiliary electrode may be appropriately adjusted in accordance with the required off current or on current. Note that the second gate electrode and the second auxiliary electrode may be connected without being separated.

  Through the above steps, a TFT having a different gate insulating film thickness and an LDD region can be manufactured over the same substrate by applying a conventional process without using a special process. A first auxiliary electrode and a second auxiliary electrode are formed in the vicinity of the LDD region and the channel formation region. Therefore, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode can be finely adjusted. Thereby, the hot carrier effect can be further suppressed. Therefore, by applying a TFT having a thin gate insulating film to a TFT of a functional circuit and applying a TFT having a thick gate insulating film to a TFT in a pixel region and a TFT in a driver circuit, the operating characteristics of the semiconductor device In addition, the reliability can be improved and the power consumption can be reduced.

(Third embodiment)
An example of the present invention is shown in FIG. In the present embodiment, the second auxiliary electrode is formed only on the TFT having the thin gate insulating film (the TFT having the gate insulating film G1 in FIG. 3) in the active matrix substrate described in the first embodiment. .

  As shown in FIG. 3A, after a crystalline semiconductor film is formed over a substrate 301 with an insulating film 302 as a base film, the crystalline semiconductor film is etched into an arbitrary shape and separated. Crystalline semiconductor films 303 to 306 are formed. Thereafter, a first gate insulating film (hereinafter referred to as G1 in this embodiment and FIG. 3) 307 is formed. The first gate insulating film (G1) 307 is thin, and the thickness of the first gate insulating film is 1 to 100 nm, preferably 5 to 50 nm.

  Next, after forming the first conductive film, a mask (not shown) is formed using a photolithography technique, and then unnecessary portions of the first conductive film are removed by a known etching method. First gate electrodes 308 and 309 and first auxiliary electrodes 310a, 310b, 311a, and 311b having a desired shape are formed. A TFT having a thin gate insulating film serves as a gate electrode (hereinafter referred to as a first gate electrode in the present embodiment), and an auxiliary electrode (hereinafter referred to as present embodiment) in a TFT having a thick gate insulating film. In the embodiment, it is referred to as a first auxiliary electrode). The first auxiliary electrodes in one TFT are preferably arranged at an arbitrary interval. Typically, they are arranged with an interval of approximately a channel length (4 to 12 μm, preferably 6 to 10 μm).

  Next, as shown in FIG. 3B, a second gate insulating film 320 (hereinafter referred to as G2 in this embodiment and FIG. 3) is formed. The first gate insulating film (G1) and the second gate insulating film (G2) are gate insulating films of TFTs having a thick gate insulating film (TFTs having gate insulating films G1 and G2 in FIG. 3). It is a film, and the thickness (G2) of the second gate insulating film is preferably 5 to 100 nm thicker than the first gate insulating film. Next, after the second conductive film 321 is formed, the resist mask 322 covers part of the second conductive film 321.

  Next, unnecessary portions of the second conductive film are removed by a known etching method to form second auxiliary electrodes 331a, 331b, 332a, and 332b having desired shapes. At this time, by appropriately adapting the conditions, the second auxiliary electrode having a curved surface, that is, the first gate insulating film 302 formed on the semiconductor layers 303 to 306 having an arbitrary shape is directed. The inclined second auxiliary electrodes 331a, 331b, 332a, and 332b are formed. Next, resist masks 333, 335, and 336 are formed (FIG. 3C).

  Next, the second conductive film is etched into a desired shape to form a second gate electrode. After that, by removing the resist masks 333, 335, and 336, second gate electrodes 337 and 338 are formed.

  In this embodiment, the second auxiliary electrodes 331a, 331b, 332a, and 332b are formed first, and then the second gate electrodes 337 and 338 are formed. However, this process may be reversed. . That is, first, after forming the second gate electrode, the second auxiliary electrode may be formed.

Next, the first gate electrodes 308 and 309, the second auxiliary electrodes 331a, 331b, 332a and 332b, the second gate electrodes 337 and 338, and the first auxiliary electrodes 310a, 310b, 311a, and 311b are used as masks. By adding an impurity, a source region and a drain region are formed. The source or drain regions 341 and 343 of the p-channel TFT and the source or drain regions 340 and 342 of the n-channel TFT are n-type or p-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. An impurity element imparting a mold is added (FIG. 3D).

  Note that an LDD region may be provided by adding an impurity to the crystalline semiconductor film below the first auxiliary electrodes 310a, 310b, 311a, and 311b. With this structure, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode can be finely adjusted by applying an arbitrary voltage to the first auxiliary electrode.

  Through the above steps, an n-channel TFT 350, a p-channel TFT 351 with a thin gate insulating film, an n-channel TFT 352 with a thick gate insulating film, and a p-channel TFT 353 are formed at the same time.

  In the present embodiment, the first gate electrode, the second auxiliary electrode, the second gate electrode, and the first auxiliary electrode are each independently patterned, so that an arbitrary voltage is applied to each electrode. be able to. Therefore, in consideration of the required function of each TFT, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode, the crystalline semiconductor film below each auxiliary electrode The carrier concentration inside can be controlled. In other words, it has the same function as the LDD region and can suppress the hot carrier effect. Typically, in a TFT with a low on-state current, the voltage applied to the auxiliary electrode may be controlled to increase the carrier concentration and decrease the resistance in the crystalline semiconductor film. In a TFT with a high off-state current, the resistance in the crystalline semiconductor film may be increased by controlling the voltage applied to the auxiliary electrode to lower the carrier concentration.

  In addition, the potentials of the first auxiliary electrode and the second auxiliary electrode do not need to be fixed, and can be changed over time in consideration of functions required of the respective TFTs. That is, in one TFT, the on-current can be increased or the off-current can be decreased by adjusting the voltage applied to the auxiliary electrode. In this case, the voltage applied to the auxiliary electrode may be appropriately adjusted in accordance with the required off current or on current.

  Through the above steps, TFTs having different gate insulating film thicknesses can be manufactured over the same substrate by applying conventional steps without using special steps. Further, by applying an arbitrary voltage to the first auxiliary electrode and the second auxiliary electrode without forming the LDD region, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode is changed. be able to. Thereby, the hot carrier effect generated at the junction surface between the channel formation region and the source region or the drain region can be suppressed. For this reason, a TFT having a thick gate insulating film is applied to a TFT and a pixel TFT of a drive circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, etc. It is possible to reduce the power consumption and to manufacture a highly reliable TFT. Furthermore, by applying a TFT having a short channel length and a thin gate insulating film to a TFT of a functional circuit including a CPU, DRAM, an image processing circuit, an audio processing circuit, and the like, the operating characteristics and reliability can be improved.

(Fourth embodiment)
An example of the present invention is shown in FIG. In the present embodiment, the active matrix substrate described in the second embodiment is manufactured without forming the second auxiliary electrode.

  As shown in FIG. 4A, after a crystalline semiconductor film is formed over a substrate 401 with an insulating film 402 as a base film, the crystalline semiconductor film is etched into an arbitrary shape and separated. Crystalline semiconductor films 403 to 406 are formed. After that, a first gate insulating film (hereinafter referred to as G1 in this embodiment and FIG. 4) 407 is formed. The first gate insulating film (G1) 407 is thin, and the thickness of the first gate insulating film is 1 to 100 nm, preferably 5 to 50 nm.

  Next, after forming the first conductive film, a mask (not shown) is formed using a photolithography technique, and then unnecessary portions of the first conductive film are removed by a known etching method. First gate electrodes 408 and 409 and first auxiliary electrodes 410a, 410b, 411a, and 411b having a desired shape are formed. A TFT having a thin gate insulating film is formed as a gate electrode (hereinafter referred to as a first gate electrode in this embodiment). On the other hand, a TFT having a thick gate insulating film is formed as an auxiliary electrode (hereinafter referred to as a first auxiliary electrode in this embodiment). The first auxiliary electrodes in one TFT are preferably arranged at an arbitrary interval. Typically, they are arranged with an interval of approximately a channel length (4 to 12 μm, preferably 6 to 10 μm).

Next, an impurity is added into the crystalline semiconductor film other than the channel formation region. Although not shown in FIG. 4A, in a TFT having a thick gate insulating film (in FIG. 4, TFTs having the gate insulating films G1 and G2), between the first auxiliary electrodes ( An impurity is added after covering with a resist mask so that an impurity is not added to the crystalline semiconductor film in the regions 410a and 410b and between 411a and 411b in FIG. An LDD region is formed by adding impurities. In the LDD regions 416 and 418 of the P-channel TFT and the LDD regions 415 and 417 of the N-channel TFT, an impurity element imparting n-type or p-type in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ Is added.

  Next, as shown in FIG. 4B, a second gate insulating film 420 (hereinafter referred to as G2 in this embodiment and FIG. 4) is formed. The first gate insulating film (G1) and the second gate insulating film (G2) are gate insulating films of TFTs having a thick gate insulating film (TFTs having gate insulating films G1 and G2 in FIG. 4). It is a membrane. The film thickness (G2) of the second gate insulating film is thicker than that of the first gate insulating film and is preferably 5 to 100 nm. Next, after the second conductive film 421 is formed, masks (422 and 423) are formed using a photolithography technique.

  Next, as shown in FIG. 4C, unnecessary portions of the second conductive film are removed by a known etching method to form second gate electrodes 435 and 436 having desired shapes.

Next, after forming a resist mask 431 for forming a source region and a drain region on the n-channel TFT, the first gate electrodes 408 and 409, the second gate electrodes 435 and 436, and the first auxiliary electrode are formed. Source regions and drain regions are formed by adding impurities using 410a, 410b, 411a, 411b, and the resist mask 431 as a mask. The source or drain regions 441 and 443 of the p-channel TFT and the source or drain regions 440 and 442 of the n-channel TFT are n-type or p-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. An impurity element imparting a mold is added. On the other hand, an impurity element imparting n-type conductivity is added to the LDD region of the n-channel TFT 450 in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ .

  Note that an LDD region may be provided by adding an impurity to the crystalline semiconductor film below the first auxiliary electrodes 410a, 410b, 411a, and 411b. With this structure, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode can be finely adjusted by applying an arbitrary voltage to the first auxiliary electrode.

  Further, instead of the step of forming the LDD region using the resist mask 431, after forming the first gate electrodes 408 and 409, an insulating film such as a silicon oxide film is formed on the side surface, and this film is etched. Thus, an insulating film having a curved surface and a substantially triangular sectional shape may be formed. After that, an LDD region can be formed by adding an impurity.

  Through the above steps, an n-channel TFT 450 having a thin gate insulating film and an LDD region, a p-channel TFT 451 having a single drain, an n-channel TFT 452 having an auxiliary electrode and a thick gate insulating film, A type TFT 453 is formed at the same time.

  Through the above steps, TFTs can be manufactured on the same substrate with different gate insulating film thicknesses by applying conventional steps without using special steps. By applying an arbitrary voltage to the first auxiliary electrode, the carrier concentration in the crystalline semiconductor film under each auxiliary electrode can be changed. Thereby, the hot carrier effect can be further suppressed. Therefore, a TFT having a thick gate insulating film is applied to a TFT and a pixel TFT of a driving circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit, so that a high withstand voltage function and low power consumption are achieved. Therefore, a highly reliable TFT can be manufactured. Furthermore, by applying a TFT having a short channel length and a thin gate insulating film to a TFT of a functional circuit including a CPU, DRAM, an image processing circuit, an audio processing circuit, and the like, the operating characteristics and reliability can be improved.

  Here, a method for manufacturing a liquid crystal display device using an active matrix substrate having a functional circuit region and a pixel region will be described with reference to FIGS.

  An active matrix liquid crystal display device using TFT as a switching element has a structure in which a substrate (active matrix substrate) in which pixel electrodes are arranged in a matrix and an opposite substrate on which a counter electrode is formed are opposed to each other with a liquid crystal layer interposed therebetween. It has become. The distance between the two substrates is controlled to a predetermined interval via a spacer or the like, and a liquid crystal layer is sealed by using a sealing material on the outer periphery of the pixel portion.

  An example of manufacturing an active matrix substrate having a functional circuit region and a pixel region is described below. In this example, the TFT having the structure shown in the first embodiment is applied. In FIG. 5, since the n-channel TFTs 542 and 543 in the pixel region have the same structure, only the n-channel TFT 542 will be described.

  First, a base film 502 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 501 using a known technique. The base film may be a single layer or a stacked structure of two or more layers. In this embodiment, a two-layer base film is formed. First, a silicon nitride oxide film having a thickness of 10 to 100 nm is formed as a first base film in contact with the substrate surface by plasma CVD, and then is formed in a thickness of 50 to 150 nm by plasma CVD in contact with the surface of the first base film. A silicon oxynitride film is formed as a second base film. In this embodiment, barium borosilicate glass is used for the substrate. However, the present invention is not limited to this. Aluminoborosilicate glass, synthetic quartz glass, silicon, metal substrate or stainless steel substrate, which can withstand the processing temperature of this embodiment. A heat-resistant plastic substrate or the like can be used.

  Next, a semiconductor film with a thickness of 25 to 70 nm (preferably 30 to 50 nm) is formed on the second base film, a mask (not shown) is formed using a photolithography technique, and then a known etching method is used. Unnecessary portions are removed to form a semiconductor film having a desired shape. Note that a semiconductor film can be formed by a known method (an amorphous silicon film formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like by using a solid phase deposition method, a laser crystallization method, or a metal-based heat treatment method). For example, a crystalline silicon film may be formed by a crystallization method. There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this embodiment, after forming an amorphous silicon film of 50 nm and irradiating a laser to form a crystalline silicon film, a semiconductor layer is formed by an etching process.

Note that in the case where a crystalline silicon film is formed by a laser crystallization method, a pulsed oscillation type or a continuous emission type excimer laser, a YAG laser, or a YVO4 laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 1 to 10 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ]. / cm ² ]). Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlay rate of the linear laser beam at this time is 50. Perform as ~ 90 [%].

  Further, after forming the semiconductor film, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the thin film transistor. (Not shown).

  Next, a first gate insulating film 503 having a thickness of 1 to 100 nm, preferably 5 to 50 nm, is formed on the surface of the base film and the semiconductor layer using a known technique. In this embodiment, a silicon oxynitride film with a thickness of 50 nm is formed by a plasma CVD method. Note that the first gate insulation is not limited to the silicon oxynitride film, and other insulating films (such as a silicon oxide film, a silicon nitride oxide film, and a silicon nitride film) may be used.

  Next, a first conductive film is formed by a known film formation method. In this embodiment, a tantalum nitride film with a thickness of 30 nm is in contact with the first gate insulating film, and then a tungsten film with a thickness of 370 nm is stacked to form a first conductive film. The tantalum nitride film and the tungsten film are formed by sputtering.

  In this embodiment, the first conductive film is a stacked layer of a tantalum nitride film and a tungsten film. However, the first conductive film is not particularly limited, and any of them is tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo ), Aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or an alloy material or compound material containing these elements as main components. Alternatively, a silver-copper-palladium alloy (AgPdCu alloy) may be used.

  Next, after forming a mask (not shown) using a photolithography technique, unnecessary portions of the first conductive film are removed by a known etching method (RIE method, ECR method, etc.) Gate electrodes 504 and 505 and first auxiliary electrodes 506a and 506b are formed.

  Next, a second gate insulating film 507 having a thickness of 5 to 100 nm is formed over the first gate insulating film, the first gate electrode, and the first auxiliary electrode by using a known technique.

  In this embodiment, a silicon oxynitride film having a thickness of 60 nm is formed by a plasma CVD method. Note that the second gate insulating film is not limited to the silicon oxynitride film, and other insulating films (such as a silicon oxide film, a silicon nitride oxide film, and a silicon nitride film) may be used.

  Next, a second conductive film is formed. In this embodiment, the second conductive film has a stacked structure of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 370 nm, like the first conductive film.

  Next, unnecessary portions of the second conductive film are removed by a known etching method (RIE method, ECR method, etc.) to form a second gate electrode and a second auxiliary electrode. To do. First, after a portion to be a second gate electrode is covered with a resist mask, the second conductive film is etched to form second auxiliary electrodes 509a, 509b, 510a, 510b, 512a, and 512b at the same time.

A known technique (ion An impurity element is introduced into the semiconductor film by a doping method, an ion implantation method, or the like to form a source region and a drain region. In this embodiment, when doping an n-type impurity, the impurity dose is set to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is set to 80 keV. Note that an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used as an impurity element imparting n-type conductivity. In this embodiment, a compound containing phosphorus (P) is used as an impurity. At this time, the p-type TFT is covered with a resist mask so that n-type impurities are not introduced.

Next, when doping the p-type impurity, the impurity dose is set to 3 × 10 ¹⁵ / cm ² and the acceleration voltage is set to 30 keV. Note that as the impurity element imparting p-type conductivity, an element belonging to Group 13, typically boron (B), can be used. At this time, the n-type TFT is covered with a resist mask so that p-type impurities are not introduced.

  Through the above steps, n-type source and drain regions 515 and 517 and p-type source and drain regions 516 are formed.

  Next, heat treatment is performed to recover the crystallinity of the semiconductor film and to activate the impurity element introduced into each semiconductor film. As a heat treatment method, a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) can be applied. In this embodiment, a thermal annealing method is used, and the temperature is set to 550 ° C. in a nitrogen atmosphere and heated for 4 hours.

  Next, a first interlayer insulating film 520 and a second interlayer insulating film 521 are formed. The first interlayer insulating film 520 may be used as a single layer or a stacked structure. In this embodiment, a silicon nitride film having a thickness of 50 nm is formed as the first interlayer insulating film 520 by plasma CVD. Next, hydrogenation may be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor film with hydrogen contained in the first interlayer insulating film 520. As other means for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen is performed. May be. In this embodiment, heating is performed at 410 ° C. for 1 hour in a nitrogen atmosphere.

  Next, a film made of an inorganic material or an organic material can be formed as the second interlayer insulating film 521. Typical examples of the inorganic material include silicon oxide, silicon nitride oxide, silicon oxynitride, and the like. Typical examples of the organic material include acrylic, polyimide, polysilazane, and the like. When an interlayer insulating film is formed of an organic material having positive or negative photosensitivity as an organic material, since there is a contact hole having a curvature, there is an effect that the coverage (coverage) of an electrode to be formed later is increased. . In addition, a siloxane polymer is applied and baked, and a skeleton structure is formed by the bond of silicon (Si) and oxygen (O), and the substituent includes at least hydrogen, or the substituent includes fluorine, an alkyl group, or an aromatic group. You may form with the material which has at least 1 sort (s) among group hydrocarbons. In this case, an interlayer insulating film having heat resistance and flatness can be formed. In this embodiment, after forming a silicon oxide film having a thickness of 800 nm, planarization is performed by etching back.

  Then, contact holes reaching the source and drain regions 515 to 517 are formed, and wirings 522 to 525 that are electrically connected to the source region and the drain region are formed.

  Note that these wirings are formed by etching a laminated film of a titanium film with a thickness of 100 nm, an alloy film with a thickness of 350 nm (typically an alloy film of aluminum and silicon), and a titanium film with a thickness of 100 nm. To do. The wiring material is not limited to Ti, an alloy of Al and Si, and other low-resistance materials may be used.

  Next, a third interlayer insulating film 530 is formed. In this embodiment, an acrylic resin with a film thickness of 530 nm is formed. The third interlayer insulating film has a laminated structure, and a light shielding film is formed by etching a film having high light shielding properties such as Al, Ti, W, Cr, or black resin into a desired shape between the interlayer insulating films. May be. The light shielding film is arranged in a mesh shape so as to shield light other than the pixel electrodes.

Next, a contact hole leading to the drain wiring in the pixel region is formed, a conductive film is formed to 100 nm, and a pixel electrode 531 is formed by etching into a desired shape. Note that in the case of obtaining a reflective liquid crystal display device, a metal film with high light reflectance, typically a film containing aluminum or silver as a main component, or a stacked film thereof may be used as a pixel electrode. When obtaining a liquid crystal display device of a type, a light-transmitting conductive film, typically, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO) ), An indium tin oxide alloy containing silicon oxide, or the like may be used.

  As described above, the pixel portion 555 including the functional circuit 554 including the n-channel TFT 540 and the p-channel TFT 541 and the pixel TFTs 542 and 543 can be formed over the same substrate. Thus, the active matrix substrate is completed.

  As described above, a TFT having a thin gate insulating film is applied to a TFT of a functional circuit (typically, a CPU, DRAM, an image processing circuit, an audio processing circuit, etc.), and a thick gate insulating film is formed. By applying a TFT having a TFT to a TFT in a pixel region or a TFT in a driver circuit (typically a buffer circuit, a shift register circuit, a level shifter circuit, a sampling circuit, etc.), the operating characteristics and reliability of a semiconductor device are improved. In addition, low power consumption can be achieved. In this embodiment, TFTs relating to driver circuits (shift register circuits, level shifter circuits, sampling circuits, etc.) are not described, but the n-channel type with a thick gate insulating film described in the first to fourth embodiments. A TFT and a p-channel TFT may be applied.

  Although the TFT described in the first embodiment is applied to the functional circuit and the TFT in the pixel region of this embodiment, the present invention is not limited to this, and is described in the second to fourth embodiments. An adapted TFT can also be applied.

  Here, a method for manufacturing a light-emitting display device using an active matrix substrate having a pixel region and a functional circuit region will be described with reference to FIGS.

  A light-emitting display device using a TFT as a switching element includes a substrate in which pixel electrodes are arranged in a matrix (active matrix substrate) and a sealing member, and a layer containing a light-emitting substance is interposed on the pixel electrode. A counter electrode is formed. The substrate and the sealing member are sealed with an adhesive or the like.

  An example of manufacturing an active matrix substrate is shown below.

  In the functional circuit region, an n-channel TFT 640 and a p-channel TFT 641 are formed in the functional circuit region, and a current control TFT 642 composed of a p-channel TFT and a switching TFT 643 composed of an n-channel TFT are formed in the pixel region. To do. In this example, the TFT having the structure shown in the first embodiment is applied. That is, the n-channel TFT 640 and the p-channel TFT 641 in the functional circuit region include the first gate electrodes 611 and 612 and the second auxiliary electrodes 613a, 613b, 614a, and 614b, and the p-channel TFT 642 in the pixel region. The n-channel TFT 643 includes second gate electrodes 615 and 616, first auxiliary electrodes 617a, 617b, 618a and 618b, and second auxiliary electrodes 635a, 635b, 636a and 636b.

  Next, a 100-nm-thick silicon nitride film is formed over the second gate insulating film, the second auxiliary electrode, and the second gate electrode of the n-channel TFT 640, the p-channel TFT 641, the current control TFT 642, and the switching TFT 643. After the first interlayer insulating film 620 is formed, the semiconductor layer is hydrogenated by heating at 300 to 550 ° C. for 1 to 12 hours. In this embodiment, heating is performed in a nitrogen atmosphere at 410 ° C. for 1 hour. This step is a step of terminating dangling bonds in the semiconductor layer of each TFT with hydrogen contained in the first interlayer insulating film 620.

  Thereafter, a second interlayer insulating film 621 made of an organic insulating material is formed on the first interlayer insulating film. As the material of the second interlayer insulating film, the same material as that of the first interlayer insulating film can be used. As the organic insulator material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used. When a photosensitive organic resin is used, a first opening having a curvature can be formed by performing an exposure process by a photolithography process and etching the photosensitive organic resin. Forming an opening having a curvature in this manner has an effect of increasing the coverage (coverage) of an electrode to be formed later. In this embodiment, a photosensitive acrylic resin film having a thickness of 1.05 μm is formed on the second interlayer insulating film. Thereafter, the second interlayer insulating film is patterned and etched to form a first opening having a gentle inner wall.

  Note that since the positive photosensitive resin is colored brown, when the positive photosensitive organic resin is used for the second interlayer insulating film 621, it is necessary to perform a decoloring process of the photosensitive organic resin after the etching. .

  Next, a third interlayer insulating film 622 made of a nitride insulating film (typically a silicon nitride film or a silicon nitride oxide film) is formed so as to cover the first opening and the second interlayer insulating film 621. . In this embodiment, a silicon nitride film is used as the third interlayer insulating film. By forming the third interlayer insulating film made of the nitride insulating film, degassing generated from the second interlayer insulating film can be suppressed.

  Next, after performing an exposure process by a photolithography process, the third interlayer insulating film 622, the second interlayer insulating film 621, the first interlayer insulating film 620, the second gate insulating film 638, and the first gate The insulating film 669 is etched sequentially to form a second opening. The etching process at this time may be a dry etching process or a wet etching process. In this embodiment, the second opening is formed by dry etching.

  Next, after forming the second opening, a metal film is formed over the third interlayer insulating film and in the second opening, and after exposure by a photolithography process, the metal film is etched to form the source electrode and Drain electrodes 623 to 629 and wiring (not shown) are formed. As the metal film, a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements is used. In this embodiment, a titanium film / aluminum-silicon alloy film / titanium film (Ti / Al-Si / Ti) is laminated to 100/350/100 nm, respectively, and then patterned and etched into a desired shape to form a source electrode and a drain electrode. 623 to 629 and wiring (not shown) are formed.

  Then, after forming the first electrode 631, a fourth interlayer insulating film is formed, and a third opening is formed. An inorganic material or an organic material can be used for the fourth interlayer insulating film. Typical examples of the inorganic material include silicon oxide, silicon nitride oxide, silicon oxynitride, and the like. Typical examples of the organic material include acrylic, polyimide, polysilazane, and the like. When the fourth interlayer insulating film is formed of an organic material having a positive or negative photosensitivity as an organic material, it has a contact hole having a curvature, so that the coverage (coverage) of an electrode to be formed later is increased. effective. In addition, a siloxane polymer is applied and baked, and a skeleton structure is formed by the bond of silicon (Si) and oxygen (O), and the substituent includes at least hydrogen, or the substituent includes fluorine, an alkyl group, or an aromatic group. You may form with the material which has at least 1 sort (s) among group hydrocarbons. In this embodiment, a photosensitive acrylic resin film is used for the fourth interlayer insulating film, and patterning and wet etching are performed to form a third opening having a gentle inner wall.

  Over the first electrode 631 and the fourth interlayer insulating film 630, a layer 632 containing a light-emitting substance, a second electrode 633 functioning as a cathode, and a passivation film (not shown) are provided. A portion where the first electrode 631, the layer 632 containing a light-emitting substance, and the second electrode 633 overlap with each other substantially becomes a light-emitting element.

  A known structure can be used for the layer 632 containing the light-emitting substance. The layer containing a light emitting material disposed between the first electrode 631 and the second electrode 633 includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. These layers may be stacked or a part or all of the materials forming these layers may be mixed. Specifically, a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like are included. Basically, the EL element has a structure in which an anode / light emitting layer / cathode is laminated in order, and in addition to this structure, an anode / hole injection layer / light emitting layer / cathode and an anode / hole injection layer. It may have a structure in which / light emitting layer / electron transport layer / cathode is laminated in this order.

  The light emitting layer is typically formed using an organic compound. Typically, it has one or a plurality of layers selected from a low molecular organic compound, a medium molecular organic compound such as an oligomer or a dendrimer, and a high molecular organic compound classified according to the number of molecules. Moreover, you may form combining the electron injection transport layer or hole injection transport layer formed from the inorganic compound which has electron injection transport property or hole injection transport property.

  The light emitting materials that are the main components of the light emitting layer are summarized below. Low molecular organic compounds include metal complexes such as tris-8-quinolinolato aluminum complex and bis (benzoquinolinolato) beryllium complex, as well as phenylanthracene derivatives, tetraaryldiamine derivatives, and distyrylbenzene derivatives. is there. Further, by using these materials as a host and adding a coumarin derivative, DCM, quinacridone, rubrene, or the like as a dopant, quantum efficiency can be increased, and high luminance and high efficiency can be achieved.

  High molecular organic compounds include polyparaphenylene vinylene, polyparaphenylene, polythiophene, polyfluorene, and the like. Poly (p-phenylene vinylene): (PPV), poly (2,5-dialkoxy-1,4-phenylene vinylene) (RO-PPV), poly (2- (2′-ethyl-hexoxy) ) -5-methoxy-1,4-phenylene vinylene (poly [2- (2'-ethylhexoxy) -5-methoxy-1,4-phenylene vinylene]): (MEH-PPV), poly (2- (di (Alkoxyphenyl) -1,4-phenylene vinylene) (poly [2- (dialkoxyphenyl) -1,4-phenylene vinylene]): (ROPh-PPV), polyparaphenylene (poly [p-phenylene]): (PPP) , Poly (2,5-dialkoxy-1,4-phenylene) (poly (2,5-dialkoxy-1,4-pheny) lene)): (RO-PPP), poly (2,5-dihexoxy-1,4-phenylene) (poly (2,5-dihexoxy-1,4-phenylene)), polythiophene: (PT), Poly (3-alkylthiophene): (PAT), poly (3-hexylthiophene): (PHT), poly (3-cyclohexylthiophene) (poly ( 3-cyclohexylthiophene)): (PCHT), poly (3-cyclohexyl-4-methylthiophene): (PCHMT), poly (3,4-dicyclohexylthiophene) (poly ( 3,4-dicyclohexylthiophene)): (PDCHT), poly [3- (4-octylphenyl) -thiophene]: (POPT), poly [3- (4-octyl) Phenyl) -2,2-bithiophene] (poly [3- (4-octylphenyl) -2,2-bithioph ene]): (PTOPT), polyfluorene: (PF), poly (9,9-dialkylfluorene) (poly (9,9-dialkylfluorene): (PDAF), poly (9,9-dioctylfluorene) (poly (9,9-dioctylfluorene): (PDOF)) and the like.

  Inorganic compounds that can be used as an electron injecting and transporting layer or a hole injecting and transporting layer include diamond-like carbon (DLC), CN, and Si, Ge, vanadium, molybdenum, and oxides or nitrides thereof. Some are appropriately doped with P, B, N, or the like. Alkali metal or alkaline earth metal oxides, nitrides or fluorides can also be used. Furthermore, it may be a compound or alloy of the metal and Zn, Sn, V, Ru, Sm, or In.

  Moreover, you may form the mixed junction structure which mixed each of these layers.

  Note that light emission of the light-emitting element includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. The light emitting element according to the present invention may use either one of the light emission or both light emission.

  As the second electrode 633, a multi-component alloy or compound including a metal component and an alkali metal or alkaline earth metal, or a component including both is used. Examples of the metal component include Al, Au, Fe, V, and Pd. Specific examples of the alkali metal or alkaline earth metal include Li (lithium), Na (sodium), K (potassium), and Rb (rubidium). ), Cs (cesium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), and the like. Other than these, Yb (ytterbium), Lu (lutetium), Nd (neodymium), Tm (thulium), or the like may be applied. The composition of the second electrode is an alloy or compound containing 0.01 to 10% by weight of an alkali metal or alkaline earth metal having a work function of 3 eV or less in the metal component. For the purpose of functioning as a cathode, the thickness of the second electrode may be set as appropriate, and may be formed by an electron beam evaporation method within a range of approximately 0.01 to 1 μm.

  As the passivation film (not shown), a silicon nitride film, an aluminum nitride film, a diamond-like carbon film, or other insulating films having a high blocking property against moisture and oxygen can be used.

In this embodiment, light emitted from the layer containing a light emitting substance is emitted to the substrate 601. On the other hand, as a first electrode, a conductive film having a high work function (ITO (oxidized oxide) is formed on a reflective conductive film formed of aluminum-silicon alloy, tantalum nitride, tantalum, titanium, tungsten, titanium containing nitrogen, or the like. Indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), indium tin oxide containing silicon oxide (ITSO), or the like) is used. On the other hand, for the second electrode, an aluminum film of 1 nm to 10 nm or an aluminum film containing a small amount of Li is used. In this case, light is emitted upward (on the side opposite to the substrate 601) because the film thickness is thin.
Furthermore, when the first electrode is formed of a transparent conductive film instead of the first electrode formed of a reflective conductive film and a conductive film having a high work function, light is emitted both upward and downward. can do.

  As described above, the functional circuit 650 including the n-channel TFT 640 and the p-channel TFT 641, the current control TFT 642 including the p-channel TFT, and the pixel region 651 including the switching TFT 643 including the n-channel TFT are formed on the same substrate. An active matrix substrate for an EL display device to be formed can be obtained. In this embodiment, TFTs relating to TFTs of a drive circuit (shift register circuit, decoder circuit, memory circuit, level shifter circuit, sampling circuit, etc.) are not shown, but gate insulation described in the first to fourth embodiments is not used. A thick n-channel TFT and p-channel TFT may be applied.

  Furthermore, the TFT described in the first embodiment is applied to the TFT of this example, but the present invention is not limited to this, and the TFT described in the second to fourth embodiments should be applied. You can also.

  As described above, a TFT having a thin gate insulating film is applied to a TFT of a functional circuit (typically, a CPU, a DRAM, an image processing circuit, an audio processing circuit, etc.), and a TFT in a pixel region or a driving circuit By applying TFTs with thick gate insulating films to TFTs (typically buffer circuits, shift register circuits, level shifter circuits, sampling circuits, etc.), the operating characteristics and reliability of EL display devices are improved. In addition, low power consumption can be achieved.

  In this example, an example of a method for manufacturing a semiconductor layer applied to the TFTs in the first to fourth embodiments, the first example, and the second example will be described with reference to FIGS. In this embodiment, the amorphous silicon film formed on the insulating surface is crystallized by scanning with continuous wave laser light.

  In FIG. 7A, a base film 702 made of a 100 nm silicon oxynitride film is formed over a glass substrate 701. An amorphous silicon film 703 formed thereon by plasma CVD is formed to a thickness of 54 nm.

  Next, as illustrated in FIG. 7B, the semiconductor layer is irradiated with laser light. The laser light used for irradiation of the semiconductor layer is continuous light emitted from the Nd: YVO4 laser oscillation device by continuous oscillation, and is the second harmonic (532 nm) obtained by the wavelength conversion element. The continuous wave laser beam is condensed into an elliptical shape by an optical system, and the amorphous silicon film 703 is crystallized by moving the irradiation position of the substrate 701 and the laser beam 705 relatively to form a crystalline silicon film 704. To do. As an optical system, a cylindrical lens of F20 is applied, so that a laser beam of Φ2.5 mm can be formed into an elliptical shape having a major axis of 2.5 mm and a minor axis of 20 μm on the irradiation surface.

  Of course, other laser oscillating devices can be applied. As a continuous oscillation solid-state laser oscillating device, crystals such as YAG, YVO4, YLF, and YAlO3 can be formed on Cr, Nd, Er, Ho, Ce, Co, Ti, and the like. Alternatively, a laser oscillation device using a crystal doped with Tm can be applied.

  Furthermore, after converting infrared laser light emitted from a solid-state laser into green laser light by a nonlinear optical element, ultraviolet laser light obtained by another nonlinear optical element can also be used.

  When the second harmonic (532 nm) of the Nd: YVO4 laser oscillation device is used, the wavelength is transmitted through the glass substrate 701 and the base film 702, so that the laser beam 706 is emitted from the glass substrate 701 side as shown in FIG. May be irradiated.

  Thus, as shown in FIG. 7D, crystallization proceeds from the region irradiated with the laser light 705 or 706, so that a crystalline silicon film 704 can be formed. The scanning of the laser beam may be reciprocal scanning instead of scanning in only one direction. In the case of reciprocal scanning, it is also possible to change the laser energy density for each scanning and cause crystal growth in stages. It is also possible to serve as a hydrogen removal process often required when crystallizing an amorphous silicon film. First, scanning is performed at a low energy density, hydrogen is released, and then the energy density is increased to 2 Crystallization may be completed by scanning a second time. Also by such a manufacturing method, a crystalline silicon film in which crystal grains extend in the laser beam scanning direction can be obtained. Thereafter, a semiconductor layer divided into island shapes can be formed and applied to the first embodiment.

  Note that the configuration shown in this embodiment is an example, and a combination with another laser oscillation device or an optical system may be applied as long as the same effect can be obtained.

  As described above, by applying the method for manufacturing a semiconductor layer of this embodiment to Embodiments 1 and 2, the operation characteristics and reliability of the semiconductor device can be further improved and the power consumption can be reduced. be able to.

  In this embodiment, an example of a method for manufacturing a semiconductor layer applied to a TFT in Embodiments 1 and 2 will be described with reference to FIGS. In this embodiment, an amorphous silicon film formed on an insulating surface is crystallized in advance, and the crystal grain size is increased by continuous wave laser light.

  As shown in FIG. 8A, a base film 802 and an amorphous silicon film 803 are formed over a glass substrate 801 as in the first embodiment. Thereafter, in order to add Ni as a metal element that promotes lowering of the crystallization temperature and crystal growth, an aqueous solution containing 5 ppm of nickel acetate is spin-coated to form the catalyst element-containing layer 804.

  Thereafter, as shown in FIG. 8B, the amorphous silicon film is crystallized by heat treatment at 580 ° C. for 4 hours. Crystallization diffuses while forming silicide in the amorphous silicon film by the action of Ni and simultaneously grows. The crystalline silicon film 806 thus formed is formed by a collection of rod-like or needle-like crystals, and each crystal grows macroscopically in a specific direction, so that the crystallinity is uniform. In addition, there is a feature that the orientation ratio of the (110) plane is high.

  After that, the continuous wave laser beam 808 is scanned as shown in FIG. 8C to improve the crystallinity of the crystalline silicon film 806, and a crystalline silicon film 807 as shown in FIG. 8D is obtained. The crystalline silicon film is melted and recrystallized by laser light irradiation. Along with this recrystallization, crystal growth is performed so that crystal grains extend in the scanning direction of the laser beam. In this case, since a crystalline silicon film having a uniform crystal plane is formed in advance, it is possible to prevent the precipitation of crystals on different planes and the occurrence of dislocations. After that, a semiconductor layer divided into island shapes can be formed and applied to Example 1 or Example 2.

  As described above, by applying the method for manufacturing a semiconductor layer of this embodiment to Embodiments 1 and 2, the operation characteristics and reliability of the semiconductor device can be further improved and the power consumption can be reduced. be able to.

  In this embodiment, an example of a method for manufacturing a semiconductor layer applied to a TFT in Embodiment 1 or Embodiment 2 will be described with reference to FIGS.

  As shown in FIG. 9A, a base film 912 and an amorphous silicon film 913 are formed over a glass substrate 911 as in the third embodiment. A 100 nm silicon oxide film is formed thereon as a mask insulating film 914 by a plasma CVD method, and an opening 915 is provided. Thereafter, in order to add Ni as a catalyst element, an aqueous solution 916 containing 5 ppm of nickel acetate is spin-coated. Ni contacts the amorphous silicon film at the opening 915.

  Thereafter, as shown in FIG. 9B, the amorphous silicon film is crystallized by heat treatment at 580 ° C. for 4 hours. Crystallization grows in the direction parallel to the substrate surface from the opening 915 by the action of the catalytic element. The crystalline silicon film 917 formed in this manner is formed by a collection of rod-like or needle-like crystals, and each crystal grows macroscopically in a specific direction, so that the crystallinity is uniform. In addition, there is a feature that the orientation ratio in a specific direction is high.

  After the heat treatment is completed, the mask insulating film 914 is removed by etching, whereby a crystalline silicon film 917 as shown in FIG. 9C can be obtained. After that, a semiconductor layer divided into island shapes can be formed and applied to Example 1 or Example 2.

In the method for manufacturing the semiconductor layer of Example 4 or Example 5, after forming the crystalline silicon film 1007, a step of removing the catalyst element remaining in the film at a concentration of 10 ¹⁹ / cm ³ or more by gettering is added. May be. In this embodiment, a gettering process will be described.

As shown in FIG. 10, a barrier layer 1009 made of a thin silicon oxide film is formed on a crystalline silicon film 1007, and argon or phosphorus is used as a gettering site 1010 on the barrier layer 1009, 1 × 10 ²⁰ / cm ³ to 1 ×. An amorphous silicon film doped with 10 ²¹ / cm ³ is formed by sputtering.

Thereafter, it is added as a catalyst element by heat treatment at 600 ° C. for 12 hours in a furnace annealing furnace, or heat treatment at 650 to 800 ° C. for 30 to 60 minutes by RTA using lamp light or heated gas as a heating means. Ni that is present can be segregated at the gettering site 1010. By this treatment, the concentration of the catalytic element in the crystalline silicon film 1007 can be made 10 ¹⁷ / cm ³ or less.

  A gettering process performed under similar conditions is also effective for the crystalline silicon film manufactured in the third embodiment. A trace amount of metal elements contained in the crystalline silicon film formed by irradiating the amorphous silicon film with laser light can be removed by this gettering treatment.

  As described above, by applying the gettering method of this embodiment to the semiconductor layer manufacturing method of Embodiments 3 to 5, the operating characteristics and reliability of the semiconductor device are further improved and the power consumption is reduced. It can be done.

  In this example, a process of manufacturing an active matrix type liquid crystal module from the active matrix substrate of Example 1 will be described below. FIG. 13 is used for the description.

  A pixel portion 1101 is arranged in the center of the active matrix substrate 1105. A source signal line driver circuit 1102 for driving the source signal lines is disposed above the pixel portion 1101. On the left side of the pixel portion 1101, a gate signal line driving circuit 1103 for driving the gate signal line is disposed. In the example shown in this embodiment, the gate signal line driver circuit 1103 is arranged only on one side of the pixel portion, but this may be arranged symmetrically with respect to the pixel, and the substrate size of the liquid crystal module can be reduced. In consideration, the designer may select as appropriate. However, a symmetrical arrangement is desirable in view of operation reliability of the circuit, driving efficiency, and the like. In addition, a functional circuit 1104 is provided over the panel, and various signals output from the functional circuit 1104 are supplied to the pixel portion 1101, the source signal line driver circuit 1102, and the gate signal line driver circuit 1103. A functional circuit 1104 that has been conventionally connected to the outside of the panel using an FPC or the like is manufactured on an active matrix substrate, whereby the liquid crystal display device can be downsized.

  Further, a power supply voltage output from an external power supply circuit (not shown) is supplied to the pixel portion 1101, the source driver circuit 1102, and the gate driver circuit 1103 of the panel via the FPC 1109.

  A sealant 1107 is applied around the periphery of the driving circuit and the pixel portion along the outer periphery of the substrate, and a predetermined gap (a distance between the substrate 1105 and the counter substrate 1106) is maintained by a spacer formed on the active matrix substrate in advance. In this state, the counter substrate 1106 is attached. Thereafter, a liquid crystal material is injected from a portion where the sealant 1107 is not applied, and is sealed with the sealant 1108. The liquid crystal module is completed through the above steps.

  Note that several ICs may be used as part of the driver circuit or the functional circuit.

  Similarly to this embodiment, various modules (such as an active matrix EL module and an active matrix EC module) can be manufactured using an active matrix substrate formed by implementing the present invention.

  TFTs formed by implementing the present invention can be used in various modules (active matrix liquid crystal modules, active matrix EL modules, active matrix EC modules). That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.

  Examples thereof include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, television receivers, mobile phones, projection display devices, and the like. Examples of these are shown in FIGS.

  FIG. 11A illustrates an example in which the present invention is applied to complete a television receiver, which includes a housing 3001, a support base 3002, a display portion 3003, and the like. The TFT substrate manufactured according to the present invention is applied to the display portion 3003, and a television receiver that is thinner and has higher resolution can be completed according to the present invention.

  FIG. 11B shows an example in which the present invention is applied to complete a video camera, which includes a main body 3011, a display portion 3012, an audio input portion 3013, operation switches 3014, a battery 3015, an image receiving portion 3016, and the like. . A TFT substrate manufactured according to the present invention is applied to the display portion 3012. According to the present invention, a small video camera with high resolution can be completed.

  FIG. 11C illustrates an example in which a laptop personal computer is completed by applying the present invention, which includes a main body 3021, a housing 3022, a display portion 3023, a keyboard 3024, and the like. The TFT substrate manufactured according to the present invention is applied to the display portion 3023, and a personal computer that is small in size and low in power consumption can be completed according to the present invention.

  FIG. 11D shows an example in which a PDA (Personal Digital Assistant) is completed by applying the present invention, which includes a main body 3031, a stylus 3032, a display portion 3033, operation buttons 3034, an external interface 3035, and the like. The TFT substrate manufactured according to the present invention is applied to the display portion 3033. According to the present invention, a PDA having a small size, high resolution, and high performance can be completed.

  FIG. 11E is an example in which a sound reproducing device is completed by applying the present invention, specifically, an in-vehicle audio device, which includes a main body 3041, a display portion 3042, operation switches 3043, 3044, and the like. Has been. The TFT substrate manufactured according to the present invention is applied to the display portion 3042, and according to the present invention, an audio device having a small and high-resolution display portion can be completed.

  FIG. 11F illustrates an example in which the present invention is applied to complete a digital camera. A main body 3051, a display portion (A) 3052, an eyepiece portion 3053, an operation switch 3054, a display portion (B) 3055, a battery 3056. Etc. The TFT substrate manufactured according to the present invention is applied to the display portion (A) 3052 and the display portion (B) 3055, and according to the present invention, a small digital camera having a display portion with high resolution can be completed.

  FIG. 11G illustrates an example of a cellular phone completed by applying the present invention, which includes a main body 3061, an audio output unit 3062, an audio input unit 3063, a display unit 3064, operation switches 3065, an antenna 3066, and the like. Yes. The TFT substrate manufactured according to the present invention is applied to the display portion 3064. According to the present invention, a small mobile phone having a display portion with high resolution can be completed.

  FIG. 12A illustrates a projector, which includes a projection device 2601, a screen 2602, and the like.

  FIG. 12B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like.

  FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 12D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 12D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  Note that the projector shown in FIG. 12 shows a case where a transmissive active matrix liquid crystal module is used, and an application example in a reflective active matrix liquid crystal module is not shown, but a reflective type is shown. An active matrix liquid crystal module can also be applied.

  In a conventional projector, when a TFT having a crystalline silicon layer crystallized using a metal element is used, it is considered that one of the causes is that the off current cannot be suppressed due to insufficient gettering of the metal element. There is a problem that a bright spot (a pixel in which the pixel TFT is not smoothly switched and continues to shine) is generated. Although the display unevenness is caused by the bright spots, the bright matrix can be reduced by applying the active matrix liquid crystal module shown in the second embodiment to the projector as shown in the present embodiment. Become. Thereby, a projector capable of high-definition display can be manufactured. Furthermore, according to the present invention, an active matrix liquid crystal module having a TFT in which defects in a crystalline silicon film are reduced can be manufactured. Therefore, a projector capable of high-speed operation can be manufactured.

  In addition, the apparatus shown here is only an example and is not limited to these uses.

The figure which shows 1st Embodiment. The figure which shows 2nd Embodiment. The figure which shows 3rd Embodiment. The figure which shows 4th Embodiment. FIG. 4 is a diagram illustrating an example of a cross-sectional view of a liquid crystal display device. Example 1 FIG. 14 illustrates an example of a cross-sectional view of an EL display device. (Example 2) FIG. FIG. FIG. 6 shows a fifth embodiment. FIG. 6 shows a sixth embodiment. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. The figure showing a liquid crystal module.

Claims (5)

A first channel formation region, a first source region, a first drain region, the first source region, or a first channel formed between the first drain region and the first channel formation region; A first semiconductor layer having a region;
A second channel formation region, a second source region, a second drain region, the second source region, or a second channel formed between the second drain region and the second channel formation region A second semiconductor layer having a region and a third region formed between the second source region or the second drain region and the second region;
A first insulating film formed on the first semiconductor layer and the second semiconductor layer;
A first auxiliary electrode formed on the second semiconductor layer via the first insulating film;
A first gate electrode formed on the first semiconductor layer via the first insulating film;
A second insulating film formed on the first insulating film, the first auxiliary electrode, and the first gate electrode;
A second gate electrode formed on the second channel formation region via the second insulating film;
A second auxiliary electrode having a curved surface or an inclined surface formed on the third region via the second insulating film;
A third auxiliary electrode having a curved surface or an inclined surface formed on the first region via the second insulating film,
The second gate electrode, the second auxiliary electrode, and the third auxiliary electrode are made of the same material,
The first auxiliary electrode is formed on the second region via the first insulating film,
Having first to fifth wirings;
The first wiring is electrically connected to the first gate electrode;
The second wiring is electrically connected to the second gate electrode;
The third wiring is electrically connected to the first auxiliary electrode;
The fourth wiring is electrically connected to the second auxiliary electrode;
The fifth wiring is electrically connected to the third auxiliary electrode;
The semiconductor device according to claim 1, wherein the first auxiliary electrode partially overlaps the second gate electrode. In claim 1,
A semiconductor device, wherein an impurity is added to the first region or the second region. In claim 1 or claim 2,
A semiconductor device, wherein an impurity is added to the third region. A first channel forming region, a first source region, a first drain region, and a first source region or a first channel formed between the first drain region and the first channel forming region; A first semiconductor layer having a first region, a first gate electrode, a third auxiliary electrode having a curved surface or an inclined surface, a first insulating film, and a second insulating film. A thin film transistor of
A second channel formation region, a second source region, a second drain region, the second source region, or a second channel formed between the second drain region and the second channel formation region A second semiconductor layer having a region, a third region formed between the second source region or the second drain region and the second region, a second gate electrode, A first thin film transistor having a first auxiliary electrode, the first insulating film, the second insulating film, and a second auxiliary electrode having a curved surface or an inclined surface;
Having first to fifth wirings;
The first wiring is electrically connected to the first gate electrode;
The second wiring is electrically connected to the second gate electrode;
The third wiring is electrically connected to the first auxiliary electrode;
The fourth wiring is electrically connected to the second auxiliary electrode;
The fifth wiring is a method for manufacturing a semiconductor device electrically connected to the third auxiliary electrode,
Forming the first semiconductor layer and the second semiconductor layer on an insulating surface;
Forming the first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming the first gate electrode on the first channel formation region via the first insulating film;
Forming the first auxiliary electrode on the second region via the first insulating film;
Forming the second insulating film on the first gate electrode, the first auxiliary electrode, and the first insulating film;
Forming a conductive film on the second insulating film;
Forming a resist mask on a portion for forming the second gate electrode;
By etching the conductive film, a second gate electrode is formed on the second channel formation region through the second insulating film, and a third region is formed on the third region through the second insulating film. Forming a second auxiliary electrode and a third auxiliary electrode having a curved surface or an inclined surface on the first region via the second insulating film;
The method for manufacturing a semiconductor device, wherein the second gate electrode is formed so as to overlap with part of the first auxiliary electrode. In claim 4,
A method for manufacturing a semiconductor device, wherein the first thin film transistor is used as a thin film transistor in a functional circuit, and the second thin film transistor is used as a thin film transistor in a pixel region or a thin film transistor in a driver circuit.

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