JP4983692B2 - Multiplex transmission equipment - Google Patents

Description

  The present invention relates to a multiplexing transmission apparatus that multiplexes data in units of frames from a plurality of transmission paths and outputs the multiplexed data to a single transmission path, and more particularly to a multiplexing transmission apparatus that uses a cross-connect method. .

  In recent years, with the spread of the Internet, the use of broadband communication has increased, and there has been a demand for higher data transfer rates and higher capacities by terminal devices. In addition, terminal devices are diversified, and there are many cases where data output from the terminal devices is not synchronized with the data transmission system as a relay device on the network or the internal timing of the multiplexing device in the system. Exists.

  For this reason, in the conventional data transmission system, in order for the built-in cross-connect unit to function normally, in the terminal interface unit disposed on the front stage side or the rear stage side of the cross-connect unit, in the multiplexing device or system It is necessary to convert to the entire timing. In order to realize this timing conversion, a conventional data transmission system includes a buffer such as a memory or FIFO (First-In First-Out), and a control circuit that controls writing and reading with respect to the buffer. It was.

Although it is a cross-connect device that captures multiplexed signals that have already been multiplexed, a separating means that separates the multiplexed signals for each line based on the configuration, and the separated lines for each destination indicated by the routing control information Internal multiplexing means for combining and multiplexing, and sending frames individually corresponding to the output ports; input means corresponding to each input port; and frames sent from the internal multiplexing means to a specific destination It has internal separation means that takes in the corresponding one and separates it for each line, and multiplexing means that multiplexes the separated line to an output port corresponding to a specific destination and sends it out, individually corresponding to the output port There is known a technique called a cross-connect device configured to include the output means.
Japanese Patent Application Laid-Open No. 07-79247

  However, in a conventional data transmission system, a built-in memory, a buffer such as a FIFO, and a control circuit tend to be physically large. In particular, there has been a problem that each control for the memory and the FIFO becomes complicated and causes a failure in data transfer.

  The present invention has been made to solve the above-described problems, and adjusts the phase of data in units of frames input from a plurality of transmission lines without incorporating a FIFO, thereby providing a single transmission. A multiplexed transmission apparatus that can output to a channel is provided.

In the multiplex transmission apparatus according to the present invention, at least three memories are provided corresponding to each of the plurality of transmission paths, and data in units of frames transmitted by the at least three memories through each transmission path. And a frame phase that is arranged corresponding to each transmission path of the plurality of transmission paths and detects the phase of each frame with respect to data in units of frames transmitted through the transmission paths. Based on the phase of each frame, which is disposed corresponding to each transmission path of the plurality of transmission paths, and is detected by the frame phase detection section, a plurality of data constituting the one frame is stored in each frame. A write control unit that sequentially counts the data of each frame in correspondence with each memory of the storage unit, and sets the count value as an address, and writes in the storage unit A read control unit for designating data at the predetermined address among data written to a memory different from the memory in the memory, and reading data at the designated address in synchronization with a common memory in the storage units; A multiplexing unit that multiplexes a plurality of data read by the read control unit, and the write control unit cyclically switches each of the memories to write the data, and the write timing and the read timing are synchronized In this case, the memory holding the data in the immediately preceding frame is a memory to be written, and the read control unit cyclically switches each memory to read the data, and the write timing and the read timing but if you are in sync, the memory writing the data in the previous frame, which is to shall and memory to be read.

  The disclosed multiplex transmission device generates multiplexed data in which the time relationships of data from a plurality of transmission paths are matched even when the write timing and read timing of the memory of the storage unit are asynchronous. There is an effect that can be.

(First embodiment of the present invention)
FIG. 1 is a block diagram showing a schematic configuration in an example of a multiplexing transmission apparatus according to the present embodiment, FIG. 2 is a time chart for explaining an example of processing operation of the multiplexing transmission apparatus shown in FIG. Is a time chart for explaining another example of the processing operation of the multiplexing transmission apparatus shown in FIG. 1, and FIG. 4 is a time chart for explaining still another example of the processing operation of the multiplexing transmission apparatus shown in FIG. FIG. 5 is an explanatory diagram for explaining the limit of the phase difference of the read timing with respect to the write timing.

  The multiplex transmission apparatus 100 has an interface unit (hereinafter referred to as a terminal interface unit 1) to which frame unit data (terminal data) from the terminal apparatus 200 is input via a transmission path as determined by the apparatus specifications. Have only.

  The terminal data from the terminal device 200 is an optical fiber in which SONET (Synchronous Optical Network), which is a communication standard, is standardized as SDH (Synchronous Digital Hierarchy) by the International Telecommunications Union / Telecommunication Standardization Sector (ITU-TS). Data conforming to the international standard (SONET / SDH) of the high-speed digital communication system used, and is transmitted in a certain frame unit.

  The terminal interface unit 1 corresponds to the protocol of each terminal device 200 and performs electrical conversion, and outputs terminal data to the cross-connect unit 10 described later.

  The cross-connect unit 10 includes a storage unit 2, a frame phase detection unit 3, and a write control unit 4 corresponding to each terminal interface unit 1, and a common read control unit 5 and A multiplexing unit 6 is provided. That is, the cross-connect unit 10 includes a storage unit 2 that stores terminal data, and performs time slot conversion by controlling writing or reading of the storage unit 2.

  The storage unit 2 receives at least three memories (first memory 21, second memory 22, third memory) for terminal data in units of frames from one transmission path input via the terminal interface unit 1. The memory 23) is used as a buffer.

  In order to facilitate understanding of the present invention, the multiplex transmission apparatus 100 according to the present embodiment will be described in the case where the number of memories in the cross-connect unit 10 is three. For example, the operational effects of the multiplex transmission apparatus 100 according to the present embodiment can be achieved. In particular, it is preferable to set the number of memories in the cross-connect unit 10 to three because the cost can be reduced and the mounting area can be reduced with the minimum memory.

  The frame phase detection unit 3 detects the phase of each frame with respect to terminal data in units of frames from one transmission path input via the terminal interface unit 1 and outputs the detected phase to a write control unit 4 to be described later. . In addition, the frame phase detection unit 3 generates a timing for writing data in each memory of the storage unit 2 (hereinafter referred to as a write timing) and outputs the timing to the write control unit 4 described later.

  The write control unit 4 has a counter function, and counts a plurality of data constituting one frame in order from the head of each frame based on the phase of each frame detected by the frame phase detection unit 3. . Then, the write control unit 4 sets the count value as an address (write address), and matches each frame of the storage unit 2 with each frame in accordance with the write timing generated by the frame phase detection unit 3. The terminal data is sequentially written.

  In particular, the write control unit 4 has a first memory 21, a second memory 22, a third memory 23, a first memory 21,. In addition, each memory of the storage unit 2 is fixedly switched and terminal data is written.

  The read control unit 5 designates data at a predetermined address (read address) among data written in a memory different from the memory being written in the storage unit 2, and each storage unit 2 corresponding to each terminal interface unit 1. Read synchronously from the corresponding memory. Further, the read control unit 5 controls a multiplexing unit 6 described later.

  Note that the read control unit 5 corresponds to an ACM (Access Control Memory), and reads the memory of the storage unit 2 in the order determined by the network settings stored in the ACM memory. The predetermined read address is indicated by a counter (not shown) outside the multiplex transmission apparatus 100, and a reference timing in the multiplex transmission apparatus 100 can be given.

  In particular, the read control unit 5 reads data from the third memory 23 of the storage unit 2 at the initial startup of the timing of reading data from each memory of the storage unit 2 (hereinafter referred to as read timing). . Then, the read control unit 5 determines a synchronous or asynchronous state between the write timing and the read timing at the write timing, and sets the memory of the storage unit 2 that reads data according to the synchronous or asynchronous state. .

  That is, when the write timing and the read timing are synchronized, the memory of the storage unit 2 that reads data is made to correspond to the memory in which the terminal data in the immediately previous frame is written. As a result, the cross-connect can function in the same delay time as the time switch in the double-buffer cross-connect. When the write timing and the read timing are asynchronous, the memory of the storage unit 2 that reads the terminal data at the next read timing corresponds to the memory that has written the terminal data in the immediately preceding frame with respect to the current write timing. Let

  The multiplexing unit 6 multiplexes a plurality of data read by the read control unit 5 and supplies the multiplexed data to an interface unit (hereinafter referred to as a transmission path interface unit 7) that is an interface with the output side transmission path 300. Output.

  The transmission path interface unit 7 is a part that performs electrical conversion, optical conversion, and the like corresponding to the multiplexed transmission apparatus 100, and outputs multiplexed data to the transmission path 300.

Next, the processing operation of the multiplex transmission apparatus according to the present embodiment will be described with reference to FIGS.
In order to facilitate understanding of the present invention, the multiplex transmission apparatus 100 will be described with respect to a case where terminal data is input from each of the two terminal apparatuses 200, but the terminal apparatus connected to the multiplex transmission apparatus 100 is described. The same effect can be obtained without depending on the number of 200.

  Moreover, in the following description, the two terminal devices 200 will be described as a first terminal device 200a and a second terminal device 200b. Moreover, about each component of the multiplex transmission apparatus 100 corresponding to the 1st terminal device 200a, it adds a at the end of a code | symbol, and each component of the multiplex transmission apparatus 100 corresponding to the 2nd terminal device 200b Will be described by appending b to the end of the code.

  2, FIG. 3 and FIG. 4 show the first write timing, the first terminal data, the first write buffer surface (the write target of the storage unit 2a) corresponding to the first terminal device 200a. Memory), first read timing, first read buffer surface (memory to be read from the storage unit 2a), and first read data are shown in order from the top.

  Similarly, FIG. 2, FIG. 3 and FIG. 4 show the second write timing, the second terminal data, the second write buffer surface (the write of the storage unit 2b) corresponding to the second terminal device 200b. (Target memory), second read timing, second read buffer surface (read target memory of the storage unit 2b), and second read data are shown in order from the top.

  2, 3, and 4, multiplexed data obtained by multiplexing the first read data corresponding to the first terminal device 200 a and the second read data corresponding to the second terminal device 200 b is obtained. Shown at the bottom.

2, 3, and 4 show the read timings corresponding to the first terminal device 200 a and the second terminal device 200 b, respectively. These read timings are read by the read control unit 5. The reference timing is common within the multiplexed transmission apparatus 100 to be controlled.
2, 3, and 4, the A surface corresponds to the first memory 21, the B surface corresponds to the second memory 22, and the C surface corresponds to the third memory 23. It corresponds to.

  2, 3, and 4, among the terminal data from the first terminal device 200 a, a time switch (TSW) is used for data d <b> 11, d <b> 12, d <b> 13, d <b> 14, d <b> 15, and d <b> 16. An example is shown. In addition, an example is shown in which time switching is performed on data d21, d22, d23, d24, d25, and d26 among the terminal data from the second terminal device 200b.

  That is, data corresponding to the write address from the write control unit 4a and the read address from the read control unit 5a are d11, d12, d13, d14, d15, and d16, respectively. The data corresponding to the write address from the write control unit 4b and the read address from the read control unit 5b are d21, d22, d23, d24, d25 and d26, respectively.

First, as shown in FIG. 2, it is a case where the phase of the frame by the terminal data from the two terminal devices 200 is synchronously input to the multiplexing transmission device 100, and the write timing for each memory in the storage unit 2 A case where the read timing is asynchronous will be described.
Here, the processing operation of the multiplex transmission apparatus 100 corresponding to the first terminal data from the first terminal apparatus 200a will be described.

  The terminal interface unit 1a is a first frame unit (corresponding to # 1, # 2, # 3, # 4, # 5, and # 6 in the first terminal data shown in FIG. 2) from the first terminal device 200a. 1 terminal data is received, converted into a predetermined electrical signal, and output to the storage unit 2a.

  The frame phase detector 3a detects the phase of each frame, generates a write timing (corresponding to the first write timing shown in FIG. 2) based on the first terminal data at the beginning of each frame, The data is output to the write control unit 4a.

The write control unit 4a designates a predetermined write address in each frame, and first terminal data of the designated write address is associated with each memory in the storage unit 2a based on the first write timing. Are written sequentially. Here, the write buffer surface corresponding to the first frame # 1 is the A surface (corresponding to the first memory 21a), and the data d11 is written. The write buffer surface corresponding to the second frame # 2 is the B surface (corresponding to the second memory 22a), and the data d12 is written. The write buffer surface corresponding to the third frame # 3 is the C surface (corresponding to the third memory 23a), and the data d13 is written.
In this way, the write control unit 4a switches the write buffer surface corresponding to each frame and writes the corresponding first terminal data.

  Read control unit 5 designates a predetermined read address in each frame, and designates the read address corresponding to each memory in storage unit 2a based on the reference timing (corresponding to the first read timing shown in FIG. 2). Are sequentially read out. In particular, FIG. 2 is a diagram for explaining the case where the write timing and the read timing for each memory in the storage unit 2 are asynchronous, and the write timing and the reference timing generated by the frame phase detection unit 3 are asynchronous. .

  When the write buffer surface is the B surface (corresponding to the second memory 22a), the read buffer surface is the C surface (corresponding to the third memory 23a) or the A surface (corresponding to the first memory 21a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 2, d11 is read from the A side of the read buffer when data d12 is written to the B side of the write buffer.

  When the write buffer surface is the C surface (corresponding to the third memory 23a), the read buffer surface is the A surface (corresponding to the first memory 21a) or the B surface (corresponding to the second memory 22a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 2, d12 is read from the B surface of the read buffer when the data d13 is written to the C surface of the write buffer.

When the write buffer surface is the A surface (corresponding to the first memory 21a), the read buffer surface is the B surface (corresponding to the second memory 22a) or the C surface (corresponding to the third memory 23a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 2, when data d14 is written to the A side of the write buffer, d13 is read from the C side of the read buffer.
In this way, the read control unit 5 switches the read buffer surface corresponding to each frame and reads the corresponding first terminal data.

Next, the processing operation of the multiplex transmission apparatus 100 corresponding to the second terminal data from the second terminal apparatus 200b will be described.
The terminal interface unit 1b receives the first frame unit from the second terminal device 200b (corresponding to # 1, # 2, # 3, # 4, # 5, and # 6 in the second terminal data shown in FIG. 2). 2 terminal data is received, converted into a predetermined electrical signal, and output to the storage unit 2b.

  The frame phase detector 3b detects the phase of each frame, generates a write timing (corresponding to the second write timing shown in FIG. 2) based on the second terminal data at the head of each frame, The data is output to the write control unit 4b. In particular, FIG. 2 is a diagram for explaining a case where the phase of the frame based on the terminal data from the two terminal devices 200 is synchronously input to the multiplexing transmission device 100. The frame phase detection unit 3a and the frame phase detection unit The write timing generated by 3b is synchronized.

The write control unit 4b designates a predetermined write address in each frame, and based on the second write timing, the second terminal data of the designated write address is associated with each memory in the storage unit 2b. Are written sequentially. Here, the write buffer surface corresponding to the first frame # 1 is the A surface (corresponding to the first memory 21b), and the data d21 is written. The write buffer surface corresponding to the second frame # 2 is the B surface (corresponding to the second memory 22b), and the data d22 is written. The write buffer plane corresponding to the third frame # 3 is the C plane (corresponding to the third memory 23b), and the data d23 is written.
In this way, the write control unit 4b switches the write buffer surface corresponding to each frame and writes the corresponding second terminal data.

  Read control unit 5 designates a predetermined read address in each frame, and designates the read address corresponding to each memory of storage unit 2b based on the reference timing (corresponding to the second read timing shown in FIG. 2). Are sequentially read out.

  When the write buffer surface is the B surface (corresponding to the second memory 22b), the read buffer surface is the C surface (corresponding to the third memory 23b) or the A surface (corresponding to the first memory 21b). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 2, d21 is read from the A side of the read buffer when data d22 is written to the B side of the write buffer.

  When the write buffer surface is the C surface (corresponding to the third memory 23b), the read buffer surface is the A surface (corresponding to the first memory 21b) or the B surface (corresponding to the second memory 22b). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 2, d22 is read from the B surface of the read buffer when data d23 is written to the C surface of the write buffer.

When the write buffer surface is the A surface (corresponding to the first memory 21b), the read buffer surface is the B surface (corresponding to the second memory 22b) or C (corresponding to the third memory 23b). Thus, the write buffer surface and the read buffer surface are made to correspond to each other. In FIG. 2, when data d24 is written to the A side of the write buffer, d23 is read from the C side of the read buffer.
In this way, the read control unit 5 switches the read buffer surface corresponding to each frame and reads the corresponding second terminal data.

  Then, the multiplexing unit 6 multiplexes the first terminal data read from the storage unit 2a and the second terminal data read from the storage unit 2b by the read control unit 5, and transmits the transmission path interface. The multiplexed data is output to the unit 7.

  As for terminal data to be time-switched, the first terminal data from the first terminal device 200a is switched in the first half of the frame, and the second terminal data from the second terminal device 200b is switched in the second half of the frame. Is done.

  Here, the timing for switch-multiplexing the first terminal data from the first terminal device 200a and the second terminal data from the second terminal device 200b is, for example, the first readout timing and the second readout timing. Consider the case of the third frame.

  In this case, both the first read buffer and the second read buffer plane are the A plane, and the data to be read is the first frame data (d21) in the second terminal data and the first terminal data. This is the data (d11) of the first frame.

  Therefore, the first terminal data and the second terminal data are multiplexed by configuring the same frame (time pairs are matched), and the time relationships of the terminal data from the different terminal devices 200 are matched and transmitted. be able to.

  As shown in FIG. 3, this is a case where the phase of the frame based on the terminal data from the two terminal devices 200 is synchronously input to the multiplexing transmission device 100, and the write timing for each memory in the storage unit 2 The case where the read timing is synchronized is also the same as in the case of FIG. 2, and thus the description thereof is omitted here.

  In particular, FIG. 3 is a diagram illustrating a case where the write timing and the read timing for each memory in the storage unit 2 are synchronized, and the write timing and the reference timing generated by the frame phase detection unit 3 are synchronized. .

  FIG. 3 is a diagram for explaining a case in which the phase of the frame based on the terminal data from the two terminal devices 200 is input to the multiplexing transmission device 100 in synchronization with the frame phase detection unit 3a and the frame phase detection. The write timing generated by the unit 3b is synchronized.

  Next, as shown in FIG. 4, the phase of the frame based on the data from the two terminal devices 200 is asynchronously input to the multiplexing transmission device 100, and the writing timing and reading to each memory in the storage unit 2 A case where the timing is asynchronous will be described.

First, the processing operation of the multiplex transmission apparatus 100 corresponding to the first terminal data from the first terminal apparatus 200a will be described.
The terminal interface unit 1a is the first frame unit (corresponding to # 1, # 2, # 3, # 4, # 5, and # 6 in the first terminal data shown in FIG. 4) from the first terminal device 200a. 1 terminal data is received, converted into a predetermined electrical signal, and output to the storage unit 2a.

  The frame phase detector 3a detects the phase of each frame, generates a write timing (corresponding to the first write timing shown in FIG. 4) based on the first terminal data at the beginning of each frame, The data is output to the write control unit 4a.

The write control unit 4a designates a predetermined write address in each frame, and first terminal data of the designated write address is associated with each memory in the storage unit 2a based on the first write timing. Are written sequentially. Here, the write buffer surface corresponding to the first frame # 1 is the C surface (corresponding to the third memory 23a), and the data d11 is written. The write buffer surface corresponding to the second frame # 2 is the A surface (corresponding to the first memory 21a), and the data d12 is written. The write buffer surface corresponding to the third frame # 3 is the B surface (corresponding to the second memory 22a), and the data d13 is written.
In this way, the write control unit 4a switches the write buffer surface corresponding to each frame and writes the corresponding first terminal data.

  Read control unit 5 designates a predetermined read address in each frame, and designates the read address corresponding to each memory in storage unit 2a based on the reference timing (corresponding to the first read timing shown in FIG. 4). Are sequentially read out. In particular, FIG. 4 is a diagram for explaining a case where the write timing and the read timing for each memory in the storage unit 2 are asynchronous, and the write timing and the reference timing generated by the frame phase detection unit 3 are asynchronous. .

  When the write buffer surface is the A surface (corresponding to the first memory 21a), the read buffer surface is the B surface (corresponding to the second memory 22a) or the C surface (corresponding to the third memory 23a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 4, d11 is read from the C surface of the read buffer when data d12 is written to the A surface of the write buffer.

  When the write buffer surface is the B surface (corresponding to the second memory 22a), the read buffer surface is the C surface (corresponding to the third memory 23a) or the A surface (corresponding to the first memory 21a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 4, d12 is read from the A side of the read buffer when data d13 is written to the B side of the write buffer.

When the write buffer surface is the C surface (corresponding to the third memory 23a), the read buffer surface is the A surface (corresponding to the first memory 21a) or the B surface (corresponding to the second memory 22a). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 4, d13 is read from the B surface of the read buffer when the data d14 is written to the C surface of the write buffer.
In this way, the read control unit 5 switches the read buffer surface corresponding to each frame and reads the corresponding first terminal data.

Next, the processing operation of the multiplex transmission apparatus 100 corresponding to the second terminal data from the second terminal apparatus 200b will be described.
The terminal interface unit 1b is the first frame unit (corresponding to # 1, # 2, # 3, # 4, # 5, and # 6 in the second terminal data shown in FIG. 4) from the second terminal device 200b. 2 terminal data is received, converted into a predetermined electrical signal, and output to the storage unit 2b.

  The frame phase detector 3b detects the phase of each frame, generates a write timing (corresponding to the second write timing shown in FIG. 4) based on the second terminal data at the head of each frame, The data is output to the write control unit 4b. In particular, FIG. 4 is a diagram for explaining the case where the phase of the frame based on the terminal data from the two terminal devices 200 is asynchronously input to the multiplexing transmission device 100, and the frame phase detection unit 3a and the frame phase detection unit 3b. The write timing generated by is asynchronous.

The write control unit 4b designates a predetermined write address in each frame, and based on the second write timing, the second terminal data of the designated write address is associated with each memory in the storage unit 2b. Are written sequentially. Here, the write buffer surface corresponding to the first frame # 1 is the C surface (corresponding to the third memory 23b), and the data d21 is written. The write buffer plane corresponding to the second frame # 2 is the A plane (corresponding to the first memory 21b), and the data d22 is written. The write buffer surface corresponding to the third frame # 3 is the B surface (corresponding to the second memory 22b), and the data d23 is written.
In this way, the write control unit 4b switches the write buffer surface corresponding to each frame and writes the corresponding second terminal data.

  Read control unit 5 designates a predetermined read address in each frame, and designates the read address corresponding to each memory of storage unit 2b based on the reference timing (corresponding to the second read timing shown in FIG. 4). Are sequentially read out.

  When the write buffer surface is the A surface (corresponding to the first memory 21b), the read buffer surface is the B surface (corresponding to the second memory 22b) or C (corresponding to the third memory 23b). Thus, the write buffer surface and the read buffer surface are made to correspond to each other. In FIG. 4, d21 is read from the C surface of the read buffer when the data d22 is written to the A surface of the write buffer.

  When the write buffer surface is the B surface (corresponding to the second memory 22b), the read buffer surface is the C surface (corresponding to the third memory 23b) or the A surface (corresponding to the first memory 21b). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 4, d22 is read from the A side of the read buffer when the data d23 is written to the B side of the write buffer.

When the write buffer surface is the C surface (corresponding to the third memory 23b), the read buffer surface is the A surface (corresponding to the first memory 21b) or the B surface (corresponding to the second memory 22b). Thus, the write buffer surface and the read buffer surface are associated with each other. In FIG. 4, d23 is read from the B surface of the read buffer when the data d24 is written to the C surface of the write buffer.
In this way, the read control unit 5 switches the read buffer surface corresponding to each frame and reads the corresponding second terminal data.

  Then, the multiplexing unit 6 multiplexes the first terminal data read from the storage unit 2a and the second terminal data read from the storage unit 2b by the read control unit 5, and transmits the transmission path interface. The multiplexed data is output to the unit 7.

  As for terminal data to be time-switched, the first terminal data from the first terminal device 200a is switched in the first half of the frame, and the second terminal data from the second terminal device 200b is switched in the second half of the frame. Is done.

  Here, the timing for switch-multiplexing the first terminal data from the first terminal device 200a and the second terminal data from the second terminal device 200b is, for example, the first readout timing and the second readout timing. Consider the case of the third frame.

  In this case, both the first read buffer and the second read buffer are C planes, and the data to be read is the first frame data (d21) in the second terminal data and the first terminal data. This is the data (d11) of the first frame.

  Therefore, the first terminal data and the second terminal data are multiplexed by configuring the same frame (time pairs are matched), and the time relationships of the terminal data from the different terminal devices 200 are matched and transmitted. be able to.

  Note that, as shown in FIG. 5, the multiplex transmission apparatus 100 in which each storage unit 2 is provided with three memories has a write timing phase difference between all write target surfaces on the write side. There is an allowable range provided that the read target surface does not match.

  That is, the read timing is the latest write timing (here, the second write timing) among the write timings for the memories (here, the first write buffer surface and the second write buffer surface) of each storage unit 2. Timing at the boundary between the A surface and the B surface of the write buffer surface).

  In addition, the read timing is the earliest write timing (here, the first write timing) among the write timings for the memories (here, the first write buffer surface and the second write buffer surface) of each storage unit 2. The timing is one frame later than the timing at the boundary between the A and B surfaces of the write buffer surface (here, the timing at the boundary between the B and C surfaces of the first write buffer surface). Or it is necessary to make it early.

  Next, in order to explain the advantageous effect of having three or more memories in each storage unit 2 without incorporating a FIFO, which is a feature of the multiplex transmission apparatus 100 according to the present embodiment, A description will be given in comparison with a double buffer structure in which the memory of unit 2 is two.

  6 is a block diagram showing a schematic configuration of the multiplex transmission apparatus according to Comparative Example 1, and FIG. 7 is a time chart for explaining an example of processing operation of the multiplex transmission apparatus shown in FIG. 6 and 7, the same reference numerals as those in FIGS. 1 to 5 indicate the same or corresponding parts, and the description thereof is omitted.

  In addition, as shown in FIG. 6, the first comparative example includes a FIFO unit 8 (to be described later) and includes two memories in each storage unit 2 as shown in FIG. 6 with respect to the configuration of the multiplex transmission apparatus 100 according to the present embodiment. It is assumed that the multiplexing transmission device 101 has a buffer structure and does not include the frame phase detection unit 3.

  The FIFO unit 8 is disposed between the terminal interface unit 1 and the storage unit 2. The FIFO unit 8 temporarily holds terminal data output at terminal timing (timing given from the terminal device 200) by the terminal interface unit 1, and terminal data at device timing by a control device (not shown) outside the multiplexing transmission device 101. Is output to the storage unit 2.

  Further, the FIFO unit 8 synchronizes the phases between the frames formed by the terminal data from the plurality of terminal devices 200 and outputs them to each storage unit 2 of the cross-connect unit 10 by a control device (not shown). Adjusted.

  That is, the FIFO unit 8 performs the first write even when terminal data from the first terminal device 200a and the second terminal device 200b whose frame phases are asynchronous is input to the terminal interface unit 1. The timing and the second writing timing can be synchronized.

  When the first write timing and the second write timing are asynchronous, the write target memory and the read target memory overlap with the two memories of the storage unit 2. As a result, the cross-connect cannot function. For this reason, when the memory of the storage unit 2 is two, the FIFO unit 8 is an essential component.

  In addition, the multiplex transmission apparatus 101 controls the write timing designation and write timing control for the write control unit 4 and the read address designation and read timing control for the read control unit 5 by the device timing by a control device (not shown). Given by.

  Also, the multiplexing transmission apparatus 101 reads terminal data from the FIFO unit 8 at the same timing as the apparatus, and simultaneously writes it in each memory of the storage unit 2 of the cross-connect unit 10. The write control unit 4 and the read control unit 5 are controlled at device timing, and are alternately controlled so as to read from the memory B when writing to the memory A.

Next, problems of the multiplex transmission apparatus 101 according to the first comparative example will be described.
As shown in FIG. 7, the following problems occur when the write timing and the read timing for each memory in the storage unit 2 are asynchronous.

  Note that the description of the time chart for each item in FIG. 7 is the same concept as the description using FIG. 2 described above, and thus the description thereof is omitted here. Hereinafter, a time chart in the multiplexed data shown in FIG. 7 will be described.

  Here, the timing for switch-multiplexing the first terminal data from the first terminal device 200a and the second terminal data from the second terminal device 200b is, for example, the first readout timing and the second readout timing. Consider the case of the third frame.

  In this case, the second read buffer plane is the A plane, and the read data is the first frame data (d21) in the second terminal data. On the other hand, the first read buffer is the B side, and the data to be read is the second frame data (d12) in the first terminal data.

  Therefore, in the multiplex transmission apparatus 101, the data of the previous frame is input as the second terminal data and the data of the subsequent frame is input as the first terminal data in the same frame. That is, it can be seen that the multiplexed transmission apparatus 101 transmits multiplexed data in which the time relationship of terminal data from different terminal apparatuses 200 is shifted. In this way, transmitting multiplexed data with a shifted time relationship means that when the data of each frame is assembled and restored to the original data, the order in which the data is arranged changes, and there is a possibility that it cannot be restored to the original data. There is a problem that there is.

  As described above, in the multiplex transmission apparatus 100 according to this embodiment, even when the write timing and the read timing with respect to the memory of the storage unit 2 are asynchronous, the terminal data between the plurality of terminal apparatuses 200 is Multiplexed data with matching time relationships can be generated.

Further, while the write control unit 4 writes data to the two memories over two frames, the read control unit 5 can read data from the remaining memories, and the write timing and the read timing are asynchronous. Even in this case, the cross connect can function normally.
In particular, the multiplex transmission apparatus 100 does not need to synchronize the write timing to the memory of each storage unit 2 of the cross-connect unit 10, so that it is not necessary to provide the FIFO unit 8 in front of the cross-connect unit 10. Reduction of cost and mounting area can be realized.

[Appendix] The following appendices are further disclosed with respect to the embodiment.
(Supplementary Note 1) In a multiplexing transmission apparatus that multiplexes data in units of frames from a plurality of transmission paths and outputs the multiplexed data to a single transmission path, at least three memories corresponding to each transmission path of the plurality of transmission paths The at least three memories are arranged corresponding to each transmission path of the plurality of transmission paths, and a storage unit that sequentially stores data in units of frames that transmit each transmission path. A frame phase detector that detects the phase of each frame for data in units of frames that transmit the path, and a frame phase detector that detects the phase of each frame, and is detected by the frame phase detector. Based on the phase of each frame, a plurality of data constituting the one frame are counted in order from the top of each frame, and the count value is set as an address to correspond to each memory in the storage unit. The write control unit for sequentially writing the data of each frame, and the data at the predetermined address among the data written in a memory different from the memory being written in the storage unit. A multiplexed transmission comprising: a read control unit that reads data at a specified address in synchronization with a common memory; and a multiplexing unit that multiplexes a plurality of data read by the read control unit apparatus.

(Additional remark 2) Each said memory | storage part consists of three memories, The said read-out control part sets the read timing which reads the data from the memory of the reading object in each said memory | storage part to the writing object in each said memory | storage part. One frame after the earliest write timing among the write timings to be written to the memory to be written in each storage unit, which is the same or later than the latest write timing among the write timings to be written to the memory A multiplex transmission apparatus characterized in that the timing is the same as or earlier than the timing.

(Supplementary Note 3) Multiplexed transmission characterized in that the memory in which the data in the previous frame is written is the memory to be read when the read control unit synchronizes the write timing and the read timing. apparatus.

(Supplementary Note 4) When the read control unit and the read timing are asynchronous, the memory in which the data in the immediately previous frame with respect to the current write timing is written is the memory to be read. Multiplexing transmission device to be used.

(Supplementary Note 5) A write operation in which the three memories cyclically execute write, hold, and read operations, and the write control unit switches one of the three memories to a write target. A multiplexing transmission apparatus characterized in that a read timing for switching the one memory to a read target by the read control unit is a timing from one frame later to two frames before the read timing.

It is a block diagram which shows schematic structure in one Example of the multiplex transmission apparatus which concerns on this embodiment. 3 is a time chart for explaining an example of processing operation of the multiplex transmission apparatus shown in FIG. 1. 6 is a time chart for explaining another example of the processing operation of the multiplex transmission apparatus shown in FIG. 1. 6 is a time chart for explaining still another example of the processing operation of the multiplex transmission apparatus shown in FIG. 1. It is explanatory drawing for demonstrating the limit of the phase difference of the read timing with respect to write timing. It is a block diagram which shows schematic structure of the multiplexing transmission apparatus which concerns on the comparative example 1. It is a time chart for demonstrating an example of the processing operation of the multiplexing transmission apparatus shown in FIG.

Explanation of symbols

1, 1a, 1b Terminal interface unit 2, 2a, 2b Storage unit 3, 3a, 3b Frame phase detection unit 4, 4a, 4b Write control unit 5, 5a, 5b Read control unit 6 Multiplexing unit 7 Transmission path interface unit 8 FIFO section 10 Cross-connect section 21, 21a, 21b First memory 22, 22a, 22b Second memory 23, 23a, 23b Third memory 100, 101 Multiplex transmission apparatus 200 Terminal apparatus 200a First terminal apparatus 200b Second terminal device 300 Transmission path

Claims (4)

In a multiplexing transmission apparatus that multiplexes data in units of frames from a plurality of transmission paths and outputs the multiplexed data to a single transmission path,
A storage unit configured to store at least three memories corresponding to each of the plurality of transmission lines, and sequentially store data in units of frames transmitted through the transmission lines by the at least three memories;
A frame phase detector that is arranged corresponding to each transmission path of the plurality of transmission paths and detects the phase of each frame for data in units of frames that transmit the transmission paths;
Based on the phase of each frame arranged corresponding to each transmission path of the plurality of transmission paths and detected by the frame phase detection unit, the plurality of data constituting the one frame is sequentially ordered from the head of each frame. A write control unit for sequentially writing data of each frame corresponding to each memory of the storage unit, setting the count value as an address,
Reading out the data at the designated address by synchronizing the common memory in each storage unit among the data written in a memory different from the memory being written in the storage unit A control unit;
A multiplexing unit that multiplexes a plurality of data read by the read control unit;
Equipped with a,
The write control unit cyclically switches each memory to write data, and when the write timing and the read timing are synchronized, the memory holding the data in the immediately preceding frame is changed to the write target. Memory and
When the read control unit cyclically switches each of the memories to read data and the write timing and the read timing are synchronized, the memory in which the data in the immediately previous frame is written is the memory to be read. multiplex transmission apparatus according to claim to Rukoto.   In a multiplexing transmission apparatus that multiplexes data in units of frames from a plurality of transmission paths and outputs the multiplexed data to a single transmission path,
  A storage unit configured to store at least three memories corresponding to each of the plurality of transmission lines, and sequentially store data in units of frames transmitted through the transmission lines by the at least three memories;
  A frame phase detector that is arranged corresponding to each transmission path of the plurality of transmission paths and detects the phase of each frame for data in units of frames that transmit the transmission paths;
  Based on the phase of each frame arranged corresponding to each transmission path of the plurality of transmission paths and detected by the frame phase detection unit, the plurality of data constituting the one frame is sequentially ordered from the head of each frame. A write control unit for sequentially writing data of each frame corresponding to each memory of the storage unit, setting the count value as an address,
  Reading out the data at the designated address by synchronizing the common memory in each storage unit among the data written in a memory different from the memory being written in the storage unit A control unit;
  A multiplexing unit that multiplexes a plurality of data read by the read control unit;
  With
  The write control unit cyclically switches each memory to write data, and when the write timing and the read timing are asynchronous, the memory holding the data in the immediately previous frame with respect to the current hold timing is written. Memory to be included,
  The read control unit cyclically switches each memory to read data, and when the write timing and the read timing are asynchronous, reads the memory in which the data in the immediately previous frame with respect to the current write timing is written A multiplexing transmission apparatus characterized by being a target memory.   In the multiplex transmission apparatus according to claim 1 or 2,
  Each of the storage units consists of three memories,
  The readout control unit reads the data from the memory to be read in each storage unit at the same timing as the latest write timing among the write timings to write to the memory to be written in each storage unit. Or a multiplex timing characterized by being the same timing or a timing earlier than the timing one frame after the earliest writing timing among the writing timings to be written in the memory to be written in each storage unit. Transmission equipment.   In the multiplex transmission apparatus according to claim 2,
  The three memories are cyclically executed for write, hold and read operations,
  With respect to the write timing at which one of the three memories is switched to the write target by the write control unit, the read timing at which the read control unit switches the one memory to the read target is one frame later. A multiplex transmission apparatus characterized in that the timing is two frames before.

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