JP4977194B2 - Electronic component mounting method - Google Patents

Electronic component mounting method Download PDF

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JP4977194B2
JP4977194B2 JP2009282782A JP2009282782A JP4977194B2 JP 4977194 B2 JP4977194 B2 JP 4977194B2 JP 2009282782 A JP2009282782 A JP 2009282782A JP 2009282782 A JP2009282782 A JP 2009282782A JP 4977194 B2 JP4977194 B2 JP 4977194B2
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electronic component
substrate
circuit board
insulating resin
resin layer
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JP2010062589A (en
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一人 西田
英信 西川
義則 和田
博之 大谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/2908Plural core members being stacked
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    • H01L2224/29099Material
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    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/732Location after the connecting process
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/92Specific sequence of method steps
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    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a packaging process of electronic components which joins an electronic component to a board with good productivity and high reliability, without a resin sealing process or bump leveling process after the circuit board and electronic components are bonded. <P>SOLUTION: The process includes positioning of a bump and board electrode by placing insulating resins 6 and 6b containing an inorganic filler 6f between a bump 3 formed on an electrode 2 of an IC chip 1, and the board electrode, and curing the insulating resins, while pressing the board with a head 8 via the chip by applying the force of &ge;20 gf per a bump for correction of warpage of the chip and the board and crushing the bumps, to join the chip and board. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、電子回路用プリント基板(本明細書では、代表例として「基板」と称するが、この「基板」にはインタポーザや電子部品が装着される他の部品などの被装着体を意味する。)に電子部品例えばICチップや表面弾性波(SAW)デバイスなどを単体(ICチップの場合にはベアIC)状態で実装する回路基板への電子部品の実装方法に関するものである。   The present invention relates to a printed circuit board for electronic circuits (referred to herein as a “substrate” as a representative example, but this “substrate” means an object to be mounted such as an interposer or other component on which an electronic component is mounted. .) Is related to a method of mounting an electronic component on a circuit board in which an electronic component such as an IC chip or a surface acoustic wave (SAW) device is mounted as a single unit (a bare IC in the case of an IC chip).

今日、電子回路基板は、あらゆる製品に使用されるようになり、日増しにその性能が向上し、回路基板上で用いられる周波数も高くなっており、インピーダンスが低くなるフリップチップ実装は高周波を使用する電子機器に適した実装方法となっている。また、携帯機器の増加から、回路基板にICチップをパッケージではなく裸のまま搭載するフリップチップ実装が求められている。このために、ICチップそのまま単体で回路基板に搭載したときのICチップや、電子機器及びフラットパネルディスブレイへ実装したICチップには、一定数の不良品が混在している。また、上記フリップチップ以外にもCSP(Chip Size Package)、BGA(Ball Grid Array)等が用いられるようになってきている。   Today, electronic circuit boards are used in various products, their performance improves day by day, the frequency used on the circuit board is also increasing, and flip chip mounting where impedance is low uses high frequency It is a mounting method suitable for electronic equipment. Also, with the increase in portable devices, flip chip mounting is required for mounting an IC chip on a circuit board as it is, not as a package. For this reason, a certain number of defective products are mixed in an IC chip that is mounted on a circuit board as it is alone or mounted on an electronic device or a flat panel display. In addition to the flip chip, CSP (Chip Size Package), BGA (Ball Grid Array) and the like have been used.

従来の電子機器の回路基板へICチップを接合する方法(従来例1)としては特公平06−66355号公報等により開示されたものがある。これを図15に示す。図15に示すように、バンプ73を形成したICチップ71にAgペースト74を転写して回路基板76の電極75に接続したのちAgペースト74を硬化し、その後、封止材78をICチップ71と回路基板76の間に流し込む方法が一般的に知られている。   As a method for joining an IC chip to a circuit board of a conventional electronic device (conventional example 1), there is one disclosed in Japanese Patent Publication No. 06-66355. This is shown in FIG. As shown in FIG. 15, the Ag paste 74 is transferred to the IC chip 71 on which the bump 73 is formed and connected to the electrode 75 of the circuit board 76, and then the Ag paste 74 is cured, and then the sealing material 78 is attached to the IC chip 71. A method of pouring between the circuit board 76 and the circuit board 76 is generally known.

また、液晶ディスプレイにICチップを接合する方法(従来例2)として、図16に示される特公昭62−6652号公報のように、異方性導電フィルム80を使用するものであって、絶縁性樹脂83中に導電性微片82を加えて構成する異方性導電接着剤層81をセパレータ85から剥がして基板や液晶ディスプレイ84のガラスに塗布し、ICチップ86を熱圧着することによって、Auバンプ87の下以外のICチップ86の下面と基板84の間に上記異方性導電接着剤層81が介在している半導体チップの接続構造が、一般に知られている。   Further, as a method of joining an IC chip to a liquid crystal display (conventional example 2), an anisotropic conductive film 80 is used as shown in Japanese Patent Publication No. 62-6652 shown in FIG. An anisotropic conductive adhesive layer 81 formed by adding conductive fine pieces 82 in a resin 83 is peeled off from the separator 85 and applied to the glass of the substrate or the liquid crystal display 84, and the IC chip 86 is thermocompression bonded, thereby making the Au A semiconductor chip connection structure in which the anisotropic conductive adhesive layer 81 is interposed between the lower surface of the IC chip 86 other than under the bumps 87 and the substrate 84 is generally known.

従来例3としては、UV硬化樹脂を基板に塗布し、その上にICチップをマウントし加圧しながら、UV照射することにより両者の間の樹脂を硬化し、その収縮力により両者間のコンタクトを維持する方法が、知られている。   In Conventional Example 3, a UV curable resin is applied to a substrate, an IC chip is mounted on the substrate, and the resin between the two is cured by applying UV while applying pressure. Methods of maintaining are known.

このように、ICチップを接合するには、フラットパッケージのようなICチップをリードフレーム上にダイボンディングし、ICチップの電極とリードフレームをワイヤボンドしてつなぎ、樹脂成形してパッケージを形成した後に、クリームハンダを回路基板に印刷し、その上にフラットパッケージICを搭載しリフローするという工程を行うことにより、上記接合が行われていた。これらのSMT(Surface Mount Technology)といわれる工法では、ICをパッケージにする工程が長く、IC部品の生産に時間を要し、また、回路基板を小型化するのが困難であった。例えばICチップは、フラットパックに封止された状態では、ICチップの約4〜10倍程度の面積を必要とするため、小型化を妨げる要因となっていた。   Thus, in order to join the IC chips, an IC chip such as a flat package is die-bonded on the lead frame, the IC chip electrodes and the lead frame are connected by wire bonding, and resin molding is performed to form a package. Later, the bonding was performed by printing a cream solder on a circuit board, mounting a flat package IC thereon, and performing a reflow process. In these methods called SMT (Surface Mount Technology), the process of packaging the IC is long, and it takes time to produce the IC components, and it is difficult to reduce the size of the circuit board. For example, when the IC chip is sealed in a flat pack, it requires about 4 to 10 times the area of the IC chip, and this has been a factor that hinders downsizing.

これに対し、工程の短縮と小型軽量化の為にICチップを裸の状態でダイレクトに基板に搭載するフリップチップ工法が最近では用いられるようになってきた。このフリップチップ工法は、ICチップへのバンプ形成、バンプレベリング、Ag・Pdペースト転写、実装、検査、封止樹脂による封止、検査とを行うスタッド・バンプ・ボンディング(SBB)や、ICチップへのバンプ形成と基板へのUV硬化樹脂塗布とを並行して行い、その後、実装、樹脂のUV硬化、検査を行うUV樹脂接合のような多くの工法が開発されている。   On the other hand, a flip chip method in which an IC chip is directly mounted on a substrate in a bare state for shortening the process and reducing the size and weight has recently been used. This flip chip method is used for stud bump bonding (SBB) for bump formation to IC chip, bump leveling, transfer of Ag / Pd paste, mounting, inspection, sealing with sealing resin, and inspection. Many methods have been developed, such as the formation of bumps and the application of UV curable resin to a substrate in parallel, followed by mounting, UV curing of the resin, and UV resin bonding for inspection.

ところが、どの工法においてもICチップのバンプと基板の電極を接合するペーストの硬化や封止樹脂の塗布硬化に時間がかかり生産性が悪いという欠点を有していた。また、回路基板として、反り量を管理されたセラミックやガラスを用いる必要が有り、高価となる欠点を有していた。   However, each method has a drawback that it takes time to cure the paste for joining the bumps of the IC chip and the electrodes of the substrate and to apply and cure the sealing resin, resulting in poor productivity. Further, it is necessary to use a ceramic or glass whose warpage is controlled as a circuit board, which has a disadvantage of being expensive.

また、従来例1のような導電性ペーストを接合材に用いる工法においては、その転写量を安定化するために、ICチップのバンプはレベリングして、平坦化してから用いる必要があった。   Further, in the method of using the conductive paste as the bonding material as in Conventional Example 1, it is necessary to use the bumps of the IC chip after leveling and flattening in order to stabilize the transfer amount.

また、従来例2のような異方性導電接着剤による接合構造においては、回路基板の基材としてガラスを用いるものが開発されているが、導電性接着剤中の導電粒子を均一に分散することが困難であり、粒子の分散異常によりショートの原因になったり、導電性接着剤が高価であったり、バンプの高さをそろえる為に、ICチップの電極のバンプは電気メッキにより形成しなければならなかったりした。   Moreover, in the joining structure by anisotropic conductive adhesive like the prior art example 2, what uses glass as a base material of a circuit board is developed, but the conductive particle in a conductive adhesive is disperse | distributed uniformly. In order to cause a short circuit due to abnormal dispersion of particles, an expensive conductive adhesive, or to make the bump height uniform, bumps on the electrodes of the IC chip must be formed by electroplating. I had to.

また、従来例3のようにUV硬化樹脂を用いて接合する方法においては、バンプの高さバラツキを±1(μm)以下にしなければならず、また、樹脂基板(ガラスエポキシ基板)等の平面度の悪い基板には接合することができないといった問題があった。また、ハンダを用いる方法においても、接合後に基板とICチップの熱膨張収縮差を緩和する為に封止樹脂を流し込み硬化する必要があった。この樹脂封止の硬化には、2〜8時間の時間を必要とし、生産性がきわめて悪いといった問題があった。   Further, in the method of bonding using a UV curable resin as in Conventional Example 3, the bump height variation must be ± 1 (μm) or less, and a flat surface such as a resin substrate (glass epoxy substrate) or the like. There was a problem that it could not be bonded to a poor substrate. Also in the method using solder, it is necessary to pour and harden the sealing resin after bonding in order to alleviate the thermal expansion / contraction difference between the substrate and the IC chip. The curing of the resin sealing requires a time of 2 to 8 hours, and there is a problem that productivity is extremely poor.

従って、本発明の目的は、上記問題を解決することにあって、回路基板と電子部品を接合した後に、電子部品と基板の間に流し込む封止樹脂工程やバンプの高さを一定に揃えるバンプレベリング工程を必要とせず、電子部品を基板に生産性良くかつ高信頼性で接合する回路基板への電子部品の実装方法を提供することにある。   Accordingly, an object of the present invention is to solve the above-mentioned problem, and after bonding the circuit board and the electronic component, the sealing resin process that flows between the electronic component and the substrate and the bumps that make the bump height uniform It is an object of the present invention to provide a method of mounting an electronic component on a circuit board that does not require a leveling step and bonds the electronic component to the substrate with high productivity and high reliability.

上記目的を達成するために、本発明は以下のように構成する。   In order to achieve the above object, the present invention is configured as follows.

本発明の第1態様によれば、電子部品の電極にバンプを形成し、
縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法を提供する。
According to the first aspect of the present invention, bumps are formed on the electrodes of the electronic component,
While interposing an insulating resin layer of the insulation resin blended with inorganic filler solid or semi-solid, the electronic component mounted on the substrate to align the electrodes of the electrode and the circuit board of the electronic component ,
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The above inorganic filler to be blended in the insulating resin, Ri inorganic filler der was to have a plurality of peaks in the particle size distribution curve as a mixture of plural kinds of inorganic fillers having different average particle diameter,
The insulating resin layer provides a method for mounting an electronic component in which a portion in contact with the electronic component and the substrate has a smaller amount of the inorganic filler than other portions .

本発明の第2態様によれば、電子部品の電極にバンプを形成し、
縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーの平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーの平均粒径の2倍以上異なっており、
上記絶縁性樹脂層は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法を提供する。
According to the second aspect of the present invention, bumps are formed on the electrodes of the electronic component,
While interposing an insulating resin layer of the insulation resin blended with inorganic filler solid or semi-solid, the electronic component mounted on the substrate to align the electrodes of the electrode and the circuit board of the electronic component ,
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, The average particle size of one inorganic filler of at least two types of inorganic fillers is different from the average particle size of the other inorganic filler of at least two types of inorganic fillers by more than twice ,
The insulating resin layer provides a method for mounting an electronic component in which a portion in contact with the electronic component and the substrate has a smaller amount of the inorganic filler than other portions .

本発明の第3態様によれば、電子部品の電極にバンプを形成し、
縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーは3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーは3μm以下の平均粒径を持ち、
上記絶縁性樹脂層は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法を提供する。
According to the third aspect of the present invention, bumps are formed on the electrodes of the electronic component,
While interposing an insulating resin layer of the insulation resin blended with inorganic filler solid or semi-solid, the electronic component mounted on the substrate to align the electrodes of the electrode and the circuit board of the electronic component ,
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, One inorganic filler of at least two types of inorganic fillers has an average particle size exceeding 3 μm, and the other inorganic filler of the at least two types of inorganic fillers has an average particle size of 3 μm or less,
The insulating resin layer provides a method for mounting an electronic component in which a portion in contact with the electronic component and the substrate has a smaller amount of the inorganic filler than other portions .

本発明の第4態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法を提供する。
According to the fourth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended with the insulating resin is an inorganic filler in which a plurality of inorganic fillers having different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve,
The insulating resin layer is positioned at a portion that contacts either the electronic component or the substrate, and includes a first resin layer in which the inorganic filler is blended with the same insulating resin as the insulating resin, and the first resin layer. A second resin layer made of an insulating resin in contact with one resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the second resin layer on the opposite side of the first resin layer And a third resin layer made of an insulating resin having a smaller amount of the inorganic filler than the first resin layer, and the first resin layer and the third resin layer are each composed of the electronic component and Provided is a method for mounting an electronic component in contact with the substrate .

本発明の第5態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーの平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーの平均粒径の2倍以上異なっており、
上記絶縁性樹脂層は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法を提供する。
According to the fifth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, The average particle size of one inorganic filler of at least two types of inorganic fillers is different from the average particle size of the other inorganic filler of at least two types of inorganic fillers by more than twice,
The insulating resin layer is positioned at a portion that contacts either the electronic component or the substrate, and includes a first resin layer in which the inorganic filler is blended with the same insulating resin as the insulating resin, and the first resin layer. A second resin layer made of an insulating resin in contact with one resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the second resin layer on the opposite side of the first resin layer And a third resin layer made of an insulating resin having a smaller amount of the inorganic filler than the first resin layer, and the first resin layer and the third resin layer are each composed of the electronic component and Provided is a method for mounting an electronic component in contact with the substrate .

本発明の第6態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーは3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーは3μm以下の平均粒径を持ち、
上記絶縁性樹脂層は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法を提供する。
According to the sixth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, One inorganic filler of at least two types of inorganic fillers has an average particle size exceeding 3 μm, and the other inorganic filler of the at least two types of inorganic fillers has an average particle size of 3 μm or less,
The insulating resin layer is positioned at a portion that contacts either the electronic component or the substrate, and includes a first resin layer in which the inorganic filler is blended with the same insulating resin as the insulating resin, and the first resin layer. A second resin layer made of an insulating resin in contact with one resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the second resin layer on the opposite side of the first resin layer And a third resin layer made of an insulating resin having a smaller amount of the inorganic filler than the first resin layer, and the first resin layer and the third resin layer are each composed of the electronic component and Provided is a method for mounting an electronic component in contact with the substrate .

本発明の第態様によれば、上記電子部品に接触する上記第1又は第3樹脂層では、電子部品表面に用いられる膜素材に対して上記第2樹脂層よりも密着性を向上させる絶縁性樹脂を用いる一方、上記基板に接触する上記第1又は第3樹脂層では、基板表面の材料に対して上記第2樹脂層よりも密着性を向上させる絶縁性樹脂を用いるようにした第4〜6のいずれか1つ態様に記載の電子部品の実装方法を提供する。 According to the seventh aspect of the present invention, in the first or third resin layer that contacts the electronic component, the insulation that improves the adhesion to the film material used on the surface of the electronic component than the second resin layer. while the use of sexual resin, 4 which is adapted in the first or third resin layer in contact with the substrate, an insulating resin to improve adhesion than the second resin layer to the material of the substrate surface The mounting method of the electronic component as described in any one aspect of -6 is provided.

本発明の第態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法を提供する。
According to the eighth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended with the insulating resin is an inorganic filler in which a plurality of inorganic fillers having different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve,
The insulating resin layer has a small amount of the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. to provide the implementation method of the electronic component.

本発明の第態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーの平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーの平均粒径の2倍以上異なっており、
上記絶縁性樹脂層は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法を提供する。
According to the ninth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, The average particle size of one inorganic filler of at least two types of inorganic fillers is different from the average particle size of the other inorganic filler of at least two types of inorganic fillers by more than twice,
The insulating resin layer has a small amount of the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. to provide the implementation method of the electronic component.

本発明の第10態様によれば、電子部品の電極にバンプを形成し、
絶縁性樹脂に無機フィラーを配合した固体又は半固体の絶縁性樹脂層を介在させながら、上記電子部品の上記電極と回路基板の電極とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツールにより上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラーを混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラーは3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラーは3μm以下の平均粒径を持ち、
上記絶縁性樹脂層は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法。
According to the tenth aspect of the present invention , bumps are formed on the electrodes of the electronic component,
While interposing a solid or semi-solid insulating resin layer in which an inorganic filler is blended with an insulating resin, the electrode of the electronic component and the electrode of the circuit board are aligned, and the electronic component is mounted on the substrate.
Then, while heating from the electronic component side, while heating from the substrate side, or while heating from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board with a tool, While correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting an electrode and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic filler in which at least two kinds of inorganic fillers having a plurality of different average particle diameters are mixed to have a plurality of peaks in a particle size distribution curve, One inorganic filler of at least two types of inorganic fillers has an average particle size exceeding 3 μm, and the other inorganic filler of the at least two types of inorganic fillers has an average particle size of 3 μm or less,
The insulating resin layer has a small amount of the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. mounting method of electronic components.

本発明によれば、回路基板と電子部品を接合した後に、電子部品と基板の間に流し込む封止樹脂工程やバンプの高さを一定に揃えるバンプレベリング工程を必要とせず、電子部品を基板に生産性良くかつ高信頼性で接合する回路基板への電子部品の実装方法を提供することができる。   According to the present invention, after joining the circuit board and the electronic component, there is no need for a sealing resin process that flows between the electronic component and the board or a bump leveling process that keeps the bump height constant. It is possible to provide a method for mounting an electronic component on a circuit board to be bonded with high productivity and high reliability.

(A)、(B)、(C)、(D)、(E)、(F)、(G)はそれぞれ本発明の第1実施形態にかかる回路基板への電子部品例えばICチップの実装方法を示す説明図である。(A), (B), (C), (D), (E), (F), and (G) are each a method of mounting an electronic component, for example, an IC chip, on the circuit board according to the first embodiment of the present invention. It is explanatory drawing which shows. (A),(B)はそれぞれ第1実施形態にかかる回路基板への電子部品例えばICチップの実装方法において、熱硬化性樹脂中の無機フィラーが接合開始当初に熱硬化性樹脂中に入り込んできた尖っているバンプによりバンプ外側方向へ押し出される状態を示す説明図、及び、(C)はバンプと基板電極の間に無機フィラーが入り込まない状態を示す説明図である。(A) and (B) are the methods for mounting an electronic component such as an IC chip on the circuit board according to the first embodiment, respectively, and the inorganic filler in the thermosetting resin enters the thermosetting resin at the beginning of bonding. FIG. 5 is an explanatory view showing a state where the bump is sharply pushed out toward the outer side of the bump, and (C) is an explanatory view showing a state where an inorganic filler does not enter between the bump and the substrate electrode. (A)、(B)、(C)、(D)、(E)、(F)、(G)はそれぞれ本発明の第1実施形態における実装方法において、ICチップのワイヤボンダーを用いたバンプ形成工程を示す説明図である。(A), (B), (C), (D), (E), (F), (G) are bumps using a wire bonder of an IC chip in the mounting method according to the first embodiment of the present invention. It is explanatory drawing which shows a formation process. (A)、(B)、(C)はそれぞれ本発明の第1実施形態にかかる実装方法において、回路基板とICチップの接合工程を示す説明図である。(A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip, respectively, in the mounting method concerning 1st Embodiment of this invention. (A)、(B)、(C)はそれぞれ本発明の第1実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。(A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 1st Embodiment of this invention, respectively. (A)、(B)、(C)は、それぞれ、本発明の第3実施形態の実装方法において熱硬化性樹脂シートに代えて、熱硬化性接着剤を回路基板上に配置することを説明するための説明図である。(A), (B), and (C) explain that a thermosetting adhesive is disposed on a circuit board in place of the thermosetting resin sheet in the mounting method according to the third embodiment of the present invention. It is explanatory drawing for doing. (A)、(B)、(C)、(D)、(E),(F)は、それぞれ、本発明の第3実施形態の実装方法において、図6の変形例として、熱硬化性樹脂シートに代えて、熱硬化性接着剤を回路基板上に配置することを説明するための説明図である。(A), (B), (C), (D), (E), and (F) are thermosetting resins as a modification of FIG. 6 in the mounting method of the third embodiment of the present invention. It is explanatory drawing for demonstrating replacing with a sheet | seat and arrange | positioning a thermosetting adhesive agent on a circuit board. (A)、(B)、(C)はそれぞれ本発明の第5実施形態にかかる実装方法において、回路基板とICチップの接合工程を示す説明図である。(A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method concerning 5th Embodiment of this invention, respectively. (A)、(B)、(C)はそれぞれ本発明の第5実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。(A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 5th Embodiment of this invention, respectively. (A)、(B)、(C)、(D)はそれぞれ本発明の第6実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。(A), (B), (C), (D) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 6th Embodiment of this invention, respectively. (A)、(B)、(C)、(D)、(E)はそれぞれ本発明の第6実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。(A), (B), (C), (D), and (E) are explanatory views showing a bonding step of a circuit board and an IC chip in the mounting method according to the sixth embodiment of the present invention. (A)、(B)、(C)、(D)はそれぞれ本発明の第7実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。(A), (B), (C), (D) is explanatory drawing which shows the joining process of a circuit board and an IC chip, respectively, in the mounting method which is 7th Embodiment of this invention. は本発明の第7実施形態である実装方法において回路基板とICチップの接合工程を示す説明図である。These are explanatory drawings which show the joining process of a circuit board and an IC chip in the mounting method which is 7th Embodiment of this invention. (A),(B)はそれぞれ熱硬化性樹脂シートをICチップ1側に形成した第1実施形態の変形例を示す説明図、及び、熱硬化性接着剤をICチップ1側に形成した第1実施形態の変形例を示す説明図である。(A), (B) is explanatory drawing which shows the modification of 1st Embodiment which formed the thermosetting resin sheet in the IC chip 1 side, respectively, and the 1st which formed the thermosetting adhesive in the IC chip 1 side It is explanatory drawing which shows the modification of 1 embodiment. 従来の回路基板とのICチップの接合方法を示す断面図である。It is sectional drawing which shows the joining method of the IC chip with the conventional circuit board. (A)、(B)はそれぞれ従来の回路基板とのICチップの接合方法を示す説明図である。(A), (B) is explanatory drawing which shows the joining method of IC chip with the conventional circuit board, respectively. 上記第1実施形態において、80μmの外径のバンプの場合の抵抗値と荷重との関係のグラフの図である。In the said 1st Embodiment, it is a figure of the graph of the relationship between resistance value and a load in the case of a bump of an outer diameter of 80 micrometers. 上記第1実施形態において、80μm,40μmのそれぞれの外径のバンプと最低荷重との関係に基づき信頼性の高い領域を示したグラフの図である。In the said 1st Embodiment, it is a figure of the graph which showed the area | region with high reliability based on the relationship between the bump | vamp of each outer diameter of 80 micrometers and 40 micrometers, and the minimum load. 上記第3実施形態において、樹脂シートの加熱温度と反応率とのグラフの図である。In the said 3rd Embodiment, it is a figure of the graph of the heating temperature and reaction rate of a resin sheet. 上記第1実施形態で使用される電子部品搭載装置の斜視図である。It is a perspective view of the electronic component mounting apparatus used by the said 1st Embodiment. (A)、(B)、(C)、(D)はそれぞれ図20の電子部品搭載装置での部品側での位置認識動作を示す斜視図、部品の位置認識画像の図、基板側での位置認識動作を示す斜視図、基板の位置認識画像の図である。(A), (B), (C), and (D) are perspective views showing the position recognition operation on the component side in the electronic component mounting apparatus of FIG. It is a perspective view which shows position recognition operation | movement, and the figure of the position recognition image of a board | substrate. 上記第4実施形態で使用する超音波印加装置の概略図である。It is the schematic of the ultrasonic application apparatus used in the said 4th Embodiment. 上記第5実施形態で使用される貼り付け装置の概略図である。It is the schematic of the sticking apparatus used by the said 5th Embodiment. (A),(B)はそれぞれACF工法と上記実施形態の工法との比較説明のためのバンプ付近の拡大断面図である。(A), (B) is an expanded sectional view of the vicinity of a bump for comparison explanation of the ACF method and the method of the above embodiment, respectively. 本発明の第9実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により接合された接合状態の模式断面図である。It is a schematic cross section of the joining state joined by the mounting method and apparatus of the electronic component, for example, IC chip, to the circuit board concerning 9th Embodiment of this invention. 上記第9実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される樹脂シートの部分拡大模式断面図である。It is a partial expanded schematic cross section of the resin sheet used with the mounting method and apparatus of an electronic component, for example, IC chip, on the circuit board according to the ninth embodiment. 本発明の第13実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により接合された接合状態での絶縁性樹脂と無機フィラーの模式断面図である。It is a schematic cross section of an insulating resin and an inorganic filler in a joined state joined by a mounting method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a thirteenth embodiment of the present invention. (A),(B),(C),(D)はそれぞれ本発明の第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層の種々の例を示す電子部品ユニットの模式断面図である。(A), (B), (C), (D) are various types of insulating resin layers used by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the fourteenth embodiment of the present invention. It is a schematic cross section of the electronic component unit which shows the example. (A),(B),(C),(D)はそれぞれ本発明の第14実施形態の変形例にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層の種々の例の模式断面図である。(A), (B), (C), and (D) are insulating resins used by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a modification of the fourteenth embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of various examples of layers. 図29(A)に示された上記第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層を使用して接合された接合状態の模式断面図である。29A is a schematic cross-section of a joined state joined using an insulating resin layer used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIG. FIG. 図29(B)に示された上記第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層を使用して接合された接合状態の模式断面図である。A schematic cross-section of a joined state joined using an insulating resin layer used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIG. FIG. (A),(B)は図29(C),(D)にそれぞれ示された上記第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層を使用して接合された接合状態の模式断面図である。(A) and (B) are insulating resins used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIGS. 29 (C) and (D), respectively. It is a schematic cross section of the joining state joined using the layer. (A),(B),(C),(D),(E),(F)はそれぞれ上記第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層の無機フィラーの量と絶縁性樹脂層の厚み方向の位置との様々な関係のグラフを示す図である。(A), (B), (C), (D), (E), and (F) are respectively used by the mounting method and apparatus of an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment. It is a figure which shows the graph of the various relationship between the quantity of the inorganic filler of an insulating resin layer, and the position of the thickness direction of an insulating resin layer. 本発明の第15実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により使用される絶縁性樹脂層の製造工程の説明図である。It is explanatory drawing of the manufacturing process of the insulating resin layer used with the mounting method and apparatus of an electronic component, for example, IC chip, on the circuit board concerning 15th Embodiment of this invention. 図34の部分拡大図である。It is the elements on larger scale of FIG.

以下に、本発明にかかる実施の形態を図面に基づいて詳細に説明する。
(第1実施形態)
以下、本発明の第1実施形態にかかる電子部品例えばICチップの実装方法及びその装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置の一例としての回路基板へのICチップの実装方法及びその実装装置を図1(A)から図14を参照しながら説明する。
Embodiments according to the present invention will be described below in detail with reference to the drawings.
(First embodiment)
Hereinafter, an electronic component according to the first embodiment of the present invention, for example, an IC chip mounting method and apparatus, and an electronic component unit or module in which the IC chip is mounted on the substrate by the mounting method, for example, a circuit as an example of a semiconductor device A method of mounting an IC chip on a substrate and a mounting apparatus thereof will be described with reference to FIGS.

まず、本発明の第1実施形態にかかる回路基板へのICチップ実装方法を図1(A)〜図4(C)を用いて説明する。図1(A)の電子部品の一例であるICチップ1においてICチップ1のAlパッド電極2にワイヤボンディング装置により図3(A)〜図3(F)のごとき動作によりバンプ(突起電極)3を形成する。すなわち、図3(A)でホルダであるキャピラリー93から突出したワイヤ95の下端にボール96を形成し、図3(B)でワイヤ95を保持するキャピラリー93を下降させ、ボール96をICチップ1の電極2に接合して大略バンプ3の形状を形成し、図3(C)でワイヤ95を下方に送りつつキャピラリー93の上昇を開始し、図3(D)に示すような大略矩形のループ99にキャピラリー93を移動させて図3(E)に示すようにバンプ3の上部に湾曲部98を形成し、引きちぎることにより図3(F)に示すようなバンプ3を形成する。あるいは、図3(B)でワイヤ95をキャピラリー93でクランプして、キャピラリー93を上昇させて上方に引き上げることにより、金属線、例えば、金ワイヤ(金線)95(なお、金属線の例としては、スズ、アルミニウム、銅、又はこれらの金属に微量元素を含有させた合金のワイヤなどがあるが、以下の実施形態では代表例として金ワイヤ(金線)として記載する。)を引きちぎり、図3(G)のようなバンプ3の形状を形成するようにしてもよい。このように、ICチップ1の各電極2にバンプ3を形成した状態を図1(B)に示す。   First, an IC chip mounting method on a circuit board according to the first embodiment of the present invention will be described with reference to FIGS. 1 (A) to 4 (C). In the IC chip 1 which is an example of the electronic component of FIG. 1A, bumps (projection electrodes) 3 are formed on the Al pad electrode 2 of the IC chip 1 by the operation shown in FIGS. 3A to 3F by a wire bonding apparatus. Form. That is, the ball 96 is formed at the lower end of the wire 95 protruding from the capillary 93 which is the holder in FIG. 3A, the capillary 93 holding the wire 95 is lowered in FIG. 3 is joined to the electrode 2 to form the shape of the bump 3. In FIG. 3C, the wire 95 is sent downward, and the capillary 93 starts to rise, and a substantially rectangular loop as shown in FIG. The capillary 93 is moved to 99 to form the curved portion 98 on the upper portion of the bump 3 as shown in FIG. 3E, and the bump 3 as shown in FIG. 3F is formed by tearing. Alternatively, in FIG. 3B, the wire 95 is clamped by the capillary 93, and the capillary 93 is lifted and pulled upward, so that a metal wire, for example, a gold wire (gold wire) 95 (as an example of the metal wire) Is a wire of tin, aluminum, copper, or an alloy in which a trace element is contained in these metals, but in the following embodiment, it is described as a gold wire (gold wire) as a representative example. You may make it form the shape of bump 3 like FIG.3 (G). FIG. 1B shows a state in which the bump 3 is formed on each electrode 2 of the IC chip 1 as described above.

次に、図1(C)に示す回路基板4の電極5上に、図1(D)に示すように、ICチップ1の大きさより若干大きな寸法にてカットされた無機フィラー6fを配合した固体又は半固体の絶縁性樹脂層の一例としての絶縁性樹脂シート例えば熱硬化性樹脂シート6を配置し、例えば80〜120℃に熱せられた貼付けツール7により、例えば5〜10kgf/cm2程度の圧力で熱硬化性樹脂シート6をステージ109上の基板4の電極5上に貼り付ける。この後、無機フィラー6fを配合した固体又は半固体の熱硬化性樹脂シート6のツール7側に取り外し可能に配置されたセパレータ6aを剥がすことにより、基板4の準備工程が完了する。このセパレータ6aは、ツ−ル7に無機フィラー6fを配合した固体又は半固体の熱硬化性樹脂シート6が貼り付くのを防止するためのものである。ここで、図1(G)に図1(F)のG部分を部分的に拡大して示すように、熱硬化性樹脂シート6は、球状又は破砕シリカ、アルミナ等のセラミクスなどの無機系フィラー6fを絶縁性樹脂6mに分散させて混合し、これをドクターブレード法などにより平坦化し溶剤成分を気化させ固体化したものが好ましいとともに、後工程のリフロー工程での高温に耐えうる程度の耐熱性(例えば、240℃に10秒間耐えうる程度の耐熱性)を有することが好ましい。上記絶縁性樹脂は、例えば、絶縁性熱硬化性樹脂(例えば、エポキシ樹脂、フェノール樹脂、ポリイミドなど)、又は絶縁性熱可塑性樹脂(例えば、ポニフェニレンサルファイド(PPS)、ポリカーボネイト、変性ポリフェニレンオキサイド(PPO)など)、又は、絶縁性熱硬化性樹脂に絶縁性熱可塑性樹脂を混合したものなどが使用できるが、ここでは、代表例として絶縁性熱硬化性樹脂として説明を続ける。この熱硬化性樹脂6mのガラス転移点は一般に120〜200℃程度である。なお、熱可塑性樹脂のみを使用する場合には、最初は加熱して一旦軟化させたのち、加熱を停止して自然冷却させることにより硬化させる一方、絶縁性熱硬化性樹脂に熱可塑性樹脂を混合したものを使用する場合には、熱硬化性樹脂のほうが支配的に機能するため、熱硬化性樹脂のみと場合と同様に加熱することにより硬化する。 Next, as shown in FIG. 1 (D), a solid in which an inorganic filler 6f cut to a size slightly larger than the size of the IC chip 1 is blended on the electrode 5 of the circuit board 4 shown in FIG. 1 (C). Alternatively, an insulating resin sheet as an example of a semi-solid insulating resin layer, for example, a thermosetting resin sheet 6 is disposed, and for example, about 5 to 10 kgf / cm 2 by a pasting tool 7 heated to 80 to 120 ° C. The thermosetting resin sheet 6 is stuck on the electrode 5 of the substrate 4 on the stage 109 with pressure. Then, the preparatory process of the board | substrate 4 is completed by peeling the separator 6a arrange | positioned so that removal to the tool 7 side of the solid or semisolid thermosetting resin sheet 6 which mix | blended the inorganic filler 6f was carried out. The separator 6a is for preventing the solid or semi-solid thermosetting resin sheet 6 in which the inorganic filler 6f is blended with the tool 7 from sticking. Here, as shown in FIG. 1 (G) by partially enlarging the G portion of FIG. 1 (F), the thermosetting resin sheet 6 is made of an inorganic filler such as ceramics such as spherical or crushed silica or alumina. 6f is dispersed in an insulating resin 6m and mixed, and this is flattened by a doctor blade method or the like, and the solvent component is vaporized and solidified, and heat resistance sufficient to withstand high temperatures in the subsequent reflow process It is preferable to have (for example, heat resistance that can withstand 240 ° C. for 10 seconds). The insulating resin may be, for example, an insulating thermosetting resin (for example, epoxy resin, phenol resin, polyimide, etc.), or an insulating thermoplastic resin (for example, poniphenylene sulfide (PPS), polycarbonate, modified polyphenylene oxide (PPO). Etc.), or a mixture of an insulating thermosetting resin and an insulating thermoplastic resin can be used. Here, the description will continue as an insulating thermosetting resin as a representative example. The glass transition point of this thermosetting resin 6m is generally about 120 to 200 ° C. When using only thermoplastic resin, first heat and soften it first, then stop heating and let it cool naturally, while mixing insulating thermoplastic resin with thermoplastic resin In the case of using the above-mentioned one, the thermosetting resin functions more dominantly, so that it is cured by heating with only the thermosetting resin as in the case.

次に、図1(E)及び図1(F)に示すように、図20の電子部品搭載装置600において、部品保持部材601の先端の熱せられた接合ツール8により、上記前工程でバンプ3が電極2上に形成されたICチップ1をトレー602から吸着保持しつつ、該ICチップ1を、上記前工程で準備されかつステージ9上に載置された基板4に対して、ICチップ1の電極2が対応する基板4の電極5上に位置するように位置合わせしたのち、上記熱せられた接合ツール8によりICチップ1を基板4に押圧する。この位置合わせは、公知の位置認識動作を使用する。例えば、図21(C)に示すように、基板4に形成された位置認識マーク605又はリード若しくはランドパターンを、電子部品搭載装置600の基板認識用カメラ604で認識して、図21(D)に示すようにカメラ604で得られた画像606を基に、基板4のステージ9上での直交するXY方向のXY座標位置とXY座標の原点に対する回転位置とを認識して基板4の位置を認識する。一方、図21(A)に示すように、接合ツール8に吸着保持されたICチップ1の位置認識用マーク608又は回路パターンをICチップ用位置認識カメラ603で認識して、図21(B)に示すようにカメラ603で得られた画像607を基に、ICチップ1の上記XY方向のXY座標位置とXY座標の原点に対する回転位置とを認識してICチップ1の位置を認識する。そして、上記基板4とICチップ1との位置認識結果を基に、接合ツール8又はステージ9を移動させて、ICチップ1の電極2が対応する基板4の電極5上に位置するように位置合わせしたのち、上記熱せられた接合ツール8によりICチップ1を基板4に押圧する。   Next, as shown in FIGS. 1 (E) and 1 (F), in the electronic component mounting apparatus 600 of FIG. While the IC chip 1 formed on the electrode 2 is sucked and held from the tray 602, the IC chip 1 is fixed to the substrate 4 prepared in the previous step and placed on the stage 9. Then, the IC chip 1 is pressed against the substrate 4 by the heated bonding tool 8 after positioning so that the electrode 2 is positioned on the electrode 5 of the corresponding substrate 4. This alignment uses a known position recognition operation. For example, as shown in FIG. 21C, the position recognition mark 605 or the lead or land pattern formed on the substrate 4 is recognized by the substrate recognition camera 604 of the electronic component mounting apparatus 600, and FIG. As shown in FIG. 4, based on the image 606 obtained by the camera 604, the position of the substrate 4 is determined by recognizing the XY coordinate position of the substrate 4 in the XY direction perpendicular to the stage 9 and the rotation position of the XY coordinate with respect to the origin. recognize. On the other hand, as shown in FIG. 21A, the IC chip 1 position recognition camera 603 recognizes the position recognition mark 608 or the circuit pattern of the IC chip 1 attracted and held by the bonding tool 8, and FIG. As shown in FIG. 5, the position of the IC chip 1 is recognized by recognizing the XY coordinate position of the IC chip 1 in the XY direction and the rotation position with respect to the origin of the XY coordinate based on the image 607 obtained by the camera 603. Then, based on the result of position recognition between the substrate 4 and the IC chip 1, the bonding tool 8 or the stage 9 is moved so that the electrode 2 of the IC chip 1 is positioned on the electrode 5 of the corresponding substrate 4. After the alignment, the IC chip 1 is pressed against the substrate 4 by the heated joining tool 8.

このとき、バンプ3は、その頭部3aが、基板4の電極5上で図4(A)から図4(B)に示すように変形されながら押しつけられていく。このとき、図2(A)から図2(B)に示すように、熱硬化性樹脂6m中の無機フィラー6fは、接合開始当初に熱硬化性樹脂6m中に入り込んできた尖っているバンプ3により、バンプ3の外側方向へ押し出される。また、図2(C)に示すように、この外側方向への押し出し作用によりバンプ3と基板電極5の間に無機フィラー6fが入り込まないことにより、接続抵抗値を低下させる効果を発揮する。このとき、もし、バンプ3と基板電極5の間に無機フィラー6fが多少入り込んだとしても、バンプ3と基板電極5とが直接接触していることにより、全く問題はない。   At this time, the bump 3 is pressed while its head 3a is deformed on the electrode 5 of the substrate 4 as shown in FIGS. 4 (A) to 4 (B). At this time, as shown in FIG. 2 (A) to FIG. 2 (B), the inorganic filler 6f in the thermosetting resin 6m has sharp bumps 3 that have entered the thermosetting resin 6m at the beginning of bonding. As a result, the bump 3 is pushed outward. Further, as shown in FIG. 2 (C), the inorganic filler 6f does not enter between the bump 3 and the substrate electrode 5 due to the outward pushing action, thereby exhibiting an effect of reducing the connection resistance value. At this time, even if the inorganic filler 6f slightly enters between the bump 3 and the substrate electrode 5, there is no problem at all because the bump 3 and the substrate electrode 5 are in direct contact.

このとき、ICチップ1を介してバンプ3側に印加する荷重は、バンプ3の外径により異なるが、折れ曲がって重なり合うようになっているバンプ3の頭部3aが、必ず図4(C)のように変形する程度の荷重を加えることが必要である。この荷重は、最低で20(gf/バンプ1ケあたり)を必要とする。すなわち、図17には、80μmの外径のバンプの場合の抵抗値と荷重との関係のグラフより20(gf/バンプ1ケあたり)未満では抵抗値100mmΩ/バンプより大きくなって抵抗値が大きくなりすぎて実用上問題があるため、20(gf/バンプ1ケあたり)以上であることが好ましいことが示されている。また、図18には、80μm,40μmのそれぞれの外径のバンプと最低荷重との関係に基づき信頼性の高い領域を示したグラフである。これより、40μm以上の外径のバンプでは最低荷重は25(gf/バンプ1ケあたり)以上であることが好ましく、40μm未満の外径のバンプでは最低荷重は20(gf/バンプ1ケあたり)以上ぐらいが信頼性が高いことが推定される。なお、今後、リードの狭ピッチ化とともにバンプ外径が40μm未満と小さくなった場合、バンプの投影面積に応じて、その2乗に比例して荷重が減少する傾向があることが推定される。よって、ICチップ1を介してバンプ3側に印加する最低荷重は、最低で20(gf/バンプ1ケあたり)を必要とするのが好ましい。上記ICチップ1を介してバンプ3側に印加する荷重の上限は、ICチップ1、バンプ3、回路基板4などが損傷しない程度とする。場合によって、その最大荷重は150(gf/バンプ1ケあたり)を越えることもある。なお、図中、参照符号6sは、熱硬化性樹脂シート6のうち接合ツール8の熱により溶融した溶融中の熱硬化性樹脂6mが溶融後に熱硬化された樹脂である。   At this time, the load applied to the bump 3 side via the IC chip 1 varies depending on the outer diameter of the bump 3, but the head 3 a of the bump 3 that is bent and overlapped is surely shown in FIG. Thus, it is necessary to apply a load that deforms. This load requires a minimum of 20 (gf / per bump). That is, FIG. 17 shows that the resistance value is larger than the bump value of 100 mmΩ / bump and less than 20 mm (per gf / bump) from the graph of the relationship between the resistance value and the load in the case of the 80 μm outer diameter bump. It is shown that it is preferable to be 20 (gf / per bump) or more because it becomes too much to be practically problematic. FIG. 18 is a graph showing a highly reliable area based on the relationship between the bumps having outer diameters of 80 μm and 40 μm and the minimum load. Accordingly, the minimum load is preferably 25 (gf / per bump) for bumps with an outer diameter of 40 μm or more, and the minimum load is 20 (gf / per bump) for bumps with an outer diameter of less than 40 μm. It is estimated that the above is highly reliable. In the future, when the outer diameter of the bump is reduced to less than 40 μm as the lead pitch is reduced, it is estimated that the load tends to decrease in proportion to the square of the bump according to the projected area of the bump. Therefore, it is preferable that the minimum load applied to the bump 3 side via the IC chip 1 requires 20 (gf / per bump). The upper limit of the load applied to the bump 3 side via the IC chip 1 is set such that the IC chip 1, the bump 3, the circuit board 4 and the like are not damaged. In some cases, the maximum load may exceed 150 (gf / per bump). In the figure, reference numeral 6s is a resin in which the thermosetting resin 6m being melted by the heat of the joining tool 8 in the thermosetting resin sheet 6 is thermally cured after being melted.

なお、セラミックヒータ又はパルスヒータなどの内蔵ヒータ8aにより熱せられた接合ツール8により、上記前工程でバンプ3が電極2上に形成されたICチップ1を、上記前工程で準備された基板4に対してICチップ1の電極2が対応する基板4の電極5上に図1(E)に示すように位置するように位置合わせする位置合わせ工程と、位置合わせしたのち図1(F)に示すように押圧接合する工程とを、1つの位置合わせ兼押圧接合装置、例えば、図1(E)の位置合わせ兼押圧接合装置で行うようにしてもよい。しかしながら、別々の装置、例えば、多数の基板を連続生産する場合において位置合わせ作業と押圧接合作業とを同時的に行うことにより生産性を向上させるため、上記位置合わせ工程は図5(B)の位置合わせ装置で行い、上記押圧接合工程は図5(C)の接合装置で行うようにしてもよい。なお、図5(C)では、生産性を向上させるため、2つの接合装置8を示しており、1枚の回路基板4の2個所を同時に押圧接合できるようにしている。   The IC chip 1 in which the bumps 3 are formed on the electrodes 2 in the previous process is applied to the substrate 4 prepared in the previous process by the bonding tool 8 heated by the built-in heater 8a such as a ceramic heater or a pulse heater. On the other hand, an alignment process for aligning the electrode 2 of the IC chip 1 so as to be positioned on the electrode 5 of the corresponding substrate 4 as shown in FIG. 1E, and after the alignment, as shown in FIG. The step of pressing and bonding in this manner may be performed by one positioning and pressing bonding apparatus, for example, the positioning and pressing bonding apparatus of FIG. However, in order to improve productivity by performing the alignment operation and the press bonding operation simultaneously in separate apparatuses, for example, when a large number of substrates are continuously produced, the alignment process is performed as shown in FIG. You may make it perform with the aligning apparatus and perform the said press joining process with the joining apparatus of FIG.5 (C). In FIG. 5C, two bonding apparatuses 8 are shown to improve productivity, and two locations of one circuit board 4 can be pressed and bonded simultaneously.

回路基板4は、セラミック多層基板、FPC、ガラス布積層エポキシ基板(ガラエポ基板)やガラス布積層ポリイミド樹脂基板、アラミド不織布エポキシ基板(例えば、松下電器産業株式会社製の登録商標アリブ「ALIVH」として販売されている樹脂多層基板)などが用いられる。これらの基板4は、熱履歴や、裁断、加工により反りやうねりを生じており、必ずしも完全な平面ではない。そこで、図5(A)及び図5(B)に示すように、例えば約10μm以下に調整されるように平行度がそれぞれ管理された接合ツール8とステージ9とにより、接合ツール8側からステージ9側に向けて熱と荷重をICチップ1を通じて回路基板4に局所的に印加することにより、その印加された部分の回路基板4の反りが矯正せしめられる。また、ICチップ1は、アクティブ面の中心を凹として反っているが、これを接合時に1バンプあたり20gf以上の強い荷重で加圧することで、基板4とICチップ1の両方の反りやうねりを矯正することができる。このICチップ1の反りは、ICチップ1を形成するとき、Siに薄膜を形成する際に生じる内部応力により発生するものである。バンプの変形量は10〜25μm程度であり、この程度の基板が当初から持っている内層銅箔から表面に現れるうねりの影響にバンプ3の変形でそれぞれのバンプ3が順応することで許容できるようになる。   The circuit board 4 is sold as a ceramic multilayer board, FPC, glass cloth laminated epoxy board (glass epoxy board), glass cloth laminated polyimide resin board, aramid non-woven cloth epoxy board (for example, registered trade mark “ALIVH” manufactured by Matsushita Electric Industrial Co., Ltd.) Resin multilayer substrate) or the like is used. These substrates 4 are warped and wavy due to thermal history, cutting, and processing, and are not necessarily a perfect plane. Therefore, as shown in FIGS. 5 (A) and 5 (B), for example, a stage from the joining tool 8 side by the joining tool 8 and the stage 9 in which the parallelism is respectively controlled so as to be adjusted to about 10 μm or less. By applying heat and a load locally to the circuit board 4 through the IC chip 1 toward the 9 side, the warp of the applied part of the circuit board 4 can be corrected. In addition, the IC chip 1 is warped with the center of the active surface being concave, but by pressing it with a strong load of 20 gf or more per bump at the time of bonding, warping and undulation of both the substrate 4 and the IC chip 1 are caused. It can be corrected. The warpage of the IC chip 1 is caused by internal stress generated when a thin film is formed on Si when the IC chip 1 is formed. The deformation amount of the bump is about 10 to 25 μm, and it can be allowed by adapting each bump 3 to the influence of the undulation appearing on the surface from the inner layer copper foil that the substrate of this level has from the beginning by adapting the deformation of the bump 3. become.

こうして回路基板4の反りが矯正された状態で、例えば140〜230℃の熱がICチップ1と回路基板4の間の熱硬化性樹脂シート6に例えば数秒〜20秒程度印加され、この熱硬化性樹脂シート6が硬化される。このとき、最初は熱硬化性樹脂シート6を構成する熱硬化性樹脂6mが流れてICチップ1のエッジまで封止する。また、樹脂であるため、加熱されたとき、当初は自然に軟化するため、このようにエッジまで流れるような流動性が生じる。熱硬化性樹脂6mの体積はICチップ1と回路基板4との間の空間の体積より大きくすることにより、この空間からはみ出すように流れ出て、封止効果を奏することができる。この後、加熱されたツール8が上昇することにより、加熱源がなくなるためICチップ1と熱硬化性樹脂シート6の温度が急激に低下して、熱硬化性樹脂シート6は流動性を失い、図1(F)及び図4(C)に示すように、ICチップ1は硬化した熱硬化性樹脂6sにより回路基板4上に固定される。また、回路基板4側をステージ9のヒータ9aなどにより加熱しておくと、接合ツール8の温度をより低く設定することができる。   In a state where the warping of the circuit board 4 is corrected in this way, for example, heat of 140 to 230 ° C. is applied to the thermosetting resin sheet 6 between the IC chip 1 and the circuit board 4 for about several seconds to 20 seconds, for example. The functional resin sheet 6 is cured. At this time, first, the thermosetting resin 6m constituting the thermosetting resin sheet 6 flows and seals to the edge of the IC chip 1. In addition, since it is a resin, it is naturally softened when heated, so that fluidity flows to the edge in this way. By making the volume of the thermosetting resin 6 m larger than the volume of the space between the IC chip 1 and the circuit board 4, the thermosetting resin 6 m flows out of the space and can provide a sealing effect. Thereafter, when the heated tool 8 rises, the heating source disappears, so that the temperature of the IC chip 1 and the thermosetting resin sheet 6 rapidly decreases, and the thermosetting resin sheet 6 loses fluidity, As shown in FIGS. 1 (F) and 4 (C), the IC chip 1 is fixed on the circuit board 4 by a cured thermosetting resin 6s. Moreover, if the circuit board 4 side is heated by the heater 9a of the stage 9, etc., the temperature of the joining tool 8 can be set lower.

(第2実施形態)
次に、本発明の第2実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を説明する。
(Second Embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a second embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. explain.

この第2実施形態においては、第1実施形態において、熱硬化性樹脂シート6に配合する無機フィラー6fの混合割合を上記絶縁性熱硬化性樹脂例えば絶縁性熱硬化性エポキシ樹脂6mの5〜90wt%として、一層好適なものとしたものである。5wt%未満では無機フィラー6fを混合する意味がない一方、90wt%を超えると、接着力が極度に低下するとともに、シート化するのが困難になるため好ましくない。一例として、高い信頼性を維持させる観点から、樹脂基板では20〜40wt%、セラミック基板では40〜70wt%が好ましいとともに、ガラエポ基板では20wt%程度でもシート封止剤の線膨張係数をかなり低下させることができ、樹脂基板において効果がある。なお、体積%では、wt%のおよそ半分の割合、又はエポキシ樹脂が1に対してシリカ約2の比重の割合とする。通常では、熱硬化性樹脂6mのシート化する際の製造上の条件と基板4の弾性率、及び最終的には信頼性試験結果により、この無機フィラー6fの混合割合が決定される。   In this 2nd Embodiment, the mixing ratio of the inorganic filler 6f mix | blended with the thermosetting resin sheet 6 in 1st Embodiment is 5-90 wt of the said insulating thermosetting resin, for example, the insulating thermosetting epoxy resin 6m. % Is more suitable. If it is less than 5 wt%, there is no point in mixing the inorganic filler 6f. On the other hand, if it exceeds 90 wt%, the adhesive strength is extremely lowered and it becomes difficult to form a sheet, which is not preferable. As an example, from the viewpoint of maintaining high reliability, 20 to 40 wt% is preferable for a resin substrate and 40 to 70 wt% for a ceramic substrate, and the linear expansion coefficient of the sheet sealant is considerably reduced even when the glass epoxy substrate is about 20 wt%. This is effective in the resin substrate. In volume%, the ratio is approximately half of wt%, or the ratio of specific gravity of about 2 silica to 1 epoxy resin. Usually, the mixing ratio of the inorganic filler 6f is determined by the manufacturing conditions when the thermosetting resin 6m is formed, the elastic modulus of the substrate 4, and finally the reliability test result.

上記したような混合割合の無機フィラー6fを熱硬化性樹脂シート6に配合することにより、熱硬化性樹脂シート6の熱硬化性樹脂6mの弾性率を増加させることができ、熱膨張係数を低下させてICチップ1と基板4の接合信頼性を向上させることができる。また、基板4の材料に合わせて、熱硬化性樹脂6mの材料常数、すなわち弾性率、線膨張係数を最適なものとするように、無機フィラー6fの混合割合を決定することができる。なお、無機フィラー6fの混合割合が挿花するにつれて、弾性率は大きくなるが、線膨張係数は小さくなる傾向がある。   By blending the inorganic filler 6f in the mixing ratio as described above into the thermosetting resin sheet 6, the elastic modulus of the thermosetting resin 6m of the thermosetting resin sheet 6 can be increased, and the thermal expansion coefficient is lowered. Thus, the bonding reliability between the IC chip 1 and the substrate 4 can be improved. Further, the mixing ratio of the inorganic filler 6f can be determined so as to optimize the material constant of the thermosetting resin 6m, that is, the elastic modulus and the linear expansion coefficient, in accordance with the material of the substrate 4. Note that, as the mixing ratio of the inorganic filler 6f increases, the elastic modulus increases, but the linear expansion coefficient tends to decrease.

第1実施形態及び第2実施形態においては、液体ではなく固体の熱硬化性樹脂シート6を使用するため取り扱いやすいとともに、液体成分が無いため高分子で形成することができ、ガラス転移点の高いものを形成しやすいといった利点がある。   In the first embodiment and the second embodiment, it is easy to handle because it uses a solid thermosetting resin sheet 6 instead of a liquid, and since it has no liquid component, it can be formed of a polymer and has a high glass transition point. There is an advantage that it is easy to form things.

なお、図1(A)から図1(G)及び図2(A)〜図2(C)、後述する図6及び図7においては、絶縁性樹脂層の一例としての熱硬化性樹脂シート6又は熱硬化性接着剤6bを回路基板4側に形成することについて説明したが、これに限定されるものではなく、図14(A)又は図14(B)に示すように、ICチップ1側に形成したのち、基板4に接合するようにしてもよい。この場合、特に、熱硬化性樹脂シート6の場合には、熱硬化性樹脂シート6の回路基板側に取り外し可能に配置されたセパレータ6aとともに、ステージ201上のゴムなどの弾性体117に吸着ノズルなどの保持部材200により保持されたICチップ1を押し付けて、バンプ3の形状に沿って熱硬化性樹脂シート6がICチップ1に貼り付けられるようにしてもよい。   In addition, in FIGS. 1 (A) to 1 (G) and FIGS. 2 (A) to 2 (C) and FIGS. 6 and 7 described later, a thermosetting resin sheet 6 as an example of an insulating resin layer. Alternatively, the thermosetting adhesive 6b is formed on the circuit board 4 side, but the present invention is not limited to this, and as shown in FIG. 14A or FIG. 14B, the IC chip 1 side is formed. After being formed, it may be bonded to the substrate 4. In this case, particularly in the case of the thermosetting resin sheet 6, the suction nozzle is attached to the elastic body 117 such as rubber on the stage 201 together with the separator 6 a detachably disposed on the circuit board side of the thermosetting resin sheet 6. Alternatively, the IC chip 1 held by the holding member 200 may be pressed so that the thermosetting resin sheet 6 is attached to the IC chip 1 along the shape of the bump 3.

(第3実施形態)
次に、本発明の第3実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図6(A)〜図6(C)及び図7(A)〜図7(F)を用いて説明する。
(Third embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a third embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 6A to 6C and FIGS. 7A to 7F.

この第3実施形態では、第1実施形態において、熱硬化性樹脂シート6を基板4に貼り付ける代わりに、図6(A)及び図7(A),(D)に示すように、絶縁性樹脂層の一例としての液体状の熱硬化性接着剤6bを回路基板4上に、ディスペンス502などによる塗布、又は印刷、又は転写するようにしたのち、半固体状態、いわゆるBステージ状態、まで固化し。その後、上記第1又は第2実施形態と同様に、上記ICチップ1を上記基板4に搭載する。   In this third embodiment, instead of attaching the thermosetting resin sheet 6 to the substrate 4 in the first embodiment, as shown in FIGS. 6 (A) and 7 (A), (D), an insulating property is provided. A liquid thermosetting adhesive 6b as an example of a resin layer is applied, printed, or transferred onto the circuit board 4 with a dispense 502 or the like, and then solidified to a semi-solid state, so-called B-stage state. Yes. Thereafter, the IC chip 1 is mounted on the substrate 4 as in the first or second embodiment.

詳しくは、図6(A)に示すように、液体状の熱硬化性接着剤6bを回路基板4上に、図7(A)に示すような空気圧で吐出量が制御されかつ基板平面上で直交する2方向に移動可能なディスペンス502などによる塗布、又は印刷、又は転写する。次いで、図6(B)のごとくヒータ78aを内蔵したツール78により、熱と圧力を印加して均一化しながら、図6(C)のように半固体状態、いわゆるBステージ状態、まで固化する。   Specifically, as shown in FIG. 6A, the liquid thermosetting adhesive 6b is applied onto the circuit board 4, the discharge amount is controlled by air pressure as shown in FIG. Application, printing, or transfer is performed by a dispense 502 that is movable in two orthogonal directions. Next, as shown in FIG. 6 (B), a tool 78 incorporating a heater 78a is applied to heat and pressure to make it uniform and solidify to a semi-solid state, so-called B stage state, as shown in FIG. 6 (C).

又は、液体状の熱硬化性接着剤6bの粘性が低い場合には、図7(A)に示すように、ディスペンサ502で基板4上の所定位置に液体の熱硬化性接着剤6bを塗布したのち、熱硬化性接着剤6bの粘性が低いために自然に基板上で広がり、図7(B)に示すような状態となる。その後、図7(C)に示すように、コンベヤのような搬送装置505により上記基板4を炉503内に入れて、炉503のヒータ504により上記塗布された絶縁性樹脂の液体状熱硬化性接着剤6bを硬化させることにより、半固体化、すなわち、いわゆるBステージ状態まで固化する。   Alternatively, when the viscosity of the liquid thermosetting adhesive 6b is low, the liquid thermosetting adhesive 6b is applied to a predetermined position on the substrate 4 with a dispenser 502 as shown in FIG. After that, since the thermosetting adhesive 6b has a low viscosity, it naturally spreads on the substrate, resulting in a state as shown in FIG. Thereafter, as shown in FIG. 7C, the substrate 4 is placed in a furnace 503 by a transfer device 505 such as a conveyor, and the liquid thermosetting of the insulating resin applied by the heater 504 of the furnace 503 is performed. By curing the adhesive 6b, it is solidified to a semi-solid state, that is, a so-called B-stage state.

一方、液体状の熱硬化性接着剤6bの粘性が高い場合には、図7(D)に示すように、ディスペンサ502で基板4上の所定位置に液体の熱硬化性接着剤6bを塗布したのち、熱硬化性接着剤6bの粘性が高いために自然に基板上で広がらないため、図7(E),(F)に示すように、スキージ506で平らに延ばす。その後、図7(C)に示すように、コンベヤのような搬送装置505により上記基板4を炉503内に入れて、炉503のヒータ504により上記塗布された絶縁性樹脂の液体状熱硬化性接着剤6bを硬化させることにより、半固体化、すなわち、いわゆるBステージ状態、まで固化する。   On the other hand, when the viscosity of the liquid thermosetting adhesive 6b is high, the liquid thermosetting adhesive 6b is applied to a predetermined position on the substrate 4 with the dispenser 502 as shown in FIG. After that, since the thermosetting adhesive 6b has a high viscosity and does not naturally spread on the substrate, it is flattened with a squeegee 506 as shown in FIGS. Thereafter, as shown in FIG. 7C, the substrate 4 is placed in a furnace 503 by a transfer device 505 such as a conveyor, and the liquid thermosetting of the insulating resin applied by the heater 504 of the furnace 503 is performed. By curing the adhesive 6b, it is solidified to a semi-solid state, that is, a so-called B-stage state.

このように熱硬化性接着剤6bを半固体化するときには、熱硬化性接着剤6b中の熱硬化性樹脂の特性により差はあるものの、該熱硬化性樹脂のガラス転移点の30〜80%の温度である80〜130℃で押圧する。通常は、熱硬化性樹脂のガラス転移点の30%程度の温度で行う。このように熱硬化性樹脂のガラス転移点の30〜80%とする理由は、図19の樹脂シートの加熱温度と反応率とのグラフより、80〜130℃の範囲内ならば、まだ、後工程でさらに反応する範囲を充分に残すことができる。言い換えれば、80〜130℃の範囲内の温度ならば、時間にもよるが、絶縁性樹脂たとえばエポキシ樹脂の反応率が10〜50%程度に抑制できるので、後工程のICチップ圧着時の接合に問題が生じない。すなわち、ICチップ圧着時に押圧するときに所定の押圧量を確保することができ、押し切れなくなるという問題を生じにくい。なお、反応を抑えて溶剤分のみを気化させることにより、半固体化することもある。   Thus, when making thermosetting adhesive 6b semi-solid, although there is a difference depending on the characteristics of the thermosetting resin in thermosetting adhesive 6b, 30 to 80% of the glass transition point of the thermosetting resin. It presses at 80-130 degreeC which is the temperature of this. Usually, it is performed at a temperature of about 30% of the glass transition point of the thermosetting resin. As described above, the reason why the glass transition point of the thermosetting resin is 30 to 80% is that if it is within the range of 80 to 130 ° C. from the graph of the heating temperature and the reaction rate of the resin sheet in FIG. A sufficient range for further reaction can be left in the process. In other words, if the temperature is in the range of 80 to 130 ° C., depending on the time, the reaction rate of the insulating resin such as epoxy resin can be suppressed to about 10 to 50%. There is no problem. That is, a predetermined pressing amount can be ensured when pressing at the time of IC chip press-bonding, and it is difficult to cause a problem that the pressing cannot be performed. In addition, semi-solid may be obtained by suppressing the reaction and vaporizing only the solvent.

上記熱硬化性接着剤6bを上記したように半固体化させたのち、基板4に複数のICチップ1を装着する場合には、基板4の複数のICチップ1を装着する複数の個所において上記熱硬化性接着剤6bの上記半固体化工程を前段取り工程とし予め行っておき、このように前段取りされた基板4を供給して供給された基板4に複数のICチップ1を上記複数の個所に接合することでより生産性が高くなる。この後の工程では、熱硬化性接着剤6bを使用する場合でも、基本的には上記した第1又は第2実施形態の熱硬化性樹脂シート6を用いる工程と同一の工程を行う。上記半固定化工程を加えることで、液体の熱硬化性接着剤6bを熱硬化性樹脂シート6と同様に使用することができ、固体ゆえに取り扱いやすいとともに、液体成分が無いため高分子で形成することができ、ガラス転移点の高いものを形成しやすいといった利点がある。このように流動性のある熱硬化性接着剤6bを使用する場合には、固体の熱硬化性樹脂シート6を使用する場合と比較して、基板4の任意の位置に任意の大きさに塗布、印刷、又は転写することができる利点をも合わせて持つ。   In the case where a plurality of IC chips 1 are mounted on the substrate 4 after the thermosetting adhesive 6b is semi-solidified as described above, the plurality of IC chips 1 on the substrate 4 are mounted at a plurality of locations. The semi-solidification step of the thermosetting adhesive 6b is performed in advance as a pre-setup step, and the plurality of IC chips 1 are placed on the substrate 4 supplied by supplying the substrate 4 thus pre-set. Productivity becomes higher by joining to the place. In the subsequent steps, even when the thermosetting adhesive 6b is used, the same steps as those using the thermosetting resin sheet 6 of the first or second embodiment described above are basically performed. By adding the semi-fixing step, the liquid thermosetting adhesive 6b can be used in the same manner as the thermosetting resin sheet 6, and since it is solid, it is easy to handle and has no liquid component, so it is formed of a polymer. And has an advantage of easily forming a glass transition point. When the fluid thermosetting adhesive 6b is used as described above, it is applied to an arbitrary position on the substrate 4 in an arbitrary size as compared with the case where the solid thermosetting resin sheet 6 is used. It also has the advantage that it can be printed or transferred.

(第4実施形態)
次に、本発明の第4実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図22を用いて説明する。第4実施形態が第1実施形態と異なる点は、ICチップ1を基板4に接合するとき、荷重に加えて超音波も印加して、バンプ3をレベリングせずに、必要に応じて20gf以下の荷重で押圧して、バンプ形成時の引き千切りにより生じた上記バンプ3の先端のネック(ヒゲ)部分の倒れによる隣接バンプ又は電極とのショートを防止するようにバンプ先端を整えたのち、ICチップ1と位置合わせしてICチップ1を基板4に搭載して、金属バンプ3を基板側の電極表面の金属と超音波併用熱圧着することである。ICチップ1を基板4に接合する状態は、先の実施形態での図2及び図6などと同様である。
(Fourth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fourth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIG. The fourth embodiment differs from the first embodiment in that when the IC chip 1 is bonded to the substrate 4, an ultrasonic wave is also applied in addition to the load, and the bump 3 is not leveled and is 20 gf or less as required. The bump tip is adjusted so as to prevent a short-circuit with an adjacent bump or electrode due to a fall of the neck (whisker) portion of the tip of the bump 3 caused by the shredding at the time of bump formation. The IC chip 1 is mounted on the substrate 4 in alignment with the chip 1, and the metal bump 3 is thermocompression-bonded with the metal on the electrode surface on the substrate side in combination with ultrasonic waves. The state in which the IC chip 1 is bonded to the substrate 4 is the same as in FIGS. 2 and 6 in the previous embodiment.

上記超音波を印加して上記金バンプと上記基板の上記電極とを金属接合するとき、上記電子部品の上記上面側から加熱しながら、又は、上記基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱するようにしてもよい。   When applying the ultrasonic wave to metal-bond the gold bump and the electrode of the substrate, heating from the upper surface side of the electronic component, heating from the substrate side, or the electronic component Heating may be performed from both the substrate side and the substrate side.

この第4実施形態では、絶縁性熱硬化性樹脂6mに無機フィラー6fを配合した固体の熱硬化性樹脂シート6又は液体の熱硬化性接着剤6bを上記したように半固体化させたものを基板4に貼り付け、又は熱硬化性樹脂を含む熱硬化性接着剤6bを基板4に塗布し半固体化させたのち、回路基板4の電極5と電子部品1の電極2にワイヤボンディングと同様に図3(A)〜図3(F)のごとき動作により金線95の先端に電気スパークによりボール96を形成し、このボール96をキャピラリー93により基板電極5に超音波熱圧着して形成されたバンプ3を、レベリングせずに、ICチップ1と位置合わせしてICチップ1を基板4に搭載する。ここで、上記「液体の熱硬化性接着剤6bを上記したように半固体化させたもの」とは、第3実施形態で説明したような液体の熱硬化性接着剤6bを半分固体化したものであり、Bステージ化したものとほぼ同じものである。これを使用することにより、シート封止材料やACF(異方性導電膜)よりも安価な材料が利用できる。このとき、図22に示す超音波印加装置620において、内蔵ヒータ622により予め加熱された接合ツール628により、該接合ツール628に吸着されたICチップ1の上面からエアシリンダ625による荷重と、ピエゾ素子のような超音波発生素子623により発生させられて超音波ホーン624を介して印加される超音波とを作用させて金バンプ3のネック部分の倒れを防止するように先端を整えつつ金バンプ3と基板側の金メッキとを金属接合する。次に、ICチップ1の上面又は、及び基板側から加熱しながら、上記ICチップ1を上記回路基板4に1バンプあたり20gf以上の加圧力により押圧し、上記基板4の反りの矯正とバンプ3を押しつぶしながら、上記ICチップ1と上記回路基板4の間に介在する上記熱硬化性樹脂シート6又は熱硬化性接着剤6bを上記熱により硬化して、上記ICチップ1と上記回路基板4を接合して両電極2,5を電気的に接続する。なお、超音波印加装置620による上記金属接合時に、上記ICチップ1の上記上面側から、又は、上記基板側から、又は、上記ICチップ1側と上記基板側の両方から加熱するようにしてもよい。すなわち、具体的には、内蔵ヒータ622により上記ICチップ1の上記上面側から加熱したり、又は、上記基板側から回路基板4側をステージ9のヒータ9aにより加熱したり、又は、内蔵ヒータ622とステージ9のヒータ9aとにより上記ICチップ1側と上記基板側の両方から加熱するようにしてもよい。   In the fourth embodiment, a solid thermosetting resin sheet 6 in which an insulating filler 6f is blended with an insulating thermosetting resin 6m or a liquid thermosetting adhesive 6b semi-solidified as described above is used. After bonding to the substrate 4 or applying a thermosetting adhesive 6b containing a thermosetting resin to the substrate 4 to make it semi-solid, the electrode 5 of the circuit substrate 4 and the electrode 2 of the electronic component 1 are similar to the wire bonding. 3A to 3F, a ball 96 is formed by electric spark at the tip of the gold wire 95, and this ball 96 is formed on the substrate electrode 5 by ultrasonic thermocompression bonding using a capillary 93. The bump 3 is aligned with the IC chip 1 without being leveled, and the IC chip 1 is mounted on the substrate 4. Here, “the liquid thermosetting adhesive 6b semi-solidified as described above” means that the liquid thermosetting adhesive 6b as described in the third embodiment is semi-solidified. It is almost the same as the B stage. By using this, a material cheaper than the sheet sealing material or ACF (anisotropic conductive film) can be used. At this time, in the ultrasonic wave application device 620 shown in FIG. 22, the load by the air cylinder 625 from the upper surface of the IC chip 1 attracted to the bonding tool 628 by the bonding tool 628 preliminarily heated by the built-in heater 622, and the piezoelectric element The gold bump 3 while adjusting the tip so as to prevent the neck portion of the gold bump 3 from collapsing by applying the ultrasonic wave generated by the ultrasonic generator 623 and applied via the ultrasonic horn 624. And the gold plating on the substrate side are metal-bonded. Next, while heating from the upper surface of the IC chip 1 or the substrate side, the IC chip 1 is pressed against the circuit board 4 with a pressing force of 20 gf or more per bump to correct the warp of the board 4 and the bump 3. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured by the heat to crush the IC chip 1 and the circuit board 4. It joins and both the electrodes 2 and 5 are electrically connected. In addition, at the time of the metal joining by the ultrasonic wave application device 620, heating may be performed from the upper surface side of the IC chip 1, from the substrate side, or from both the IC chip 1 side and the substrate side. Good. Specifically, the built-in heater 622 heats the IC chip 1 from the upper surface side, the circuit board 4 side from the substrate side is heated by the heater 9a of the stage 9, or the built-in heater 622. The heater 9a of the stage 9 may be heated from both the IC chip 1 side and the substrate side.

なお、1バンプあたり20gf以上の加圧力を必要とする理由は、このように超音波を用いた接合でも摩擦熱が生じにくくなるので、接合できなくなるためである。金と金とを接合するような場合においても、ある一定加重でバンプを押しつけて、そこに超音波を印加することにより摩擦熱が生じて金属同士が接合される。したがって、この場合にもバンプを押圧する程度の一定荷重すなわち1バンプあたり20gf以上の加圧力が必要となる。加圧力の一例としては、1バンプあたり50gf以上とする。   The reason why a pressing force of 20 gf or more per bump is required is that the frictional heat is hardly generated even in the joining using ultrasonic waves as described above, so that the joining cannot be performed. Even in the case of bonding gold and gold, the bumps are pressed with a certain load, and ultrasonic waves are applied thereto to generate frictional heat, thereby bonding the metals together. Therefore, in this case as well, a constant load enough to press the bumps, that is, a pressing force of 20 gf or more per bump is required. As an example of the applied pressure, it is set to 50 gf or more per bump.

上記第4実施形態によれば、金属バンプ3と基板4の金属メッキが金属拡散接合されるので、よりバンプ部分での強度を持たせたいような場合や、接続抵抗値をさらに低くしたいような場合に好適である。   According to the fourth embodiment, since the metal plating of the metal bump 3 and the substrate 4 is metal diffusion bonded, when it is desired to increase the strength at the bump portion or when it is desired to further reduce the connection resistance value. It is suitable for.

(第5実施形態)
次に、本発明の第5実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図8(A)〜図8(C)及び図9(A)〜図9(C)を用いて説明する。第5実施形態は、第1実施形態とは封止工程を省略することができる点が異なる。
(Fifth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fifth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 8A to 8C and FIGS. 9A to 9C. The fifth embodiment is different from the first embodiment in that the sealing step can be omitted.

上記したようにICチップ1上の電極2に突起電極(バンプ)3を形成しておき、回路基板4には、図8(B),図8(C),図9(A)及び図23に示すように、ICチップ1の複数の電極2の内端縁を結んだ大略矩形の外形寸法OLより小さい形状寸法の矩形のシート状の熱硬化性樹脂シート6又は熱硬化性接着剤6bを回路基板4の電極5を結んだ中心部分に貼り付け又は塗布しておく。このとき、シート状の熱硬化性樹脂シート6又は熱硬化性接着剤6bの厚みは、その体積がICチップ1と基板4との隙間より大きくなるようにする。また、図23の貼り付け装置640により、巻き戻しロール644から巻き戻されて巻き付けロール643に巻き取られる矩形のシート状の熱硬化性樹脂シート656を、その切り目657が予め入れられた部分で、上下のカッター641により、ICチップ1の複数の電極2の内端縁を結んだ大略矩形の外形寸法OLより小さい形状寸法に切断する。切断された矩形のシート状の熱硬化性樹脂シート6は、内蔵ヒータ646で予め加熱された貼り付けヘッド642で吸着保持されて、上記回路基板4の電極5を結んだ中心部分に貼り付けされる。次に、バンプ3と回路基板4の電極5を位置合わせし、図8(A)及び図9(B)に示すように、ヒータ8aにより加熱された接合ツール8によりICチップ1を回路基板4に加圧押圧して、基板4の反りの矯正を同時に行いながら、ICチップ1と回路基板4の間に介在する熱硬化性樹脂シート6又は熱硬化性接着剤6bを硬化する。このとき、熱硬化性樹脂シート6又は熱硬化性接着剤6bは、接合ツール8からICチップ1を介して加えられた熱により上記したように軟化し、図9(C)のごとく貼り付けられた又は塗布された位置より加圧されて外側へ向かって流れ出る。この流れ出た熱硬化性樹脂シート6又は熱硬化性接着剤6bが封止材料(アンダーフィル)となり、バンプ3と電極5との接合の信頼性を著しく向上する。また、ある一定時間がたつと、上記熱硬化性樹脂シート6又は熱硬化性接着剤6bでは徐々に硬化が進行し、最終的には硬化した樹脂6sによりICチップ1と回路基板4を接合することになる。ICチップ1を押圧している接合ツール8を上昇することで、ICチップ1と回路基板4の電極5の接合が完了する。厳密に言えば、熱硬化の場合には、熱硬化性樹脂の反応は加熱している間に進み、接合ツール8が上昇するとともに流動性はほとんど無くなる。上記したような方法によると、接合前では熱硬化性樹脂シート6又は熱硬化性接着剤6bが電極5を覆っていないので、接合する際にバンプ3が電極5に直接接触し、電極5の下に熱硬化性樹脂シート6又は熱硬化性接着剤6bが入り込まず、バンプ3と電極5との間での接続抵抗値を低くすることができる。また、回路基板側を加熱しておくと、接合ヘッド8の温度をより低くすることができる。この方法を上記第3実施形態に適用すると金バンプと回路基板の金電極(例えば、銅やタングステンにニッケル、金メッキしたもの)との接合がより容易に行える。   As described above, the protruding electrodes (bumps) 3 are formed on the electrodes 2 on the IC chip 1, and the circuit board 4 is formed on the circuit board 4 as shown in FIGS. 8B, 8 C, 9 A, and 23. As shown in the figure, a rectangular sheet-like thermosetting resin sheet 6 or a thermosetting adhesive 6b having a shape dimension smaller than a substantially rectangular outer dimension OL connecting the inner edges of the plurality of electrodes 2 of the IC chip 1 is provided. Affixed or applied to the central portion of the circuit board 4 where the electrodes 5 are connected. At this time, the thickness of the sheet-like thermosetting resin sheet 6 or the thermosetting adhesive 6 b is set so that the volume thereof is larger than the gap between the IC chip 1 and the substrate 4. Further, a rectangular sheet-like thermosetting resin sheet 656 that is unwound from the rewinding roll 644 and wound around the winding roll 643 by the affixing device 640 in FIG. The upper and lower cutters 641 are cut into shapes smaller than the generally rectangular outer dimensions OL connecting the inner edges of the plurality of electrodes 2 of the IC chip 1. The cut rectangular sheet-like thermosetting resin sheet 6 is sucked and held by a pasting head 642 preheated by a built-in heater 646 and pasted to the central portion of the circuit board 4 connecting the electrodes 5. The Next, the bump 3 and the electrode 5 of the circuit board 4 are aligned, and as shown in FIGS. 8A and 9B, the IC chip 1 is attached to the circuit board 4 by the bonding tool 8 heated by the heater 8a. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured while simultaneously correcting the warp of the board 4 by pressing and pressing. At this time, the thermosetting resin sheet 6 or the thermosetting adhesive 6b is softened as described above by the heat applied from the joining tool 8 through the IC chip 1, and is attached as shown in FIG. 9C. Pressurized from the position where it is applied or applied and flows outward. The flowing thermosetting resin sheet 6 or thermosetting adhesive 6b becomes a sealing material (underfill), and the bonding reliability between the bumps 3 and the electrodes 5 is remarkably improved. Further, after a certain period of time, the thermosetting resin sheet 6 or the thermosetting adhesive 6b gradually cures, and finally the IC chip 1 and the circuit board 4 are joined by the cured resin 6s. It will be. By raising the joining tool 8 pressing the IC chip 1, the joining of the IC chip 1 and the electrode 5 of the circuit board 4 is completed. Strictly speaking, in the case of thermosetting, the reaction of the thermosetting resin proceeds while heating, and the joining tool 8 rises and the fluidity is almost lost. According to the method as described above, since the thermosetting resin sheet 6 or the thermosetting adhesive 6b does not cover the electrode 5 before joining, the bump 3 directly contacts the electrode 5 when joining, and the electrode 5 The thermosetting resin sheet 6 or the thermosetting adhesive 6b does not enter below, and the connection resistance value between the bump 3 and the electrode 5 can be lowered. Further, if the circuit board side is heated, the temperature of the bonding head 8 can be further lowered. When this method is applied to the third embodiment, it is possible to more easily join the gold bump and the gold electrode of the circuit board (for example, nickel or gold plated copper or tungsten).

(第6実施形態)
次に、第6実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図10〜図11を用いて説明する。第6実施形態においては、第1実施形態と異なる点は、バンプ103を回路基板4の電極5にズレて実装された場合においても、信頼性の高い接合を達成することもできる点である。
(Sixth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a sixth embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. The sixth embodiment is different from the first embodiment in that highly reliable bonding can be achieved even when the bump 103 is mounted on the electrode 5 of the circuit board 4 in a shifted manner.

第6実施形態においては、図10(A)に示すように、バンプ3をICチップ1上に形成する際にワイヤボンディングと同様に金線95を電気スパークにより金ボール96を形成する。次に、電気スパークするときの時間でボールの大きさを調整しつつ、95aで示す直径Φd−Bumpのボール96aを形成し、
このように形成された直径Φd−Bumpのボール96aを、電気スパークを発生させるための時間又は電圧のパラメータを制御して、チャムファー角θcが100°以下のキャピラリー193の93aで示すチャムファー直径φDが金ボール直径d−Bumpの1/2から3/4となるようにボール96aを成形し、
図10(C)に示すようにキャピラリー93の金ボールと接する部分に平らな部位93bを設けて図10(D)に示すようなバンプ3を形成するのではなく、図10(A)に示すようにキャピラリー193の金ボール96aと接する部分に平らな部位を設けない先端部位193aを有する先端形状としたキャピラリー193で、ICチップ1の電極2に、超音波熱圧着により、図10(B)に示すようなバンプ103を形成する。上記先端形状のキャピラリー193を用いることで、図10(B)のbのような先端が大略円錐状のバンプ103をICチップ1の電極2に形成することができる。上記方法で形成した先端が大略円錐状のバンプ103を回路基板4の電極5に図11(C)のごとくズレて実装された場合においても、バンプ103がその先端が大略円錐形であるため、バンプ103の外径の半分までのズレである場合は、バンプ103の一部が必ず基板4の電極5と接触することができる。
In the sixth embodiment, as shown in FIG. 10A, when the bump 3 is formed on the IC chip 1, a gold ball 96 is formed by electric sparking with a gold wire 95 similarly to wire bonding. Next, while adjusting the size of the ball according to the time when electric sparking is performed, a ball 96a having a diameter Φd-Bump indicated by 95a is formed,
The ball 96a having the diameter Φd-Bump thus formed is controlled by the time or voltage parameter for generating an electric spark, and the Chamfer diameter indicated by 93a of the capillary 193 having a Chamfer angle θc of 100 ° or less. The ball 96a is formed so that φD is 1/2 to 3/4 of the gold ball diameter d-Bump.
As shown in FIG. 10C, the flat portion 93b is not provided in the portion of the capillary 93 that contacts the gold ball to form the bump 3 as shown in FIG. As shown in FIG. 10B, the capillary 193 has a tip-shaped capillary 193 having a tip portion 193a that does not provide a flat portion at the portion in contact with the gold ball 96a. A bump 103 as shown in FIG. By using the tip-shaped capillary 193, the bump 103 having a generally conical tip as shown in FIG. 10B can be formed on the electrode 2 of the IC chip 1. Even when the bump 103 having a generally conical tip formed by the above method is mounted on the electrode 5 of the circuit board 4 as shown in FIG. 11C, the bump 103 has a generally conical tip. If the deviation is up to half of the outer diameter of the bump 103, a part of the bump 103 can always be in contact with the electrode 5 of the substrate 4.

これに対して、図11(D)に示すようなバンプ3では、バンプ3を回路基板4の電極5に図11(C)のごとく寸法Zだけズレて実装された場合には、図11(E)に示すように、幅寸法dのいわゆる台座3gの一部が電極5に接触するが、部分的にしか接触せず、接触状態が不安定な接合となる。このような不安定な接合状態のままでは、このような基板4を冷熱衝撃試験やリフローにかけた場合には、上記不安定な接合状態の接合がオープンすなわち接合不良となってしまう可能性があった。これに対して、上記第6実施形態では、図11(C)のごとく先端が大略円錐状のバンプ103が回路基板4の電極5に対して寸法Zだけズレて実装された場合においても、バンプ103が円錐形であるため、バンプ103の外径の半分までのズレである場合は、バンプ103の一部が必ず基板4の電極5と接触することができ、冷熱衝撃試験やリフローにかけた場合でも接合不良となることが防止できる。   On the other hand, in the bump 3 as shown in FIG. 11D, when the bump 3 is mounted on the electrode 5 of the circuit board 4 by being shifted by the dimension Z as shown in FIG. As shown in E), a part of the so-called pedestal 3g having the width dimension d is in contact with the electrode 5, but it is only in partial contact, resulting in an unstable contact state. In such an unstable bonding state, when the substrate 4 is subjected to a thermal shock test or reflow, the bonding in the unstable bonding state may be open, that is, a bonding failure. It was. On the other hand, in the sixth embodiment, even when the bump 103 having a substantially conical tip at the tip is displaced by the dimension Z with respect to the electrode 5 of the circuit board 4 as shown in FIG. Since 103 is a conical shape, when the deviation is up to half of the outer diameter of the bump 103, a part of the bump 103 can always come into contact with the electrode 5 of the substrate 4 and is subjected to a thermal shock test or reflow However, it is possible to prevent poor bonding.

(第7実施形態)
次に、第7実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図12〜図13を用いて説明する。この第7実施形態では、第1実施形態において、回路基板4へのICチップ1の接合したのちの熱硬化性樹脂の硬化時にICチップ1と回路基板4の応力を緩和することができるようにしたものである。
(Seventh embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a seventh embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. In the seventh embodiment, in the first embodiment, the stress of the IC chip 1 and the circuit board 4 can be relieved when the thermosetting resin is cured after the IC chip 1 is bonded to the circuit board 4. It is a thing.

第7実施形態においては、絶縁性熱硬化性樹脂6mに無機フィラー6fを配合した固体又は半固体の熱硬化性樹脂シート6又は熱硬化性接着剤6bを介在させながら、ICチップ1の電極2に上記ワイヤボンディングにより形成されたバンプ3を、レベリングせずに、回路基板4の電極5と位置合わせする。例えば230℃程度の一定温度に加熱されたツール8によりICチップ1をその裏面から加熱しながら、上記ICチップ1を上記回路基板4に1バンプあたりセラミック基板の場合には圧力P1=80gf以上の加圧力により押圧し、上記基板4の反りの矯正を行いながら、上記ICチップ1と上記回路基板4の間に介在する上記熱硬化性樹脂シート6又は熱硬化性接着剤6bを上記熱により硬化する。次に、一定時間t1後、すなわち、全体時間を例えば20秒とすれば、材料の反応率により変わるが、その1/4とか1/2の5秒〜10秒後、言い換えれば、材料の反応率が90%に達する前に、上記圧力P1より低い圧力P2まで下げて熱硬化性接着剤6bの硬化時の応力を緩和し、上記ICチップ1と上記回路基板4を接合して両電極2,5を電気的に接続する。好適には、バンプが変形していくためには最低限20gf程度は必要であるため、すなわち、バンプの変形及び順応に必要な圧力を得るとともに、余分な樹脂をICチップ1と基板4との間から押し出すため、上記圧力P1は20gf/バンプ以上である一方、バンプの変形等の前に樹脂内部に偏在した硬化歪み除去するため、圧力P2は20gf/バンプ未満とすることにより、より信頼性が向上する。その理由は詳しくは以下のとおりである。すなわち、図12(C)に示すように、熱硬化性樹脂シート6又は熱硬化性接着剤6b中の熱硬化性樹脂の応力分布は圧着時にICチップ1と基板4側とで大きくなっている。 In the seventh embodiment, the electrode 2 of the IC chip 1 is interposed with a solid or semi-solid thermosetting resin sheet 6 or a thermosetting adhesive 6b in which an insulating filler 6m is mixed with an inorganic filler 6f. The bumps 3 formed by wire bonding are aligned with the electrodes 5 of the circuit board 4 without leveling. For example, while heating the IC chip 1 from the back surface thereof with the tool 8 heated to a constant temperature of about 230 ° C., the pressure of P1 = 80 gf or more in the case where the IC chip 1 is a ceramic substrate per bump on the circuit board 4. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured by the heat while pressing with pressure to correct the warp of the board 4. To do. Next, after a certain time t 1 , that is, if the total time is 20 seconds, for example, it changes depending on the reaction rate of the material, but after 1/4 or 1/2 of 5 seconds to 10 seconds, in other words, Before the reaction rate reaches 90%, the pressure is lowered to a pressure P2 lower than the pressure P1 to relieve the stress at the time of curing the thermosetting adhesive 6b, and the IC chip 1 and the circuit board 4 are joined to both electrodes. 2 and 5 are electrically connected. Preferably, a minimum of about 20 gf is necessary for the deformation of the bump, that is, a pressure necessary for the deformation and adaptation of the bump is obtained, and excess resin is used between the IC chip 1 and the substrate 4. Since the pressure P1 is 20 gf / bump or more because it is pushed out from the space, the pressure P2 is less than 20 gf / bump in order to remove the hardened strain that is unevenly distributed inside the resin before the deformation of the bump. Will improve. The reason is as follows in detail. That is, as shown in FIG. 12C, the stress distribution of the thermosetting resin in the thermosetting resin sheet 6 or the thermosetting adhesive 6b is large between the IC chip 1 and the substrate 4 side at the time of pressure bonding. .

このままでは、信頼性試験や通常の長期使用で繰り返し疲労が与えられると、ICチップ1又は基板4側で熱硬化性樹脂シート6又は熱硬化性接着剤6b中の熱硬化性樹脂が応力に耐えきれずに剥離することがある。このような状態になると、ICチップ1と回路基板4の接着力が十分でなくなり、接合部がオープンすることになる。そこで、図13のように、より高い圧力P1とより低い圧力P2との2段階の圧力プロファイルを用いることにより、熱硬化性接着剤6bの硬化時に上記圧力P1より低い圧力P2まで下げることができて、図12(D)のごとく、圧力P2のときに樹脂内部に偏在した硬化歪み除去してICチップ1と回路基板4の応力を緩和する(言い換えれば、応力の集中度合いを減らす)ことができ、その後、上記圧力P1まで上げることにより、バンプの変形及び順応に必要な圧力を得るとともに、余分な樹脂をICチップ1と基板4との間から押し出すことができて、信頼性が向上する。   In this state, when fatigue is repeatedly given in a reliability test or normal long-term use, the thermosetting resin in the thermosetting resin sheet 6 or the thermosetting adhesive 6b on the IC chip 1 or the substrate 4 side can withstand stress. May peel without being broken. In such a state, the adhesive force between the IC chip 1 and the circuit board 4 becomes insufficient, and the joint is opened. Therefore, as shown in FIG. 13, by using a two-stage pressure profile of a higher pressure P1 and a lower pressure P2, the pressure can be lowered to a pressure P2 lower than the pressure P1 when the thermosetting adhesive 6b is cured. Thus, as shown in FIG. 12D, the stress of the IC chip 1 and the circuit board 4 can be relieved (in other words, the degree of concentration of stress is reduced) by removing the curing strain unevenly distributed inside the resin at the pressure P2. Then, by raising the pressure to the pressure P1, the pressure required for the deformation and adaptation of the bumps can be obtained, and excess resin can be pushed out from between the IC chip 1 and the substrate 4 to improve the reliability. .

なお、上記「ICチップ1と回路基板4の接着力」とは、ICチップ1と基板4をひっつける力のことを意味する。これは、接着剤による接着力と、接着剤を硬化したときの硬化収縮力と、Z方向の収縮力(例えば180℃に熱せられている接着剤が常温に戻るときに収縮するときの収縮力)のこれら3つの力によって、IC1と基板4とは接合されている。   The “adhesive force between the IC chip 1 and the circuit board 4” means a force that holds the IC chip 1 and the board 4 together. This is because the adhesive force by the adhesive, the curing shrinkage force when the adhesive is cured, and the shrinkage force in the Z direction (for example, the shrinkage force when the adhesive heated to 180 ° C. shrinks to normal temperature) The IC 1 and the substrate 4 are bonded by these three forces.

(第8実施形態)
次に、第8実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図12〜図13を用いて説明する。この第8実施形態では、上記各実施形態において、上記絶縁性樹脂6mに配合する上記無機フィラー6fの平均粒径が3μm以上であるようにしたものである。ただし、上記無機フィラー6fの最大平均粒径は、ICチップ1と基板4との接合後の隙間寸法を超えない大きさとする。
(Eighth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the eighth embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. In the eighth embodiment, in each of the above embodiments, the average particle diameter of the inorganic filler 6f blended in the insulating resin 6m is 3 μm or more. However, the maximum average particle diameter of the inorganic filler 6f is set to a size that does not exceed the gap size after the IC chip 1 and the substrate 4 are joined.

もし、無機フィラー6fを絶縁性樹脂6mに配合するときに、平均粒径が3μm未満の細かな粒子を無機フィラー6fとして用いると、それらの粒子の表面積自体が全体として大きくなり、平均粒径が3μm未満の細かな粒子である無機フィラー6fの周りに吸湿することがあり、ICチップ1と基板4との接合において好ましくない。   If the inorganic filler 6f is blended with the insulating resin 6m and fine particles having an average particle size of less than 3 μm are used as the inorganic filler 6f, the surface area of the particles itself increases as a whole, and the average particle size becomes smaller. Moisture absorption may occur around the inorganic filler 6f which is fine particles of less than 3 μm, which is not preferable in joining the IC chip 1 and the substrate 4.

従って、同じ重量の無機フィラー6fを配合する場合には、平均粒径が3μm以上の大きな無機フィラー6fを用いることで、無機フィラー6fの周りにおける吸湿量を減らしめることができ、耐湿性を向上させることが可能となる。また、一般に、平均粒径(言い換えれば平均粒度)の大きな無機フィラーの方が安価であるため、コスト的にも好ましい。また、図24(A)に示すように、ICチップ1と基板4との接合においてACF(Anisotropic Conductive Film:異方性導電膜)598を使用する工法では、ACF598中の導電粒子599をバンプ3と基板電極5との間に必ず挟む必要があるが、本発明の上記実施形態では導電粒子が無いためそのような必要は無く、図24(B)に示すようにバンプ3を基板電極5で押しつぶしながら圧着するので、この圧着のときにバンプ3と基板電極4との間の絶縁性樹脂層6,6bとともに無機フィラー6fもバンプ3と基板電極4と間から抜け出ることになり、基板電極4とバンプ3の間に不要な無機フィラー6fが挟まることにより導電性を阻害することがほとんど無いという特徴に基づき、3μm以上の大きな平均粒径の無機フィラー6fを使用することができる。   Therefore, when blending the same weight of the inorganic filler 6f, the amount of moisture absorption around the inorganic filler 6f can be reduced by using a large inorganic filler 6f having an average particle diameter of 3 μm or more, and the moisture resistance is improved. It becomes possible to make it. In general, an inorganic filler having a larger average particle size (in other words, average particle size) is less expensive and therefore preferable in terms of cost. Further, as shown in FIG. 24A, in the method of using an ACF (Anisotropic Conductive Film) 598 for bonding the IC chip 1 and the substrate 4, the conductive particles 599 in the ACF 598 are bumps 3. However, since there is no conductive particle in the above-described embodiment of the present invention, there is no such need, and the bump 3 is formed by the substrate electrode 5 as shown in FIG. Since the pressure is applied while being squeezed, the inorganic filler 6f also escapes from between the bump 3 and the substrate electrode 4 together with the insulating resin layers 6 and 6b between the bump 3 and the substrate electrode 4 during the pressure bonding. Based on the characteristic that there is almost no hindrance to conductivity due to the unnecessary inorganic filler 6f sandwiched between the bump 3 and the bump 3 It can be used an inorganic filler 6f of average particle size.

(第9実施形態)
次に、本発明の第9実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置を図25,26を用いて説明する。図25,26は、それぞれ、上記第9実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置により製造された接合状態の模式断面図及びそのときに使用される樹脂シート6の部分拡大模式断面図である。この第9実施形態では、上記各実施形態において、上記絶縁性樹脂層6,6bの上記絶縁性樹脂6mに配合する上記無機フィラー6fは、複数の異なる平均粒径を持つ無機フィラー6f−1,6f−2とするものである。具体例としては、0.5μmの平均粒径を持つ無機フィラーと、2〜4μmの平均粒径を持つ無機フィラーとする。
(Ninth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a ninth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 25 and 26 are schematic cross-sectional views of a joined state manufactured by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the ninth embodiment, and a resin sheet 6 used at that time, respectively. It is a partial expanded schematic cross section. In the ninth embodiment, in each of the above embodiments, the inorganic filler 6f to be blended in the insulating resin 6m of the insulating resin layers 6 and 6b is an inorganic filler 6f-1 having a plurality of different average particle diameters. 6f-2. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

上記第9実施形態によれば、複数の異なる平均粒径を持つ無機フィラー6f−1,6f−2を絶縁性樹脂6mに混合することにより、絶縁性樹脂6mに混合する無機フィラー6fの量を増加させることができて、、無機フィラーの周りにおける吸湿量を減らしめることができ、耐湿性を向上させることが可能となるとともに、フィルム化(固体化)することが容易になる。すなわち、重量%で考えた場合、一種類の無機フィラーよりも、粒径の異なる無機フィラーを混在して入れた方が、単位体積あたりの無機フィラーの量を増やすことが可能である。これによって、封止シートとしての樹脂シート6又は接着剤6bへの無機フィラー6fの配合量を増加し、樹脂シート6又は接着剤6bの線膨張係数を低下させることができ、より長寿命化させることができて、信頼性を向上させることができる。   According to the ninth embodiment, by mixing the inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters with the insulating resin 6m, the amount of the inorganic filler 6f mixed with the insulating resin 6m is reduced. The amount of moisture absorption around the inorganic filler can be reduced, the moisture resistance can be improved, and film formation (solidification) is facilitated. That is, when considered in terms of% by weight, it is possible to increase the amount of inorganic filler per unit volume when mixed with inorganic fillers having different particle diameters, rather than one kind of inorganic filler. Thereby, the compounding quantity of the inorganic filler 6f to the resin sheet 6 or the adhesive 6b as the sealing sheet can be increased, the linear expansion coefficient of the resin sheet 6 or the adhesive 6b can be reduced, and the life can be extended. And reliability can be improved.

(第10実施形態)
次に、本発明の第10実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置においては、上記第9実施形態における効果をより確実なものとするため、さらに、上記複数の異なる平均粒径を持つ無機フィラー6f−1,6f−2のうちの一方の無機フィラー6f−1の平均粒径は、他方の無機フィラー6f−2の平均粒径の2倍以上異なっているものである。具体例としては、0.5μmの平均粒径を持つ無機フィラーと、2〜4μmの平均粒径を持つ無機フィラーとする。
(10th Embodiment)
Next, in a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a tenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In order to make the effect in the ninth embodiment more reliable, the average of one inorganic filler 6f-1 among the plurality of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters is further provided. The particle diameter is different from the average particle diameter of the other inorganic filler 6f-2 by at least twice. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

このようにすることにより、上記第9実施形態での効果をより一層高めることができる。すなわち、一方の無機フィラー6f−1の平均粒径は、他方の無機フィラー6f−2の平均粒径の2倍以上異なっている複数の異なる平均粒径を持つ無機フィラー6f−1,6f−2を絶縁性樹脂6mに混合することにより、絶縁性樹脂6mに混合する無機フィラー6fの量をより確実に増加させることができて、フィルム化(固体化)することがより容易になり、樹脂シート6又は接着剤6bへの無機フィラー6fの配合量を増加し、樹脂シート6又は接着剤6bの線膨張係数をより低下させることができ、より長寿命化させることができて、信頼性をより向上させることができる。   By doing in this way, the effect in the said 9th Embodiment can be improved further. That is, the average particle diameter of one inorganic filler 6f-1 is different from the average particle diameter of the other inorganic filler 6f-2 by more than twice, and the inorganic fillers 6f-1 and 6f-2 have a plurality of different average particle diameters. Is mixed with the insulating resin 6m, the amount of the inorganic filler 6f mixed with the insulating resin 6m can be increased more reliably, and it becomes easier to form a film (solidify), and the resin sheet. 6 or the amount of the inorganic filler 6f in the adhesive 6b can be increased, the linear expansion coefficient of the resin sheet 6 or the adhesive 6b can be further reduced, the life can be extended, and the reliability can be further improved. Can be improved.

(第11実施形態)
次に、本発明の第11実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置においては、上記第9実施形態における効果をより確実なものとするため、さらに、上記絶縁性樹脂6mに配合する上記無機フィラー6fは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー6f−1,6f−2であって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー6f−1は3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー6f−2は3μm以下の平均粒径を持つことが好ましい。具体例としては、0.5μmの平均粒径を持つ無機フィラーと、2〜4μmの平均粒径を持つ無機フィラーとする。
(Eleventh embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to an eleventh embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In order to make the effect in the ninth embodiment more reliable, the inorganic filler 6f to be blended in the insulating resin 6m further includes at least two kinds of inorganic fillers 6f- having a plurality of different average particle diameters. 1 and 6f-2, and one inorganic filler 6f-1 of the at least two types of inorganic fillers has an average particle diameter exceeding 3 μm, and the other inorganic filler of the at least two types of inorganic fillers 6f-2 preferably has an average particle size of 3 μm or less. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

(第12実施形態)
次に、本発明の第12実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置においては、上記各実施形態において、さらに、上記絶縁性樹脂6mに配合する上記無機フィラー6fは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー6f−1,6f−2であって、上記少なくとも2種類の無機フィラーのうちの平均粒径の大きい一方の無機フィラー6f−1は上記絶縁性樹脂6mと同一材料からなることにより、応力緩和作用を奏するようにすることもできる。具体例としては、0.5μmの平均粒径を持つ無機フィラーと、2〜4μmの平均粒径を持つ無機フィラーとする。
(Twelfth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a twelfth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, the inorganic filler 6f blended in the insulating resin 6m is at least two types of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters, Of the at least two types of inorganic fillers, one of the inorganic fillers 6f-1 having a large average particle diameter can be made of the same material as the insulating resin 6m, thereby exerting a stress relaxation action. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

この第12実施形態によれば、第9実施形態での作用効果に加えて、平均粒径の大きい一方の無機フィラー6f−1は上記絶縁性樹脂6mと同一材料からなることにより、上記絶縁性樹脂6mに応力が作用したとき、平均粒径の大きい一方の無機フィラー6f−1が上記絶縁性樹脂6mと一体化することにより、応力緩和作用を奏することができる。   According to the twelfth embodiment, in addition to the function and effect of the ninth embodiment, one of the inorganic fillers 6f-1 having a large average particle diameter is made of the same material as the insulating resin 6m. When stress acts on the resin 6m, one of the inorganic fillers 6f-1 having a large average particle diameter is integrated with the insulating resin 6m, so that a stress relaxation action can be achieved.

(第13実施形態)
次に、本発明の第13実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置においては、上記各実施形態において、さらに、上記絶縁性樹脂6mに配合する上記無機フィラー6fは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー6f−1,6f−2であって、上記少なくとも2種類の無機フィラーのうちの平均粒径の大きい一方の無機フィラー6f−1は上記絶縁性樹脂6mであるエポキシ樹脂よりも柔らかく、上記一方の無機フィラー6f−1が圧縮されることにより、応力緩和作用を奏するようにすることもできる。
(13th Embodiment)
Next, a mounting method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a thirteenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, the inorganic filler 6f blended in the insulating resin 6m is at least two types of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters, One inorganic filler 6f-1 having a large average particle size among at least two kinds of inorganic fillers is softer than the epoxy resin that is the insulating resin 6m, and the one inorganic filler 6f-1 is compressed. It is also possible to exert a stress relaxation action.

この第13実施形態によれば、第9実施形態での作用効果に加えて、平均粒径の大きい一方の無機フィラー6f−1は上記絶縁性樹脂6mと同一材料からなることにより、上記絶縁性樹脂6mに応力が作用したとき、平均粒径の大きい一方の無機フィラー6f−1が上記絶縁性樹脂6mであるエポキシ樹脂よりも柔らかいため、上記応力により、上記一方の無機フィラー6f−1が図27に示すように圧縮されてその周囲で圧縮に対する反力である引張力が分散されることにより、応力緩和作用を奏することができる。   According to the thirteenth embodiment, in addition to the function and effect of the ninth embodiment, one of the inorganic fillers 6f-1 having a large average particle diameter is made of the same material as the insulating resin 6m. When stress is applied to the resin 6m, the one inorganic filler 6f-1 having a large average particle diameter is softer than the epoxy resin that is the insulating resin 6m. As shown in 27, by compressing and dispersing a tensile force which is a reaction force against the compression around it, a stress relaxation action can be achieved.

(第14実施形態)
次に、本発明の第14実施形態にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置においては、上記各実施形態において、さらに、図28(A),(B),図29(A),(B),図30及び図31に示されるように、上記絶縁性樹脂層6,6bは、上記ICチップ1又は上記基板4に接触する部分700又は層6xが、他の部分701又は層6yよりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しないようにすることができる。この場合、図28(A),(B)に示すように、上記ICチップ1又は上記基板4に接触する部分700と、他の部分701とを明確に区別することなく、徐々に無機フィラー量が変わるようにしてもよいし、図29(A),(B)及び図30,図31に示すように明確に区別するようにしてもよい。すなわち、図29(A),(B)及び図30,図31において、上記絶縁性樹脂層6,6bは、上記ICチップ1又は上記基板4に接触する部分に位置されかつ上記絶縁性樹脂6mと同一の絶縁性樹脂に上記無機フィラー6fを配合した第1樹脂層6xと、上記第1樹脂層6xに接触し、かつ、上記第1樹脂層6xよりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しない上記絶縁性樹脂で構成される第2樹脂層6yとを備えて多層構造にすることもできる。
(14th Embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fourteenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, as shown in FIGS. 28 (A), (B), FIGS. 29 (A), (B), FIG. 30 and FIG. The portion 700 or the layer 6x in contact with the IC chip 1 or the substrate 4 has a smaller amount of the inorganic filler than the other portion 701 or the layer 6y, or may not contain the inorganic filler 6f. . In this case, as shown in FIGS. 28A and 28B, the amount of inorganic filler is gradually increased without clearly distinguishing between the portion 700 that contacts the IC chip 1 or the substrate 4 and the other portion 701. May be changed, or may be clearly distinguished as shown in FIGS. 29A and 29B and FIGS. That is, in FIGS. 29A, 29B, 30 and 31, the insulating resin layers 6 and 6b are located at a portion in contact with the IC chip 1 or the substrate 4 and the insulating resin 6m. The first resin layer 6x in which the inorganic filler 6f is blended with the same insulating resin and the first resin layer 6x is in contact with the first resin layer 6x, and the amount of the inorganic filler is less than the first resin layer 6x, or A multilayer structure can also be provided by including the second resin layer 6y made of the insulating resin not containing the inorganic filler 6f.

このようにすれば、以下のような効果を奏することができる。すなわち、もし、上記無機フィラー6fを絶縁性樹脂層全体に同じ重量パーセント(wt%)で入れると、ICチップ側又は基板側又はその両方の対向面の近傍に無機フィラー6fが多くなることがあり、ICチップ1と基板4との中間部分では逆に少なくなる。この結果、ICチップ側又は基板側又はその両方の対向面の近傍に無機フィラー6fが多いため、絶縁性樹脂層6,6bとICチップ1又は基板4又はその両方との間での接着力が低下することがある。上記第14実施形態によれば、上記ICチップ1又は上記基板4のいずれか一方に接触する部分700又は層6xが、他の部分701又は層6yよりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しないようにすることにより、無機フィラー量が多いために接着力が低下することを防止できる。   In this way, the following effects can be achieved. That is, if the inorganic filler 6f is added to the entire insulating resin layer at the same weight percent (wt%), the inorganic filler 6f may increase in the vicinity of the IC chip side or the substrate side or both opposing surfaces. On the other hand, there is a decrease in the intermediate portion between the IC chip 1 and the substrate 4. As a result, since there are many inorganic fillers 6f in the vicinity of the opposing surface on the IC chip side or the substrate side or both, the adhesive force between the insulating resin layers 6 and 6b and the IC chip 1 or the substrate 4 or both is high. May decrease. According to the fourteenth embodiment, the portion 700 or the layer 6x in contact with either the IC chip 1 or the substrate 4 has a smaller amount of the inorganic filler than the other portion 701 or the layer 6y, or the above By not blending the inorganic filler 6f, it is possible to prevent the adhesive force from being lowered due to the large amount of the inorganic filler.

以下に、この第14実施形態の種々の変形例について説明する。   Hereinafter, various modifications of the fourteenth embodiment will be described.

まず、第1の変形例として、図28(C),図29(C)及び図32(A)に示されるように、上記絶縁性樹脂層6,6bは、上記ICチップ1及び上記基板4の両方にそれぞれ接触する部分700が、他の部分701よりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しないようにすることもできる。この場合も、図28(C)に示すように、上記ICチップ1及び上記基板4の両方に接触する部分700と、他の部分701とを明確に区別することなく、徐々に無機フィラー量が変わるようにしてもよいし、図29(C)及び図32(A)に示されるように、明確に区別するようにしてもよい。すなわち、図29(C)及び図32(A)において、上記絶縁性樹脂層6,6bは、上記第1樹脂層6xの上記第2樹脂層6yとは反対側に、上記第1樹脂層6xよりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しない上記絶縁性樹脂で構成される第3樹脂層6zをさらに備えて多層構造とし、上記第1樹脂層6xと上記第3樹脂層6zは、それぞれ、上記ICチップ1と上記基板4とに接触するようにすることもできる。   First, as a first modification, as shown in FIGS. 28C, 29C, and 32A, the insulating resin layers 6 and 6b are formed of the IC chip 1 and the substrate 4 as described above. It is also possible that the portion 700 that contacts both of the above portions has a smaller amount of the inorganic filler than the other portion 701 or does not contain the inorganic filler 6f. Also in this case, as shown in FIG. 28C, the amount of the inorganic filler is gradually increased without clearly distinguishing between the portion 700 that contacts both the IC chip 1 and the substrate 4 and the other portion 701. It may be changed or may be clearly distinguished as shown in FIGS. 29C and 32A. That is, in FIGS. 29C and 32A, the insulating resin layers 6 and 6b are disposed on the opposite side of the first resin layer 6x to the second resin layer 6y, and the first resin layer 6x. The first resin layer 6x and the third resin are further provided with a third resin layer 6z made of the insulating resin having a smaller amount of the inorganic filler than the inorganic filler 6f or not containing the inorganic filler 6f. The layers 6z may be in contact with the IC chip 1 and the substrate 4, respectively.

さらに、別の変形例として、上記ICチップ1又は上記基板4又はその両方にそれぞれ接触する部分700は、その上記無機フィラー量が20wt%未満か、もしくは上記無機フィラー6fを配合しないようにする一方、上記他の部分701はその上記無機フィラー量が20wt%以上であるようにすることもできる。この場合、図28(A),(B),(C)に示すように上記ICチップ1又は上記基板4又は両方に接触する部分700と、他の部分701とを明確に区別することなく、徐々に無機フィラー量が変わるようにしてもよいし、図29(A),(B),図29(C),図30,図31,及び図32(A)に示すように明確に区別するようにしてもよい。すなわち、上記第1樹脂層6x又は第1樹脂層6x及び上記第3樹脂層6zは、その上記無機フィラー量が20wt%未満か、もしくは上記無機フィラー6fを配合しないようにする一方、上記第2樹脂層6yはその上記無機フィラー量が20wt%以上であるようにすることもできる。   Furthermore, as another modified example, the portion 700 that is in contact with the IC chip 1 or the substrate 4 or both, respectively, has an amount of the inorganic filler of less than 20 wt%, or does not contain the inorganic filler 6f. The other portion 701 may have the inorganic filler content of 20 wt% or more. In this case, as shown in FIGS. 28A, 28 </ b> B, and 28 </ b> C, the portion 700 that contacts the IC chip 1 or the substrate 4 or both and the other portion 701 are not clearly distinguished, The amount of the inorganic filler may be gradually changed, and is clearly distinguished as shown in FIGS. 29 (A), (B), FIG. 29 (C), FIG. 30, FIG. 31, and FIG. You may do it. That is, the first resin layer 6x or the first resin layer 6x and the third resin layer 6z have an amount of the inorganic filler of less than 20 wt% or do not contain the inorganic filler 6f, while the second The resin layer 6y may have an inorganic filler content of 20 wt% or more.

具体例としては、上記第2樹脂層6yは、絶縁性樹脂6mとして熱硬化性エポキシ樹脂としたとき、セラミック基板の場合には50wt%であり、ガラエポ基板の場合は20wt%とする。また、一例として、第1樹脂層6x又は第3樹脂層6z又はその両方の厚さは15μm、第2樹脂層6yの厚さは40〜60μmとする。また、上記絶縁性樹脂層6,6bの厚さは、ICチップ1と基板4との接合後の隙間寸法よりも大きな寸法として、ICチップ1と基板4との接合時にICチップ1と基板4との間に完全に満たされるようにして接合をより確実なものとする。   As a specific example, when the second resin layer 6y is a thermosetting epoxy resin as the insulating resin 6m, it is 50 wt% in the case of a ceramic substrate and 20 wt% in the case of a glass epoxy substrate. As an example, the thickness of the first resin layer 6x or the third resin layer 6z or both is 15 μm, and the thickness of the second resin layer 6y is 40 to 60 μm. Further, the thickness of the insulating resin layers 6 and 6b is larger than the gap size after bonding the IC chip 1 and the substrate 4, and the IC chip 1 and the substrate 4 are bonded when the IC chip 1 and the substrate 4 are bonded. To ensure complete joining between the two.

また、別の変形例として、図28(C),図29(C)及び図32(A)に示す変形例と無機フィラーの配合量を逆にするようにしてもよい。すなわち、図28(D)に示されるように、上記絶縁性樹脂層6,6bは、上記ICチップ1及び上記基板4の両方にそれぞれ接触する部分703の中間部分702が、上記ICチップ1及び上記基板4の両方にそれぞれ接触する部分703よりも上記無機フィラー量が少ないか、もしくは上記無機フィラー6fを配合しないようにすることもできる。この場合も、上記ICチップ1又は上記基板4又は両方に接触する部分703と、中間部分702とを明確に区別することなく、徐々に無機フィラー量が変わるようにしてもよいし、図29(D)及び図32(B)に示されるように、明確に区別するようにしてもよい。すなわち、図29(D)及び図32(B)に示されるように、上記絶縁性樹脂層6,6bは、上記ICチップ1及び上記基板4に接触する部分に位置されかつ上記無機フィラー6fを配合した絶縁性樹脂6mで構成される第4樹脂層6vと、上記ICチップ1と上記基板4との中間部分に位置されかつ上記第4樹脂層6vよりも上記無機フィラー量が少ないか又は含まれていない絶縁性樹脂6mで構成される第5樹脂層6wとを備えるようにすることもできる。   As another modification, the blending amount of the inorganic filler and the modification shown in FIGS. 28C, 29C, and 32A may be reversed. That is, as shown in FIG. 28 (D), the insulating resin layers 6 and 6b are formed such that the intermediate portion 702 of the portion 703 that contacts both the IC chip 1 and the substrate 4 is the IC chip 1 and The amount of the inorganic filler may be less than the portion 703 that contacts both of the substrates 4, or the inorganic filler 6f may not be blended. Also in this case, the amount of the inorganic filler may be gradually changed without clearly distinguishing between the portion 703 that contacts the IC chip 1 or the substrate 4 or both, and the intermediate portion 702. FIG. As shown in FIG. 32D and FIG. 32B, it may be clearly distinguished. That is, as shown in FIGS. 29 (D) and 32 (B), the insulating resin layers 6 and 6b are located at the portions in contact with the IC chip 1 and the substrate 4, and the inorganic filler 6f is removed. 4th resin layer 6v comprised by the mix | blended insulating resin 6m, and it is located in the intermediate part of the said IC chip 1 and the said board | substrate 4, and the said inorganic filler amount is less than or contains the said 4th resin layer 6v It is also possible to provide a fifth resin layer 6w composed of an insulating resin 6m that is not provided.

このようにすれば、上記ICチップ1と上記基板4との上記中間部分702又は上記第5樹脂層6wでは、上記ICチップ1と上記基板4とにそれぞれ接触する部分703又は上記第4樹脂層6vよりも上記無機フィラー量が少ないか又は含まれていないため、弾性率が低くなり、応力緩和効果を奏することができる。また、上記ICチップ1と上記基板4とにそれぞれ接触する部分703又は上記第4樹脂層6vの絶縁性樹脂としてICチップ1と基板4とに対する密着力の高いものを選択して使用すれば、上記ICチップ1に接触する部分703又はICチップ1の近傍部分の上記第4樹脂層6vでは、ICチップ1の線膨張係数にできるだけ近くなるように無機フィラー6fの配合量又は材料を選択する一方、上記基板4に接触する部分703又は基板4の近傍部分の上記第4樹脂層6vでは、基板4の線膨張係数にできるだけ近くなるように無機フィラー6fの配合量又は材料を選択することができる。この結果、上記ICチップ1に接触する部分703又はICチップ1の近傍部分の上記第4樹脂層6vとICチップ1との線膨張係数が接近するため、両者の間での剥離が生じにくくなるとともに、上記基板4に接触する部分703又は基板4の近傍部分の上記第4樹脂層6vと基板4との線膨張係数が接近するため、両者の間での剥離が生じにくくなる。   In this way, in the intermediate portion 702 or the fifth resin layer 6w between the IC chip 1 and the substrate 4, the portion 703 or the fourth resin layer that contacts the IC chip 1 and the substrate 4 respectively. Since the amount of the inorganic filler is less than or not contained in 6v, the elastic modulus is lowered and a stress relaxation effect can be achieved. Further, if a part 703 that contacts the IC chip 1 and the substrate 4 or an insulating resin of the fourth resin layer 6v is selected and used, a resin having high adhesion to the IC chip 1 and the substrate 4 is used. In the portion 703 that contacts the IC chip 1 or the fourth resin layer 6v in the vicinity of the IC chip 1, the amount or material of the inorganic filler 6f is selected so as to be as close as possible to the linear expansion coefficient of the IC chip 1. In the fourth resin layer 6v in the portion 703 in contact with the substrate 4 or in the vicinity of the substrate 4, the blending amount or material of the inorganic filler 6f can be selected so as to be as close as possible to the linear expansion coefficient of the substrate 4. . As a result, the linear expansion coefficient between the IC chip 1 and the fourth resin layer 6v in the vicinity of the portion 703 that contacts the IC chip 1 or in the vicinity of the IC chip 1 approaches, so that separation between the two is less likely to occur. At the same time, the linear expansion coefficient between the fourth resin layer 6v and the substrate 4 in the portion 703 in contact with the substrate 4 or in the vicinity of the substrate 4 approaches, so that the separation between the two hardly occurs.

さらに、図33(A),(B)に実線で示すように、上記絶縁性樹脂層6,6bは、上記ICチップ1又は上記基板4のいずれか一方に接触する部分P1から他の部分P2に向かって、上記無機フィラー量が徐々に又は段階的に少なくなるようにすることもできる。   Further, as shown by solid lines in FIGS. 33A and 33B, the insulating resin layers 6 and 6b are changed from the portion P1 in contact with either the IC chip 1 or the substrate 4 to the other portion P2. The amount of the inorganic filler can be decreased gradually or stepwise.

また、図33(C),(D)に実線で示すように、上記絶縁性樹脂層6,6bは、上記ICチップ1及び上記基板4にそれぞれ接触する部分P3,P4から他の部分すなわちICチップ1と上記基板4との中間部分P5に向かって、上記無機フィラー量が徐々に又は段階的に多くなるようにすることもできる。   Further, as shown by solid lines in FIGS. 33C and 33D, the insulating resin layers 6 and 6b are separated from the portions P3 and P4 that are in contact with the IC chip 1 and the substrate 4 respectively, that is, ICs. The amount of the inorganic filler can be increased gradually or stepwise toward the intermediate portion P5 between the chip 1 and the substrate 4.

また、図33(E)に実線で示すように、上記絶縁性樹脂層6,6bは、上記ICチップ1及び上記基板4にそれぞれ接触する部分(図28(D)の変形例における接触部分703に相当する部分)から、上記ICチップ1及び上記基板4との中間部分(図28(D)の変形例における中間部分702に相当する部分)に向かって、上記無機フィラー量が徐々に少なくなるようにすることもできる。   In addition, as shown by a solid line in FIG. 33 (E), the insulating resin layers 6 and 6b are in contact with the IC chip 1 and the substrate 4, respectively (contact portions 703 in the modification of FIG. 28D). From the portion corresponding to the IC chip 1 and the substrate 4 (portion corresponding to the intermediate portion 702 in the modified example of FIG. 28D) gradually decreases in amount of the inorganic filler. It can also be done.

また、図33(F)に実線で示すように、上記絶縁性樹脂層6,6bは、上記ICチップ1の近傍部分、次いで、上記基板4の近傍部分、次いで、上記ICチップ1の近傍部分と上記基板4の近傍部分との中間部分の順に上記無機フィラー量が少ないようにすることもできる。なお、図33(F)では、上記順に徐々に上記無機フィラー量が変化するように例示しているが、これに限られるものではなく、段階的に変化するようにしてもよい。   Further, as indicated by a solid line in FIG. 33 (F), the insulating resin layers 6 and 6b are formed in the vicinity of the IC chip 1, the vicinity of the substrate 4, and then the vicinity of the IC chip 1. The amount of the inorganic filler can be reduced in the order of the intermediate portion between the substrate 4 and the vicinity of the substrate 4. In FIG. 33 (F), the inorganic filler amount is exemplified to change gradually in the above order, but the present invention is not limited to this, and it may be changed stepwise.

上記図33(E),(F)の変形例のようにすれば、上記ICチップ1と上記基板4との中間部分では、上記ICチップ1及び上記基板4にそれぞれ接触する部分よりも上記無機フィラー量が少ないか又は含まれていないため、弾性率が低くなり、応力緩和効果を奏することができる。また、上記ICチップ1及び上記基板4にそれぞれ接触する部分の絶縁性樹脂としてICチップ1と基板4とに対する密着力の高いものを選択して使用すれば、ICチップ1に接触する部分では、ICチップ1の線膨張係数にできるだけ近くなるように無機フィラー6fの配合量又は材料を選択する一方、基板4に接触する部分では、基板4の線膨張係数にできるだけ近くなるように無機フィラー6fの配合量又は材料を選択することができる。この観点で無機フィラー6fの配合量を決定すると、通常は、図33(F)に実線で示すように、上記ICチップ1の近傍部分、次いで、上記基板4の近傍部分、次いで、上記ICチップ1の近傍部分と上記基板4の近傍部分との中間部分の順に上記無機フィラー量が少ないようなる。このような構成とすることにより、ICチップ1に接触する部分とICチップ1との線膨張係数が接近するため、両者の間での剥離が生じにくくなるとともに、基板4に接触する部分と基板4との線膨張係数が接近するため、両者の間での剥離が生じにくくなる。   33E and 33F, the intermediate portion between the IC chip 1 and the substrate 4 is more inorganic than the portion in contact with the IC chip 1 and the substrate 4 respectively. Since the amount of filler is small or not contained, the elastic modulus is lowered and a stress relaxation effect can be achieved. In addition, if a part having high adhesion to the IC chip 1 and the substrate 4 is selected and used as the insulating resin for the part that contacts the IC chip 1 and the substrate 4 respectively, While the blending amount or material of the inorganic filler 6f is selected so as to be as close as possible to the linear expansion coefficient of the IC chip 1, the portion of the inorganic filler 6f that is in contact with the substrate 4 is as close as possible to the linear expansion coefficient of the substrate 4. The amount or material can be selected. When the blending amount of the inorganic filler 6f is determined from this viewpoint, normally, as shown by a solid line in FIG. 33 (F), the vicinity of the IC chip 1, then the vicinity of the substrate 4, and then the IC chip The amount of the inorganic filler decreases in the order of the intermediate portion between the vicinity portion of 1 and the vicinity portion of the substrate 4. By adopting such a configuration, the linear expansion coefficient between the IC chip 1 and the portion that contacts the IC chip 1 approaches, so that separation between the two is less likely to occur, and the portion that contacts the substrate 4 and the substrate Since the linear expansion coefficient with 4 approaches, peeling between them becomes difficult to occur.

図33(A)〜(F)のいずれの場合でも、実用上、上記無機フィラー量は5〜90wt%の範囲内とすることが好ましい。5wt%未満では無機フィラー6fを混合する意味がない一方、90wt%を超えると、接着力が極度に低下するとともに、シート化するのが困難になるため好ましくないためである。   In any case of FIGS. 33A to 33F, the amount of the inorganic filler is preferably in the range of 5 to 90 wt% for practical use. If it is less than 5 wt%, there is no point in mixing the inorganic filler 6f. On the other hand, if it exceeds 90 wt%, the adhesive strength is extremely lowered and it is difficult to form a sheet, which is not preferable.

なお、上記のような複数の樹脂層6x,6y又は6x,6y,6zで構成される多層構造の膜を絶縁性樹脂層として用いてICチップ1を基板4に熱圧着した場合には、接合時の熱により絶縁性樹脂6mが軟化、溶融して上記樹脂層が混じり合うので、最終的には、各樹脂層の明確な境界が無くなり、図33のように傾斜した無機フィラー分布となる。   In the case where the IC chip 1 is thermocompression bonded to the substrate 4 using a multilayered film composed of a plurality of resin layers 6x, 6y or 6x, 6y, 6z as described above as an insulating resin layer, bonding is performed. Since the insulating resin 6m is softened and melted by the heat of time and the resin layers are mixed, finally, there is no clear boundary between the resin layers, and an inclined inorganic filler distribution is obtained as shown in FIG.

さらに、上記第14実施形態又は各変形例において、無機フィラー6fの入った部分又は層を有する絶縁性樹脂層、又は、無機フィラー分布が傾斜した絶縁性樹脂層において、上記部分又は樹脂層に応じて、異なった絶縁性樹脂を用いることも可能である。例えば、ICチップ1に接触する部分又は樹脂層では、ICチップ表面に用いられる膜素材に対して密着性を向上させる絶縁性樹脂を用いる一方、基板4に接触する部分又は樹脂層では、基板表面の材料に対して密着性を向上させる絶縁性樹脂を用いることも可能となる。   Furthermore, in the fourteenth embodiment or each modification, in the insulating resin layer having a portion or layer containing the inorganic filler 6f or the insulating resin layer having an inclined inorganic filler distribution, depending on the portion or the resin layer. It is also possible to use different insulating resins. For example, an insulating resin that improves adhesion to a film material used on the surface of the IC chip is used in the portion or resin layer that contacts the IC chip 1, while the substrate surface is used in the portion or resin layer that contacts the substrate 4. It is also possible to use an insulating resin that improves adhesion to the material.

上記第14実施形態及びそれらの上記種々の変形例によれば、ICチップ1又は上記基板4と絶縁性樹脂層6,6bとの接合界面では無機フィラー6fが存在しないかその量が少なく、絶縁性樹脂本来の接着性が発揮されて、上記接合界面で接着性の高い絶縁性樹脂が多くなり、ICチップ1又は上記基板4と絶縁性樹脂6mとの密着強度を向上させることができて、ICチップ1又は上記基板4との接着性が向上する。これにより、各種信頼性試験での寿命が向上するとともに、曲げに対しての剥離強度が向上する。   According to the fourteenth embodiment and the various modifications thereof, the inorganic filler 6f does not exist or is small in the bonding interface between the IC chip 1 or the substrate 4 and the insulating resin layers 6 and 6b. The inherent adhesiveness of the conductive resin is exhibited, the insulating resin having high adhesiveness at the bonding interface is increased, and the adhesion strength between the IC chip 1 or the substrate 4 and the insulating resin 6m can be improved. Adhesiveness with the IC chip 1 or the substrate 4 is improved. Thereby, the life in various reliability tests is improved, and the peel strength against bending is improved.

もし、接着そのものには寄与しないが線膨張係数を下げる効果を持つ無機フィラー6fが絶縁性樹脂6m中に均一に分散されていると、基板4又はICチップ表面に無機フィラー6fが接触し、接着に寄与する接着剤の量が減少することになり、接着性の低下を招く。この結果、もしICチップ1または基板4と接着剤の間で剥離が生じると、そこから水分が侵入し、ICチップ1の電極の腐食などの原因となる。また、剥離部分から剥がれが進行すると、ICチップ1と基板4の接合そのものが不良となり、電気的に接続不良となる。   If the inorganic filler 6f, which does not contribute to the bonding itself but has the effect of reducing the linear expansion coefficient, is uniformly dispersed in the insulating resin 6m, the inorganic filler 6f comes into contact with the substrate 4 or the IC chip surface and adheres. As a result, the amount of the adhesive that contributes to the decrease is reduced, resulting in a decrease in adhesiveness. As a result, if peeling occurs between the IC chip 1 or the substrate 4 and the adhesive, moisture enters from there and causes corrosion of the electrodes of the IC chip 1. Moreover, when peeling progresses from the peeled portion, the bonding itself between the IC chip 1 and the substrate 4 becomes defective, resulting in poor electrical connection.

これに対して、上記第14実施形態及びそれらの上記種々の変形例によれば、上記したように、無機フィラー6fによる線膨張係数を下げる効果を持たせたまま接着力を向上させることができる。これによって、ICチップ1及び基板4との密着強度が向上し、信頼性が向上する。   On the other hand, according to the fourteenth embodiment and the various modifications thereof, as described above, it is possible to improve the adhesive force while having the effect of reducing the linear expansion coefficient by the inorganic filler 6f. . Thereby, the adhesion strength between the IC chip 1 and the substrate 4 is improved, and the reliability is improved.

さらに、無機フィラー6fの少ない部分700又は樹脂層6xをICチップ側に配置した場合、又は、ICチップ側において無機フィラー分布を小さくした場合には、当該部分700又は樹脂層6xは、ICチップ表面の窒化シリコンや酸化珪素からなるパッシベイション膜に対して密着力を向上させることが可能となる。また、これらICチップ表面に用いられる膜素材に対して密着性を向上させる絶縁性樹脂を適宜選択して用いることも可能となる。また、ICチップ近傍での弾性率を下げることで、絶縁性樹脂層の一例である封止シート材料のなかでの応力集中が緩和される。基板4に用いられる材料がセラミックのように固い(弾性率の高い)場合には、このような構造をとると、基板近傍での封止シート材料との弾性率、線膨張係数がマッチングして、尚、好適である。   Further, when the portion 700 or the resin layer 6x with a small amount of the inorganic filler 6f is arranged on the IC chip side, or when the inorganic filler distribution is reduced on the IC chip side, the portion 700 or the resin layer 6x is formed on the surface of the IC chip. It is possible to improve the adhesion to a passivation film made of silicon nitride or silicon oxide. It is also possible to appropriately select and use an insulating resin that improves adhesion to the film material used on the surface of the IC chip. Moreover, the stress concentration in the sealing sheet material which is an example of an insulating resin layer is relieved by reducing the elastic modulus in the vicinity of the IC chip. When the material used for the substrate 4 is hard like ceramic (high modulus of elasticity), such a structure matches the modulus of elasticity and the linear expansion coefficient with the sealing sheet material in the vicinity of the substrate. In addition, it is preferable.

一方、無機フィラー6fの少ない部分700又は樹脂層6xを基板側に配置した場合には、又は、基板側において無機フィラー分布を小さくした場合には、樹脂基板やフレキシブル基板(FPC)などのように基板4に曲げが加わるような場合において、基板4を電子機器の筐体に組み込む際に曲げ応力が加わるようなとき、基板4と絶縁性樹脂層の一例である封止シートとの密着強度を向上する目的で用いることができる。ICチップ側の表面層がポリイミド膜で形成された保護膜よりなる場合においては、一般に、絶縁性樹脂の密着が良好で、問題とならない場合にICチップ1から基板4にかけて、弾性率と線膨張係数が連続的または段階的に変化することで、ICチップ側で封止シートが固く、基板側では柔らかい材料とすることができる。これにより、封止シート内部での応力発生が小さくなることから信頼性が向上する。   On the other hand, when the portion 700 having a small amount of the inorganic filler 6f or the resin layer 6x is arranged on the substrate side, or when the inorganic filler distribution is reduced on the substrate side, such as a resin substrate or a flexible substrate (FPC). In the case where bending is applied to the substrate 4, when bending stress is applied when the substrate 4 is incorporated into the housing of the electronic device, the adhesion strength between the substrate 4 and the sealing sheet which is an example of the insulating resin layer is increased. It can be used for the purpose of improving. When the surface layer on the IC chip side is made of a protective film formed of a polyimide film, in general, when the insulating resin adheres well and there is no problem, the elastic modulus and linear expansion from the IC chip 1 to the substrate 4 By changing the coefficient continuously or stepwise, the sealing sheet can be made hard on the IC chip side and soft on the substrate side. Thereby, since generation | occurrence | production of the stress inside a sealing sheet becomes small, reliability improves.

さらに、ICチップ側と基板側の両側に無機フィラー6fの少ない部分700又は樹脂層6x,6zを配置した場合、又は、ICチップ側と基板側の両側において無機フィラー分布を小さくした場合には、上記ICチップ側と基板側との2つの場合を両立させるものであり、ICチップ側及び基板側の両方での密着性を向上させることができるとともに、線膨張係数を下げてICチップ1と基板4の両者を高い信頼性で接続させることができる。また、ICチップ側表面の材質及び基板材質に応じて、より密着性、樹脂塗れ性の良好な絶縁性樹脂を選択して用いることができる。また、これらの無機フィラー6fの量の多い少ないの傾斜は自由に変えることができるので、無機フィラー6fの少ない部分又は層を極薄くしたりすることで、基板材料とのマッチングが可能である。   Furthermore, when the portion 700 or the resin layer 6x, 6z with a small amount of the inorganic filler 6f is disposed on both sides of the IC chip side and the substrate side, or when the inorganic filler distribution is reduced on both sides of the IC chip side and the substrate side, The above-mentioned two cases of the IC chip side and the substrate side are made compatible, and the adhesion on both the IC chip side and the substrate side can be improved, and the linear expansion coefficient is lowered to reduce the IC chip 1 and the substrate. 4 can be connected with high reliability. In addition, an insulating resin having better adhesion and better resin coating can be selected and used according to the material of the IC chip side surface and the substrate material. In addition, since the inclination with a large amount of these inorganic fillers 6f can be freely changed, matching with the substrate material is possible by making the portion or layer with a small amount of the inorganic fillers 6f extremely thin.

(第15実施形態)
次に、本発明の第15実施形態においては、上記第8〜14実施形態及びそれらの変形例にかかる回路基板への電子部品例えばICチップの実装方法及び装置及び上記実装方法により上記ICチップが上記基板に実装された電子部品ユニット若しくはモジュール例えば半導体装置により使用される絶縁性樹脂層の製造工程を図34,図35に基づいて説明する。
(Fifteenth embodiment)
Next, in the fifteenth embodiment of the present invention, the IC chip is mounted by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the eighth to fourteenth embodiments and modifications thereof, and the mounting method. A manufacturing process of an insulating resin layer used by an electronic component unit or module mounted on the substrate, for example, a semiconductor device will be described with reference to FIGS.

まず、直接、回路基板4上で絶縁性樹脂層を形成する場合には、回路基板4の上に、第1樹脂シートを貼付け、その上に第2樹脂シートを貼付ける。このとき、第1樹脂シートに無機フィラー6fが多い場合は図28(A)または図30のようになり、逆の場合には図28(B)または図31のようになる。すなわち、前者の場合には、第1樹脂シートは上記無機フィラー6fが多い部分701又は第2樹脂層6yに対応する樹脂シートであり、後者の場合には、上記無機フィラー6fが少ない部分700又は第1樹脂層6xに対応する樹脂シートとなる。   First, when forming an insulating resin layer directly on the circuit board 4, a 1st resin sheet is affixed on the circuit board 4, and a 2nd resin sheet is affixed on it. At this time, when the first resin sheet contains a large amount of the inorganic filler 6f, the result is as shown in FIG. 28 (A) or FIG. 30, and in the opposite case, the result is as shown in FIG. 28 (B) or FIG. That is, in the former case, the first resin sheet is a portion 701 with a large amount of the inorganic filler 6f or a resin sheet corresponding to the second resin layer 6y, and in the latter case, the portion 700 with a small amount of the inorganic filler 6f or A resin sheet corresponding to the first resin layer 6x is obtained.

また、第2樹脂シートの上にさらに第3樹脂シートを形成して、第1樹脂シートと第3樹脂シートとが無機フィラー6fが少ない部分700又は第1樹脂層6xに対応する場合には、図28(C)または図32(A)のようになる。   Further, when a third resin sheet is further formed on the second resin sheet, and the first resin sheet and the third resin sheet correspond to the portion 700 or the first resin layer 6x with a small amount of the inorganic filler 6f, As shown in FIG. 28C or FIG.

また、これらを、図34,図35に示すように、予めセパレータと呼ばれるベースフィルム672上で、第1樹脂シート673と第2樹脂シート674とをこの順に(図34,図35にはこの場合のみ示す。)、又はこれとは逆に、又はさらに第3樹脂シートをも、貼り付けて形成してもよい。この場合には、図34,図35のように、上下一対の加熱可能なローラ670,270などで複数の樹脂シート673,674を、必要に応じて加熱しつつ、貼り付けていく。その後、形成された樹脂シート体671を所定寸法毎に切断すれば、図28(A)〜(C),図29(A)〜(C),図30〜32のいずれかに示すような上記絶縁性樹脂シート6となる。   Further, as shown in FIGS. 34 and 35, the first resin sheet 673 and the second resin sheet 674 are placed in this order on a base film 672 called a separator in advance (in this case in FIGS. 34 and 35). Only the third resin sheet may be formed by attaching the third resin sheet. In this case, as shown in FIGS. 34 and 35, a plurality of resin sheets 673 and 674 are attached while being heated as necessary with a pair of upper and lower heatable rollers 670 and 270. Then, if the formed resin sheet body 671 is cut into predetermined dimensions, the above-mentioned as shown in any of FIGS. 28 (A) to (C), FIGS. 29 (A) to (C), and FIGS. The insulating resin sheet 6 is obtained.

また、別の変形例として、絶縁性樹脂シート6が連続した絶縁性樹脂シート体を作製する際には、溶剤に溶かせたエポキシ及び無機フィラーをドクターブレード法などによりセパレーターと呼ばれるベースフィルム上に塗布する。この溶剤を乾燥させて絶縁性樹脂シート体が製作される。   As another modification, when producing an insulating resin sheet body in which the insulating resin sheet 6 is continuous, an epoxy and an inorganic filler dissolved in a solvent are applied onto a base film called a separator by a doctor blade method or the like. To do. This solvent is dried to produce an insulating resin sheet body.

このとき、一旦、無機フィラー6fの濃度が低いか、又は、無機フィラー6fが入っていない液体状の絶縁性樹脂を第1層としてベースフィルム上に塗布し、場合によっては、その塗布された第1層の乾燥を行う。乾燥しない場合には、無機フィラー6fが、若干、第1層に第2層の無機フィラー6fが混入していき、図33のように無機フィラー分布が傾斜した構造となる。   At this time, once the concentration of the inorganic filler 6f is low, or a liquid insulating resin not containing the inorganic filler 6f is applied as a first layer on the base film. Dry one layer. When the inorganic filler 6f is not dried, the inorganic filler 6f of the second layer is slightly mixed with the first layer, and the inorganic filler distribution is inclined as shown in FIG.

上記塗布形成された第1層の上に、無機フィラー6fを第1層よりも多く混入した液体状の絶縁性樹脂を塗布して第2層とする。第2層を乾燥することにより、ベースフィルム上に第1層と第2層とが形成された2層構造の絶縁性樹脂シート体が形成できる。絶縁性樹脂シート体を所定寸法毎に切断すれば、図28(A),図29(A),図30に示すような上記絶縁性樹脂シート6となる。   A liquid insulating resin in which more inorganic filler 6f is mixed than the first layer is applied on the first layer formed by coating to form a second layer. By drying the second layer, an insulating resin sheet having a two-layer structure in which the first layer and the second layer are formed on the base film can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (A), 29 (A), and 30 is obtained.

なお、基板側に無機フィラー6fが少ない層を配置する場合には、上記と逆の工程、すなわち、ベースフィルム上に第2層を形成したのち、第2層上に第1層を形成して、2層構造の絶縁性樹脂シート体が形成できる。絶縁性樹脂シート体を所定寸法毎に切断すれば、図28(B),図29(B),図31に示すような上記絶縁性樹脂シート6となる。   In addition, when arrange | positioning the layer with few inorganic fillers 6f on the board | substrate side, after forming a 2nd layer on a base film and a 2nd layer on a base film, a 1st layer is formed on a 2nd layer. An insulating resin sheet having a two-layer structure can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (B), 29 (B), and 31 is obtained.

また、一旦、無機フィラー6fの濃度が低い、又は、無機フィラー6fが入っていない絶縁性樹脂6mを第1層として塗布乾燥(省略されることもある。)し、第1層の上に無機フィラー3fを第1層よりも多く混入した絶縁性樹脂を塗布して第2層として塗布乾燥(省略されることもある。)し、この上に無機フィラーの量が第2層より少ないまたは無い第3層を塗布する。これを乾燥することにより、ベースフィルム上に第1層と第2層と第3層とが形成された3層構造の絶縁性樹脂シート体が形成できる。絶縁性樹脂シート体を所定寸法毎に切断すれば、図28(C),図29(C),図32(A)に示すような上記絶縁性樹脂シート6となる。   In addition, once the concentration of the inorganic filler 6f is low or the insulating resin 6m not containing the inorganic filler 6f is applied and dried (may be omitted) as a first layer, the inorganic layer 6f is inorganic on the first layer. An insulating resin mixed with more filler 3f than the first layer is applied, applied and dried as the second layer (may be omitted), and the amount of the inorganic filler is smaller or absent than the second layer. Apply a third layer. By drying this, an insulating resin sheet having a three-layer structure in which the first layer, the second layer, and the third layer are formed on the base film can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (C), 29 (C), and 32 (A) is obtained.

上記直接、回路基板4上で絶縁性樹脂層を形成する方法によれば、上記電子部品ユニットを製造する側で、上記絶縁性樹脂層において、電子部品に最適な材料の樹脂を選択して電子部品側に配置する一方、基板に最適な材料の樹脂を選択して基板側に配置することができ、樹脂の選択の自由度を高めることができる。   According to the method of directly forming the insulating resin layer on the circuit board 4, the electronic component unit is manufactured on the side of manufacturing the electronic component unit by selecting a resin of the material most suitable for the electronic component in the electronic component unit. On the other hand, it is possible to select the resin of the optimum material for the substrate and arrange it on the substrate side while arranging on the component side, so that the degree of freedom in selecting the resin can be increased.

これに対して、絶縁性樹脂シート体を製造する方法では、上記したほど選択の自由度は無いが、一括して多数の上記絶縁性樹脂シート6を製造することかできて、製造効率が良いとともに安価なものとなるとともに、貼り付け装置が1台で十分になる。   On the other hand, in the method of manufacturing the insulating resin sheet body, there is no degree of freedom of selection as described above, but a large number of the insulating resin sheets 6 can be manufactured at once, and the manufacturing efficiency is good. At the same time, it becomes inexpensive, and a single attaching device is sufficient.

上記したように、本発明の上記各実施形態によれば、電子部品例えばICチップと回路基板を接合するのに従来要した工程の多くを無くすことができ、非常に生産性を向上させることができる。すなわち、例えば、従来例として記載したスタッド・バンプ・ボンディングや半田バンプによる接合では、フリップチップ接合した後に封止材を注入してバッチ炉に入れて硬化する必要がある。この封止材の注入には、1ケあたり数分、また、封止材の硬化に、2から5時間を要する。スタッド・バンプ・ボンディング実装においては、さらにその前行程として、バンプにAgペーストを転写して、これを基板に搭載した後、Agペーストを硬化するという工程が必要となる。この工程には2時間を要する。これに対して、上記実施形態の方法では、上記封止工程を無くすことができ、非常に生産性を向上させることができる。さらに、上記実施形態では、固体又は半固体の絶縁性樹脂の封止シート等を用いることにより、例えば分子量の大きなエポキシ樹脂を用いることができることとなり、10〜20秒程度の短時間で接合が可能となり、接合時間の短縮も図ることができ、さらに生産性を向上させることができる。また、接合材料として導電粒子の無い熱硬化性樹脂シート6又は熱硬化性接着剤6bを用いた場合には、従来例2で示した方法に比べて絶縁性樹脂中に導電性微片を加える必要が無いため、安価なICチップの実装方法及び装置を提供することができる。   As described above, according to the above embodiments of the present invention, it is possible to eliminate many of the processes conventionally required for bonding an electronic component such as an IC chip and a circuit board, thereby greatly improving productivity. it can. That is, for example, in the case of bonding by stud bump bonding or solder bump described as a conventional example, it is necessary to inject a sealing material after flip-chip bonding and put it in a batch furnace to be cured. The injection of the sealing material takes several minutes per one piece, and it takes 2 to 5 hours to cure the sealing material. In the stud bump bonding mounting, as a previous process, a process of transferring the Ag paste to the bump, mounting it on the substrate, and then curing the Ag paste is required. This process takes 2 hours. On the other hand, in the method of the above embodiment, the sealing step can be eliminated, and the productivity can be greatly improved. Furthermore, in the above embodiment, by using a sealing sheet of a solid or semi-solid insulating resin, for example, an epoxy resin having a large molecular weight can be used, and can be joined in a short time of about 10 to 20 seconds. Thus, the joining time can be shortened, and the productivity can be further improved. Further, when the thermosetting resin sheet 6 or the thermosetting adhesive 6b without conductive particles is used as the bonding material, conductive fine pieces are added to the insulating resin as compared with the method shown in the conventional example 2. Since it is not necessary, an inexpensive IC chip mounting method and apparatus can be provided.

さらに、以下のような効果をも奏することができる。   Furthermore, the following effects can also be achieved.

(1)バンプ形成
バンプをメッキで形成する方法(従来例3)では、専用のバンプ形成工程を半導体メーカーで行う必要があり、限定されたメーカーでしかバンプの形成ができない。ところが、本発明の上記実施形態によれば、ワイヤボンディング装置により、汎用のワイヤボンディング用のICチップを用いることができ、ICチップの入手が容易となる。すなわち、汎用のワイヤボンディング用のICチップを用いることができる理由は、ワイヤボンディングであれば、Alパッドが形成された通常のICパッド上に、ワイヤボンディング装置やバンプボンディング装置を用いてバンプが形成可能であるからである。一方、バンプをメッキで形成する方法(従来例3)によりメッキバンプを形成するには、Alパッドの上に、Ti、Cu、Crなどのバリヤメタルを形成したのちにレジストをスピンコートで塗布し、露光してバンプ形成部のみ穴をあける。これに電気を通電して、その穴部分にAuなどからなるメッキを行うことで形成する。従って、メッキバンプを形成するには、大規模なメッキ装置や、シアン化合物などの危険物の廃液処理装置を必要とするので、通常のアセンブリ工程を行う工場では現実には実施不可能である。
(1) Bump formation In the method of forming bumps by plating (conventional example 3), it is necessary to carry out a dedicated bump formation process by a semiconductor manufacturer, and bumps can be formed only by a limited manufacturer. However, according to the embodiment of the present invention, a general-purpose wire bonding IC chip can be used by the wire bonding apparatus, and the acquisition of the IC chip is facilitated. In other words, the reason why a general-purpose wire bonding IC chip can be used is that, when wire bonding is used, bumps are formed on a normal IC pad on which an Al pad is formed using a wire bonding apparatus or a bump bonding apparatus. It is possible. On the other hand, in order to form plated bumps by a method of forming bumps by plating (conventional example 3), a barrier metal such as Ti, Cu, Cr or the like is formed on an Al pad, and then a resist is applied by spin coating. Expose only the bump forming part. It is formed by energizing this and plating the hole with Au or the like. Accordingly, in order to form the plating bump, a large-scale plating apparatus and a waste liquid processing apparatus for hazardous materials such as cyanide are required.

また、従来例1の方法に比べて、導電性接着剤の転写といった不安定な転写工程での接着剤の転写量を安定させるためのバンプレベリングが不要となり、そのようなレベリング工程用のレベリング装置が不要となる。その理由は、バンプを押圧しながら基板の電極上で押しつぶすため、予めバンプだけをレベリングしておく必要がないためである。   Further, compared to the method of the conventional example 1, bump leveling for stabilizing the transfer amount of the adhesive in the unstable transfer process such as transfer of the conductive adhesive becomes unnecessary, and the leveling device for such leveling process Is no longer necessary. This is because the bumps are crushed on the electrodes of the substrate while pressing the bumps, so that it is not necessary to level the bumps in advance.

また、上記実施形態において以下のようにすれば、バンプ103を回路基板4の電極5にズレて実装された場合においても、信頼性の高い接合を達成することもできる。すなわち、バンプ3をICチップ1上に形成する際にワイヤボンディングと同様に金線を電気スパークにより金ボール96aを形成する。次に、95aで示す直径Φd−Bumpのボール96aを形成し、これをチャムファー角θcが100°以下となるキャピラリー193の93aで示すチャムファー直径φDを金ボール96aの直径d−Bumpの1/2から3/4とし、キャピラリー193の金ボール96aと接する部分に平らな部位を設けない先端形状としたキャピラリー193でICチップ1の電極2に超音波及び熱圧着によりバンプ103を形成する。上記形状のキャピラリー193を用いることで図10(B)のような先端が大略円錐状のバンプ103をICチップ1の電極2に形成することができる。上記方法で形成したバンプ103を回路基板4の電極5に図11(C)のごとく寸法Zだけズレて実装された場合においても、バンプ103がその先端が大略円錐形であるためバンプ103の外径の半分までのズレである場合はバンプ103の一部が必ず基板4の電極5と接触することができる。従来のバンプ3の図11(D)ではバンプ3のいわゆる台座3gの幅寸法dの一部が接触するが、部分的にしか接触せず不安定な接合となる。これを冷熱衝撃試験やリフローにかけた場合に接合部分がオープンとなる。本発明では、このような不安定な接合がなくなり、生産歩留まりと信頼性の高い接合を提供することができる。   Further, in the embodiment described above, even when the bump 103 is mounted on the electrode 5 of the circuit board 4 in a shifted manner, highly reliable bonding can be achieved. That is, when the bump 3 is formed on the IC chip 1, a gold ball 96a is formed by electric sparking of a gold wire in the same manner as wire bonding. Next, a ball 96a having a diameter Φd-Bump indicated by 95a is formed, and a Chamfer diameter φD indicated by 93a of the capillary 193 having a Chamfer angle θc of 100 ° or less is set to 1 of the diameter d-Bump of the gold ball 96a. The bumps 103 are formed on the electrodes 2 of the IC chip 1 by ultrasonic waves and thermocompression bonding with the capillaries 193 having a tip shape that does not provide a flat portion at the portion that contacts the gold ball 96a of the capillaries 193. By using the capillary 193 having the above-described shape, the bump 103 having a substantially conical tip as shown in FIG. 10B can be formed on the electrode 2 of the IC chip 1. Even when the bump 103 formed by the above method is mounted on the electrode 5 of the circuit board 4 so as to be displaced by the dimension Z as shown in FIG. 11C, the bump 103 has a substantially conical tip. When the deviation is up to half of the diameter, a part of the bump 103 can always be in contact with the electrode 5 of the substrate 4. In FIG. 11D of the conventional bump 3, a part of the width dimension d of the so-called pedestal 3 g of the bump 3 is in contact, but it is only in partial contact, resulting in unstable bonding. When this is subjected to a thermal shock test or reflow, the joint portion becomes open. In the present invention, such unstable bonding is eliminated, and a bonding with high production yield and reliability can be provided.

(2)ICチップと回路基板の接合
従来例2の方法によれば、接続抵抗は、バンプと回路基板の電極の間に存在する導電粒子の数に依存していたが、本発明の上記実施形態では、独立した工程としてのレベリング工程においてバンプ3をレベリングせずに回路基板4の電極5に従来例1、2よりも強い荷重(例えば、1バンプ3あたり20gf以上の加圧力)で押しつけてバンプ3と電極5とを直接的に接合することができるため、介在する粒子数に接続抵抗値が依存せず、安定して接続抵抗値が得られる。
(2) Bonding of IC chip and circuit board According to the method of Conventional Example 2, the connection resistance depends on the number of conductive particles existing between the bump and the electrode of the circuit board. In the embodiment, the bump 3 is not leveled in the leveling process as an independent process, and is pressed against the electrode 5 of the circuit board 4 with a load stronger than the conventional examples 1 and 2 (for example, a pressing force of 20 gf or more per bump 3). Since the bump 3 and the electrode 5 can be directly joined, the connection resistance value does not depend on the number of intervening particles, and the connection resistance value can be obtained stably.

また、従来のレベリング工程では基板電極との接合時のバンプ高さを一定に整えるために行っているが、本発明の上記各実施形態ではバンプ3の押しつぶしを電極2又は5への接合と同時に行うことができるので、独立したレベリング工程が不要であるばかりでなく、接合時に回路基板4の反りやうねりを変形させて矯正しながら接合することができるので、又は、バンプ3,103に付着させた導電性ペーストを硬化して接合時に導電性ペーストを変形させることにより、バンプ3,103のレベリングを一切不要として、接合時に回路基板4の反りやうねりを変形させて矯正しながら接合するので、反りやうねりに強い。   In the conventional leveling process, the bump height at the time of bonding to the substrate electrode is made constant. In the above embodiments of the present invention, the crushing of the bump 3 is performed simultaneously with the bonding to the electrode 2 or 5. In addition to eliminating the need for an independent leveling process, it is possible to perform bonding while deforming and correcting the warping and undulation of the circuit board 4 at the time of bonding, or to adhere to the bumps 3 and 103. Since the conductive paste is cured and the conductive paste is deformed at the time of bonding, the leveling of the bumps 3 and 103 is not required at all, and the warping and undulation of the circuit board 4 is deformed and bonded at the time of bonding. Strong against warping and swell.

ところで、従来例1では10μm/ICチップ(1個のICチップ当たり10μmの厚み反り寸法精度が必要であることを意味する。)、従来例2では2μm/IC、従来例3でも1μm/ICチップ(バンプ高さバラツキ±1μm以下)というような高精度の基板4やバンプ3,103の均一化が必要であり、実際上は、LCDに代表されるガラス基板が用いられている。これに対して、本発明の上記実施形態によれば、接合時に回路基板4の反りやうねりを変形させて矯正しながら接合するので、反りやうねりのある平面度の悪い基板、例えば、樹脂基板、フレキシブル基板、多層セラミック基板などを用いることができ、より低廉で汎用性のあるICチップの接合方法を提供することができる。   By the way, the conventional example 1 has a 10 μm / IC chip (meaning that 10 μm thickness warpage dimension accuracy is required per IC chip), the conventional example 2 has a 2 μm / IC, and the conventional example 3 has a 1 μm / IC chip. It is necessary to make the substrate 4 and the bumps 3 and 103 with high accuracy such as (bump height variation ± 1 μm or less) uniform, and in practice, a glass substrate typified by LCD is used. On the other hand, according to the above-described embodiment of the present invention, since the warp and undulation of the circuit board 4 are deformed and bonded at the time of bonding, the substrate is warped and undulated and has poor flatness, for example, a resin substrate. In addition, a flexible substrate, a multilayer ceramic substrate, or the like can be used, and a more inexpensive and versatile IC chip bonding method can be provided.

また、ICチップ1と回路基板4との間の熱硬化性樹脂6mの体積をICチップ1と回路基板4との間の空間の体積より大きくするようにすれば、この空間からはみ出すように流れ出て、封止効果を奏することができる。よって、従来例1で必要とした導電性接着剤でICチップと回路基板を接合した後にICチップの下に封止樹脂(アンダーフィルコート)を行う必要がなく、工程を短縮することができる。   Further, if the volume of the thermosetting resin 6m between the IC chip 1 and the circuit board 4 is made larger than the volume of the space between the IC chip 1 and the circuit board 4, it will flow out of this space. Thus, a sealing effect can be achieved. Therefore, it is not necessary to perform sealing resin (underfill coating) under the IC chip after bonding the IC chip and the circuit board with the conductive adhesive required in Conventional Example 1, and the process can be shortened.

なお、無機フィラー6fを熱硬化性樹脂6mにその5〜90wt%程度配合することにより、熱硬化性樹脂の弾性率、熱膨張係数を基板4に最適なものにコントロールすることができる。これに加えて、通常のメッキバンプでこれを利用すると、バンプと回路基板の間に無機フィラーが入り込み、接合信頼性が低くなる。しかしながら、本発明の上記実施形態のようにスタッドバンプ(ワイヤーボンディングを応用した形成方法)を用いるようにすれば、接合開始当初に熱硬化性樹脂6m中に入り込んできた尖っているバンプ3,103により、無機フィラー6fを、よって、熱硬化性樹脂6mを、バンプ3,103の外側方向へ押し出さすことにより、バンプ3,103が変形していく過程で無機フィラー6fと熱硬化性樹脂6mをバンプ3,103と電極5,2の間から押し出し、不要な介在物を存在させないようにすることができ、より信頼性を向上させることができる。   In addition, the elastic modulus and thermal expansion coefficient of the thermosetting resin can be controlled to be optimal for the substrate 4 by blending about 5 to 90 wt% of the inorganic filler 6f with the thermosetting resin 6m. In addition to this, when this is used in a normal plating bump, an inorganic filler enters between the bump and the circuit board, and the bonding reliability is lowered. However, if stud bumps (formation method applying wire bonding) are used as in the above-described embodiment of the present invention, the sharp bumps 3, 103 that have entered the thermosetting resin 6m at the beginning of bonding. By pushing the inorganic filler 6f and thus the thermosetting resin 6m toward the outside of the bumps 3 and 103, the inorganic filler 6f and the thermosetting resin 6m are transformed in the process of the bumps 3 and 103 being deformed. It is possible to extrude from between the bumps 3 and 103 and the electrodes 5 and 2 so that unnecessary inclusions do not exist, and the reliability can be further improved.

以上、本発明によれば、従来の接合工法よりも生産性よく、低廉な電子部品例えばICチップと回路基板の接合方法及びその装置を提供することができる。   As described above, according to the present invention, it is possible to provide a method and an apparatus for joining an electronic component such as an IC chip and a circuit board, which are more productive than the conventional joining method and are inexpensive.

1…ICチップ、2,5…電極、3,103…バンプ、3g…台座、4…回路基板、6…熱硬化性樹脂シート、6a…セパレータ、6b…熱硬化性接着剤、6f…無機フィラー、6f−1…平均粒径の大きな無機フィラー、6f−2…平均粒径の小さな無機フィラー、6m…絶縁性樹脂層(例としては熱硬化性樹脂)、6s…熱硬化された樹脂、6v…第4樹脂層、6w…第5樹脂層、6x…第1樹脂層、6y…第2樹脂層、6z…第3樹脂層、7…貼付けツール、8…接合ツール、8a…ヒータ、9,109,201…ステージ、93,193…キャピラリー、193a…先端部位、93b…平らな部位、95…ワイヤ、96,96a…ボール、98…湾曲部、99…ループ、200…保持部材、670…ローラ、671…絶縁性樹脂シート体、672…ベースフィルム、673…第1樹脂シート、674…第2樹脂シート、700…ICチップ及び/又は基板に接触する部分(無機フィラー量が少ないか、もしくは上記無機フィラーを配合しない部分)、701…他の部分(無機フィラー量が多い部分)、702…無機フィラー量が少ないか、もしくは上記無機フィラーを配合しない部分、703…無機フィラー量が多い部分。   DESCRIPTION OF SYMBOLS 1 ... IC chip, 2,5 ... Electrode, 3,103 ... Bump, 3g ... Base, 4 ... Circuit board, 6 ... Thermosetting resin sheet, 6a ... Separator, 6b ... Thermosetting adhesive, 6f ... Inorganic filler , 6f-1 ... inorganic filler having a large average particle diameter, 6f-2 ... inorganic filler having a small average particle diameter, 6m ... an insulating resin layer (for example, thermosetting resin), 6s ... a thermosetting resin, 6v ... 4th resin layer, 6w ... 5th resin layer, 6x ... 1st resin layer, 6y ... 2nd resin layer, 6z ... 3rd resin layer, 7 ... Pasting tool, 8 ... Joining tool, 8a ... Heater, 9, 109, 201 ... stage, 93,193 ... capillary, 193a ... tip portion, 93b ... flat portion, 95 ... wire, 96,96a ... ball, 98 ... curved portion, 99 ... loop, 200 ... holding member, 670 ... roller 671: Insulating resin sheath Body, 672 ... base film, 673 ... first resin sheet, 674 ... second resin sheet, 700 ... part in contact with IC chip and / or substrate (part where the amount of inorganic filler is small or the above inorganic filler is not blended) 701: Other portion (a portion with a large amount of inorganic filler), 702 ... A portion with a small amount of inorganic filler, or a portion not containing the inorganic filler, 703 ... A portion with a large amount of inorganic filler.

Claims (10)

電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層(6,6b)は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic material in which a plurality of types of inorganic fillers (6f-1, 6f-2) having different average particle sizes are mixed to have a plurality of peaks in the particle size distribution curve. A filler,
The insulating resin layer (6,6b), said electronic components and parts in contact respectively with the substrate, a mounting method of electronic components as the inorganic filler amount is less than the other portions.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)の平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)の平均粒径の2倍以上異なっており、
上記絶縁性樹脂層(6,6b)は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. The average particle diameter of one inorganic filler (6f-1) of the at least two types of inorganic fillers is the other inorganic filler (6f- 2) more than twice the average particle size of
The insulating resin layer (6,6b), said electronic components and parts in contact respectively with the substrate, a mounting method of electronic components as the inorganic filler amount is less than the other portions.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)は3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)は3μm以下の平均粒径を持ち、
上記絶縁性樹脂層(6,6b)は、上記電子部品及び上記基板にそれぞれ接触する部分が、他の部分よりも上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. An inorganic filler (6f-1) of the at least two types of inorganic fillers having an average particle diameter exceeding 3 μm, and the other inorganic of the at least two types of inorganic fillers The filler (6f-2) has an average particle size of 3 μm or less,
The insulating resin layer (6,6b), said electronic components and parts in contact respectively with the substrate, a mounting method of electronic components as the inorganic filler amount is less than the other portions.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層(6,6b)は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層(6x)と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層(6y)と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層(6z)とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic material in which a plurality of types of inorganic fillers (6f-1, 6f-2) having different average particle sizes are mixed to have a plurality of peaks in the particle size distribution curve. A filler,
The insulating resin layer (6, 6b) is a first resin in which the inorganic filler is blended with the same insulating resin as the insulating resin, which is located at a portion in contact with either the electronic component or the substrate. A layer (6x), a second resin layer (6y) made of an insulating resin in contact with the first resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the first resin on the opposite side of the said second resin layer of the layer, the provided third resin layer and (6z) composed of the inorganic filler amount is small insulating resin than the first resin layer, the first resin layer and the third resin layer, respectively, the electronic component and the mounting method that electronic components to contact the substrate.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)の平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)の平均粒径の2倍以上異なっており、
上記絶縁性樹脂層(6,6b)は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層(6x)と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層(6y)と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層(6z)とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. The average particle diameter of one inorganic filler (6f-1) of the at least two types of inorganic fillers is the other inorganic filler (6f- 2) more than twice the average particle size of
The insulating resin layer (6, 6b) is a first resin in which the inorganic filler is blended with the same insulating resin as the insulating resin, which is located at a portion in contact with either the electronic component or the substrate. A layer (6x), a second resin layer (6y) made of an insulating resin in contact with the first resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the first resin on the opposite side of the said second resin layer of the layer, the provided third resin layer and (6z) composed of the inorganic filler amount is small insulating resin than the first resin layer, the first resin layer and the third resin layer, respectively, the electronic component and the mounting method that electronic components to contact the substrate.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)は3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)は3μm以下の平均粒径を持ち、
上記絶縁性樹脂層(6,6b)は、上記電子部品又は上記基板のいずれか一方に接触する部分に位置されかつ上記絶縁性樹脂と同一の絶縁性樹脂に上記無機フィラーを配合した第1樹脂層(6x)と、上記第1樹脂層に接触し、かつ、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第2樹脂層(6y)と、上記第1樹脂層の上記第2樹脂層とは反対側に、上記第1樹脂層よりも上記無機フィラー量が少ない絶縁性樹脂で構成される第3樹脂層(6z)とを備えて、上記第1樹脂層と上記第3樹脂層は、それぞれ、上記電子部品と上記基板に接触する電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. An inorganic filler (6f-1) of the at least two types of inorganic fillers having an average particle diameter exceeding 3 μm, and the other inorganic of the at least two types of inorganic fillers The filler (6f-2) has an average particle size of 3 μm or less,
The insulating resin layer (6, 6b) is a first resin in which the inorganic filler is blended with the same insulating resin as the insulating resin, which is located at a portion in contact with either the electronic component or the substrate. A layer (6x), a second resin layer (6y) made of an insulating resin in contact with the first resin layer and having a smaller amount of the inorganic filler than the first resin layer, and the first resin on the opposite side of the said second resin layer of the layer, the provided third resin layer and (6z) composed of the inorganic filler amount is small insulating resin than the first resin layer, the first resin layer and the third resin layer, respectively, the electronic component and the mounting method that electronic components to contact the substrate.
上記電子部品に接触する上記第1又は第3樹脂層では、電子部品表面に用いられる膜素材に対して上記第2樹脂層よりも密着性を向上させる絶縁性樹脂を用いる一方、上記基板に接触する上記第1又は第3樹脂層では、基板表面の材料に対して上記第2樹脂層よりも密着性を向上させる絶縁性樹脂を用いるようにした請求項4〜6のいずれか1つに記載の電子部品の実装方法。 In the first or third resin layer in contact with the electronic component, an insulating resin that improves adhesion to the film material used on the surface of the electronic component than the second resin layer is used, while in contact with the substrate. in the first or third resin layer, according to any one of claims 4-6 as adapted to use an insulating resin to improve adhesion than the second resin layer to the material of the substrate surface to Electronic component mounting method. 電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、異なる平均粒径を持つ複数種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであり、
上記絶縁性樹脂層(6,6b)は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler to be blended in the insulating resin is an inorganic material in which a plurality of types of inorganic fillers (6f-1, 6f-2) having different average particle sizes are mixed to have a plurality of peaks in the particle size distribution curve. A filler,
The insulating resin layer (6, 6b) includes the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. implementation of electronic parts as the amount is small.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)の平均粒径は、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)の平均粒径の2倍以上異なっており、
上記絶縁性樹脂層(6,6b)は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. The average particle diameter of one inorganic filler (6f-1) of the at least two types of inorganic fillers is the other inorganic filler (6f- 2) more than twice the average particle size of
The insulating resin layer (6, 6b) includes the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. implementation of electronic parts as the amount is small.
電子部品(1)の電極(2)にバンプ(3,103)を形成し、
絶縁性樹脂(6m)に無機フィラー(6f)を配合した固体又は半固体の絶縁性樹脂層(6,6b)を介在させながら、上記電子部品の上記電極と回路基板(4)の電極(5)とを位置合わせして上記電子部品を上記基板に搭載し、
その後、上記電子部品側から加熱しながら、又は基板側から加熱しながら、又は、上記電子部品側と上記基板側の両方から加熱しながら、ツール(8)により上記電子部品を上記回路基板に押圧し、上記基板の反りの矯正と上記バンプを押しつぶしながら、上記電子部品と上記回路基板の間に介在する上記絶縁性樹脂層を硬化して、上記電子部品と上記回路基板を接合して上記電子部品の上記電極と上記回路基板の上記電極を電気的に接続する電子部品の実装方法であって、
上記絶縁性樹脂に配合する上記無機フィラーは、複数の異なる平均粒径を持つ少なくとも2種類の無機フィラー(6f−1,6f−2)を混合して粒径分布曲線に複数のピークを持つようにした無機フィラーであって、上記少なくとも2種類の無機フィラーのうちの一方の無機フィラー(6f−1)は3μmを超える平均粒径を持ち、上記少なくとも2種類の無機フィラーのうちの他方の無機フィラー(6f−2)は3μm以下の平均粒径を持ち、
上記絶縁性樹脂層(6,6b)は、上記電子部品の近傍部分、次いで、上記基板の近傍部分、次いで、上記電子部品の近傍部分と上記基板の近傍部分との中間部分の順に上記無機フィラー量が少ないようにした電子部品の実装方法。
Form bumps (3, 103) on the electrodes (2) of the electronic component (1),
While interposing a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m), the electrode of the electronic component and the electrode (5) of the circuit board (4) ) And position the electronic component on the substrate,
Then, while heating from the electronic component side, from the substrate side, or from both the electronic component side and the substrate side, the electronic component is pressed against the circuit board by the tool (8). Then, while correcting the warp of the substrate and crushing the bumps, the insulating resin layer interposed between the electronic component and the circuit board is cured, and the electronic component and the circuit board are joined to each other. An electronic component mounting method for electrically connecting the electrode of the component and the electrode of the circuit board,
The inorganic filler compounded in the insulating resin has a plurality of peaks in the particle size distribution curve by mixing at least two types of inorganic fillers (6f-1, 6f-2) having a plurality of different average particle sizes. An inorganic filler (6f-1) of the at least two types of inorganic fillers having an average particle diameter exceeding 3 μm, and the other inorganic of the at least two types of inorganic fillers The filler (6f-2) has an average particle size of 3 μm or less,
The insulating resin layer (6, 6b) includes the inorganic filler in the order of the vicinity of the electronic component, then the vicinity of the substrate, and then the intermediate portion between the vicinity of the electronic component and the vicinity of the substrate. implementation of electronic parts as the amount is small.
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